SMPTE-292 Scrambler and Descrambler/Framer

April 24, 1999 Product Specification

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WKH Core Facts
Core Specifics
Device Families XC4000E, XC4000EX,
XC4000XL,XC4000XLA,
XC4000XV, Spartan
Andraka Consulting Group, Inc. CLBs Used Transmit: 45 CLBs in a
16 Arcadia Drive 5W x 10 H area
North Kingstown, RI USA Receive: 135 CLBs in a
Phone: +1 401-884-7930 12W x 14 H area
Fax: +1 401-884-7950 IOBs Used Transmit: none in macro
URL: http://users.ids.net/~randraka (21 inputs, 20 outputs
E-mail: [email protected] plus clock)
Receive: none in macro
Features (20 inputs, 21 outputs
plus clock)
• Fully compatible with SMPTE specification for 292M
System clock System clock: 74.25 MHz
Bit-Serial Digital Interface for High Definition Television
(specified by SMPTE 292M)
Systems
Device Carry logic, CLB RAM,
• Designed for use with AMCC S8401/S8501 serializer
Features used relative placement
and deserializer chipset
• Separate Macro blocks for transmit scrambler and Supported Devices
receiver descrambler/framer Family Minimum speed Maximum clock
• Fully synchronous operation grade (receive) for listed speed
grade
• 75 MHz performance in XC4005E-1, XC4005XL-2,
XCS10-4 (XC4006 or larger required to hold both) XC4000E -1 84 MHz
XC4000EX -2 77 MHz
• Transmit macro accepts 20 bit parallel data (10 bit EY
XC4000XL -2 75 MHz
and 10 bit ECb ECr), then codes it using the scramble
XC4000XLA -09 108 MHz
polynomial (X9 + X4 + 1) and NRZI (x+1) encoding.
Spartan -4 81 MHz
Outputs 20 bits parallel to AMCC S8401serializer on
SpartanXL -4 119 MHz
each cycle of transmit word clock.
Minimum Transmit only: XC4002/XCS05
• Receive macro accepts 20 bit de-serialized data from
AMCC S8501 deserializer, reverses the NRZI coding device size Receive only: XC4005/XCS10
and descrambles the data. Framing logic aligns the bits Both: XC4006/XCS20
with the 20 bit parallel output (aligns 10 bit EY and 10 bit Provided with Core
ECb ECr) Documentation Core interface document
• Both Macros are relatively placed to ensure a Design file format EDIF netlist
successful route and timing Viewlogic source schematics
Applications available extra
The SMPTE 292 Scrambler and Descrambler/Framing Constraints .UCF file with timing constraint.
Cores are used with the AMCC S8401/S8501 High Definition Placement information
Serial Interface (HD-SCI) chipset. The chipset and these embedded in design
cores form the basic SMPTE 292M interface for HDTV Entry/ Verification Viewlogic schematic / VHDL
applications. tools
Schematic symbols Viewlogic
General Description Evaluation model VHDL behavioral model
The SMPTE292 core set, coupled with the AMCC Reference Designs none
S8401/S8501 serializer/deserializer chipset is fully compliant and application notes
to the SMPTE 292M specification for Bit Serial Interfaces for Additional Items none
High Definition Television Design tools
Systems. The core set includes separate Xilinx 4K cores for Xilinx Core tools M1.5
Transmitter coding (scrambling and NRZI) and receiver Design verification
decoding (NRZ, descrambling, sync detect and word Support
framing). Provided by Andraka Consulting Group
Functional Description
The CORE set is supplied as two cores, one for transmit and
one for receive. The block diagrams are shown in Figure 1
in a system context.

Copyright 1999, Andraka Consulting Group, Inc. All rights reserved.

SMPTE-292 Scrambler and Descrambler/Framer
TX WORD CLOCK

G1(X) = G2(X) = AMCC S8401 Driver

20 9 4 20 Serializer
TX DATA IN X +X +1 X+1

TXRST
Transmit Macro

Coax or Fiber

EQ

AMCC S8501 20 G2(X) = G1(X) = Delay 20 RX DATA OUT

De-serializer 9 4
X+1 X +X +1 Delay 1
Header
RX WORD CLOCK
Detect
Logic SYNC OUT
Delay
Receive Macro

Figure 1. Transmit and Receiver block diagrams shown in system context

Scrambler (Transmit) Block the 20 bit parallel data word. When a header sync pattern is
9 4 found, a rotator shifts the data to align the bits with the
The transmitter block performs the X +X +1 scrambled
parallel output word. That alignment is maintained until the
channel coding, followed by the X+1 NRZI scrambling.
next header is detected. The header detect signal is also
Clock latency through the block is one clock cycle. The
output for use as a frame sync signal. That frame sync is
block performs scrambling on the 20 bit parallel data word.
coincident with the first word of the output header sync
Figure 3 shows the equivalent bit serial scrambler circuit.
pattern (the 1’s word).
This is the scrambler circuit that would be used if the
unscrambled stream was first serialized then scrambled. The example in Figure 2 shows the unscrambled data
misaligned by 6 bits. The header detect logic recognizes the
Inputs to the scrambler block are the 20 bit data,
misaligned header sync sequence then selects the amount
synchronous reset and the word rate clock. The 20 bit data
of shift required to align the data with the parallel output.
input consists of the 10 bit EY channel and the separate10 bit
That alignment is maintained until another header is
ECb ECr channel. This bit assignment interleaves the data
detected. The output listing also shows the timing of the
per the SMPTE 292 specification. The word rate clock
sync signal.
should be 74.25 MHz, and is the same clock applied to the
AMCC S8401 serializer’s REFCLK input. The AMCC
19 Unscrambled Din 0
serializer has an internal phase lock loop that synthesizes
11 1111 1111 11 11xx xxxx
the serial bit clock from this word clock. The synchronous
00 0000 0000 00 0011 1111
reset forces the scrambler outputs to zero when the macro is
00 0000 0000 00 0000 0000
clocked.
aa aaaa aaaa aa aa00 0000
The macro output is 20 bit parallel scrambled data. The bb bbbb bbbb bb bbbb bbbb
output should be connected to the AMCC serializer via cc cccc cccc cc cccc cccc
registered outputs on the FPGA (OFD I/O macros), also
clocked by the transmit word clock. Transmit data is clocked Dout Sync
19 0
through the core by the rising edge of the transmit word xx xxxx xxxx xx xxxx xxxx 0
clock. 11 1111 1111 11 1111 1111 1
00 0000 0000 00 0000 0000 0
Descrambler/Framer (Receive) Block 00 0000 0000 00 0000 0000 0
The receiver block descrambles the 20 bit parallel receive bb bbbb aaaa aa aaaa aaaa 0
data using the complement of the scramble polynomial. cc cccc bbbb bb bbbb bbbb 0
Header sync detect logic parses the descrambled data for a
frame header (EAV or SAV block) sync pattern consisting of Figure 2. Framing example
string of 20 ‘1’ bits followed immediately by 40 ‘0’ bits (serial
data is presented to the AMCC S8501 least significant bit
first). The sync word is at an arbitrary alignment relative to

ENCODED
DATA OUT
Z Z Z Z Z Z Z Z Z Z
SERIAL
DATA IN

Figure 3. Equivalent serial scrambler circuit

Copyright 1999, Andraka Consulting Group, Inc. All rights reserved.

SMPTE-292 Scrambler and Descrambler/Framer
The input to the scrambler should come directly from the Ordering Information
AMCC S8501 via registered inputs to the FPGA (IFD
This product is available directly from Andraka Consulting
macros). The descrambler macro does not include these
Group, Inc. Please contact them for further information,
IOBs to provide flexibility to the designer. Output from the
pricing, and functional models.
receiver block is 20 bit data aligned to the 20 bit word. The
user’s logic should use the header sync output as a marker
to aid in recovering the EAV/SAV frame timing. Latency Recommended Design Experience
through the receiver block is 10 cycles of the word clock Users should be familiar with SMPTE 292 and related
(from input word containing MSB of aligned data). Data is standards, as well as with standard Xilinx tool flows. The
always left shifted to obtain alignment. The core and the user should also be familiar with incorporating black box
registered inputs should be clocked by the receive word designs into his tool flow.
clock generated by the AMCC S8501 deserializer. The core
uses the rising edge of the clock input throughout. Related Information
ANSI/SMPTE 292M-1996 Standard
Core Modifications SMPTE
The core is provided as a black box relatively placed macro 595 West Hartsdale Avenue
(RPM). Andraka Consulting Group, Inc can customize or White Plains, NY 10607 USA
retarget the core for additional cost. This includes adding or Phone: +1 914 761 1100
removing blocks, changing the scrambler polynomial, or Fax: +1 914 761 3115
integrating the macro into your design. The design source email: [email protected]
document (Viewlogic schematic) is available at additional URL: www.smpte.org
cost. For information on Xilinx programmable logic or
development system software, contact your local Xilinx sales
Pinout office, or:
Signal names for interfacing the cores are shown in figure 1 Xilinx Inc.
and described in tables 1 and 2. The core must be wired to 2100 Logic Drive
FPGA I/O pads by the user. San Jose, CA 95124
Phone: +1 408-559-7778
Verification Methods Fax: +1 408-559-7114
The FPGA core was verified through functional simulation URL: www.xilinx.com
and static timing analysis. Functional simulation included
comparison of the scrambler and descrambler function to the For general Xilinx literature, contact:
bit serial model presented in this document, and thorough Phone: +1 800-231-3386 (inside the US)
simulation of the framing logic. A system simulation was +1 408-879-5017 (outside the US)
performed with the scrambler output serialized, subjected to E-mail: [email protected]
a variable bit delay, de-serialized and passed trough the Table 2. Receive macro interface signals
receiver. The results were compared to the input to the
scrambler to check for data integrity. A functionally accurate Signal Signal Description
VHDL behavioral model is supplied with the core, and is Direction
available at no charge upon request. RCLKN Input Receive word clock
from S8501 RCLKN
Table 1. Transmit macro interface signals pin. Nominally 74.25
MHz.
Signal Signal Description Din[19:0] Input Parallel output data
Direction from S8501. Bit
TCLK Input Transmit word clock: indexes match indexes
74.25 MHz. Same as on S8501. Data is
AMCC S8401 clocked in on rising
reference clock edge of RCLKN
TXRST Input Synchronous Reset: Dout[19:0] Output 20 bit parallel data
‘1’ at clock rising edge output. The 10 bit EY
clears scrambler word is output from
Din[19:0] Input 20 bit parallel data Dout[19:10], The 10 bit
input. The 10 bit EY ECb ECr word is output
word is input to from Dout[9:0]. Data
Din[19:10], The 10 bit changes on rising edge
ECb ECr word is input to of RCLKN
Din[9:0]. Data is Sync Output Header Sync pulse.
clocked in on rising Logic ‘1’ when 1’s word
edge of TCLK of header sync is at
Dout[19:0] Output Parallel output data to Dout[19:0], Logic ‘0’
S8401. Bit indexes otherwise. This signal
match indexes on should be used for
S8401. Data changes frame synchronization
on rising edge of TCLK by the user’s logic.

Copyright 1999, Andraka Consulting Group, Inc. All rights reserved.