Dual Output Digital Multi-Phase Controller
IR3565A
FEATURES DESCRIPTION
Dual output 4+2 phase PWM Controller The IR3565A is a dual-loop digital multi-phase buck
Easiest layout and fewest pins in the industry controller designed for CPU voltage regulation and is fully
©
compliant with AMD® SVI1 & SVI2 and Intel VR12
Fully supports AMD® SVI1 & SVI2 with dual specifications.
OCP
and Intel® VR12
The IR3565A includes IR’s Efficiency Shaping
Overclocking & Gaming Mode Technology to deliver exceptional efficiency at minimum
Switching frequency from 200kHz to 2MHz cost across the entire load range. IR Variable Gate Drive
per phase optimizes the MOSFET gate drive voltage based on real-
time load current. IR’s Dynamic Phase Control
IR Efficiency Shaping Features including adds/drops active phases based upon load current and
Dynamic Phase Control and Automatic Power can be configured to enter 1-phase operation and diode
State Switching emulation mode automatically or by command.
Programmable 1-phase operation for Light
Loads and Active Diode Emulation for Very IR’s unique Adaptive Transient Algorithm (ATA), based
Light Loads on proprietary non-linear digital PWM algorithms,
IR Adaptive Transient Algorithm (ATA) on minimizes output bulk capacitors and Multiple Time
both loops minimizes output bulk capacitors Programmable (MTP) storage saves pins and enables a
and system cost small package size. Device configuration and fault
parameters are easily defined using the IR Digital Power
Auto-Phase Detection with auto-
compensation Design Center (DPDC) GUI and stored in on-chip MTP.
Per-Loop Fault Protection: OVP, UVP, OCP, The IR3565A provides extensive OVP, UVP, OCP and
OTP, CFP OTP fault protection and includes thermistor based
I2C/SMBus/PMBus system interface for temperature sensing with VRHOT signal.
telemetry
of Temperature, Voltage, Current & Power for The IR3565A includes numerous features like register
both loops diagnostics for fast design cycles and platform
Multiple Time Programming (MTP) with differentiation, simplifying VRD design and enabling
integrated charge pump for easy custom fastest time-to-market (TTM) with “set-and-forget”
configuration methodology.
Compatible with IR ATL and 3.3V tri-state
Drivers APPLICATIONS
+3.3V supply voltage; -40°C to 85°C ambient AMD® SVI1 & SVI2, Intel® VR12 based systems
operation
Desktop & Notebook CPU VRs
Pb-Free, RoHS, 6x6mm, 48-pin, 0.4mm pitch High Performance Graphics Processors
QFN
ORDERING INFORMATION
Base Part Standard Pack Orderable
Package Type
Number Form Quantity Part Number
1
IR3565A QFN 6 mm x 6 mm Tape and Reel 3000 IR3565AMxxyyTRP
IR3565A QFN 6 mm x 6 mm Tape and Reel 3000 IR3565AMTRPBF
IR3565A QFN 6 mm x 6 mm Tray 4900 IR3565AMTYPBF
Notes 1: Customer Specific Configuration File, where xx = Customer ID and yy = Configuration File (Codes assigned by IR Marketing).
1 www.irf.com | © 2013 International Rectifier | Product Brief | October 1, 2013 | V3.04
Dual Output Digital Multi-Phase Controller
IR3565A
ORDERING INFORMATION
IR3565AM
P/PBF – Lead Free
TR – Tape & Reel / TY - Tray
yy – Configuration File ID
xx – Customer ID
Package Type (QFN)
ISEN1_L2
IRTN1_L2
IRTN2_L2
ISEN2_L2
ISEN1
ISEN2
ISEN3
ISEN4
IRTN1
IRTN2
IRTN3
IRTN4
48 47 46 45 44 43 42 41 40 39 38 37
RCSP 1 36 RCSP_L2
RCSM 2 35 RCSM_L2
VRDY2 3 34 VCC
CFP 4 33 VSEN_L2
VSEN 5 32 VRTN_L2
IR3565A
VRTN 6 31 PWM1_L2
48 Pin 6x6 QFN
RRES 7 30 PWM2_L2
Top View
TSEN1 8 29 PWM4
V18A 9 28 PWM3
PWRGD/
10 27 PWM2
VRDY1
PWROK/EN_L2/
11 26 PWM1
INMODE
49 GND
VINSEN 12 VGD/TSEN2/
25
VAUXSEN
13 14 15 16 17 18 19 20 21 22 23 24
NC
SVT/
SV_ALERT
SV_CLK/
VIDSEL1
VIDDIO/
SV_ADDR
SV_DIO/
VIDSEL0
VRHOT_ICRIT
EN
ADDR_PRO
T
SM_ALERT
SM_DIO
SM_CLK
NC
Figure 1: IR3565A Pin Diagram Enlarged
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Dual Output Digital Multi-Phase Controller
IR3565A
TYPICAL APPLICATION DIAGRAM
5V
V
12V
Boot CHL8505
RCSP Vcc HiGate V_CPU_L1
Switch
R series Vdrv
CCS L
RTh RCS PWM LoGate
GND O
A
R series PWM1 D
RCSM ISEN1
+3.3V IRTN1
VCC 5V
V
12V
IR3565A Boot
Vcc
CHL8505
HiGate
Switch
Vdrv
VSEN
PWM LoGate
VRTN GND
PWM2
RRES
ISEN2
IRTN2
TSEN1 5V
V
12V
RTh 2
Boot CHL8505
Vcc HiGate
Switch
Vdrv
V18A
PWM LoGate
GND
PWM3
ISEN3
TSEN2
IRTN3
12V RTh 3
R VIN _ 1
VINSEN 5V
V
12V
R VIN _ 2 VRDY1
Boot CHL8505
VRDY2 Vcc HiGate
Switch
Vdrv
CPU SVT/SV_ALERT PWM LoGate
Serial SV_DIO GND
V
PWM4
Bus SV_CLK
V
ISEN4
IRTN4
VRHOT_CRIT#
5V
V
From EN 12V
V
System PWROK/EN_L2/INMODE
V
Boot CHL8505
Vcc HiGate V_CPU_L2
Switch
VDDIO VDDIO/SV_ADDR Vdrv
Applicable circuit when pin is PWM LoGate L
GND O
configured as VDDIO only
PWM1_L2 A
SM_DIO D
V
ISEN1_L2
I2C Bus SM_CLK
V
IRTN1_L2
SM_ALERT#
V
5V
V
12V
RCSP_L2
R series Boot CHL8505
CCS Vcc HiGate
RTh RCS Switch
Vdrv
R series PWM LoGate
GND
RCSM_L2 PWM2_L2
ISEN2_L2
VSEN_L2
IRTN2_L2
VRTN_L2
ADDR_PROT
GND
Figure 2: Dual-loop VR using IR3565A Controller and CHL8505 MOSFET Drivers in 4+2 Configuration
3 www.irf.com | © 2013 International Rectifier | Product Brief | October 1, 2013 | V3.04
Dual Output Digital Multi-Phase Controller
IR3565A
Data and specifications subject to change without notice.
This product will be designed and qualified for the Consumer market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.
www.irf.com
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