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Commits on Jan 18, 2024

• Updated copyright to 2024

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  a104327

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Commits on Feb 23, 2023

• FIX: Auto test (hexbus) works again, -lpthreads

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  07ab145

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• Design builds again, -lpthread, but tests fail

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  8eabb2d

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• Upgraded copyrights to 2023

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  04f4637

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• Upgraded the bench memdev to arbitrary widths

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  6d125f3

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Commits on Dec 30, 2021

• Updated: HBExecAXI for blog post. All tests pass.

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  6105d5c

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Commits on Dec 4, 2021

• Upgraded components for better clarity and readability, vim folding

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  ba6b1e3

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Commits on Apr 2, 2020

• Removed broken port.h symlink, added cover checks to hbexecaxi

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  9a83c98

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Commits on Feb 25, 2020

• HBAXIL: an AXI-Lite implementation of the hexbus

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  4f50c37

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Commits on Jan 21, 2020

• Merge branch 'master' into dev

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  dbf2b57

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• Updated submodule files and copyright

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  6531a0b

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Commits on Jan 3, 2020

• Merge branch 'master' into dev

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  18da4d6

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• Pre-AutoFPGA update changes, hbbus arg order, AW param

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  e692e24

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Commits on Dec 30, 2019

• Draft AXI-lite hexbus driver

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  1b43c02

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Commits on Nov 28, 2019

• Merge pull request #2 from tocisz/master

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Commits on Nov 26, 2019

• Fix path to verilog file

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  2274ca5

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Commits on Nov 12, 2019

• Adds an automatic test for the dbgbus

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  645653d

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• Created an automatic test script

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  6f6b4e2

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Commits on Nov 7, 2019

• Fixed parameter setup, now using newer xuartlites

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  ce13934

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• Fixed the make clean failure

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  ce68fa6

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• Updated UART-lites to match WBUART

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  9afceee

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• Updated copyrights to current year

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  bb41368

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• Fixed the skynet bug in hbexec

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  43cf80d

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• Fixed a Verilator warning on hbbus, moved declarations to the top

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  a313742

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• Added (some) formal properties to the console.v

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  ee9b37b

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• Added a GTKWave trace configuration to the project

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  00e4f6a

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Commits on Nov 15, 2018

• Formal verification work for HEXBUS

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  660e6b8

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• Formally verified hexbus interrupts

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  d3f9f22

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Commits on May 11, 2018

• Updated UARTSIM to match wbuart32

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  fe6c419

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• Added throttling to the hexbus idle output, fixed a race condition in addr

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  4ef3250

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• Added a random access capability to the scope class

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• Added to wbregs the capability to connect to non-default network port

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Commits on Oct 4, 2017

• Made the baud rate in netuart (somewhat) adjustable)

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Commits on Aug 8, 2017

• Added MEM as a name for the RAM, to line up with the blog article

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  b113d44

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• Fixed a bug that kept the UARTSIM from closing the connection

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