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Currently, async support for SPI (and implementation of the embedded-hal-async traits) is dependent on CONFIG_SPI_MASTER_ISR_IN_IRAM being disabled:
Lines 570 to 571 in 4f44787
| #[cfg(not(esp_idf_spi_master_isr_in_iram))] | |
| pub async fn read_async(&mut self, words: &mut [u8]) -> Result<(), EspError> { |
There are two things:
- The crate documentation doesn't make this obvious at all. One has to dig into the source to figure out why
read_asyncand co aren't defined and figure out that it's a IDF setting. - Async SPI support should still be provided with the interrupt handler in IRAM.
The first point is pretty straightforward to address, but addressing the second would make that irrelevant - not sure how much effort the second point actually is.
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