AIInfra（AI 基础设施）指AI系统从底层芯片等硬件，到上层软件栈支持AI大模型训练和推理。

AISystem 主要是指AI系统，包括AI芯片、AI编译器、AI推理和训练框架等AI全栈底层技术

Robust Speech Recognition via Large-Scale Weak Supervision

Automatic Speech Recognition (ASR), Speaker Verification, Speech Synthesis, Text-to-Speech (TTS), Language Modelling, Singing Voice Synthesis (SVS), Voice Conversion (VC)

Timeloop performs modeling, mapping and code-generation for tensor algebra workloads on various accelerator architectures.

NeuroSpector: Dataflow and Mapping Optimizer for Deep Neural Network Accelerators

A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)

HW Architecture-Mapping Design Space Exploration Framework for Deep Learning Accelerators

A co-design architecture on sparse attention

Processing-In-Memory (PIM) Simulator

A large-scale simulation framework for LLM inference

SHMT for MICRO 2023

DRAMsim3: a Cycle-accurate, Thermal-Capable DRAM Simulator

NeuPIMs: NPU-PIM Heterogeneous Acceleration for Batched LLM Inferencing

Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore designs

Writing AI Conference Papers: A Handbook for Beginners

🚀 Awesome System for Machine Learning ⚡️ AI System Papers and Industry Practice. ⚡️ System for Machine Learning, LLM (Large Language Model), GenAI (Generative AI). 🍻 OSDI, NSDI, SIGCOMM, SoCC, MLSy…

Awesome Lists for Tenure-Track Assistant Professors and PhD students. (助理教授/博士生生存指南)

MLIR For Beginners tutorial

A list of tutorials, paper, talks, and open-source projects for emerging compiler and architecture

compiler learning resources collect.

A 32-bit RISC-V Processor Designed with High-Level Synthesis

RISC-V ISA based 32-bit processor written in HLS

Repository to host and maintain SCALE-Sim code

An Open-Source SCAlable Interface for ISA Extensionsfor RISC-V Processors. New Version: