diff --git a/src/acpi/spcr/spcr.c b/src/acpi/spcr/spcr.c
index 1d865a3e..fe297c88 100644
--- a/src/acpi/spcr/spcr.c
+++ b/src/acpi/spcr/spcr.c
@@ -100,16 +100,42 @@ static int spcr_test1(fwts_framework *fw)
 		str = "16550 compatible";
 		break;
 	case 0x01:
-		str = "16450 compatible";
+		str = "16550 subset compatible with DBGP Revision 1";
+		break;
+	case 0x02:
+		str = "MAX311xE SPI UART";
 		break;
 	case 0x03:
 		str = "ARM PL011 UART";
 		break;
-	case 0x02:
-	case 0x04 ... 0x0c:
+	case 0x04:
+		str = "MSM8x60 (e.g. 8960)";
+		break;
+	case 0x05:
+		str = "Nvidia 16550";
+		break;
+	case 0x06:
+		str = "TI OMAP";
+		break;
+	case 0x07:
 		str = "Reserved (Do not Use)";
 		reserved = true;
 		break;
+	case 0x08:
+		str = "APM88xxxx";
+		break;
+	case 0x09:
+		str = "MSM8974";
+		break;
+	case 0x0a:
+		str = "SAM5250";
+		break;
+	case 0x0b:
+		str = "Intel USIF";
+		break;
+	case 0x0c:
+		str = "i.MX6";
+		break;
 	case 0x0d:
 		str = "(deprecated) ARM SBSA";
 		break;
@@ -122,6 +148,21 @@ static int spcr_test1(fwts_framework *fw)
 	case 0x10:
 		str = "BCM2835";
 		break;
+	case 0x11:
+		str = "SDM845 with clock rate of 1.8432 MHz";
+		break;
+	case 0x12:
+		str = "16550-compatible with parameters defined in Generic Address Structure";
+		break;
+	case 0x13:
+		str = "SDM845 with clock rate of 7.372 MHz";
+		break;
+	case 0x14:
+		str = "Intel LPSS";
+		break;
+	case 0x15:
+		str = "RISC-V SBI console (any supported SBI mechanism)";
+		break;
 	default:
 		str = "Reserved";
 		reserved = true;
@@ -140,12 +181,6 @@ static int spcr_test1(fwts_framework *fw)
 	reserved1 = spcr->reserved1[0] + (spcr->reserved1[1] << 8) + (spcr->reserved1[2] << 16);
 	fwts_acpi_reserved_zero("SPCR", "Reserved1", reserved1, &passed);
 
-	if (spcr->interrupt_type == 0) {
-		passed = false;
-		fwts_failed(fw, LOG_LEVEL_HIGH,
-			"SPCRUnknownInterruptType",
-			"SPCR interrupt type field is zero, expecting support bits to be set");
-	}
 	if (spcr->interrupt_type & 0xf0) {
 		passed = false;
 		fwts_failed(fw, LOG_LEVEL_HIGH,
diff --git a/src/lib/include/fwts_cpu.h b/src/lib/include/fwts_cpu.h
index f5f66108..b023c5e3 100644
--- a/src/lib/include/fwts_cpu.h
+++ b/src/lib/include/fwts_cpu.h
@@ -63,7 +63,7 @@ int fwts_cpu_is_Intel(bool *is_intel);
 int fwts_cpu_is_AMD(bool *is_amd);
 int fwts_cpu_is_Hygon(bool *is_hygon);
 
-int fwts_cpu_has_c1e(void);
+fwts_bool fwts_cpu_has_c1e(void);
 fwts_cpuinfo_x86 *fwts_cpu_get_info(const int which_cpu);
 void fwts_cpu_free_info(fwts_cpuinfo_x86 *cpu);
 
diff --git a/src/lib/include/fwts_memorymap.h b/src/lib/include/fwts_memorymap.h
index f79113b9..b2a39705 100644
--- a/src/lib/include/fwts_memorymap.h
+++ b/src/lib/include/fwts_memorymap.h
@@ -38,7 +38,7 @@ typedef struct {
 } fwts_memory_map_entry;
 
 int        fwts_memory_map_type(fwts_list *memory_map_list, const uint64_t memory);
-int        fwts_memory_map_is_reserved(fwts_list *memory_map_list, const uint64_t memory);
+fwts_bool  fwts_memory_map_is_reserved(fwts_list *memory_map_list, const uint64_t memory);
 fwts_list *fwts_memory_map_table_load(fwts_framework *fw);
 void       fwts_memory_map_table_free(fwts_list *memory_map_list);
 void       fwts_memory_map_table_dump(fwts_framework *fw, fwts_list *memory_map_list);