I've been testing the LF sim functions to see why they are so erratic as to their functionality.
I believe it comes down to the use of the clock in SimulateTagLowFrequency.
could someone explain what GPIO_SSC_CLK measures?

let me illustrate the issue:
a standard HID FSK2a tag should have waves 10 samples and 8 samples long depending on whether it is bit 1 or bit 0. so digitally it should be 1111100000 and 11110000.

if this is sent through the SimulateTagLowFrequncy the output has 2 errors.

1. the number of samples have lengthened to 11111110000000 and 11111000000
   so our clock is too slow
2. if you compensate for by reducing the bits sent to the function then the second issue becomes obvious: the transition between bit 1s and bit 0s creates extra 0 waves.
   So going from 1111000011110000 to 1111100000 translates 11110000001111100000 (added 2 extra 0 bits)

img1: bad timing:

img2: bad transition:

any thoughts?

I can get ASK clocks of 32 or greater to work fine but the lower the clock the worse this affects things.