diff --git a/protos/circuit.proto b/protos/circuit.proto
index 3989c4e..7a19128 100644
--- a/protos/circuit.proto
+++ b/protos/circuit.proto
@@ -6,19 +6,6 @@ syntax = "proto3";
 package vlsir.circuit;
 import "utils.proto";
 
-// # Package
-// A Collection of Modules and ExternalModules
-message Package {
-  // Domain Name
-  string domain = 1;
-  // `Module` Definitions
-  repeated Module modules = 2;
-  // `ExternalModule` interfaces used by `modules`, and available externally
-  repeated ExternalModule ext_modules = 3;
-  // Description
-  string desc = 10;
-}
-
 // # Port
 // An externally-visible `Signal` with a `Direction`.
 message Port {
@@ -130,7 +117,6 @@ enum SpiceType {
 // Primarily for sake of port-ordering, for translation with connect-by-position
 // formats.
 message ExternalModule {
-
   // Qualified External Module Name
   vlsir.utils.QualifiedName name = 1;
   // Description
@@ -145,12 +131,3 @@ message ExternalModule {
   // Spice Type, SUBCKT by default
   SpiceType spicetype = 6;
 }
-
-// # Interface
-// Defines the logical IO of a `Module`
-message Interface {
-  // Cell Name
-  string name = 1;
-  // Port List
-  repeated Port ports = 10;
-}
\ No newline at end of file
diff --git a/protos/layout/raw.proto b/protos/layout.proto
similarity index 83%
rename from protos/layout/raw.proto
rename to protos/layout.proto
index 54c2a72..8411cfa 100644
--- a/protos/layout/raw.proto
+++ b/protos/layout.proto
@@ -6,11 +6,9 @@
 //! 
 
 syntax = "proto3";
-package vlsir.raw;
+package vlsir.layout;
 
 import "utils.proto";
-import "circuit.proto";
-
 
 // # Point
 // An (x,y) point in Cartesian layout space.
@@ -23,7 +21,6 @@ message Point {
 enum Units {
   MICRO = 0;
   NANO = 1;
-  ANGSTROM = 2;
 }
 
 // # Layer-Purpose Pair 
@@ -147,33 +144,3 @@ message AbstractPort {
   repeated LayerShapes shapes = 2; 
 }
 
-// # Cell 
-// A multi-view representation of a piece of hardware.
-message Cell {
-  // Cell Name
-  string name = 1;
-
-  // IO Interface
-  vlsir.circuit.Interface interface = 10;
-  // Circuit Module 
-  vlsir.circuit.Module module = 11;
-  // Physical Abstract
-  Abstract abstract = 12;
-  // Physical Layout Implementation
-  Layout layout = 13;
-}
-
-// # Library 
-// A collection of cells and asssociated meta-data. 
-message Library {
-  // Library Name / Domain 
-  string domain = 1;
-  // Distance Units
-  Units units = 2; 
-  // Cell Definitions
-  repeated Cell cells = 10;
-
-  // Author Information 
-  vlsir.utils.AuthorMetadata author = 20;
-} 
-
diff --git a/protos/layout/tetris.proto b/protos/layout/tetris.proto
deleted file mode 100644
index 0c1e749..0000000
--- a/protos/layout/tetris.proto
+++ /dev/null
@@ -1,374 +0,0 @@
-
-//! 
-//! # vlsir "Tetris" Gridded Layout Schema 
-//! 
-//! 
-
-syntax = "proto3";
-package vlsir.tetris;
-
-import "utils.proto";
-import "layout/raw.proto";
-import "circuit.proto";
-
-
-// # Library 
-// 
-// A collection of `Cells` and asssociated metadata. 
-// Primary data in the `cells` field is valid only if stored in dependency order, 
-// i.e. that each cell-definition must follow all cells that it depends upon. 
-// 
-message Library {
-  // Library Name / Domain 
-  string domain = 1; 
-
-  // Cell Definitions
-  repeated Cell cells = 10; 
-
-  // Author Information 
-  vlsir.utils.AuthorMetadata author = 20;
-}
-
-// # Cell 
-// A multi-view representation of a piece of hardware.
-message Cell {
-  // Cell Name
-  string name = 1;
-
-  // IO Interface
-  vlsir.circuit.Interface interface = 10;
-  // Circuit Module Definition 
-  vlsir.circuit.Module module = 11;
-  // Physical Abstract
-  Abstract abstract = 12;
-  // Physical Layout Implementation
-  Layout layout = 13;
-}
-
-// # Layout 
-// 
-// Physical implementation of a `Cell`. Tetris layouts consist of: 
-// * `Instances` of other `Cells`, 
-// * Net-assignments at grid crossings, and 
-// * Cuts of the grid 
-// (That's all.) 
-// 
-// `Layouts` have an explicit `Outline`, in which all their attributes must fit, 
-// and into which no other `Layout` can encroach. 
-// This operates similarly to "blockage" on all layers in legacy layout systems. 
-// 
-message Layout {
-  // Cell Name
-  string name = 1;
-  // Outline 
-  Outline outline = 10;
-  // Layout Instances
-  repeated Instance instances = 20;
-  // Net-to-track assignments
-  repeated Assign assignments = 21;
-  // Track cuts
-  repeated TrackCross cuts = 22;
-}
-
-// # Assignment 
-// 
-// Assigns signal `net` to the two tracks crossing in location `at`. 
-// Tetris signal-assignments are to track-crosses. 
-// This operates much like assigning to a via, plus the tracks above and below. 
-message Assign {
-  // Net Name
-  string net = 1;
-  // Location
-  TrackCross at = 2;
-}
-
-// # Track Cross
-// Crossing between two `TrackRefs`
-message TrackCross {
-  // "Primary" Track
-  TrackRef track = 1;
-  // Intersection location, on an orthogonal layer
-  TrackRef cross = 2;
-}
-
-// # Track Reference
-// Integer-pair pointer to a layer-index and track-index 
-message TrackRef {
-  // Layer Index
-  int64 layer = 1;
-  // Track Index
-  int64 track = 2;
-}
-
-// # Cell Outlines
-// ## "Tetris Shaped" rectilinear polygons
-//
-// These boundaries are closed, consist solely of 90-degree rectangular turns,
-// and are specified by a counter-clockwise set of points.
-// "Holes" such as the shapes "O" and "8" and "divots" such as the shapes "U" and "H" are not supported.
-// The z-axis top is uniform and specified by a single layer-index `top_layer`. 
-//
-// Two equal-length vectors `x` and `y` describe an Outline's (x, y) points.
-// Counter-clockwise-ness and divot-free-ness requires that:
-// * (a) `x` values are monotonically non-increasing, and
-// * (b) `y` values are monotonically non-decreasing
-//
-// In point-space terms, such an outline has vertices at:
-// `[(0,0), (x[0], 0), (x[0], y[0]), (x[1], y[0]), ... , (0, y[-1]), (0,0)]`
-// With the final point at (0, y[-1]), and its connection back to the origin both implied.
-//
-// Example: a rectangular Outline would require a single entry for each of `x` and `y`,
-// at the rectangle's vertex opposite the origin in both axes.
-//
-message Outline {
-  // X Coordinates
-  repeated int64 x = 1;
-  // Y Coordinates
-  repeated int64 y = 2;
-  // Number of metal layers used 
-  int64 metals = 3;
-}
-
-// # Abstract Layout 
-// 
-// Defines the physical interface to a [Cell], including ports and internal blockages, 
-// omitting internal implementation details.
-message Abstract {
-  // Cell Name
-  string name = 1;
-  // Outline 
-  Outline outline = 10;
-  // Ports 
-  repeated AbstractPort ports = 20; 
-}
-
-// # Abstract Port
-// Combination of a net and set of shapes
-message AbstractPort {
-  // Port Name
-  string net = 1;
-
-  // Enumerated port types
-  oneof kind {
-    // Edge 
-    EdgePort edge = 10;
-    // Z-Top, at Edge 
-    ZTopEdgePort ztop_edge = 11;
-    // Z-Top, inside Outline 
-    ZTopInner ztop_inner = 12;
-  }
-  
-  // # Edge Port
-  // On a layer less than `top_layer`. Only connectable on its `track` and `side`.
-  message EdgePort { 
-    TrackRef track = 1;
-    PortSide side = 2;
-  }
-  // # Z-Top, on Edge Port
-  // Can be connected from either `top_layer+1`, or the edge on `top_layer`. 
-  message ZTopEdgePort { 
-    // Track index
-    int64 track = 1;
-    // Side
-    PortSide side = 2;
-    // Extent into the cell. 
-    // Must be a location which intersects with (track, Side) inside the Outline.
-    TrackRef into = 3;
-  }
-  // # Z-Top, inside Outline Port
-  message ZTopInner { 
-    // Locations. All must be on layers adjacent to the top-layer.
-    repeated TrackCross locs = 1;
-  }
-  
-  // # Abstract Port Side 
-  // 
-  // A two-value enum, as each layer either runs horizontally or vertically. 
-  // Ports on the nearer-origin (bottom or left) sides use variant `BOTTOM_OR_LEFT`, 
-  // while ports on the opposite sides use `TOP_OR_RIGHT`. 
-  enum PortSide {
-    BOTTOM_OR_LEFT = 0;
-    TOP_OR_RIGHT = 1;
-  }
-}
-
-// # Cell Instance
-message Instance {
-  // Instance Name
-  string name = 1;
-  // Cell Reference
-  vlsir.utils.Reference cell = 3;
-  
-  // Location of the defined Cell's origin 
-  // this location holds regardless of reflection settings.
-  Place loc = 4; 
-  // Horizontal reflection about y-axis
-  bool reflect_horiz = 6;
-  // Vertical reflection about x-axis
-  bool reflect_vert = 7;
-}
-
-// # Place 
-// An absolute or relative placement description
-message Place {
-  oneof place {
-    // Absolute 
-    vlsir.raw.Point abs = 1;
-    // Relative 
-    RelPlace rel = 2;
-  }
-}
-
-// # Relative Place
-message RelPlace { } 
-
-
-
-// # Stack
-//
-// The z-stack, primarily including metal, via, and primitive layers
-message Stack {
-    // Measurement units
-    vlsir.raw.Units units = 1;
-    // Primitive Layer
-    PrimitiveLayer prim = 2;
-    // Set of metal layers
-    repeated MetalLayer metals = 3;
-    // Set of via layers
-    repeated ViaLayer vias = 4;
-
-    // [raw::Layer] Mappings
-    // vlsir.raw.Layers rawlayers = 1;
-    // Layer used for cell outlines/ boundaries
-    vlsir.raw.Layer boundary_layer = 11;
-}
-
-// # LayerEnum 
-// 
-// Type and index of a layer.
-// 
-message LayerEnum {
-  enum LayerType {
-    PRIMITIVE = 0;
-    METAL = 1;
-    VIA = 2;
-  }
-
-  // Layer Type
-  LayerType type = 1;
-  // Index into the associated `LayerType` set 
-  int64 index = 2;
-}
-
-// # MetalLayer
-//
-// Metal layer in a [Stack]
-// Each layer is effectively infinite-spanning in one dimension, and periodic in the other.
-// Layers with `dir=Dir::Horiz` extend to infinity in x, and repeat in y, and vice-versa.
-//
-message MetalLayer {
-  // Direction Enumeration 
-  enum Dir {
-    HORIZ = 0;
-    VERT = 1;
-  }
-  // Ownership split of a layer between Primitives and the Stack. 
-  enum PrimitiveMode {
-    PRIM = 0;   // Owned by Primitives 
-    SPLIT = 1;  // Split between Primitives and the Stack 
-    STACK = 2;  // Owned by the Stack 
-  }
-    // Layer Name
-    string name = 1;
-    // Direction Enumeration (Horizontal/ Vertical)
-    Dir dir = 2;
-    // Default size of wire-cuts
-    int64 cutsize = 3;
-    // Track Size & Type Entries
-    repeated TrackSpec entries = 4;
-    // Offset, in our periodic dimension
-    int64 offset = 5;
-    // Overlap between periods
-    int64 overlap = 6;
-    // Setting for period-by-period flipping
-    bool flip = 7;
-    // Primitive-layer relationship
-    PrimitiveMode prim = 8;
-    // Raw Layer
-    vlsir.raw.Layer raw = 11;
-}
-
-
-// # ViaLayer
-// 
-// Insulator and connector Layer Between `MetalLayers`
-message ViaLayer {
-    // Layer name
-    string name = 1;
-    // Top of the two layers connected by this layer
-    LayerEnum top = 2;
-    // Bottom of the two layers connected by this layer
-    LayerEnum bot = 3;
-    // Via size
-    Xy size = 4;
-    // Raw Layer
-    vlsir.raw.Layer raw = 11;
-}
-
-// # Primitive Layer
-// 
-// Encapsulates all layout information "below" an associated `Stack`.
-// In typical process technologies this primarily includes "base layers", 
-// such as those used in primitive transistors and logic cells. 
-message PrimitiveLayer {
-  // Pitches, in Database Units
-  Xy pitches = 1;
-}
-
-// # Track Specification 
-// 
-// Includes definitions for the single `TrackEntry`
-// and repitition thereof (`Repeat`). 
-// Sole field `spec` is one of the two. 
-// 
-message TrackSpec {
-  message TrackEntry {
-    enum TrackType {
-      GAP = 0; // Insulator Gap
-      SIGNAL = 1; // Signal Track
-      RAIL = 2; // Rail Track. FIXME: Add rail type. 
-    }
-    // TrackType
-    TrackType ttype = 1;
-    // Entry width 
-    int64 width = 2;
-  }
-
-  // Repeated Pattern of Track Entries
-  message Repeat {
-    // List of entries
-    repeated TrackEntry entries = 1;
-    // Number of repetitions 
-    int64 nrep = 2;
-}
-
-  // Sole internal field: either an entry or repetition thereof 
-  oneof spec {
-    // Single Entry 
-    TrackEntry entry = 1;
-    // Repetition 
-    Repeat repeat = 2; 
-  }
-}
-
-// # Xy 
-// 
-// Two-dimensional (x,y) pair. 
-// While similar in content to `vlsir.raw.Point`, `Xy` data does not semantically 
-// (necessarily) refer to a single point in Cartesian space. 
-// More general use-cases include the size of blocks, or the pitch of a grid.
-message Xy {
-  int64 x = 1;
-  int64 y = 2;
-}
-
diff --git a/protos/library.proto b/protos/library.proto
new file mode 100644
index 0000000..cebaff4
--- /dev/null
+++ b/protos/library.proto
@@ -0,0 +1,59 @@
+syntax = "proto3";
+package vlsir.library;
+
+import "utils.proto";
+import "circuit.proto";
+import "layout.proto";
+
+// # Cell 
+// A multi-view representation of a piece of hardware.
+message Cell {
+  // Cell Name. Serves as the default name for things in this tree, but can be
+  // overidden by the 'name' fields in child Modules and Layouts. 
+  string name = 1;
+
+  // ExternalModule describes the IO Interface to this cell's Module.
+  vlsir.circuit.ExternalModule module_abstract = 10;
+
+  // Circuit Module 
+  vlsir.circuit.Module module = 11;
+
+  // Physical Abstract
+  vlsir.layout.Abstract layout_abstract = 12;
+
+  // Physical Layout Implementation
+  vlsir.layout.Layout layout = 13;
+}
+
+message ExternalCell {
+  // Fully qualified cell name.
+  vlsir.utils.QualifiedName name = 1;
+
+  // ExternalModule describes the IO Interface to this cell's Module.
+  vlsir.circuit.ExternalModule module_abstract = 10;
+
+  // Physical Abstract
+  vlsir.layout.Abstract layout_abstract = 20;
+}
+
+// # Library
+// A Collection of Modules and ExternalModules
+message Library {
+  // Domain Name
+  string domain = 1;
+
+  // Distance Units Prefix (of Meters)
+  vlsir.utils.SIPrefix layout_units = 2; 
+
+  // Cell Definitions
+  repeated Cell cells = 10;
+
+  // `ExternalModule` interfaces used by `modules`, and available externally
+  repeated ExternalCell externals = 20;
+
+  // Description
+  string desc = 30;
+
+  // Author Information 
+  vlsir.utils.AuthorMetadata author = 40;
+}
diff --git a/protos/spice.proto b/protos/spice.proto
index fdbb75a..86c5065 100644
--- a/protos/spice.proto
+++ b/protos/spice.proto
@@ -31,7 +31,7 @@ package vlsir.spice;
 
 // Local Imports
 import "utils.proto";
-import "circuit.proto";
+import "library.proto";
 
 // ############################################################################
 // # `Spice` Simulator API
@@ -57,7 +57,7 @@ service Spice {
 message SimInput {
   // # Circuit Input 
   // The DUT circuit-package under test 
-  vlsir.circuit.Package pkg = 1;
+  vlsir.library.Library pkg = 1;
   // Top-level module (name)
   string top = 2;
 
diff --git a/protos/tech.proto b/protos/tech.proto
index a7307d1..8a4f590 100644
--- a/protos/tech.proto
+++ b/protos/tech.proto
@@ -1,13 +1,16 @@
 syntax = "proto3";
 
+import "library.proto";
+
 package vlsir.tech;
 
 message Technology {
   // Skywater130, S130, Sky130, etc
   string name = 1;
   
-  repeated Package packages = 11;
+  repeated vlsir.library.Library libraries = 11;
 
+  // TODO: move to LayoutConcernsTypeThing message
   repeated LayerInfo layers = 101;
 }
 
@@ -16,6 +19,12 @@ message Package {
   string name = 1;
 
   // Other package-specific stuff goes here.
+
+  // TODO:
+  //  - container message for circuit (incl. simulation) concerns
+  //  - container message for layout concerns
+  // optional vlsir.library.Library package = 10;
+
 }
 
 enum LayerPurposeType {
diff --git a/protos/utils.proto b/protos/utils.proto
index 84069d3..8a56e14 100644
--- a/protos/utils.proto
+++ b/protos/utils.proto
@@ -92,21 +92,6 @@ message Reference {
   }
 }
 
-// # Library Metadata
-//
-// Summary information about any of several categories of `Library`, including:
-// * Library domain
-// * (String) cell names
-// * Author information
-message LibraryMetadata {
-  // Library Name / Domain
-  string domain = 1;
-  // Cell Names
-  repeated string cell_names = 10;
-  // Author Information
-  AuthorMetadata author = 20;
-}
-
 // # Authorship Metadata
 //
 // Summary information regarding authorship, ownership, and licensing