Verilator open-source SystemVerilog simulator and lint system

Visualizer for neural network, deep learning and machine learning models

The state-of-the-art image restoration model without nonlinear activation functions.

向发起人致敬 https://github.com/WorkerLivesMatter/WorkingTime

SuperGlue: Learning Feature Matching with Graph Neural Networks (CVPR 2020, Oral)

This is originally a collection of papers on neural network accelerators. Now it's more like my selection of research on deep learning and computer architecture.

collection of works aiming at reducing model sizes or the ASIC/FPGA accelerator for machine learning

An HLS based winograd systolic CNN accelerator

A Winograd based kernel for convolutions in deep learning framework

An OpenCL-Based FPGA Accelerator for Compressed YOLOv2

A demo for accelerating YOLOv2 in xilinx's fpga pynq/zedboard

implementation of winograd minimal convolution algorithm on Intel Architecture

This is an HLS-based FPGA accelerator implementation for openpose application.

Codes to implement MobileNet V2 in a FPGA

🐵 自用的一些乱七八糟 油猴脚本~

Convolutional Autoencoder for Loop Closure

FPGA-based neural network inference project for 2020 DAC System Design Contest

The second place winner for DAC-SDC 2020

XJTU-Tripler is based on HiPU100, an FPGA-friendly DNN accelerator, developed by CAG, Institute of AI & Robotics, XJTU.

The 1st place winner's source codes for DAC 2018 System Design Contest, FPGA Track

CNN (PSPNet) + ORB_SLAM2 语义SLAM Real time semantic slam in ROS with a hand held RGB-D camera

机器人视觉 移动机器人 VS-SLAM ORB-SLAM2 深度学习目标检测 yolov3 行为检测 opencv PCL 机器学习 无人驾驶

An OpenCL-based FPGA Accelerator for Convolutional Neural Networks

Light-weighted neural network inference for object detection on small-scale FPGA board

edition 2 of the slambook

Setup and customize deep learning environment in seconds.