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Commits on Jan 8, 2022

• point to gitlab repos

  sbourdeauducq

  authored
  6c5afdc

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Commits on Jan 22, 2021

• Fix broken timing constraints

  

  slan

  authored and

  sbourdeauducq

  committed
  4a59d5d

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Commits on Sep 19, 2020

• Add option to specify spec_name

  

  DonaldKellett

  authored and

  sbourdeauducq

  committed
  39602ae

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Commits on Aug 19, 2020

• Clifford -> Claire

  sbourdeauducq

  committed
  1ad6e32

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• Add option to specify solver in nmigen.test.utils

  

  Donald Sebastian Leung

  authored and

  sbourdeauducq

  committed
  40f7f12

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Commits on Mar 14, 2020

• rm travis-ci

  sbourdeauducq

  committed
  8f5a253

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• Revert "setup: update project URLs."

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  sbourdeauducq

  committed
  63a53fa

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• Merge remote-tracking branch 'wq/master'

  sbourdeauducq

  committed
  b2d924e

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Commits on Mar 12, 2020

• vendor: fix a few issues in commit 2f8669ca.

  

  whitequark

  committed
  12c7902

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Commits on Mar 8, 2020

• lib.cdc: extract AsyncFFSynchronizer.

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  awygle

  authored
  2f8669c

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Commits on Feb 19, 2020

• hdl.ast: fix off-by-1 in Initial.__init__().

  

  whitequark

  committed
  a14a572

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• back.pysim: fix RHS codegen for Cat() and Repl(..., 0).

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  whitequark

  committed
  ec7aee6

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• back.pysim: optionally allow introspecting generated code.

  

  whitequark

  committed
  377f2d9

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Commits on Feb 16, 2020

• nmigen.compat.genlib.cdc: add PulseSynchronizer.

  awygle

  authored
  5ae8791

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• nmigen.lib.cdc: port PulseSynchronizer.

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  awygle

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  Wren6991

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  fcbabfe

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Commits on Feb 14, 2020

• Travis: prune dependencies.

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  whitequark

  committed
  71d9eea

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• Travis: test on Python 3.8.

  

  whitequark

  committed
  3fd7fe7

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Commits on Feb 12, 2020

• cli: update use of deprecated code.

  

  whitequark

  committed
  57b08db

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• back.pysim: accept write_vcd(vcd_file=None).

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  whitequark

  committed
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Commits on Feb 9, 2020

• setup: update project URLs.

  

  whitequark

  committed
  38aa9fb

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• doc: remove outdated files and references to them.

  

  whitequark

  committed
  4f17cb1

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Commits on Feb 8, 2020

• README: link to IRC channel.

  

  whitequark

  committed
  66f4510

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• README: consolidate requirements in the Installation section.

  

  whitequark

  committed
  36f498e

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Commits on Feb 7, 2020

• test_build_res: fix after commit 3e2ecdf2.

  

  whitequark

  committed
  3b67271

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Commits on Feb 6, 2020

• build.res,vendor: place clock constraint on port, not net, if possible.

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  whitequark

  committed
  3e2ecdf

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• xilinx_{7series,ultrascale}: run `report_methodology`.

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  whitequark

  committed
  5888f29

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• hdl.ast: add Value.{as_signed,as_unsigned}.

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  whitequark

  committed
  27b47fa

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• test_lib_fifo: define all referenced FSM states.

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  whitequark

  committed
  9301e31

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• hdl.dsl: make referencing undefined FSM states an error.

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  whitequark

  committed
  a1c5863

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• hdl.ir: type check ports.

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  whitequark

  committed
  97cc78a

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• back.pysim: emit toplevel inputs in VCD files as well.

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  whitequark

  committed
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• back.pysim: make `write_vcd(traces=)` actually use those traces.

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  whitequark

  committed
  d3775ee

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• hdl.dsl: reject name mismatch in `m.domains.<name> +=`.

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  whitequark

  committed
  3df4297

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• hdl.dsl: type check when adding to m.domains.

  

  whitequark

  committed
  86b57fe

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• hdl.mem: add synthesis attribute support.

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  whitequark

  committed
  31cd72c

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