NoC-Verilog

This project provides an open-source Verilog implementation for Network-on-Chip (NoC), enabling experimental studies.

Name		Name	Last commit message	Last commit date
Latest commit History 3 Commits
Buffer.v		Buffer.v
Counter.v		Counter.v
CrossBar.v		CrossBar.v
Network.v		Network.v
Output_Buffer_availablity.v		Output_Buffer_availablity.v
Packet_gen.v		Packet_gen.v
Packet_rec.v		Packet_rec.v
Process_Node.v		Process_Node.v
README.md		README.md
Route_Func.v		Route_Func.v
Router.v		Router.v
ST.v		ST.v
ST_Controler.v		ST_Controler.v
S_Alloc.v		S_Alloc.v
Select_gen.v		Select_gen.v
Test.v		Test.v
VC_Alloc.v		VC_Alloc.v
input_Unit.v		input_Unit.v
out_en_gen.v		out_en_gen.v
output_unit.v		output_unit.v
set_Alloc.v		set_Alloc.v

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