Add support for TH1520 SoC #756

kanakshilledar · 2024-09-26T15:59:35Z

TH1520 is a RISCV SoC from Alibaba T-Head. It has four C910 cores.

Few boards using this SoC are:

Beagle V Ahead
Milk-V Meles
LicheePi 4A

orangecms · 2024-09-26T16:19:44Z

reference boot log:
https://gist.github.com/kanakshilledar/04cf07c27fea8de2381760707b29fe3d

orangecms · 2024-09-27T21:11:37Z

We're now at

 TrainedVREFDQ_RANK0  : 1a
 TrainedVREFDQ_RANK1  : 1a
 RxClkDly_Margin_A0   : 0d
 VrefDac_Margin_A0    : 19
 TxDqDly_Margin_A0    : 0b
 DeviceVref_Margin_A0 : 1a
 RxClkDly_Margin_A1   : 0c
 VrefDac_Margin_A1    : 18
 TxDqDly_Margin_A1    : 0b
 DeviceVref_Margin_A1 : 1a
 TrainedVREFDQ_RANK0  : 18
 TrainedVREFDQ_RANK1  : 18
 RxClkDly_Margin_A0   : 0c
 VrefDac_Margin_A0    : 17
 TxDqDly_Margin_A0    : 0b
 DeviceVref_Margin_A0 : 18
 RxClkDly_Margin_A1   : 0c
 VrefDac_Margin_A1    : 17
 TxDqDly_Margin_A1    : 0c
 DeviceVref_Margin_A1 : 18
 [+] lp4_phy_train1d2d Complete...

kanakshilledar · 2024-09-30T10:38:39Z

We are currently at
WIP

DeviceVref_Margin_A1 : 18
PHY0 P Code 0
PHY0 N Code 0
PllCtrl1 is 0
PllCtrl2 is 0
PllCtrl4 is 0
PllTestmode is 0
Trained DB0 DFIMRL is 0
Trained DB1 DFIMRL is 0
Trained DB2 DFIMRL is 0
Trained DB3 DFIMRL is 0
DQS Preamble is 0
ARdPtrInitVal is 0
PHY0 DB0 VREF        is 0
PHY0 DB1 VREF        is 0
PHY0 DB2 VREF        is 0
PHY0 DB3 VREF        is 0
R0 TxDQSDly        is 0
R0 TxDQSDly        is 0
R1 TxDQSDly        is 0
R1 TxDQSDly        is 0
PHY1 P Code 0
PHY1 N Code 0
[+] lp4_phy_train1d2d Complete...

codecov · 2024-10-05T15:01:26Z

Codecov Report

Attention: Patch coverage is 0% with 33 lines in your changes missing coverage. Please review.

Project coverage is 0.20%. Comparing base (37a5e71) to head (9f5eff1).
Report is 10 commits behind head on main.

Files with missing lines	Patch %	Lines
src/mainboard/milk-v/meles/bt0/src/uart.rs	0.00%	21 Missing ⚠️
src/mainboard/milk-v/meles/bt0/src/main.rs	0.00%	12 Missing ⚠️

Additional details and impacted files

@@           Coverage Diff            @@
##            main    #756      +/-   ##
========================================
- Coverage   0.21%   0.20%   -0.01%     
========================================
  Files         22      25       +3     
  Lines        931     966      +35     
========================================
  Hits           2       2              
- Misses       929     964      +35

☔ View full report in Codecov by Sentry.
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orangecms · 2024-12-08T00:42:19Z

https://mastodon.social/@CyReVolt/113614408539014507

DRAM test now passes :)

orangecms · 2024-12-08T23:13:03Z

More extensive tests are showing some issues, still.
https://mastodon.social/@CyReVolt/113617971468084828

Signed-off-by: Daniel Maslowski <[email protected]> Signed-off-by: Kanak Shilledar <[email protected]>

this commit has a few functions which help in dram initialization. this is currently WORK IN PROGRESS. added clock initialization `sys_clk_config()`. board not yet tested after clock initialization. on testing on the board. the board seems to crash after entering the `pll_config()` function. exactly at L#166. more debugging required. Signed-off-by: Kanak Shilledar <[email protected]>

audio and other clocks were removed from sys_clk_config() fixed the board crashing in the pll_config() and deassert_pwrok_apb() due to some of the register write operations used a different method for writing the values which was missed durin the initial porting. Signed-off-by: Kanak Shilledar <[email protected]>

TODO: drop this commit in future Signed-off-by: Kanak Shilledar <[email protected]>

added pre training configs and setup. created a helper function to write 16 bit data required from writing to some registers. Signed-off-by: Kanak Shilledar <[email protected]>

dram training data is added along with a few helper functions output of phase1 training matches to the uboot data. phase2 training started but the output is 0 when i try to print some of the values from the registers. the uboot code prints some data corresponding to those registers but oreboot prints nothing just 0 for all. Signed-off-by: Kanak Shilledar <[email protected]>

changed the default code formatter in Rust Rover to rustfmt also changed the file format from CRLF to LF Signed-off-by: Kanak Shilledar <[email protected]>

Signed-off-by: Daniel Maslowski <[email protected]> Signed-off-by: Kanak Shilledar <[email protected]>

This looks like a dummy in the original C code, though reading from MMIO registers may actually have side effects in hardware. Signed-off-by: Daniel Maslowski <[email protected]> Signed-off-by: Kanak Shilledar <[email protected]>

Signed-off-by: Daniel Maslowski <[email protected]> Signed-off-by: Kanak Shilledar <[email protected]>

If you really want to, pass your custom command: make FASTBOOT='sudo fastboot' run Signed-off-by: Daniel Maslowski <[email protected]> Signed-off-by: Kanak Shilledar <[email protected]>

Signed-off-by: Daniel Maslowski <[email protected]> Signed-off-by: Kanak Shilledar <[email protected]>

this function was yet to be implemented required for `lpddr_init()` still the DRAM test is not passing :( Signed-off-by: Kanak Shilledar <[email protected]>

Signed-off-by: Daniel Maslowski <[email protected]> Signed-off-by: Kanak Shilledar <[email protected]>

…_DCH1 Signed-off-by: Daniel Maslowski <[email protected]> Signed-off-by: Kanak Shilledar <[email protected]>

…rface and ctrl_en Signed-off-by: Daniel Maslowski <[email protected]> Signed-off-by: Kanak Shilledar <[email protected]>

Signed-off-by: Daniel Maslowski <[email protected]> Signed-off-by: Kanak Shilledar <[email protected]>

clock seems to be an issue which is causing the board to crash after dram init during the write operation. this patch adds remaining clocks were removed previously. these are mainly the audio/gpu/npu subsys clocks. Signed-off-by: Kanak Shilledar <[email protected]>

This reverts commit 6ee08e21aee47989341563eca3bc2fad342da55d. Signed-off-by: Kanak Shilledar <[email protected]>

Signed-off-by: Daniel Maslowski <[email protected]> Signed-off-by: Kanak Shilledar <[email protected]>

switch to DRAM_BASE_0 instead of DRAM_BASE_4 Signed-off-by: Kanak Shilledar <[email protected]>

Signed-off-by: Kanak Shilledar <[email protected]>

chaged the training data to match with our type of memory. eariler we were not using the training data for dbi_off memory changed the PMP register addresses. Signed-off-by: Kanak Shilledar <[email protected]>

kanakshilledar force-pushed the add_th1520 branch from c6682ae to 3f9d5a8 Compare September 30, 2024 10:37

kanakshilledar force-pushed the add_th1520 branch 3 times, most recently from 9cb31bc to f4e38b9 Compare October 5, 2024 10:49

orangecms force-pushed the add_th1520 branch from 7fe50db to ed0a31b Compare October 24, 2024 19:09

kanakshilledar force-pushed the add_th1520 branch 2 times, most recently from 4833382 to 98effa8 Compare February 24, 2025 11:30

kanakshilledar force-pushed the add_th1520 branch from 98effa8 to 7f4d8ec Compare March 6, 2025 13:42

orangecms and others added 16 commits April 23, 2025 15:03

initially add Milk-V Meles (XuanTie/T-Head TH1520)

680c4cd

Signed-off-by: Daniel Maslowski <[email protected]> Signed-off-by: Kanak Shilledar <[email protected]>

milk-v/meles: print initial program counter

dea125c

Signed-off-by: Daniel Maslowski <[email protected]> Signed-off-by: Kanak Shilledar <[email protected]>

milk-v/meles: WIP USB gadget

6761dba

Signed-off-by: Daniel Maslowski <[email protected]> Signed-off-by: Kanak Shilledar <[email protected]>

milk-v/meles: add sudo to fastboot commands

405a66f

TODO: drop this commit in future Signed-off-by: Kanak Shilledar <[email protected]>

milk-v/meles: dram: prepare dram for training

b7a590a

added pre training configs and setup. created a helper function to write 16 bit data required from writing to some registers. Signed-off-by: Kanak Shilledar <[email protected]>

milk-v/meles: change the code formater to RUSTFMT

33bf64b

changed the default code formatter in Rust Rover to rustfmt also changed the file format from CRLF to LF Signed-off-by: Kanak Shilledar <[email protected]>

milk-v/meles: dram: expose DRAM regs

439916b

Signed-off-by: Daniel Maslowski <[email protected]> Signed-off-by: Kanak Shilledar <[email protected]>

milk-v/meles: dram_helpers: use exposed DRAM regs and simplify

2f69ec9

Signed-off-by: Daniel Maslowski <[email protected]> Signed-off-by: Kanak Shilledar <[email protected]>

milk-v/meles: dram_helpers: add ddr_phy_broadcast_en

bc1e3b1

This looks like a dummy in the original C code, though reading from MMIO registers may actually have side effects in hardware. Signed-off-by: Daniel Maslowski <[email protected]> Signed-off-by: Kanak Shilledar <[email protected]>

milk-v/meles: dram: enable ddr_phy_broadcast_en()

d362520

Signed-off-by: Daniel Maslowski <[email protected]> Signed-off-by: Kanak Shilledar <[email protected]>

milk-v/meles: do NOT run fastboot via sudo

7085311

If you really want to, pass your custom command: make FASTBOOT='sudo fastboot' run Signed-off-by: Daniel Maslowski <[email protected]> Signed-off-by: Kanak Shilledar <[email protected]>

milk-v/meles: add basic README and udev rules file

8833860

Signed-off-by: Daniel Maslowski <[email protected]> Signed-off-by: Kanak Shilledar <[email protected]>

milk-v/meles: more prints get us further again

8107714

Signed-off-by: Daniel Maslowski <[email protected]> Signed-off-by: Kanak Shilledar <[email protected]>

kanakshilledar and others added 23 commits April 23, 2025 15:03

milk-v/meles: dram: implement dwc_ddrphy_phyinit_reg_interface()

05cbf28

this function was yet to be implemented required for `lpddr_init()` still the DRAM test is not passing :( Signed-off-by: Kanak Shilledar <[email protected]>

milk-v/meles: add additional line break for readability

66da691

Signed-off-by: Daniel Maslowski <[email protected]> Signed-off-by: Kanak Shilledar <[email protected]>

milk-v/meles: rework DRAM base and test limit

cb1d395

Signed-off-by: Daniel Maslowski <[email protected]> Signed-off-by: Kanak Shilledar <[email protected]>

milk-v/meles: simplify DDR_CFG0 definition, only use DCH1_DBG1

9d906b1

Signed-off-by: Daniel Maslowski <[email protected]> Signed-off-by: Kanak Shilledar <[email protected]>

milk-v/meles: simplify DDR register definitions, remove obsolete DBG1…

00f51b4

…_DCH1 Signed-off-by: Daniel Maslowski <[email protected]> Signed-off-by: Kanak Shilledar <[email protected]>

milk-v/meles: sort comments and consts in dwc_ddrphy_phyinit_reg_inte…

1abd87b

…rface and ctrl_en Signed-off-by: Daniel Maslowski <[email protected]> Signed-off-by: Kanak Shilledar <[email protected]>

milk-v/meles: add lpddr4_auto_selref()

08f952d

Signed-off-by: Daniel Maslowski <[email protected]> Signed-off-by: Kanak Shilledar <[email protected]>

Revert "milk-v/meles: dram: add previously removed clocks"

2109d1e

This reverts commit 6ee08e21aee47989341563eca3bc2fad342da55d. Signed-off-by: Kanak Shilledar <[email protected]>

fixup after Rust upgrade

d43332c

Signed-off-by: Daniel Maslowski <[email protected]> Signed-off-by: Kanak Shilledar <[email protected]>

WORKAROUND: sbss cleanup is now broken after Rust upgrade...

efecc0e

Signed-off-by: Daniel Maslowski <[email protected]> Signed-off-by: Kanak Shilledar <[email protected]>

milk-v/meles: notes, reset PMP, DRAM test fix

9fbf452

Signed-off-by: Daniel Maslowski <[email protected]> Signed-off-by: Kanak Shilledar <[email protected]>

CHECKPOINT: IT WORKS!

da5247b

Signed-off-by: Daniel Maslowski <[email protected]> Signed-off-by: Kanak Shilledar <[email protected]>

extend DRAM test

e47ae9c

Signed-off-by: Daniel Maslowski <[email protected]> Signed-off-by: Kanak Shilledar <[email protected]>

restore values

acdd50d

Signed-off-by: Daniel Maslowski <[email protected]> Signed-off-by: Kanak Shilledar <[email protected]>

back to other values

92d1939

Signed-off-by: Daniel Maslowski <[email protected]> Signed-off-by: Kanak Shilledar <[email protected]>

CHECKPOINT: lpddr4_reinit_ctrl mostly translated, not yet working

911a4c1

Signed-off-by: Daniel Maslowski <[email protected]> Signed-off-by: Kanak Shilledar <[email protected]>

CHECKPOINT: leave note, remove obsolete note

bfacc43

Signed-off-by: Daniel Maslowski <[email protected]> Signed-off-by: Kanak Shilledar <[email protected]>

FIXUP

3efdb03

Signed-off-by: Daniel Maslowski <[email protected]> Signed-off-by: Kanak Shilledar <[email protected]>

FIXUP

bc350bb

Signed-off-by: Daniel Maslowski <[email protected]> Signed-off-by: Kanak Shilledar <[email protected]>

CHECKPOINT

9c117ab

Signed-off-by: Daniel Maslowski <[email protected]> Signed-off-by: Kanak Shilledar <[email protected]>

FIXUP - CHECKPOINT

79fed7f

Signed-off-by: Daniel Maslowski <[email protected]> Signed-off-by: Kanak Shilledar <[email protected]>

CHECKPOINT

8e82baf

Signed-off-by: Daniel Maslowski <[email protected]> Signed-off-by: Kanak Shilledar <[email protected]>

kanakshilledar force-pushed the add_th1520 branch 2 times, most recently from 2071087 to e997237 Compare April 23, 2025 11:07

meles/bt0: migrate dram test to lib::util

7c89bed

switch to DRAM_BASE_0 instead of DRAM_BASE_4 Signed-off-by: Kanak Shilledar <[email protected]>

kanakshilledar force-pushed the add_th1520 branch from e997237 to 7c89bed Compare April 23, 2025 11:21

kanakshilledar added 2 commits April 24, 2025 20:32

meles/bt0/dram: add missing cpu_clk_config()

e5f4e2e

Signed-off-by: Kanak Shilledar <[email protected]>

meles/bt0/dram: update the dram training data and other minor fixes

bd2846b

chaged the training data to match with our type of memory. eariler we were not using the training data for dbi_off memory changed the PMP register addresses. Signed-off-by: Kanak Shilledar <[email protected]>

kanakshilledar force-pushed the add_th1520 branch from 5b8fc21 to bd2846b Compare April 26, 2025 09:12

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