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Commits on Apr 9, 2017

• Merge pull request #200 from hgomersall/initial_value_support

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  jandecaluwe

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• Merge branch 'master' into initial_value_support

  jandecaluwe

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• Merge pull request #193 from hgomersall/single_bit_vhdl_representation

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  jandecaluwe

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• Merge pull request #184 from rqou/multiple_cosim

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  jandecaluwe

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Commits on Mar 27, 2017

• Merge pull request #170 from srivatsan-ramesh/master

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  jck

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Commits on Jan 12, 2017

• travis: add python 3.6

  jck

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Commits on Dec 8, 2016

• update travis badge in readme

  jck

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Commits on Nov 30, 2016

• Update README.md

  jandecaluwe

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Commits on Nov 23, 2016

• [FIX] fixed the initial value case under Verilog where a list of signals are wires.

  hgomersall

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• Merge pull request #197 from jck/travis

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  jandecaluwe

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Commits on Nov 4, 2016

• Merge remote-tracking branch 'upstream/master' into initial_value_support

  hgomersall

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• FIX: Corrected list of bools initial value support in VHDL.

  hgomersall

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Commits on Oct 25, 2016

• travis: move simulator installation to before_script

  jck

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• travis: install simulator only when needed

  jck

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• travis: use new trusty build environment

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  jck

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• travis: install ghdl only if CI_TARGET is ghdl

  jck

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• travis: remove commented out allowed failures

  jck

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Commits on Aug 25, 2016

• [BUGFIX] Tests and fix for VHDL conversion of if/elif/else->case statements for boolean signals

  hgomersall

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Commits on Jul 18, 2016

• Merge pull request #182 from rqou/fix_print_for_real

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• Remove the limitation to have only one cosimulation

  ArcaneNibble

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Commits on Jul 17, 2016

• Correctly fix _makeAST to preserve future flags

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  ArcaneNibble

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• Use compile instead of ast.parse() so that future flags can be passed #179

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  jandecaluwe

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Commits on Jun 23, 2016

• Try to get stable results with converts #176

  jandecaluwe

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Commits on Jun 20, 2016

• Merge branch 'master' of github.com:jandecaluwe/myhdl

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• manual update

  jandecaluwe

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Commits on Jun 19, 2016

• Merge pull request #150 from hgomersall/initial_value_support

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  jandecaluwe

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• Merge pull request #174 from josyb/WinCoSim

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Commits on Jun 2, 2016

• Tidied up a left-over 'print'

  josyb

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Commits on Jun 1, 2016

• _Cosimulation.py: changed split of 'exe' specification

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  josyb

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Commits on May 27, 2016

• Merge remote-tracking branch 'upstream/master' into initial_value_support

  hgomersall

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• Removed redundant print statement in VHDL conversion.

  hgomersall

  committed
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Commits on May 24, 2016

• Added test for issue 169

  srivatsan-ramesh

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• added test for issue169

  srivatsan-ramesh

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Commits on May 23, 2016

• conversion examples

  jandecaluwe

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Commits on May 22, 2016

• Review and update unittest chapter

  jandecaluwe

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