pyverilator finds internal signals by parsing VL_SIG* lines in an .h file generated by verilator. The most recent version of verilator looks like it doesn't use the VL_SIG* macros anymore. Instead it, for an 8-bit signal, it produces a line like the one below:

CData/*7:0*/ parent_module__DOT__in_reg;

pyverilator should also look for this format as well.