This custom built AES hardware accelerator performs encryption and decryption of 128-bit data with 128-bit keys according to the advanced encryption standard (AES) (FIPS PUB 197) in hardware. The AES accelerator features are:
- Encryption and decryption according to AES FIPS PUB 197 with 128-bit key
- On-the-fly key expansion
The AES accelerator is designed to be configured with device driver. This section describe the setup and operation. The steps to perform encryption are:
- Set AES_RESET_REGISTER to 0 (Ensure crypto accelerator is off)
- Set AES-128 bit key in AES_KEY_REGISTER (as shown in device driver)
- Set AES_RESET_REGISTER to 1
- Set AES_START_KEY_EXPANSION_REGISTER to 1
- Check if AES_KEY_STATUS_REGISTER is 1 when key expansion is completed
- Set 128 bit plain text in AES_PLAIN_TEXT_REGISTER
- Set AES_ENCRYPT_ENABLE_REGISTER to 1
- Check if AES_ENCRYPTION_STATUS is 1 when encryption is completed
I have used Digilent Zybo build to make complete system on chip for this AES accelerator. This architecture tightly integrates a dual-core ARM Cortex-A9 processor with Xilinx 7-series Field Programmable Gate Array (FPGA) logic.
- Encryption takes 40 clock cycles
- Key epansion takes 80 clock cycles
- Test Bench AES key expansion
- Test Bench AES encryption
Contact me regarding additional features of RTL design for
- AES-256
- Test Benches MIT licensed. Fahim Alavi : Year 2023