[FIRRTL] Advanced layer sink will sink RWProbeOps and cause verifier errors #8640
Description
The verifier for the RWProbe op ensure that the target is under at-least the same layers as the probe op itself. The verifier provided part of the guarantee that, we cannot use a RWProbe to something in the design, from within a layer. Now, two issues:
- this is no longer a restriction we want to enforce, so this verifier is outdated
- advanced layer sink is sinking RWProbeOps into layer blocks, and causing verification errors
For (2), here is an example:
FIRRTL version 5.0.0
circuit Top:
layer A, bind:
public module Top:
input i: UInt<1>
output o: UInt<1>
output p: RWProbe<UInt<1>, A>
wire w: UInt<1>
connect o, w
connect w, i
wire x : RWProbe<UInt<1>>
define x = rwprobe(w)
layerblock A:
define p = xIR before advanced layer sink:
// -----// IR Dump After Vectorization (vectorization) //----- //
firrtl.module @Top(in %i: !firrtl.uint<1>, out %o: !firrtl.uint<1>, out %p: !firrtl.rwprobe<uint<1>, @A>) attributes {convention = #firrtl<convention scalarized>} {
%w = firrtl.wire sym @sym : !firrtl.uint<1>
firrtl.matchingconnect %o, %w : !firrtl.uint<1>
firrtl.matchingconnect %w, %i : !firrtl.uint<1>
%x = firrtl.wire : !firrtl.rwprobe<uint<1>>
%0 = firrtl.ref.rwprobe <@Top::@sym> : !firrtl.rwprobe<uint<1>>
firrtl.ref.define %x, %0 : !firrtl.rwprobe<uint<1>>
firrtl.layerblock @A {
%1 = firrtl.ref.cast %x : (!firrtl.rwprobe<uint<1>>) -> !firrtl.rwprobe<uint<1>, @A>
firrtl.ref.define %p, %1 : !firrtl.rwprobe<uint<1>, @A>
}
}The error:
../scratch.fir:16:16: error: 'firrtl.ref.rwprobe' op target has insufficient layer requirements
define x = rwprobe(w)
^
../scratch.fir:16:16: note: see current operation: %2 = "firrtl.ref.rwprobe"() <{target = #hw.innerNameRef<@Top::@sym>}> : () -> !firrtl.rwprobe<uint<1>>
../scratch.fir:11:5: note: target is missing layer requirements: @A
wire w: UInt<1>
^
The bad IR:
// -----// IR Dump After AdvancedLayerSink Failed (firrtl-advanced-layer-sink) //----- //
"firrtl.circuit"() <{annotations = [], name = "Top"}> ({
"firrtl.layer"() <{convention = #firrtl<layerconvention bind>, sym_name = "A"}> ({
^bb0:
}) : () -> ()
"firrtl.module"() <{annotations = [], convention = #firrtl<convention scalarized>, layers = [], portAnnotations = [[], [], []], portDirections = array<i1: false, true, true>, portLocations = [loc("../scratch.fir":7:12), loc("../scratch.fir":8:12), loc("../scratch.fir":9:12)], portNames = ["i", "o", "p"], portSymbols = [], portTypes = [!firrtl.uint<1>, !firrtl.uint<1>, !firrtl.rwprobe<uint<1>, @A>], sym_name = "Top"}> ({
^bb0(%arg0: !firrtl.uint<1>, %arg1: !firrtl.uint<1>, %arg2: !firrtl.rwprobe<uint<1>, @A>):
%0 = "firrtl.wire"() <{annotations = [], inner_sym = #hw<innerSym@sym>, name = "w", nameKind = #firrtl<name_kind droppable_name>}> : () -> !firrtl.uint<1>
"firrtl.matchingconnect"(%arg1, %0) : (!firrtl.uint<1>, !firrtl.uint<1>) -> ()
"firrtl.matchingconnect"(%0, %arg0) : (!firrtl.uint<1>, !firrtl.uint<1>) -> ()
"firrtl.layerblock"() <{layerName = @A}> ({
%1 = "firrtl.wire"() <{annotations = [], name = "x", nameKind = #firrtl<name_kind droppable_name>}> : () -> !firrtl.rwprobe<uint<1>>
%2 = "firrtl.ref.rwprobe"() <{target = #hw.innerNameRef<@Top::@sym>}> : () -> !firrtl.rwprobe<uint<1>>
"firrtl.ref.define"(%1, %2) : (!firrtl.rwprobe<uint<1>>, !firrtl.rwprobe<uint<1>>) -> ()
%3 = "firrtl.ref.cast"(%1) : (!firrtl.rwprobe<uint<1>>) -> !firrtl.rwprobe<uint<1>, @A>
"firrtl.ref.define"(%arg2, %3) : (!firrtl.rwprobe<uint<1>, @A>, !firrtl.rwprobe<uint<1>, @A>) -> ()
}) : () -> ()
}) : () -> ()
}) : () -> ()