[FIRRTL] Add features, cleanup InstanceInfo (again) #7618
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**This reverts a revert.**
Add a number of new features to FIRRTL's `InstanceInfo` analysis. These
changes were made after downstream efforts (uncommitted work) to use this
in the `AddSeqMemPorts` pass. These new features include:
- `hasDut` to check if a circuit has a design-under-test
- `getDut` to get the design-under-test if it exists
- `getEffectiveDut` to get the "effective" design-under-test
- `isEffectiveDut` to check if a module is the "effective"
design-under-test
The "effective" design-under-test (DUT) is a weird artifact of how some
SFC-derived passes have historically worked. If a circuit has no
DUT (indicated by a circuit which contains no module annotated with a
`MarkDUTAnnotation`), then some passes will treat the top module as if it
were the DUT. This "effective" DUT concept shows up in `AddSeqMemPorts`,
`GrandCentral`, and other passes. For now, enshrine the _computation_ of
this in the `InstanceInfo` analysis to avoid having to scatter logic for
computing this across serverl passes.
Widen the accepted type of parameters that can be passed to `InstanceInfo`
member functions from `FModuleOp` to `igraph::ModuleOpInterface`. This
already works without modifications and makes these member functions much
more usable.
Signed-off-by: Schuyler Eldridge <[email protected]>
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This reverts a revert.
Add a number of new features to FIRRTL's
InstanceInfoanalysis. These changes were made after downstream efforts (uncommitted work) to use this in theAddSeqMemPortspass. These new features include:hasDutto check if a circuit has a design-under-testgetDutto get the design-under-test if it existsgetEffectiveDutto get the "effective" design-under-testisEffectiveDutto check if a module is the "effective" design-under-testThe "effective" design-under-test (DUT) is a weird artifact of how some SFC-derived passes have historically worked. If a circuit has no DUT (indicated by a circuit which contains no module annotated with a
MarkDUTAnnotation), then some passes will treat the top module as if it were the DUT. This "effective" DUT concept shows up inAddSeqMemPorts,GrandCentral, and other passes. For now, enshrine the computation of this in theInstanceInfoanalysis to avoid having to scatter logic for computing this across serverl passes.Widen the accepted type of parameters that can be passed to
InstanceInfomember functions fromFModuleOptoigraph::ModuleOpInterface. This already works without modifications and makes these member functions much more usable.