What's Changed

• [circt-verilog-lsp] Move to Slang's src mngr, drop LLVM src mngr by @Scheremo in #9045
• [circt-verilog-lsp][NFC] Break out implementation classes by @Scheremo in #9051
• [circt-verilog-lsp] Avoid recursing into other buffers when indexing by @Scheremo in #9055
• [RTG] Implement getAsmResultNames for FixedRegisterOp by @maerhart in #9058
• [CombToDatapath] Lower comb::SubOp by @uenoku in #9053
• [circt-synth] Allow AIGER file to be an input file by @uenoku in #9054
• [ESI] ChannelMMIO: decrease MMIO space per client by @teqdruid in #9062
• [RTG][EmbedValidationValuesPass] Allow ID duplicates if values match by @maerhart in #9061
• [RTG] Add isa.space operation by @maerhart in #9060
• [circt-verilog-lsp] Refactor VerilogIndex, add Package indexing by @Scheremo in #9065
• [CombToSynth] Compute Kogge-Stone prefix tree lazily in unsigned comparison lowering by @uenoku in #9050
• [ESI] Various tweaks to cosim scripts by @mortbopet in #9064
• [ESI][Runtime] Search for backends via env var by @teqdruid in #9070
• [RTG] Add VirtualRegisterConfigAttr by @maerhart in #9059
• [Comb] Fix mux canonicalizers for non-signless-ints by @teqdruid in #9071
• [circt-verilog-lsp] Minimize project-scope File IO by @Scheremo in #9056
• [circt-lsp-verilog] "Debounce" onDidChange calls; update in worker by @Scheremo in #9046
• [circt-lsp-server] Only enable unit tests if feature is enabled by @rwy7 in #9072
• [python][Synth] Provide fine-grained APIs for path queries by @uenoku in #9068
• [ImportVerilog][MooreToCore] Implement CHandle import and lowering by @Scheremo in #9077
• [ImportVerilog][MooreToCore] Re-land Implement CHandle import and low… by @Scheremo in #9079
• [FIRRTL] Add LowerDomains pass by @seldridge in #8929
• [MooreToCore] Support slicing of nested arrays by @SimonEbner in #9073
• [LLHD] Remove unused passes and unused memory types and ops by @fabianschuiki in #9078
• [circt-verilog-lsp-server] Simplify MaxCapForcesFlushDuringContinuousTyping by removing bakground thread by @uenoku in #9080
• [LLHD] Add new RefType to replace hw::InOutType by @fabianschuiki in #9081
• Fix minor typos by @SimonEbner in #9084
• [circt-lsp-server] Make time source injectable by @Scheremo in #9082
• [ImportVerilog] Add delayed assignment support by @fabianschuiki in #9085
• Revert "[circt-lsp-server] Make time source injectable" by @Scheremo in #9089
• [ImportVerilog][Moore] Add real-to-int & int-to-real operators by @Scheremo in #9088
• [FIRRTL] Add fields to domains by @seldridge in #9087
• [Synth] Enhance LowerVariadic pass with timing-aware optimization by @uenoku in #9086
• [Synth] Add MaximumAndCover Pass by @uenoku in #9090
• [ImportVerilog] Generalize materialization of constant real values by @Scheremo in #9092
• Bump LLVM to 3c53adec68b3e7be3d69bc4e24168e530097fce0. by @mikeurbach in #9063
• [FIRRTL] Add DomainDefineOp by @rwy7 in #9067
• [FIRRTL] DomainFieldAttr types are PropertyTypes by @seldridge in #9094
• Bump Slang to v9.1 by @fabianschuiki in #9097
• [FIRRTL] Update port insertion/erasure API for instance/instance-choice ops by @rwy7 in #9093
• [Synth][LowerVariaidc] Fix topological ordering and a pass phase ordering by @uenoku in #9095
• [ESI] Add opt-out of reversal in array C++ ser/de by @mortbopet in #9096
• [FIRRTL] Add LowerDomains to firtool pipeline by @seldridge in #9099
• [MooreToCore] Lower moore.real_constant to arith.constant by @Scheremo in #9100
• [FIRRTL] Fix dedup looking up wrong op in inner ref target check by @fabianschuiki in #9104
• [ImportVerilog] Allow functions to capture values from parent scope by @Scheremo in #9107
• [Synth] Fix race condition and memory corruption in longest path analysis caching by @uenoku in #9098

New Contributors

• @SimonEbner made their first contribution in #9073

Full Changelog: firtool-1.133.0...firtool-1.134.0

What's Changed

• [ESI][Cosim][Verilator] Switch to FST and dump time by @teqdruid in #9031
• Add a diagnostic for unsupported system calls with more than 1 argument by @likeamahoney in #9014
• [circt-verilog-lsp] Add support for -C command files for Slang, project-wide defintion lookup by @Scheremo in #9003
• [comb-to-synth] Implement Sklanskey Tree and Architecture Selection based on Attribute by @cowardsa in #9021
• fix: prevent canonicalize looping for extremely long time by @tianrui-wei in #9030
• [ESI][Cosim] Always use posix paths for questa by @mortbopet in #9035
• [ESI][Cosim] Add windows-equivalent for os.setsid by @mortbopet in #9034
• [ci] Set individual integration test timeout to 2m by @seldridge in #9039
• [ESI] Install CosimBackend.dll dependencies on windows by @mortbopet in #9037
• [FIRRTL] Update more symbol-sensitive ops after dedup by @fabianschuiki in #9016
• [ESI][Cosim] Switch to GUI mode via environment variable by @teqdruid in #9041
• [ESI][Cosim] Enable SAVE_WAVE functionality in SV driver by @teqdruid in #9042
• fix: guard eaglerinliner with detecting a valid circuit by @tianrui-wei in #9025
• [Datapath] Add initial delay optimisation pass by @cowardsa in #9038
• [SV] Support expressions as case patterns by @chiahsuantw in #9018
• [FIRRTL] Gate class deduplication behind an option by @fabianschuiki in #9040
• [CombToSynth] Use parallel-prefix tree for unsigned comparisons by @uenoku in #9048
• [Comb][circt-synth] Implement BalanceMux pass for optimizing mux chains by @uenoku in #9044

New Contributors

• @tianrui-wei made their first contribution in #9030

Full Changelog: firtool-1.132.0...firtool-1.133.0

What's Changed

• [ConvertToArcs] Allow ops with regions by @fabianschuiki in #8935
• [Synth][AIG] Move AIG dialect under Synth and remove AIG dialect, NFC by @uenoku in #8956
• [Arc] Add ExecuteOp by @fabianschuiki in #8949
• [ImportVerilog] Add support for materializing FixedSizeUnpackedArrayType as UnpackedArrayType. by @Scheremo in #8960
• [Synth] Implement basic canonicalization/folder to mig.maj_inv by @uenoku in #8959
• [Synth] Add support for mig.maj_inv in longest path analysis by @uenoku in #8965
• [Reduce] Various reducer improvements by @fabianschuiki in #8957
• [SV] Include CallInterface by @uenoku in #8966
• [Moore] Add builtin for $urandom by @Scheremo in #8968
• [ESI] Bump zlib tag by @mortbopet in #8963
• [ESI] Factor out inner execution in Simulator::run by @mortbopet in #8964
• [Synth] Add structural hashing pass for AIG/MIG operations by @uenoku in #8962
• [ConvertToArcs] Add llhd.combinational conversion by @fabianschuiki in #8950
• [Verif] handle self-referencing operations by @ollef in #8972
• [ArcToLLVM] Add arc.execute conversion by @fabianschuiki in #8951
• [AIG] feat : and_inv fold by @markram1729 in #8958
• [Moore] Add builtins for simulation time measurements by @Scheremo in #8970
• [ImportVerilog][Moore] Add support for %t format specifier, introduce moore.fmt.time by @Scheremo in #8979
• [FIRRTL] Emit fopen calls to get fd's not mcd's. by @dtzSiFive in #8981
• [FIRRTL] Add reduction that moves MustDedup onto children by @fabianschuiki in #8969
• [Moore] Add support for $random system task by @Scheremo in #8982
• [ESI] Add skid buffer to Cosim_Endpoint_ToHost by @teqdruid in #8983
• [ESI] Set '--output-split' for verilator compilation by @mortbopet in #8978
• [ESI] Librarify ESI cosim classes by @mortbopet in #8953
• [Datapath] Add product of sum partial product operator by @cowardsa in #8980
• [Moore] Add shortreal type, bit <-> real conversions by @Scheremo in #8985
• [ImportVerilog] Fix missing RValue conversion for struct_create by @Scheremo in #8988
• [Synth] Rename FanIn/FanOut StartPoint/EndPoint by @markram1729 in #8976
• [ESI2Phy] Adapt usage of rewriter to upcoming version. by @ingomueller-net in #8989
• [Synth][Strash] Use RegionDCE instead of UnusedOpPruner by @uenoku in #8990
• [Support] Add walkPostOrder and walkInversePostOrder to InstanceGraph by @fabianschuiki in #8974
• [FIRRTL] Handle ClassTypes properly in Dedup by @fabianschuiki in #8975
• [FIRRTL] Various small reduction pattern tweaks by @fabianschuiki in #8984
• [Moore][ImportVerilog] Add moore.fmt.string, support for $sformatf by @Scheremo in #8993
• Bump LLVM to 580860e8b7341783e8e53114f26b9a9659a3a3e1 by @fzi-hielscher in #8995
• [ImportVerilog][Bug] Fix single argument expressions in severity tasks by @Scheremo in #8998
• [LTL][ImportVerilog] Add support for $rose, $stable, $fell by @Scheremo in #8999
• [Synth] LowerWordsToBits: Improve scalability with bit-sensitive constprop by @uenoku in #8997
• [Arc] Add MergeTaps pass by @fzi-hielscher in #9000
• [Reduce] Various reduction tweaks by @fabianschuiki in #9004
• [FIRRTL] Add a missing unrealized conversion cast in LowerClasses by @fabianschuiki in #9005
• [Synth][LongestPathAnalysis] Remove hack for passing top module name through IR attribute by @uenoku in #9006
• [circt-verilog-lsp] Add definition and reference providers by @uenoku in #8280
• [circt-test] accept LoweringOptions to control the generated Verilog by @ollef in #9001
• [HWLegalizeModules] add disallowClockedAssertions lowering flag by @ollef in #9002
• [FIRRTL] Ensure all types and attributes are walkable by @fabianschuiki in #9007
• [build] Update Slang dependency properties before installing by @jmgorius in #9017
• [ESI] Allow single-file additions to SourceFiles by @mortbopet in #9019
• [Sim] Rename FormatLitOp to FormatLiteralOp, NFC by @fzi-hielscher in #9015
• [Datapath] Custom Partial Product Lowering for computing the Square of the input by @cowardsa in #9010
• [circt-verilog-lsp] Add support for package import indexing by @Scheremo in #9023
• [ESI] Route simulator compilation/exec output through callbacks by @mortbopet in #9009
• [Build] Set /utf-8 flag specifically for slang targets by @fzi-hielscher in #9027
• [ExportVerilog] Require $unsigned for outer-most expression in assignment by @uenoku in #9024

New Contributors

• @ollef made their first contribution in #8972
• @markram1729 made their first contribution in #8958
• @ingomueller-net made their first contribution in #8989
• @jmgorius made their first contribution in #9017

Full Changelog: firtool-1.131.0...firtool-1.132.0

This is a patch release that adds the -emit-chisel-asserts-as-sva to the 1.5 series of releases.

What's Changed

• [LowerToHW][firtool] Backport -emit-chisel-asserts-as-sva to 1.5 by @seldridge in #9028

Full Changelog: sifive/1/5/7...sifive/1/5/8

What's Changed

• [LLHD] Simplify single-block llhd.process terminated by llhd.halt by @mvpant in #8917
• [Synth] Support MIG lowering in CombToAIG conversion pass by @uenoku in #8932
• [ESI] Accept wider range of int types in C++ serde by @mortbopet in #8933
• Use properlyDominates in AffineToLoopSchedule by @jpienaar in #8904
• [MooreToCore] Add support for $fatal by @Scheremo in #8936
• [Reduce] Use stable sort, prune unused symbols, tweak FIRRTL reductions by @fabianschuiki in #8938
• [circt-verilog] Add commandfile input option. by @jpienaar in #8937
• [Datapath] Implement timing-driven compression algorithm by @cowardsa in #8920
• [MooreToCore] Consider element type in extract vs slice by @jpienaar in #8942
• [ImportVerilog] Fix edge case for single-bit pre- and post-increment by @Scheremo in #8945
• [AIG] Refactor AIG longest-path analysis with lazy mode and max-delay filtering by @uenoku in #8940
• [Synth] Partition trivial cuts before sorting non-trivial ones in CutRewriter, NFCI by @uenoku in #8947
• [SeqToSV] Use XMR to set up async reset and preset of firreg under ifdef by @rwy7 in #8944

New Contributors

• @Scheremo made their first contribution in #8936

Full Changelog: firtool-1.130.0...firtool-1.131.0

What's Changed

• [Moore] Add proper conversions between time and integer values by @fabianschuiki in #8900
• [FIRRTL] Domains: Operation Approach by @seldridge in #8843
• [AIGLongestPathAnalysis] Implement incremental longest path analysis for IR transformations by @uenoku in #8890
• [Synth] Refactor and improve cut rewriter infrastructure by @uenoku in #8909
• [Comb] Expand Known-Bits Analysis to Additional Operators by @cowardsa in #8902
• [Datpath] Improve Booth Encoding based on the sign-extension trick by @cowardsa in #8903
• [Datapath] Fix bug in datapath test by @cowardsa in #8915
• [Synth] Add MajorityInverterOp (synth.mig.maj_inv) to Synth dialect by @uenoku in #8912
• [ESI] Don't assume dict attribute for all objects by @mortbopet in #8911
• [ESI] Extend dll dirs on esiaccel module load by @mortbopet in #8901
• [ESI] Allow for opt-in to struct reversal by @mortbopet in #8919
• Remove ExportChiselInterface. by @dtzSiFive in #8921
• [ESI] Add serde capabilities to ESI C++ runtime types by @mortbopet in #8879
• [FIRRTL] Use the defname for deciding bindfile names of extmodules by @rwy7 in #8922
• [build] Add /utf-8 build if MSVC by @seldridge in #8926
• [ci] Release circt-{opt,synth,test} in firrtl-bin by @seldridge in #8928

Full Changelog: firtool-1.129.0...firtool-1.130.0

What's Changed

• [HW] Canonicalize array inject to create; allow struct inject loops by @fabianschuiki in #8861
• [Comb] Generalize AndOp narrowing if mask has leading/trailing zeros by @fabianschuiki in #8864
• [Comb] Avoid infinite loops by not canonicalizing recursive ops by @fabianschuiki in #8866
• [HWToLLVM] Fix struct_inject lowering using pre-lowering operand by @fabianschuiki in #8867
• Bump LLVM to 681ecae9133b0e54441529d1eb68fb3604333a93 by @fzi-hielscher in #8869
• [ArcToLLVM] Replace all i0 values with a constant 0 by @fabianschuiki in #8871
• [Arc] Consider array/struct field alignment when computing state size by @fabianschuiki in #8872
• [Synth] Add CutRewriter framework and TechMapper pass by @uenoku in #8868
• Remove some unneeded defs and unused variable warnings. by @jpienaar in #8874
• [Arc][MergeIfs] Improve performance by @maerhart in #8876
• [LowerArcToLLVM] Disable pattern rollback in dialect conversion by @fzi-hielscher in #8878
• [ImportVerilog] Add support for %f/%F format specifier by @liamslj13 in #8848
• Use isa_and_nonnull for op->getDialect() by @uenoku in #8880
• [ESI] Add type constructors to esiCppAccel API by @mortbopet in #8875
• [Moore] Add more precise conversion ops by @fabianschuiki in #8883
• [Moore] Add WaitDelayOp, support delay control in ImportVerilog by @fabianschuiki in #8884
• [Synth] Add GenericLUTMapper pass for LUT mapping by @uenoku in #8888
• [README] Fix path to MLIR in README.md by @ladisgin in #8892
• [Synth] Improve cut deduplication and non-minimal cut removal by @uenoku in #8889
• [circt-synth] Parallel Prefix Lowering Performance Bug Fix by @cowardsa in #8881
• [Sim] Create clocked and procedural sim.exit/pause ops by @fabianschuiki in #8893
• [ExportVerilog] Fix crash for variadic ops with a single operand by @7FM in #8894
• [MooreToCore] Convert unreachable, stop, finish, finish_message ops by @fabianschuiki in #8895
• [AIGLongestPathAnalysis] Allow comb.truth_table as a unit by @uenoku in #8896
• Bump slang to dd16a7947e0586d0541477f1b4b60eda7c986e35 by @jpienaar in #8887
• [Moore] Add constant folders for trunc/zext/sext ops by @fabianschuiki in #8899
• Bump LLVM to 4913aee483b69d1cc81ee77e6a155af6aac45daf. by @mikeurbach in #8898
• Remove single state restriction on FSM to SV by @jpienaar in #8665
• [FIRRTL] Lower-Layers: capture operands of subaccess op by @rwy7 in #8891

New Contributors

• @ladisgin made their first contribution in #8892

Full Changelog: firtool-1.128.0...firtool-1.129.0

What's Changed

• Bump LLVM to b63a9b7a3cdc1e41545df595215077e50bfd04af. by @mikeurbach in #8811
• [ESI][Runtime] Windows wheel: use flat directory structure by @teqdruid in #8815
• [ESI][Runtime] Fixing MMIO to account for relative paths by @teqdruid in #8814
• [Synth] Introduce Synth dialect boilerplate by @uenoku in #8813
• [ESI][Runtime] Fix Linux backend loading by @teqdruid in #8819
• [utils] Add Arcilator and Verilator comparison utility by @fabianschuiki in #8809
• [Synth] Add Priority Cuts Enumerator by @uenoku in #8818
• [ImportVerilog] Insert type conversion for variable initializer by @mvpant in #8807
• [Reducer] Allow unregistered dialects by @fabianschuiki in #8822
• Bump LLVM by @uenoku in #8820
• Add MacroErrorOp by @rwy7 in #8808
• [FIRRTL][CreateSiFiveMetadata] Add memory read-under-write behavior to emitted metadata by @fzi-hielscher in #8604
• [ImportVerilog] Add time literals by @fabianschuiki in #8824
• [FIRRTL] Remove companion assumes pass/feature. by @dtzSiFive in #8826
• [NFC] Remove %T from tests by @uenoku in #8827
• [ImportVerilog] Bump slang to version 8 by @hovind in #7792
• [LLHD] Propogate signal definitions only to dominated blocks in Mem2Reg by @mvpant in #8821
• [ImportVerilog] slang 8.0 -> 8.1 by @dtzSiFive in #8829
• [Support] Use git commit hash as version in non-release builds by @fabianschuiki in #8834
• [ImportVerilog] Bump slang to version 9 by @fabianschuiki in #8835
• [Reducer] Allow reductions to match multiple times per op by @fabianschuiki in #8837
• [ImportVerilog] Fix file locations for auto-discovered files by @fabianschuiki in #8840
• [HW] Make constantifier reduction treat results separately by @fabianschuiki in #8838
• [circt-synth] Incorporate datapath operations into circt-synth pipeline by @cowardsa in #8842
• Allow Bound-in layers under inline layers by @rwy7 in #8642
• [ImportVerilog] Fix Bug in Packed Array Lvalue by @AtticusKuhn in #8841
• [HW] Use multiple reduction matches in port pruner by @fabianschuiki in #8839
• [HW] Accept most reductions even if module size increases by @fabianschuiki in #8847
• [README] Frontload unified build to get started more easily; NFC by @fabianschuiki in #8851
• [LLHD] Add struct extract support to mem2reg by @fabianschuiki in #8854
• [LLHD] Allow projections across blocks in mem2reg by @fabianschuiki in #8855
• [LLHD] Lower processes that have ops ahead of convergence block by @fabianschuiki in #8856
• [LLHD] Handle eq and ult loop conditions in UnrollLoops pass by @fabianschuiki in #8857
• [LLHD] Properly handle local signals during mem2reg by @fabianschuiki in #8859
• [ci] Build static binaries with mimalloc by @seldridge in #8858
• Put memories in the same directory as their parent by @rwy7 in #8862
• [FIRRTL] Firtool: Add option to emit bind files for private modules by @rwy7 in #8853

Full Changelog: firtool-1.127.0...firtool-1.128.0

What's Changed

• [ESI] MessageData utility functions by @mortbopet in #8777
• [ESI] Always find_package Python3 Development by @mortbopet in #8778
• [ESI] Disallow calls on an unconnected FuncService::Function by @mortbopet in #8779
• [Datapath] Create Datapath to Comb Pass by @cowardsa in #8736
• [Comb] Fix more recursive mux folders by @TaoBi22 in #8756
• [AIG] Remove aig.cut by @uenoku in #8784
• Bump LLVM by @uenoku in #8783
• Update to new builder format. by @jpienaar in #8785
• Create .git-blame-ignore-revs by @jpienaar in #8787
• [ESI] Also publish releases on workflow_dispatch by @mortbopet in #8780
• [ESI] Yield gil before blocking operations in MessageDataFuture by @mortbopet in #8789
• [Comb] Add comb.reverse operation with Verilog Export by @mafeguimaraes in #8758
• [HW][HWAggregateToComb] Add support for hw.array_inject operation in HWAggregateToComb pass by @uenoku in #8788
• [FIRRTL] Type check in Cat operatnds in FIR parser by @uenoku in #8793
• [ESI] Expose accelerator through AcceleratorConnection py api by @mortbopet in #8781
• [ESI] Better single-argument handling for FunctionPort by @mortbopet in #8782
• [ESI] Extend instead of override CMAKE_CXX_FLAGS by @mortbopet in #8551
• [RTG] Add InsertTestToFileMappingPass by @maerhart in #8795
• Bump LLVM to 76bebb5be9daf9ca035777b17fa63d4ce13e79b9 by @maerhart in #8796
• [RTG] Don't hardcode the root op of passes where not necessary by @maerhart in #8791
• [RTG] Sequences are always private by @maerhart in #8792
• [RTG] Rely on textual pass pipeline in Python and CAPI by @maerhart in #8797
• [RTG] Simplify EmitISAEmission pass by @maerhart in #8798
• [HWToSMT] Return an unbound value for OOB hw.array_inject by @uenoku in #8794
• [HWToLLVM] Add lowering support for 'hw.array_inject' op by @mvpant in #8774
• [ESI] Always build zlib statically into ESI runtime by @mortbopet in #8801
• [FIRRTL] Add layer colour verifiers to force and release ops by @rwy7 in #8800
• [ESI][Runtime] Fix wheel build by @teqdruid in #8803
• [ESI][Runtime] Fix backend DLL loading by @teqdruid in #8805
• [ESI] Improve backend loading error on windows by @mortbopet in #8802
• [LowerFIRRTLToHW] Add SYNTHESIS guard to fprintf lib by @uenoku in #8812

New Contributors

• @mafeguimaraes made their first contribution in #8758

Full Changelog: firtool-1.126.0...firtool-1.127.0

What's Changed

• [ESI] Add a transaction snoop operation by @teqdruid in #8684
• [HW] MaterializeConstant: check for null block by @teqdruid in #8687
• [VerifToSMT] Fix lowering of initial integer values for BMC by @fzi-hielscher in #8689
• [FIRRTL] Add "knownlayers" specifications to ExtModules by @rwy7 in #8623
• [Deseq] Add bin flag to enable mux by @fabianschuiki in #8686
• [Datapath] Add Datapath to SMT conversion pass by @cowardsa in #8682
• [Comb] Avoid some non-terminating MuxOp fold cases by @TaoBi22 in #8691
• [Comb] Fix excessive const shifts causing crashes and invalid IR by @fabianschuiki in #8696
• [AIG] Add canonicalization to simplify inversion by @uenoku in #8697
• Fix filecheck directive typos and fix now-active test lines by @dtzSiFive in #8702
• [Verif][LEC] Make LECOp result optional to avoid unsafe conversion by @fzi-hielscher in #8701
• [hw] Convert HW Passes to use ODS constructors by @seldridge in #8703
• [OM] Deprecate the OM map by @prithayan in #8606
• Bump LLVM to ace1c838ca91c83c7a271d9378b86ea56051e83f. by @mikeurbach in #8705
• [RTG] Redefine RandomNumberInRangeOp upper bound to be inclusive by @maerhart in #8710
• [AIG] Add slice indexing support to LongestPathCollection in AIG python on bindings by @uenoku in #8709
• [MooreToCore] Lower empty string_constant to expected bit width. by @mvpant in #8688
• Bump LLVM to d9190f8141661bd6120dea61d28ae8940fd775d0 by @maerhart in #8715
• [RTG] Add custom tuple type to support empty tuples by @maerhart in #8711
• [RTG] Enable conditional value forwarding for ValidateOp by @maerhart in #8712
• [AIG] Use llvm::stable_sort to sort paths by @uenoku in #8717
• [circt-verilog] Enable SROA again by @maerhart in #8720
• [PyRTG] Support Python config parameters by @maerhart in #8719
• [Python] Speed up type_to_pytype and attribute_to_var by @maerhart in #8718
• [FIRRTL] Remove circuit from macro used by inline layers by @rwy7 in #8714
• [FIRRTL] SFCCompat: properly lower invalidated enums by @youngar in #8722
• [FIRRTL] FIRParser: support caching constants in match statements by @youngar in #8723
• [FIRRTL] check bundles have unique field names by @youngar in #8729
• [FIRRTL] TagExtract: make type inference parser friendly by @youngar in #8727
• [ESI] Fix wrap op canonicalizers by @teqdruid in #8730
• [ExportVerilog] localparam should always print bitwidths by @youngar in #8732
• [circt-lec] Adding support for the datapath dialect by @cowardsa in #8721
• [circt-synth] Add an option to disable WordsToBits, remove verification code from design by @uenoku in #8733
• [CombToSMT] Force conversion from bool to bv<1> after icmp by @maerhart in #8737
• [FIRRTL] LowerSigs: Add enum support by @youngar in #8731
• [RTG] Add a pass to print a list of tests by @maerhart in #8734
• [Verif] Add RefinementCheckingOp by @fzi-hielscher in #8713
• [FIRRTL] Enums: Add user-defined constructor encodings by @youngar in #8724
• [FIRRTL] FIRParser: parse tagExtract operations by @youngar in #8728
• [FIRRTL] LowerToHW: handle TagExtractOp by @youngar in #8726
• [FIRRTL] Do not allow uninferred widths or rests in enums by @youngar in #8740
• [RTG] Add immediate concat and slice operations by @maerhart in #8735
• [RTG] Add concat_immediate and slice_immediate folders by @maerhart in #8738
• [RTG] Fix ValidateOp elaboration by @maerhart in #8743
• [AIG][LongestPathAnalysis] Fix a bug in deduplicatePathsImpl by @uenoku in #8746
• [RTG] Support immediate slice/concat after validate by @maerhart in #8744
• [VerifToSMT] Move some LEC lowering code to a superclass, NFC by @fzi-hielscher in #8748
• [circt-opt][FSMToSV] Fix bug of operations not being cloned in transition region in FSMToSV Conversion by @AtticusKuhn in #8753
• [circt-bmc] Support seq.firreg with sync reset by @liuyic00 in #8698
• [RTG] Add operations to report test result by @maerhart in #8751
• [AIG][NFC] Add a module to OutputPort data structure and refactor the name handling by @uenoku in #8759
• [VerifToSMT] Fix lowering of no output, no result LEC op by @fzi-hielscher in #8763
• [ImportVerilog] Add (* full_case *) attribute support by @mvpant in #8762
• [HW][AIG] Add InstancePath CAPI and use native structures for AIG longest path analysis by @uenoku in #8760
• [Seq] Add a pass to convert an array seq.firreg to seq.firmem by @prithayan in #8716
• [FIRRTL] Make enums behave less like aggregates by @youngar in #8742
• [FIRRTL] FlattenMemories: handle memories with enums by @youngar in #8741
• [HWToSMT] Add ArrayInject lowering to HWToSMT by @uenoku in #8765
• [VerifToSMT] Lower verif.refines to SMT by @fzi-hielscher in #8749
• [Support] Add NPN class for Boolean function canonicalization by @uenoku in #8747
• [MooreToCore] Preserve module port order by @fabianschuiki in #8768
• [circt-verilog] Add register-to-memory pass to pipeline by @fabianschuiki in #8773
• [FIRRTL] Fix TagExtractOp's type inference by @youngar in #8766
• [FIRRTL] make mux type inference support enumeration types by @youngar in #8769
• [FIRRTL] FRT: support creating 0-valued enums by @youngar in #8772
• Migrate away from ArrayRef(std::nullopt_t) by @kazutakahirata in #8776

New Contributors

• @mvpant made their first contribution in #8688
• @AtticusKuhn made their first contribution in #8753
• @kazutakahirata made their first contribution in #8776

Full Changelog: firtool-1.125.0...firtool-1.126.0