本科的时候写的 _(:з」∠)_

这个项目现在主要用来测试VCS+Verdi环境是否可用

DES Encryption Verilog

use iverilog:

make ivlsim_run

use vcs:

make simv_run

make verdi

Compile verilog files and generate fsdb wave file with Synopsys VCS, then view design and wave in Verdi.