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@partcleda

Partcl, Inc.

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  1. intern_challenge intern_challenge Public

    Challenge for 2026 ML Sys Interns

    Python 8 64

  2. OpenTimer OpenTimer Public

    Forked from OpenTimer/OpenTimer

    A High-performance Timing Analysis Tool for VLSI Systems

    Verilog 1 1

  3. OpenROAD-flow-scripts OpenROAD-flow-scripts Public

    Forked from The-OpenROAD-Project/OpenROAD-flow-scripts

    OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

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  4. OpenROAD OpenROAD Public

    Forked from The-OpenROAD-Project/OpenROAD

    OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

    Verilog

  5. DREAMPlace DREAMPlace Public

    Forked from limbo018/DREAMPlace

    Deep learning toolkit-enabled VLSI placement

    C++

  6. openlane2 openlane2 Public

    Forked from efabless/openlane2

    The next generation of OpenLane, rewritten from scratch with a modular architecture

    Python

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