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Commits on Apr 10, 2025

• test: add and refactor seed data for testing (#454)

  allrob23

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  7dc29c2

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Commits on Jan 15, 2025

• Update CIflow to track with changes for ghdl-ci, #449 (#450)

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  davekeeshan

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  d0b9b7d

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Commits on Dec 21, 2024

• Class based design (#447)

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  josyb

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  a9d65c0

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Commits on Oct 5, 2024

• Fix Icarus cosimulation vpi bug for static signals (#444)

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  chiplukes

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  f0da5a6

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Commits on Aug 7, 2024

• blocked intialstaion of TristateSignals (#439)

  josyb

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  75bb3a7

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Commits on Jun 14, 2024

• _toVerilog.py: 'skip_zero_mem_init': repaired test for 'zero' value :( (#433)

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  josyb

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  e3b4d52

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Commits on Jun 12, 2024

• _toVerilog.py: 'skip_zero_mem_init': added *forgotten* condition taht the initail value must be zero to be able to skip the genberation of the initial block (#432)

  josyb

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  ac9b87c

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Commits on Jun 11, 2024

• _toVerilog.py: expanding `initial_values` kwarg to add 'skip_zero_mem_init' choice to skip generating initial block when all values are zero (#431)

  josyb

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  6520f32

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Commits on Jun 3, 2024

• Removed support for Python 3.7 (which is End Of Life since 2023-06-27) (#430)

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  josyb

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  e356d8a

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Commits on Feb 4, 2024

• Init list of enums (#428)

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  josyb

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  e95762e

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• Change how windows does pip install (#427)

  davekeeshan

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  9f25c07

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Commits on Feb 3, 2024

• corrected .vcd representation for array of enums (#426)

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  josyb

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  a0bebbf

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Commits on Oct 19, 2023

• **OpenPort** for unused outputs (#424)

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  josyb

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  7cef85c

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• **Constant** signals (#423)

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  josyb

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  15104a0

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Commits on Oct 5, 2023

• Fix pip install on windows (#422)

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  davekeeshan

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  4081474

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Commits on Apr 26, 2023

• doc: added expalantion of how reset opoerates on ListOfSignals (#417)

  josyb

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  7e235fc

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Commits on Apr 10, 2023

• Cleaning up tests: (#412)

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  josyb

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  ef206f0

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Commits on Apr 5, 2023

• Updating README.md to show alternative solutions to install MyHDL (#415)

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  josyb

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  4f8b1df

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Commits on Feb 8, 2023

• Add windows actions, python3.11 for core and ghdl (#410)

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  davekeeshan

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  5ec3d08

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Commits on Feb 3, 2023

• True case statment mapping support (#408)

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  davekeeshan

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  35bd903

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• Constant value inversion (~0x1, ~0x4523) not working in VHDL (#407)

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  davekeeshan

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  1dd830f

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Commits on Jan 19, 2023

• Binops convert in VHDL fix (#404)

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  davekeeshan

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  0c38f94

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Commits on Dec 24, 2022

• Raise traceSignals to DeprecationWarning from UserWarning (#401)

  davekeeshan

  authored
  7c6a5fd

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Commits on Dec 18, 2022

• Release 0.11.42 (#400)

  josyb

  authored
  da9adf8

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• Clean PyPi release flow 17/12/2022 (#399)

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  davekeeshan

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  3775119

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Commits on Dec 17, 2022

• Update makeflow (#396)

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  davekeeshan

  authored
  f8022d3

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Commits on Dec 7, 2022

• Update flow to compile and used cached version of tools (#387)

  davekeeshan

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  b85c166

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Commits on Nov 16, 2022

• Merge pull request #383 from jtremesay/patch-1

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  jck

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  d9054d3

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Commits on Nov 15, 2022

• Fix a typo in an error message

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  Jonathan Tremesaygues

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  504f46a

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Commits on Nov 4, 2022

• add python 3.11 to ci matrix (#382)

  jck

  authored
  32c9c7a

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Commits on Oct 10, 2022

• Added missing visit_NameConnstant() for Python versions 3.7 adn 3.8 (#380)

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  josyb

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  279941b

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Commits on Aug 2, 2022

• Removed testing with Python 3.6 - EOL <> Added testing with PyPy 3.9 (#376)

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  josyb

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  79cf221

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Commits on Aug 1, 2022

• Conversion with recursive ShadowSignals (#359)

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  josyb

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  e6ac732

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Commits on Jul 4, 2022

• [ENH] Updated the ConcatSignal conversion code to check for undriven … (#371)

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  tobygomersall

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  0477c7e

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Commits on May 24, 2022

• Removed 'casez' in Verilog onehot / onecold state encoding (#357)

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  josyb

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  ae25af4

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