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Commits on Apr 27, 2025

• Fixed UART endianess. The uart16550 and pcie_7x_aximm_msi_bd is now proved in TimeCard

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• Added UART XDC (with TX/RX SMA )

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  6b806d7

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• Added litepcie auto build files

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  94414df

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• Fix

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  ea0973d

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• Added UART auto build scripts

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  1415468

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• Updated litepcie with regular_comb=False

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Commits on Apr 1, 2025

• Added example kernel driver for Multi-Vector MSI

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• Added wrapper for Litex litepcie

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  9d0ba0e

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• Added litepcie tcl pcie_s7 generator

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  1275d78

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• Added experimental litepcie gateware

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• Updated MSI test case for multi-vector MSI

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Commits on Mar 30, 2025

• Changed default MSI vector from 0 to 5-bits (max of 32)

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Commits on Mar 20, 2025

• Added aximm_msi_bd for block design

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Commits on Mar 16, 2025

• Updated readme links

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  d9e5e7b

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• Added Makefiles

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  f17a67e

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• Updated documents

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  7b6b0ff

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• Added files for automatic Makefile gen

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Commits on Mar 14, 2025

• Added more documentation

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  4dd1b97

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Commits on Mar 10, 2025

• Added uSDR PCIe Gen2 guide

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  eec1d12

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• Added MSI interrupt kernel driver

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• Added MSI interrupt document and verilog code

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Commits on Mar 3, 2025

• Updated user clock frequency to 125 MHz on Gen2

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• Now supports Gen2 in both Vivado and OpenXC7

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  52bcd05

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• Supported uSDR PCIe Gen1

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  0215369

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Commits on Mar 1, 2025

• Optimized for OpenXC7

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  0ee1fc8

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Commits on Nov 29, 2024

• Fixed signal in block

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  927379a

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• Updated license

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  6b8c404

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Commits on Nov 24, 2024

• Added AXIMM module w/o testing

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  87cfb71

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• Added AXIS to AXI converter, and minimal AXI MM

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  05f36d7

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Commits on Nov 1, 2024

• Updated README

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  067b226

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Commits on Oct 15, 2024

• Release initial version

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