Overall CDH requirements #38
Description
CDH Board
The CDH Board is responsible only for logging and monitoring all events that occur on the satellite as it issues telecommands.
The development workflow is as follows:
ConOps -> Extract a state diagram off of the ConOps -> Implement the state Diagram as such.
| Function | Signal | MCU Pin | Type | Notes |
|---|---|---|---|---|
| 1. Main I2C | MAIN_SCL | TBD | I2C | Main I2C clock line (CDH ↔ external devices). |
| MAIN_SDA | TBD | I2C | Main I2C data line. | |
| 2. Redundant I2C | RED_SCL | TBD | I2C | Redundant I2C clock line. |
| RED_SDA | TBD | I2C | Redundant I2C data line. | |
| 3. Local/Debug I2C | RX_SCL | TBD | I2C/GPIO | I2C clock for RX module or debug lines (per design). |
| RX_SDA | TBD | I2C/GPIO | I2C data for RX module. | |
| RX_EN | TBD | GPIO | Receiver enable. | |
| TX_SCL | TBD | I2C/GPIO | I2C clock for TX module. | |
| TX_SDA | TBD | I2C/GPIO | I2C data for TX module. | |
| TX_EN | TBD | GPIO | Transmitter enable. | |
| LVDS_UART_RX_EN | TBD | GPIO | LVDS UART receiver enable. | |
| LVDS_UART_TX_EN | TBD | GPIO | LVDS UART transmitter enable. | |
| LVDS_EN | TBD | GPIO | LVDS interface enable (general). | |
| LOCAL_I2C_DIS | TBD | GPIO | Disconnect local I2C devices if needed. | |
| 4. External RAM (SPI) | SCK | TBD | SPI | SPI clock for external RAM. |
| MISO | TBD | SPI | SPI Master-In Slave-Out. | |
| MOSI | TBD | SPI | SPI Master-Out Slave-In. | |
| RAM_CS1 | TBD | GPIO | Chip Select for external RAM #1. | |
| RAM_CS2 | TBD | GPIO | Chip Select for external RAM #2 (if present). | |
| RAM_EN | TBD | GPIO | Enable line (power or interface) for external RAM. | |
| RAM_WP | TBD | GPIO | Write-protect for external RAM. | |
| 5. ADCS Control | ADCS_QF | TBD | GPIO | “Quick-Fire” or special ADCS command line. |
| ADCS_MEC_DIS | TBD | GPIO | Disable ADCS mechanical actuators (reaction wheels, etc.). | |
| ADCS_MEC2_DIS | TBD | GPIO | Second mechanical disable line if multiple actuators. | |
| ADCS_RCS_DIS | TBD | GPIO | Disable RCS thrusters (if applicable). | |
| 6. BMS (Battery Management) | BMS_CS | TBD | GPIO | Chip Select or enable line for BMS. |
| BMS_EN | TBD | GPIO | Power/communication enable for BMS. | |
| BMS_REC_DIS | TBD | GPIO | Disable BMS receiver or interface. | |
| BMS_IRQ | TBD | GPIO | BMS interrupt or fault flag to the MCU. | |
| 7. HMS (another subsystem) | HMS_CS | TBD | GPIO | Chip Select or enable line for HMS. |
| HMS_EN | TBD | GPIO | Power/communication enable for HMS. | |
| HMS_REC_DIS | TBD | GPIO | Disable HMS receiver or interface. | |
| HMS_IRQ | TBD | GPIO | HMS interrupt or fault flag to the MCU. | |
| 8. Imager (if present) | IMAGER_EN | TBD | GPIO | Enable line for Imager subsystem. |
| IMAGER_REC_DIS | TBD | GPIO | Disable Imager receiver or interface. | |
| IMAGER_IRQ | TBD | GPIO | Imager interrupt or status line. | |
| 9. Wi-Fi (if present) | WIFI_EN | TBD | GPIO | Enable line for Wi-Fi module. |
| WIFI_REC_DIS | TBD | GPIO | Disable Wi-Fi receiver/interface. | |
| WIFI_IRQ | TBD | GPIO | Wi-Fi interrupt or status line. | |
| 10. PIB (if present) | PIB_EN | TBD | GPIO | Enable line for PIB subsystem. |
| PIB_IRQ | TBD | GPIO | PIB interrupt or status line. | |
| 11. H-Bridge (if present) | HBRIDGE_EN | TBD | GPIO | Enable line for H-Bridge driver. |
| HBRIDGE_IRQ | TBD | GPIO | H-Bridge interrupt or fault flag. | |
| 12. Misc Signals | MISC1 | TBD | GPIO | General-purpose or spare line #1. |
| MISC2 | TBD | GPIO | General-purpose or spare line #2. | |
| MISC3 | TBD | GPIO | General-purpose or spare line #3. | |
| MISC4 | TBD | GPIO | General-purpose or spare line #4. | |
| 13. Transceiver Control | TRANS_ON | TBD | GPIO | Turn transceiver on. |
| TRANS_OFF | TBD | GPIO | Turn transceiver off. | |
| TRANS_REC_DIS | TBD | GPIO | Disable transceiver receiver. | |
| 14. Watchdog & Heater | WDT_SR | TBD | GPIO | Watchdog status/reset signal. |
| WDT_WRN | TBD | GPIO | Watchdog warning line. | |
| HEATER_Debug | TBD | GPIO | Debug line or override for heater control. | |
| 15. Misc/Debug | InCA | TBD | GPIO | Possibly “In-Circuit Adapter” input or external trigger. |
| UART_Debug | TBD | UART | Debug UART TX/RX line (if a single net). | |
| UART_Dis | TBD | GPIO | Possibly disables the debug UART. | |
| 16. JTAG | TCK | TBD | JTAG | JTAG clock. |
| TMS | TBD | JTAG | JTAG mode select. | |
| TDI | TBD | JTAG | JTAG data in. | |
| TDO | TBD | JTAG | JTAG data out. | |
| TEST | TBD | JTAG | Test pin (sometimes for manufacturing/boundary scan). | |
| RESET | TBD | RESET | JTAG reset (if separate from main nRESET). | |
| 17. Other Reset/Erase | ERASE | TBD | GPIO/Reset | SAMV71 erase pin (if exposed). |
| nRESET | TBD | RESET | Main hardware reset (active low). | |
| JTAGSEL | TBD | GPIO | Selects JTAG vs. SWD (depends on SAMV71 config). |
Additional Information
MRAM1 is used to do this.
MRAM2 is used to store the golden copy of the chip.
The section below highlights the functionality of each of the pins available.