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cv32e40s Public
Forked from openhwgroup/cv32e40s4 stage, in-order, secure RISC-V core based on the CV32E40P
SystemVerilog Other UpdatedOct 31, 2024 -
cv32e40x Public
Forked from openhwgroup/cv32e40x4 stage, in-order, compute RISC-V core based on the CV32E40P
SystemVerilog Other UpdatedNov 23, 2023 -
core-v-verif Public
Forked from openhwgroup/core-v-verifFunctional verification project for the CORE-V family of RISC-V cores.
Assembly Other UpdatedFeb 23, 2023 -
core-v-xif Public
Forked from openhwgroup/core-v-xifRISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
UpdatedOct 29, 2021 -
cv32e41p Public
Forked from openhwgroup/cv32e41p4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions
SystemVerilog Other UpdatedAug 31, 2021 -
cv32e40p Public
Forked from openhwgroup/cv32e40pCV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
SystemVerilog Other UpdatedDec 4, 2020 -
core-v-docs Public
Forked from openhwgroup/programsDocumentation for the OpenHW Group's set of CORE-V RISC-V cores
Python Other UpdatedNov 17, 2020
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