Hi,

I’m currently synthesizing Gemmini with Cadence Genus using the following configuration:

• Array size: 32×32
• Datatype: INT16

At the moment, the achievable Fmax is around 500 MHz, whereas our target is closer to 1 GHz. Based on the published Gemmini ASIC implementation paper, this seems to align with expectations.

My questions are:

• Are there any configuration options that could help improve Fmax? For example, tiling the PE array into a smaller mesh or enabling specific pipeline options?
• If microarchitectural modifications are necessary, which modules would be the best candidates to investigate first?

Thanks in advance for your guidance.

Best regards,
JJ