v0.7.1 Release #298
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v0.7.1 Release #298
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Offloads depthwise convolution scheduling onto the loop-unroller FSM. This improves MobileNet performance by 2-3x. Also adds more printfs to `mobilenet.c` to show the performance of each individual layer.
Also, fix MIDAS builds
This enables correct functionality of gemmini when sbus width != 16 bytes.
When testing ucb-bar/chipyard#1239, the new FIRRTL compiler errors when modules are named module. This avoids this issue.
Some of the updates made for the MLSys tutorial are also useful for general users. This PR merges in those changes.
PE was not synthesizing properly on the FPGA since it was synthesizing multiple mac units in a single PE. I added a new mac unit class and instantiate a single mac unit per PE to reduce area over head. This addresses #262 Co-authored-by: Hasan Genc <[email protected]> Co-authored-by: Eric Dong <[email protected]>
Remove parenthesized forms of asUInt(), asBool(), asSInt(), orR(), andR(), zext() Co-authored-by: Abraham Gonzalez <[email protected]> Co-authored-by: Hasan Genc <[email protected]> Co-authored-by: joey0320 <[email protected]>
--------- Co-authored-by: Hasan Genc <[email protected]>
* Bump gemmini-rocc-tests to get fix for gcc12 * Add Lean Config
add printf config for tutorials
Add smoke test | Support Gemmini spike
Bump to latest rocket-chip/chisel3.5.6
jerryz123
approved these changes
May 22, 2023
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@jerryz123 |
Thanks |
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Can you do a merge commit here? It makes the chipyard side a bit easier. |
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This is an incremental release: