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Linux kernel map

Python 1,139 143 Updated May 5, 2025

Apple iSight with a Raspberry Pi inside

Shell 477 24 Updated Mar 30, 2025

RISC-V vector and tensor compute extensions for Vortex GPGPU acceleration for ML workloads. Optimized for transformer models, CNNs, and generative AI with configurable precision (FP32/16/BF16/INT8).

Verilog 17 2 Updated Apr 25, 2025

A python CAD programming library

Python 1,040 132 Updated Oct 24, 2025

An open source GPU based off of the AMD Southern Islands ISA.

Verilog 1,249 253 Updated Aug 18, 2025

Tiny truly local voice-activated LLM Agent that runs on a Raspberry Pi

JavaScript 222 35 Updated Oct 23, 2025

Small and low cost FPGA educational and development board

632 84 Updated Feb 10, 2025

ZSBand - the Open Source Zephyr™ based Smart Band Firmware based on Xiaomi Mi Band 4 HW.

Python 16 Updated Jul 20, 2025

ZEReader is an open source hardware and software E-Book Reader platform. Originally developed as a bachelor's thesis in electrical engineering, the project now evolves as a hobby initiative dedicat…

C 111 4 Updated Nov 2, 2025

ZMK Firmware Repository

C 3,628 3,553 Updated Oct 20, 2025

ZSWatch - the Open Source Zephyr™ based Smartwatch, including both HW and FW.

C 3,009 272 Updated Oct 25, 2025

A research shell for Alveo V80

C++ 1 Updated Jun 30, 2025
Python 91 15 Updated Sep 26, 2025

Xilinx Tcl Store

Tcl 368 195 Updated Oct 8, 2025
C++ 36 8 Updated Mar 31, 2025

LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled

Verilog 66 14 Updated Oct 9, 2025

Fixed point math library for SystemVerilog

SystemVerilog 36 3 Updated Nov 14, 2024

VUnit is a unit testing framework for VHDL/SystemVerilog

VHDL 794 284 Updated Aug 13, 2025

Open, Modular, Deep Learning Accelerator

Scala 312 86 Updated Apr 10, 2024

ONNXim is a fast cycle-level simulator that can model multi-core NPUs for DNN inference

C++ 160 27 Updated Feb 10, 2025

mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)

C++ 65 11 Updated Oct 30, 2025

NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators

C++ 44 8 Updated Jan 2, 2025

A GPU acceleration flow for RTL simulation with batch stimulus

C++ 115 8 Updated Apr 1, 2024

FPGA-based neural network inference project for 2020 DAC System Design Contest

C 115 38 Updated Feb 22, 2021

BISMO: A Scalable Bit-Serial Matrix Multiplication Overlay for Reconfigurable Computing

Scala 144 31 Updated Dec 25, 2019

Python-based Hardware Design Processing Toolkit for Verilog HDL

Python 754 206 Updated Jun 15, 2024

IC implementation of TPU

Verilog 135 29 Updated Dec 18, 2019

Antmicro's open hardware baseboard for the Google Coral i.MX8 + Edge TPU SoM

79 30 Updated Aug 7, 2023
SystemVerilog 109 11 Updated Aug 14, 2025

OpenSource GPU, in Verilog, loosely based on RISC-V ISA

SystemVerilog 1,109 127 Updated Nov 22, 2024
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