Digital Realization of AdEx Neuron Model with Two-Fold Lookup Table

Abstract

This paper presents a novel approach to reduce the storage size of lookup tables and hardware resource consumption whilst implementing the adaptive-exponential integrate and fire neuron model. This approach uses a two-fold lookup table architecture, an exponent - lookup table and a fractional - lookup tTable, and a pair of logical shift registers to approximate the exponential function. The proposed technique is synthesised and simulated using Verilog as a proof of concept. The model, which is tested with a 64 kHz clock, had a latency of 31.25 s to retrieve data from the two lookup tables. The simulation results show that the two-fold lookup table requires 64.2% less storage than a conventional single lookup table with an average error of 0.14%. Furthermore, the use of shift registers negates the need for multipliers, thereby reducing the latency, power consumption, and hardware initialisation, making the proposed model suitable for large-scale neuromorphic and biologically inspired neural network implementations targeting low-cost hardware platforms. In addition, the proposed model also generates different spiking patterns of the neuron with minimal computational error.