Abstract
WebAssembly is a promising bytecode virtualization technology for embedded systems. WebAssembly interpreters for embedded demonstrate strong isolation and portability. However, they come with a significant performance penalty compared to direct bare-metal execution or compiled WebAssembly code. This creates demand for interpreter optimization. In this work, we present an approach that increases the execution speed of interpreted WASM code by offloading computed GOTOs, as used in interpreters, to a hardware accelerator. We describe the accelerator’s hardware design, as well as the integration in the popular WebAssembly Micro Runtime (WAMR). To prove the functionality and effectiveness of our approach, we integrate the accelerator into an open-source RISC-V processor core and evaluate WASM interpretation using different benchmarks. Our results show that the approach significantly increases execution speed while only creating minimal code size overhead. Finally, we give an outlook on possible future improvements of the accelerator.
This project received funding from the Chips Joint Undertaking project ISOLDE (No. 101112274) and BMBF project 16MEE0372.
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Rupp, M., Schröter, J., Wallentowitz, S. (2024). Accelerating WebAssembly Interpreters in Embedded Systems Through Hardware-Assisted Dispatching. In: Fey, D., Stabernack, B., Lankes, S., Pacher, M., Pionteck, T. (eds) Architecture of Computing Systems. ARCS 2024. Lecture Notes in Computer Science, vol 14842. Springer, Cham. https://doi.org/10.1007/978-3-031-66146-4_14
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