Abstract
One key issue in the design of Real-Time Image Processing and Computer Vision (IP/CV) systems is the massive volume of data to process. Not only the number of arithmetic and logic operations over the data but also the access to these data represents an important issue. An Application-Specific Instruction Set Processor (ASIP) focused on Real-Time IP/CV algorithms was developed in this work. Starting from a standard 32-bit Reduced Instruction Set Computer (RISC) as a benchmark, we analyzed the different issues and optimized the processor incrementally. We derived an economical image memory partition and also a new data path concept to speed up the processing. RTL models were synthesized for an FPGA, enabling an analysis of power consumption, area, and processing speed, to show the corresponding overheads in comparison with the original processor architecture.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Similar content being viewed by others
References
Brost, V., Meunier, C., Saptono, D., Yang, F.: Flexible vliw processor based on fpga for real-time image processing. In: 2011 Conference on Design and Architectures for Signal and Image Processing (DASIP), pp. 1–8, November 2011
Diamantopoulos, D., Siozios, K., Lentaris, G., Soudris, D., Rodrigalvarez, M.: Spartan project: on profiling computer vision algorithms for rover navigation. In: 2012 NASA/ESA Conference on Adaptive Hardware and Systems (AHS), pp. 174–181, June 2012
Hoozemans, J., Wong, S., Al-Ars, Z.: Using vliw softcore processors for image processing applications. In: Proceedings of the 15th International Conference on Systems, Architectures, Modeling and Simulation (SAMOS) (2015)
Kehtarnavaz, N., Gamadia, M.: Real-time image and video processing: from research to reality. Synth. Lect. Image Video Multimedia Process. 2(1), 1–108 (2006)
Mori, J., Huebner, M.: A high-level analysis of a multi-core vision processor using systemc and tlm2.0. In: 2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig), pp. 1–6, December 2014
Mori, J., Sanchez-Ferreira, C., Llanos, C.: Real-time image processing based on neighborhood operations using fpga. In: Proceedings of the XVIII International IBERCHIP Workshop, February 2012
Musoromy, Z., Bensaali, F., Ramalingam, S., Pissanidis, G.: Comparison of real-time dsp-based edge detection techniques for license plate detection. In: 2010 Sixth International Conference on Information Assurance and Security (IAS), pp. 323–328, August 2010
Schliebusch, O., Meyr, H., Leupers, R.: Optimized ASIP Synthesis from Architecture Description Language Models. Springer, The Netherlands (2007)
Acknowledgment
CAPES Foundation/Brazilian Ministry of Education (Science without Borders Program, Grant Process Nr. 9054-13-8) and the University of Brasilia.
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2016 Springer International Publishing Switzerland
About this paper
Cite this paper
Mori, J.Y., Kautz, F., Hübner, M. (2016). Efficient Camera Input System and Memory Partition for a Vision Soft-Processor. In: Bonato, V., Bouganis, C., Gorgon, M. (eds) Applied Reconfigurable Computing. ARC 2016. Lecture Notes in Computer Science(), vol 9625. Springer, Cham. https://doi.org/10.1007/978-3-319-30481-6_27
Download citation
DOI: https://doi.org/10.1007/978-3-319-30481-6_27
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-319-30480-9
Online ISBN: 978-3-319-30481-6
eBook Packages: Computer ScienceComputer Science (R0)