1 Introduction

In modern industrial sectors, automation utilizing serial or parallel manipulators has become increasingly important. In such production environments, robots often operate in isolation from human workers, performing repetitive tasks autonomously. However, in the event of a malfunction within a production line, human intervention is required to abort and reset the process chain, leading to decreased productivity and reduced overall throughput.

Furthermore, a significant number of occupational injuries occur annually due to hazardous industrial working conditions. Such hazardous environments may also exist in domestic workspaces. Whether in industrial or household settings, the risk of injury could be mitigated through the implementation of intelligent sensor systems capable of detecting and classifying objects, specifically humans, within these hazardous areas. Additionally, industrial efficiency can be substantially improved through the integration of collaborative sensing robots within production floors, facilitating seamless human-robot interaction [1,2,3,4].

Over the past decade, extensive research has been conducted on vision-based and optical sensing methodologies for robotic guidance. However, these approaches have demonstrated limited effectiveness in harsh industrial environments. More recently, capacitive-based proximity sensing systems have gained importance due to their superior performance under challenging conditions. Detecting humans and machinery in presence of dirt and mechanical disturbances presents a considerable challenge. Despite these adverse conditions, proximity sensing technologies have the potential to enable critical tasks such as decision-making, safety control, path planning, and gesture recognition within human-robot interactive settings, even at moderate operational speeds, leveraging advancements in sensing and signal processing for robotic perception and control.

For integration of capacitive proximity and gesture sensing on the robot surface in a flexible artificial skin, the sensing electronics must be highly miniaturized and has therefore been implemented as an application specific integrated circuit (ASIC). Also, the power consumption of such devices plays a major role, in particular when the devices should be operated in a wireless system. Many approaches for integrated capacitive sensor frontends have been suggested. An overview and comparison of such approaches is provided in [5]. In conclusion of this comparison, Sigma-Delta (Σ∆) capacitance-to-digital converters offer a compelling balance of performance characteristics. However, when electrode sizes increase—a common scenario in applications like proximity sensing—the power consumption of the driver circuitry can become significant. This work specifically addresses this limitation.

Capacitive sensing is realized by an array of electrodes mounted on the curved surface of a robot arm as shown in Fig. 1. The sensing principle is based on the measurement of the environmental dielectric constant variation in presence of objects or humans in proximity of the robot. The variation of dielectric constant is reflected in a variation of the electrode capacitance. This can be monitored by exciting the electrode array with sinusoidal voltages and measuring the frequency dependent amplitude and phase of the electrode displacement currents, which is known as Electrical Capacitance Tomography (ECT) [6,7,8]. The capacitance of the electrode is determined by the sensing capacitance (1 fF to 1 pF) and the parasitic capacitance [9], which can be thousand times larger than the sensing capacitance (>100 pF). High excitation signal amplitudes and frequencies up to several MHz therefore lead to high power consumption of the driver circuit. Driver power efficiency is an important design consideration. Another important aspect is the co-existence in the sensor array. A narrow band excitation signal could cause interference in their operation, leading to performance reduction [3]. Therefore, spread spectrum operation can be used, which leads to wide bandwidth requirements for the driver circuit from few kHz up to several MHz. Broad band excitation also offers the additional advantage, that the frequency dependency of the parasitic impedance can be exploited towards classification [10]. The proposed sensor front-end ASIC includes a fully on-chip broadband (10 kHz to 10 MHz) class‑D switching mode driver for power efficient driving of high-capacitance sensors up to several hundred pF parasitic capacitance. The measurement of small displacement current variations in noisy surroundings require strong signal amplification. Therefore, a differential current measurement circuit with high-gain, high common mode rejection ration (CMRR), low offset and low noise has been realized on the proposed ASIC [4, 11].

This paper introduces a capacitive sensing ASIC in 65 nm CDMOS technology, mounted on a flexible and stretchable substrate (skin), designed for human-robot collaborative environments. The ASIC includes a fully integrated wide-band class‑D driver with high power efficiency and without off-chip LC circuit components. The driving amplifier is combined with a current measurement circuit. The capacitive sensing principle is outlined in Sect. 2, followed by a detailed description of the class‑D driver and current measurement circuit implementation in Sect. 3. Section 4 summarizes the chip integration in flexible substrates, and Sect. 5 concludes with a lab verification of the sensor ASIC.

2 Principle of capacitive sensing

A proximity sensor based on capacitive sensing is used to detect the presence of a person. The underlying measurement principle is based on the interaction between a human body and an electric field as the individual approaches the sensor’s electrodes. The proximity of a human hand to the electrode perturbs the electric field, resulting in a measurable change in capacitance, denoted CObject in Fig. 2, between the transmitter electrode and the distant ground reference (ZGND). For proximity sensing applications, the single-ended measurement mode is predominantly used, as shown in Fig. 2; [12]. In this configuration, the capacitance between the transmitter electrode and the distant ground is quantified. To facilitate this measurement, an excitation signal with a frequency between about 10 kHz up 10 MHz and an amplitude of \(1\,V_{pp}\) (peak-to-peak) is applied to the electrode. The resulting displacement current is then detected and analyzed using a dedicated current measurement unit.

Fig. 1
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Flexible skin on robot arm with integrated capacitive sensors

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Fig. 2
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Principle of capacitive sensing in single-ended measurement mode

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The measurement characteristics of the capacitive proximity sensor is significantly influenced by the shape and dimensions of the connected electrodes at the sensor’s front end, which can be customized based on specific application requirements. In this study, the electrode size is constrained by the geometric dimensions of a human finger. The surface area of the electrode is directly correlated with the maximum sensing range, as larger electrode surfaces enable the detection of objects at greater distances. However, an increase in electrode size also introduces higher susceptibility to external disturbances and noise. For a human finger with an correspondingly sized electrode, the capacitance CObject is expected to be in the range of 1 fF up to 1 pF. In the experimental setup utilized in this study, variations in capacitance are translated into displacement currents within the nano-Ampere range, providing a measurable electrical response for proximity sensing applications.

A block diagram of the capacitive sensing system in single-ended measurement mode is shown in Fig. 3. The system consists of a single active transmitter electrode (TX Electrode) with an active guard electrode below. The active guard driver is connected to both, the TX-electrode and the active guard electrode (node C in Fig. 3). Therefore, the active guard electrode is shielding the TX-electrode against a very high parasitic capacitance of about 50 pF to 1 nF (active guard capacitance CAG). The circuit design of the guard driver is presented in Sect. 3. The displacement current of the TX electrode is measured by a Current Measurement Unit (CMU). A series resistor (RShunt) is included in the TX electrode signal path (node A in Fig. 3). The displacement current varies typically in the range of nano-Ampere up to micro-Ampere. A single ended current measurement via RShunt is highly sensitive to process variation with a high dc-offset, which makes the measurement of small currents impossible. To ensure an accurate measurement, a differential structure is proposed, realized by a parallel branch with a dummy shunt resistor RShunt and a dummy capacitor CTX_Offchip for dc offset current compensation (node B in Fig. 3). The value of capacitor CTX_Offchip is aligned to the nominal capacitance of the transmit electrode CTX. This dummy capacitor is implemented off-chip for flexibility in demonstrator lab evaluation. An on-chip integration is easily possible for future implementation. The differential voltage is amplified by a high gain differential amplifier (AMP), followed by an analog-to-digital converter (A/D), with digital signal processing (eg. I/Q down-conversion of the excitation signal for complex impedance measurement) and a digital I2C interface. A detailed description of the amplifier design is given in section Sect. 3. The A/D conversion and digital signal processing are not discussed in this paper. For excitation signal an external signal source is used. The on-chip signal generation by direct digital synthesis (DDS) has already been realized as reported in [13].

Fig. 3
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Block diagram of the capacitive sensing system in single-ended measurement mode

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3 Circuit design

3.1 Class D active guard driver

An optimized driver circuit is required to drive the active guard electrode together with the TX electrode by a sinusoidal excitation signal of 1 Vpp in the frequency range of 10 kHz up to 10 MHz. The active guard electrode acts as a reference plane for the TX electrode to improve sensitivity. The parasitic capacitance of the guard electrode can be very high (up to 1 nF), resulting in high currents flowing to the reactive load. Typically, broadband fully on-chip driver circuits are designed using a linear topologies such as class AB amplifiers. To achieve the required bandwidth for high load capacitance, unity gain feedback driver topologies are required to reduce the output resistance, resulting in high power consumption. In addition, compensation of the feedback loop is a critical design task and its stability depends on the load capacitance. Finally, it is not easy to guarantee the required 1 Vpp output voltage swing with a linear amplifier circuit and a 1.2 V supply.

In order to mitigate these problems, this paper proposes a class D amplifier approach [14, 15]. The basic amplifier topology is shown in Fig. 4a. It is realized in a self-resonating feedback configuration as presented in Fig. 4b. In contrast to a class AB output stage, the output of the proposed class D amplifier is realized by NMOS and PMOS switches opened and closed sequentially. Therefore, the class D driver stage do not consume a dc current, but the overall power consumption is defined by dynamic switching losses. They can be minimized by ensuring low on-resistance of NMOS and PMOS switches and careful non-overlapping clock design for NMOS and PMOS gate drivers by a dead-time circuit.

Fig. 4
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Class D driver concept (a) and block diagram (b)

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The total power loss Ploss for a driving circuit based on the class D amplifier can be calculated as

$$P_{loss}=R_{ds,on}I^{2}_{out,avg} + C_{sw}V^{2}_{DD}f_{sw}$$
(1)

where Rds,on is the PMOS/NMOS drain-source on-resistance, \(I^{2}_{out,avg}\) is the average inductor current flowing to the load capacitor, Csw is the parasitic PMOS/NMOS output capacitance (gate-drain and drain-bulk capacitance), VDD is the supply voltage, and fsw is the driver switching frequency, defined by the PWM controller feedback loop. Due to lack of resistive load, the Iout,avg is nearly zero, and hence the total dissipated switching current loss iloss,sw is given by

$$i_{loss,sw}\approx C_{sw}V_{DD}f_{sw}.$$
(2)

For the specified requirements, the average dissipated current Iloss,sw is derived as 1.8 mA, with a parasitic capacitors of Csw = 0.5 pF and a switching frequency fsw = 300 MHz derived from circuit simulation with a 65 nm CMOS technology at a VDD of 1.2 V. Furthermore, unlike the current dissipated in the class AB amplifier, which is proportional to the input excitation signal frequency fin, the current loss of a class D amplifier for driving a large shield/electrode capacitance CAG is independent on fin.

As shown in Fig. 4b the class D driver is realized in a self-oscillating unity-gain feedback configuration and contains a PWM controller realized with a rail-rail analog comparator and dead-time circuit and gate drivers to create non-overlapping gate signals for the NMOS and PMOS power switches. The amplifier feedback loop is self-oscillating without external clock at high frequency of about 400 MHz, which ensures high signal bandwidth of several MHz for the input excitation signal, with reasonable low switching noise. All components including inductor are integrated on-chip. The load capacitance CAG is representing the off-chip capacitive sensor shielding and transmit electrode.

By utilizing the advantages of the proposed class D amplifier, high signal bandwidth can be realized. The circuit can drive a load CAG of 100 pF up to a signal frequency of 10 MHz or even 1 nF up to a frequency of 1 MHz, while maintaining the signal amplitude VExc = 1 Vpp, equal to the input excitation signal. The resonance frequency of the \(L-C_{AG}\) tank is about 90 MHz. As this is well above the maximum required signal bandwidth, it acts as a filter for switching harmonics and noise and allows a wide tuning range of the input signal.

The PWM comparator is a critical design block, as it required high speed performance to guarantee the PWM oscillation frequency of 400 MHz with continuous time operation and rail-to-rail input common-mode. The comparator circuit schematic with three amplification stages is shown in Fig. 5. The input signal is first pre-amplified by two complementary differential pairs in order to achieve rail-to-rail operation and to isolate the input of the comparator from switching noise (kick-back noise), which includes transistors \(M_{1} - M_{12}\). A positive feedback stage of transistors \(M_{13} - M_{18}\) is included as second stage to increase the gain. The output buffer of \(M_{19} - M_{25}\) post-amplifies the signal creating a rail-to-rail digital output. The comparator delay is designed to be 560 pS while the input offset voltage is 12 mV. The comparator bandwidth is about 400 MHz which covers the required switching frequency. The rail-to-rail analog comparator consumes 96 µW of power.

Fig. 5
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Schematic of rail-to-rail continuous time comparator

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3.2 Current measurement amplifier

A main building block of the current measurement unit (CMU) is a differential amplifier (AMP) as shown in Fig. 3. A fully differential amplifier configuration has been realized as two-stage architecture with the block diagram shown in Fig. 6; [11]. The overall gain is defined by resistive feedback of R2/R1 and R4/R3. The differential input voltage ranges from about 5 µV to 5 mV, while the input common mode varies from rail-to-rail with the excitation signal. Therefore, offset and noise are important design challenges. For offset optimization, high pass filter (HPF) has been implemented after the first stage of the amplifier by CHPF and RHPF with a cut-off frequency of 500 Hz. This avoids the need of complex clocking based topologies, like chopping and auto-zeroing to reduce the offset. For noise optimization, the Flicker-noise corner frequency was moved below the high-pass filter’s cut-off frequency by optimized dimensioning of the input stage.

Fig. 6
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Differential amplifier topology for measuring displacement current

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The low frequency open loop gain of a single amplifier stage is 64 dB with a phase margin of 60°. Input referred noise over the frequency band of 50 kHz to 5 MHz is 35 µV/\(\sqrt{\text{Hz}}\) with thermal noise of transistors and resistors as the main contribution. The overall closed-loop differential gain and CMRR for the two-stage topology of Fig. 6 are 34 dB (between 50 kHz and 5 MHz band-pass frequency) and 97 dB respectively. The amplifier layout area is 800 µm × 600 µm.

4 ASIC assembly

The proposed capacitive sensing ASIC is designed and fabricated in TSMC 65 nm CMOS technology for an electrode load capacitance of 400 pF. The ASIC has an overall area of 1 mm2 and includes two independent channels (Ch1 and Ch 2) as shown in Fig. 7a. Each channel can drive an independent active guard/transmitter electrode. The on-chip integrated inductor has an inductance of 6.5 nH. The ASIC supply voltage is 1.2 V. The reliability and performance of the sensing system may depend on how the chip is mounted on a substrate (e.g. flexible robot skin). Therefore, two configurations of chip assembly on board were evaluated, i.e. face-up chip assembly with wire bonding and flip-chip assembly, as shown in Fig. 7a, b. Wire bonding, as shown in Fig. 7a, is in general the most cost effective and flexible assembly method. But it might be more sensitive to mechanical stress of the substrate, especially for future stretchable skin implementation. Flip-chip bonding, as shown Fig. 7b, is a more modern assembly method for high numbers of IC pins, with improved electrical performance. The small solder bumps on the chip surface provide very short electrical connections with low resistance and significantly lower inductance. The chips were first bumped with Au stud bumps, and then picked and accurately placed onto the substrate PCB for verification by using a semi-automatic flip-chip bonder. The flip-chip assembly was made by using thermocompression bonding assisted by adhesives (anisotropic conductive paste) at 170°.

Fig. 7
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ASIC assembly by wire bonding (a) and flip chip bonding (b)

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5 Experimental setup and measurement results

For the ASIC lab characterization, the fabricated prototype ASIC is flip-chip mounted on an evaluation PCB as explained in Sect. 4. The lab evaluation setup is shown in Fig. 8. Sensing electrodes are connected by SMA cables and a software defined radio platform (USRP) X310 is used for A/D conversion and digital signal processing for proximity and gesture sensing. The driver output signal is monitored with an oscilloscope and a current meter is used for supply current measurement.

Fig. 8
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Experimental lab setup for ASIC evaluation

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5.1 Class-D driver circuit

The class‑D driver time and frequency behavior is characterized for different external load capacitance of no-load, 330 pF and 1 nF. A 1 Vpp sinusoidal excitation signal with varying frequency is applied to the driver by a signal generator. The driver linearity for different load capacitors at 500 kHz signal frequency is presented in Fig. 9, showing the frequency spectrum of the driver output signal. The amplitude to the output voltage at fundamental frequency is almost independent on the input reference frequency. However, as the capacitance load increases, the amplitude of the second and third harmonics increases. Their impact on the circuit performance can be suppressed by post-digital filtering. The transient behavior at higher signal frequency of 2 and 4 MHz is shown in Fig. 10.

Fig. 9
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Frequency spectrum of driver output voltage with 500 kHz sinusoidal reference input, with different load capacitors

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Fig. 10
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Driver transient output signal for 2 and 4 MHz with 100 pF load capacitor

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The driver power consumption and signal amplitude degradation has been characterized over a wide frequency range of 10 kHz to 10 MHz for different load capacitors up to 1 nF and a 1 Vpp sinusoidal input excitation signal. The measured power consumption is between 2 mA and 3 mA for all mentioned conditions. The output signal amplitude is degrading with increasing load capacitance. Assuming a maximum allowed signal loss of 10%, the maximum signal frequency is 4 MHz for a load capacitance of 100 pF, while the maximum signal frequency is decreasing to about 500 kHz for a 1 nF load capacitance.

5.2 Gesture sensing

A feasibility study for gesture sensing was performed according to [16], using the transmitter ASIC with flip chip bonding and without external components. For this application, the capacitance between two sensor electrodes with a spatial separation of four centimeters were evaluated. The ASIC was used to provide the excitation signal to the transmitter electrode and the received signal was processed using a synchronous demodulation in the USRP software defined radio framework for rapid prototyping [17]. A carrier frequency of 1 MHz and a signal amplitude of 800 mVpp was used. Figure 11a shows the corresponding signals and the evaluation of as gesture with a motion of a human hand approximately 10 cm above the sensor. By determination of the time shift using a cross correlation approach shown in Fig. 11b, the direction of motion can be observed.

Fig. 11
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Gesture sensing application with a raw signals for two electrodes and b Cross correlation of the signals. The peak corresponds to the time delay

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6 Conclusion

We have presented an ASIC with fully integrated broad-band class‑D driver circuit, with high power efficiency to generate excitation signals for capacitive sensors without additional external components. It can be deployed in collaborative robotics environment, as demonstrated in a gesture sensing application scenario. Furthermore, an integrated current measurement circuit has been proposed, to amplify small displacement currents variation through capacitive sensing electrodes in the range of 1 µA to 1 mA. The results of the experiments indicate, that the proposed driver circuit can efficiently provide excitation signals to large surface electrodes of capacitive sensors with parasitic capacitance of up to 1 nF throughout a wide frequency range of 10 kHz to 10 MHz. The considered driver circuit is designed and fabricated in a TSMC 65 nm CMOS technology. The lowest power consumption is 1.92 mA in the setup of 1 nF load capacitance and 1 MHz excitation frequency. Both, wire bonding and flip-chip bonding has been demonstrated for ASIC assembly. The sensing performance for both assembly methods is similar.