A structural verilog parser written in Rust.

Usage

Just pass an [ArcStr] to SVerilog::parse_str. Example:

use sverilogparse::SVerilog;

let _parsed = SVerilog::parse_str(arcstr::literal!(r#"
module simple (a, b);
input a;
output b;
not n1 (.a(a), .out(b));
endmodule
"#)).expect("parse error");

sverilogparse: Structural Verilog Parser in Rust

This is a structural verilog parser written in Rust.

Similar project: https://github.com/OpenTimer/Parser-Verilog