Remove unnecessary tests in merge_three_reg_mov #15197
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`merge_three_reg_mov` tries to combine the output register of certain instructions (add, sub, etc) with following register copy instructions (mov). For example: ``` add out, a, b mov c, out ``` Becomes: ``` add c, a, b ``` `out` and `c` are combined, but only if out's live range ends at the `mov` instruction and the mov's output is a register. The tests on add's input are not necessary because we only care about the output. Co-Authored-By: Aiden Fox Ivey <[email protected]>
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XrXr
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Makes sense. Please add a test that previously didn't optimize, though.
Do we not have tests for that already? |
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Ah, nevermind. I think understand. We need a test with |
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Yeah.. On second look I think these checks are load-bearing. Edit: 3 |
XrXr
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This possibly admits more cases. Previously when right was an immediate it did not attempt to merge. So would be nice to have a test for those situations.
I might need some help writing a test like that. It looks like our existing code knew that |
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This possibly admits more cases. Previously when right was an immediate it did not attempt to merge. So would be nice to have a test for those situations.
And the problem with admitting those cases is that what reg 31 refers to changes depends on whether it's sub reg, reg, reg versus sub reg, reg, immediate
With this patch when you have:
Sub ZeroReg(regno=31), 0xf => out
Mov c, out
it would turn it into Sub c, SP(regno=31), 0xf, changing the meaning of the code.
We should add tests/comment for this. Sorry, I had a hunch these checks are actually important but didn't document that enough.
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Sorry, I'm still not following 😢 Is this not the same as: I don't understand how the meaning would be changed. |
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Never mind, I get it. I guess we do need a test for that, but isn't the existing code susceptible to the same problem? Is ZeroReg not an |
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Sorry, my explanation was bad. turn into But |
merge_three_reg_movtries to combine the output register of certain instructions (add, sub, etc) with following register copy instructions (mov).For example:
Becomes:
outandcare combined, but only if out's live range ends at themovinstruction and the mov's output is a register. The tests on add's input are not necessary because we only care about the output.