shane | 9bcbdad | 2008-05-29 20:22:37 | [diff] [blame] | 1 | /* |
| 2 | ** 2008 May 27 |
| 3 | ** |
| 4 | ** The author disclaims copyright to this source code. In place of |
| 5 | ** a legal notice, here is a blessing: |
| 6 | ** |
| 7 | ** May you do good and not evil. |
| 8 | ** May you find forgiveness for yourself and forgive others. |
| 9 | ** May you share freely, never taking more than you give. |
| 10 | ** |
| 11 | ****************************************************************************** |
| 12 | ** |
| 13 | ** This file contains inline asm code for retrieving "high-performance" |
drh | 594b124 | 2019-11-20 12:07:40 | [diff] [blame] | 14 | ** counters for x86 and x86_64 class CPUs. |
shane | 9bcbdad | 2008-05-29 20:22:37 | [diff] [blame] | 15 | */ |
drh | 43f58d6 | 2016-07-09 16:14:45 | [diff] [blame] | 16 | #ifndef SQLITE_HWTIME_H |
| 17 | #define SQLITE_HWTIME_H |
shane | 9bcbdad | 2008-05-29 20:22:37 | [diff] [blame] | 18 | |
| 19 | /* |
larrybr | bc91738 | 2023-06-07 08:40:31 | [diff] [blame] | 20 | ** The following routine only works on Pentium-class (or newer) processors. |
shane | 9bcbdad | 2008-05-29 20:22:37 | [diff] [blame] | 21 | ** It uses the RDTSC opcode to read the cycle count value out of the |
| 22 | ** processor and returns that value. This can be used for high-res |
| 23 | ** profiling. |
| 24 | */ |
drh | 594b124 | 2019-11-20 12:07:40 | [diff] [blame] | 25 | #if !defined(__STRICT_ANSI__) && \ |
| 26 | (defined(__GNUC__) || defined(_MSC_VER)) && \ |
| 27 | (defined(i386) || defined(__i386__) || defined(_M_IX86)) |
shane | 9bcbdad | 2008-05-29 20:22:37 | [diff] [blame] | 28 | |
| 29 | #if defined(__GNUC__) |
| 30 | |
| 31 | __inline__ sqlite_uint64 sqlite3Hwtime(void){ |
| 32 | unsigned int lo, hi; |
shane | 9bcbdad | 2008-05-29 20:22:37 | [diff] [blame] | 33 | __asm__ __volatile__ ("rdtsc" : "=a" (lo), "=d" (hi)); |
| 34 | return (sqlite_uint64)hi << 32 | lo; |
| 35 | } |
| 36 | |
| 37 | #elif defined(_MSC_VER) |
| 38 | |
| 39 | __declspec(naked) __inline sqlite_uint64 __cdecl sqlite3Hwtime(void){ |
| 40 | __asm { |
| 41 | rdtsc |
| 42 | ret ; return value at EDX:EAX |
| 43 | } |
| 44 | } |
| 45 | |
| 46 | #endif |
| 47 | |
drh | 594b124 | 2019-11-20 12:07:40 | [diff] [blame] | 48 | #elif !defined(__STRICT_ANSI__) && (defined(__GNUC__) && defined(__x86_64__)) |
shane | b08c1d0 | 2008-06-12 02:24:38 | [diff] [blame] | 49 | |
| 50 | __inline__ sqlite_uint64 sqlite3Hwtime(void){ |
dan | a3d0c15 | 2022-12-05 18:19:56 | [diff] [blame] | 51 | unsigned int lo, hi; |
| 52 | __asm__ __volatile__ ("rdtsc" : "=a" (lo), "=d" (hi)); |
| 53 | return (sqlite_uint64)hi << 32 | lo; |
shane | b08c1d0 | 2008-06-12 02:24:38 | [diff] [blame] | 54 | } |
| 55 | |
drh | 594b124 | 2019-11-20 12:07:40 | [diff] [blame] | 56 | #elif !defined(__STRICT_ANSI__) && (defined(__GNUC__) && defined(__ppc__)) |
shane | 5cd89cf | 2008-08-01 14:33:15 | [diff] [blame] | 57 | |
| 58 | __inline__ sqlite_uint64 sqlite3Hwtime(void){ |
| 59 | unsigned long long retval; |
| 60 | unsigned long junk; |
| 61 | __asm__ __volatile__ ("\n\ |
| 62 | 1: mftbu %1\n\ |
| 63 | mftb %L0\n\ |
| 64 | mftbu %0\n\ |
| 65 | cmpw %0,%1\n\ |
| 66 | bne 1b" |
| 67 | : "=r" (retval), "=r" (junk)); |
| 68 | return retval; |
| 69 | } |
| 70 | |
shane | 9bcbdad | 2008-05-29 20:22:37 | [diff] [blame] | 71 | #else |
| 72 | |
shane | 9bcbdad | 2008-05-29 20:22:37 | [diff] [blame] | 73 | /* |
drh | 594b124 | 2019-11-20 12:07:40 | [diff] [blame] | 74 | ** asm() is needed for hardware timing support. Without asm(), |
| 75 | ** disable the sqlite3Hwtime() routine. |
| 76 | ** |
| 77 | ** sqlite3Hwtime() is only used for some obscure debugging |
| 78 | ** and analysis configurations, not in any deliverable, so this |
| 79 | ** should not be a great loss. |
shane | 9bcbdad | 2008-05-29 20:22:37 | [diff] [blame] | 80 | */ |
| 81 | sqlite_uint64 sqlite3Hwtime(void){ return ((sqlite_uint64)0); } |
| 82 | |
| 83 | #endif |
| 84 | |
drh | 43f58d6 | 2016-07-09 16:14:45 | [diff] [blame] | 85 | #endif /* !defined(SQLITE_HWTIME_H) */ |