From 9cbfe739cc709110593e636deaee6bff55c57aa0 Mon Sep 17 00:00:00 2001 From: Chen Wang Date: Wed, 4 Jun 2025 21:00:25 +0800 Subject: [PATCH 01/34] FROMLIST: dt-bindings: pci: Add Sophgo SG2042 PCIe host Add binding for Sophgo SG2042 PCIe host controller. Signed-off-by: Chen Wang Link: https://lore.kernel.org/r/5a784afde48c44b5a8f376f02c5f30ccff8a3312.1736923025.git.unicorn_wang@outlook.com Signed-off-by: Han Gao --- .../bindings/pci/sophgo,sg2042-pcie-host.yaml | 147 ++++++++++++++++++ 1 file changed, 147 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml diff --git a/Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml b/Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml new file mode 100644 index 00000000000000..f98e7182214428 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml @@ -0,0 +1,147 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/sophgo,sg2042-pcie-host.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sophgo SG2042 PCIe Host (Cadence PCIe Wrapper) + +description: + Sophgo SG2042 PCIe host controller is based on the Cadence PCIe core. + +maintainers: + - Chen Wang + +properties: + compatible: + const: sophgo,sg2042-pcie-host + + reg: + maxItems: 2 + + reg-names: + items: + - const: reg + - const: cfg + + vendor-id: + const: 0x1f1c + + device-id: + const: 0x2042 + + msi: + type: object + $ref: /schemas/interrupt-controller/msi-controller.yaml# + unevaluatedProperties: false + + properties: + compatible: + items: + - const: sophgo,sg2042-pcie-msi + + interrupts: + maxItems: 1 + + interrupt-names: + const: msi + + msi-parent: true + + sophgo,link-id: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + SG2042 uses Cadence IP, every IP is composed of 2 cores (called link0 + & link1 as Cadence's term). Each core corresponds to a host bridge, + and each host bridge has only one root port. Their configuration + registers are completely independent. SG2042 integrates two Cadence IPs, + so there can actually be up to four host bridges. "sophgo,link-id" is + used to identify which core/link the PCIe host bridge node corresponds to. + + The Cadence IP has two modes of operation, selected by a strap pin. + + In the single-link mode, the Cadence PCIe core instance associated + with Link0 is connected to all the lanes and the Cadence PCIe core + instance associated with Link1 is inactive. + + In the dual-link mode, the Cadence PCIe core instance associated + with Link0 is connected to the lower half of the lanes and the + Cadence PCIe core instance associated with Link1 is connected to + the upper half of the lanes. + + SG2042 contains 2 Cadence IPs and configures the Cores as below: + + +-- Core (Link0) <---> pcie_rc0 +-----------------+ + | | | + Cadence IP 1 --+ | cdns_pcie0_ctrl | + | | | + +-- Core (Link1) <---> disabled +-----------------+ + + +-- Core (Link0) <---> pcie_rc1 +-----------------+ + | | | + Cadence IP 2 --+ | cdns_pcie1_ctrl | + | | | + +-- Core (Link1) <---> pcie_rc2 +-----------------+ + + pcie_rcX is PCIe node ("sophgo,sg2042-pcie-host") defined in DTS. + + Sophgo defines some new register files to add support for their MSI + controller inside PCIe. These new register files are defined in DTS as + syscon node ("sophgo,sg2042-pcie-ctrl"), i.e. "cdns_pcie0_ctrl" / + "cdns_pcie1_ctrl". cdns_pcieX_ctrl contains some registers shared by + pcie_rcX, even two RC (Link)s may share different bits of the same + register. For example, cdns_pcie1_ctrl contains registers shared by + link0 & link1 for Cadence IP 2. + + "sophgo,link-id" is defined to distinguish the two RC's in one Cadence IP, + so we can know what registers (bits) we should use. + + sophgo,syscon-pcie-ctrl: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the PCIe System Controller DT node. It's required to + access some MSI operation registers shared by PCIe RCs. + +allOf: + - $ref: cdns-pcie-host.yaml# + +required: + - compatible + - reg + - reg-names + - vendor-id + - device-id + - sophgo,link-id + - sophgo,syscon-pcie-ctrl + +unevaluatedProperties: false + +examples: + - | + #include + + pcie@62000000 { + compatible = "sophgo,sg2042-pcie-host"; + device_type = "pci"; + reg = <0x62000000 0x00800000>, + <0x48000000 0x00001000>; + reg-names = "reg", "cfg"; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x81000000 0 0x00000000 0xde000000 0 0x00010000>, + <0x82000000 0 0xd0400000 0xd0400000 0 0x0d000000>; + bus-range = <0x00 0xff>; + vendor-id = <0x1f1c>; + device-id = <0x2042>; + cdns,no-bar-match-nbits = <48>; + sophgo,link-id = <0>; + sophgo,syscon-pcie-ctrl = <&cdns_pcie1_ctrl>; + msi-parent = <&msi_pcie>; + msi_pcie: msi { + compatible = "sophgo,sg2042-pcie-msi"; + msi-controller; + interrupt-parent = <&intc>; + interrupts = <123 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi"; + }; + }; From 9aee9bf8a4b516ed6f9339972229e39b71bb104c Mon Sep 17 00:00:00 2001 From: Chen Wang Date: Wed, 4 Jun 2025 21:00:36 +0800 Subject: [PATCH 02/34] FROMLIST: PCI: sg2042: Add Sophgo SG2042 PCIe driver Add support for PCIe controller in SG2042 SoC. The controller uses the Cadence PCIe core programmed by pcie-cadence*.c. The PCIe controller will work in host mode only. Signed-off-by: Chen Wang Link: https://lore.kernel.org/r/ddedd8f76f83fea2c6d3887132d2fe6f2a6a02c1.1736923025.git.unicorn_wang@outlook.com Signed-off-by: Han Gao --- drivers/pci/controller/cadence/Kconfig | 13 + drivers/pci/controller/cadence/Makefile | 1 + drivers/pci/controller/cadence/pcie-sg2042.c | 528 +++++++++++++++++++ 3 files changed, 542 insertions(+) create mode 100644 drivers/pci/controller/cadence/pcie-sg2042.c diff --git a/drivers/pci/controller/cadence/Kconfig b/drivers/pci/controller/cadence/Kconfig index 8a0044bb398924..292eb2b20e9c52 100644 --- a/drivers/pci/controller/cadence/Kconfig +++ b/drivers/pci/controller/cadence/Kconfig @@ -42,6 +42,18 @@ config PCIE_CADENCE_PLAT_EP endpoint mode. This PCIe controller may be embedded into many different vendors SoCs. +config PCIE_SG2042 + bool "Sophgo SG2042 PCIe controller (host mode)" + depends on ARCH_SOPHGO || COMPILE_TEST + depends on OF + select IRQ_MSI_LIB + select PCI_MSI + select PCIE_CADENCE_HOST + help + Say Y here if you want to support the Sophgo SG2042 PCIe platform + controller in host mode. Sophgo SG2042 PCIe controller uses Cadence + PCIe core. + config PCI_J721E bool @@ -67,4 +79,5 @@ config PCI_J721E_EP Say Y here if you want to support the TI J721E PCIe platform controller in endpoint mode. TI J721E PCIe controller uses Cadence PCIe core. + endmenu diff --git a/drivers/pci/controller/cadence/Makefile b/drivers/pci/controller/cadence/Makefile index 9bac5fb2f13dad..4df4456d953942 100644 --- a/drivers/pci/controller/cadence/Makefile +++ b/drivers/pci/controller/cadence/Makefile @@ -4,3 +4,4 @@ obj-$(CONFIG_PCIE_CADENCE_HOST) += pcie-cadence-host.o obj-$(CONFIG_PCIE_CADENCE_EP) += pcie-cadence-ep.o obj-$(CONFIG_PCIE_CADENCE_PLAT) += pcie-cadence-plat.o obj-$(CONFIG_PCI_J721E) += pci-j721e.o +obj-$(CONFIG_PCIE_SG2042) += pcie-sg2042.o diff --git a/drivers/pci/controller/cadence/pcie-sg2042.c b/drivers/pci/controller/cadence/pcie-sg2042.c new file mode 100644 index 00000000000000..56797c2af75508 --- /dev/null +++ b/drivers/pci/controller/cadence/pcie-sg2042.c @@ -0,0 +1,528 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * pcie-sg2042 - PCIe controller driver for Sophgo SG2042 SoC + * + * Copyright (C) 2024 Sophgo Technology Inc. + * Copyright (C) 2024 Chen Wang + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../../../irqchip/irq-msi-lib.h" + +#include "pcie-cadence.h" + +/* + * SG2042 PCIe controller supports two ways to report MSI: + * + * - Method A, the PCIe controller implements an MSI interrupt controller + * inside, and connect to PLIC upward through one interrupt line. + * Provides memory-mapped MSI address, and by programming the upper 32 + * bits of the address to zero, it can be compatible with old PCIe devices + * that only support 32-bit MSI address. + * + * - Method B, the PCIe controller connects to PLIC upward through an + * independent MSI controller "sophgo,sg2042-msi" on the SOC. The MSI + * controller provides multiple(up to 32) interrupt sources to PLIC. + * Compared with the first method, the advantage is that the interrupt + * source is expanded, but because for SG2042, the MSI address provided by + * the MSI controller is fixed and only supports 64-bit address(> 2^32), + * it is not compatible with old PCIe devices that only support 32-bit MSI + * address. + * + * Method A & B can be configured in DTS, default is Method B. + */ + +#define MAX_MSI_IRQS 8 +#define MAX_MSI_IRQS_PER_CTRL 1 +#define MAX_MSI_CTRLS (MAX_MSI_IRQS / MAX_MSI_IRQS_PER_CTRL) +#define MSI_DEF_NUM_VECTORS MAX_MSI_IRQS +#define BYTE_NUM_PER_MSI_VEC 4 + +#define REG_CLEAR 0x0804 +#define REG_STATUS 0x0810 +#define REG_LINK0_MSI_ADDR_SIZE 0x085C +#define REG_LINK1_MSI_ADDR_SIZE 0x080C +#define REG_LINK0_MSI_ADDR_LOW 0x0860 +#define REG_LINK0_MSI_ADDR_HIGH 0x0864 +#define REG_LINK1_MSI_ADDR_LOW 0x0868 +#define REG_LINK1_MSI_ADDR_HIGH 0x086C + +#define REG_CLEAR_LINK0_BIT 2 +#define REG_CLEAR_LINK1_BIT 3 +#define REG_STATUS_LINK0_BIT 2 +#define REG_STATUS_LINK1_BIT 3 + +#define REG_LINK0_MSI_ADDR_SIZE_MASK GENMASK(15, 0) +#define REG_LINK1_MSI_ADDR_SIZE_MASK GENMASK(31, 16) + +struct sg2042_pcie { + struct cdns_pcie *cdns_pcie; + + struct regmap *syscon; + + u32 link_id; + + struct irq_domain *msi_domain; + + int msi_irq; + + dma_addr_t msi_phys; + void *msi_virt; + + u32 num_applied_vecs; /* used to speed up ISR */ + + raw_spinlock_t msi_lock; + DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS); +}; + +static void sg2042_pcie_msi_clear_status(struct sg2042_pcie *pcie) +{ + u32 status, clr_msi_in_bit; + + if (pcie->link_id == 1) + clr_msi_in_bit = BIT(REG_CLEAR_LINK1_BIT); + else + clr_msi_in_bit = BIT(REG_CLEAR_LINK0_BIT); + + regmap_read(pcie->syscon, REG_CLEAR, &status); + status |= clr_msi_in_bit; + regmap_write(pcie->syscon, REG_CLEAR, status); + + /* need write 0 to reset, hardware can not reset automatically */ + status &= ~clr_msi_in_bit; + regmap_write(pcie->syscon, REG_CLEAR, status); +} + +static int sg2042_pcie_msi_irq_set_affinity(struct irq_data *d, + const struct cpumask *mask, + bool force) +{ + if (d->parent_data) + return irq_chip_set_affinity_parent(d, mask, force); + + return -EINVAL; +} + +static void sg2042_pcie_msi_irq_compose_msi_msg(struct irq_data *d, + struct msi_msg *msg) +{ + struct sg2042_pcie *pcie = irq_data_get_irq_chip_data(d); + struct device *dev = pcie->cdns_pcie->dev; + + msg->address_lo = lower_32_bits(pcie->msi_phys) + BYTE_NUM_PER_MSI_VEC * d->hwirq; + msg->address_hi = upper_32_bits(pcie->msi_phys); + msg->data = 1; + + if (d->hwirq > pcie->num_applied_vecs) + pcie->num_applied_vecs = d->hwirq; + + dev_dbg(dev, "compose MSI msg hwirq[%ld] address_hi[%#x] address_lo[%#x]\n", + d->hwirq, msg->address_hi, msg->address_lo); +} + +static void sg2042_pcie_msi_irq_ack(struct irq_data *d) +{ + struct sg2042_pcie *pcie = irq_data_get_irq_chip_data(d); + + sg2042_pcie_msi_clear_status(pcie); +} + +static struct irq_chip sg2042_pcie_msi_bottom_chip = { + .name = "SG2042 PCIe PLIC-MSI translator", + .irq_ack = sg2042_pcie_msi_irq_ack, + .irq_compose_msi_msg = sg2042_pcie_msi_irq_compose_msi_msg, + .irq_set_affinity = sg2042_pcie_msi_irq_set_affinity, +}; + +static int sg2042_pcie_irq_domain_alloc(struct irq_domain *domain, + unsigned int virq, unsigned int nr_irqs, + void *args) +{ + struct sg2042_pcie *pcie = domain->host_data; + unsigned long flags; + u32 i; + int bit; + + raw_spin_lock_irqsave(&pcie->msi_lock, flags); + + bit = bitmap_find_free_region(pcie->msi_irq_in_use, MSI_DEF_NUM_VECTORS, + order_base_2(nr_irqs)); + + raw_spin_unlock_irqrestore(&pcie->msi_lock, flags); + + if (bit < 0) + return -ENOSPC; + + for (i = 0; i < nr_irqs; i++) + irq_domain_set_info(domain, virq + i, bit + i, + &sg2042_pcie_msi_bottom_chip, + pcie, handle_edge_irq, + NULL, NULL); + + return 0; +} + +static void sg2042_pcie_irq_domain_free(struct irq_domain *domain, + unsigned int virq, unsigned int nr_irqs) +{ + struct irq_data *d = irq_domain_get_irq_data(domain, virq); + struct sg2042_pcie *pcie = irq_data_get_irq_chip_data(d); + unsigned long flags; + + raw_spin_lock_irqsave(&pcie->msi_lock, flags); + + bitmap_release_region(pcie->msi_irq_in_use, d->hwirq, + order_base_2(nr_irqs)); + + raw_spin_unlock_irqrestore(&pcie->msi_lock, flags); +} + +static const struct irq_domain_ops sg2042_pcie_msi_domain_ops = { + .alloc = sg2042_pcie_irq_domain_alloc, + .free = sg2042_pcie_irq_domain_free, +}; + +static int sg2042_pcie_init_msi_data(struct sg2042_pcie *pcie) +{ + struct device *dev = pcie->cdns_pcie->dev; + u32 value; + int ret; + + raw_spin_lock_init(&pcie->msi_lock); + + /* + * Though the PCIe controller can address >32-bit address space, to + * facilitate endpoints that support only 32-bit MSI target address, + * the mask is set to 32-bit to make sure that MSI target address is + * always a 32-bit address + */ + ret = dma_set_coherent_mask(dev, DMA_BIT_MASK(32)); + if (ret < 0) + return ret; + + pcie->msi_virt = dma_alloc_coherent(dev, BYTE_NUM_PER_MSI_VEC * MAX_MSI_IRQS, + &pcie->msi_phys, GFP_KERNEL); + if (!pcie->msi_virt) + return -ENOMEM; + + /* Program the MSI address and size */ + if (pcie->link_id == 1) { + regmap_write(pcie->syscon, REG_LINK1_MSI_ADDR_LOW, + lower_32_bits(pcie->msi_phys)); + regmap_write(pcie->syscon, REG_LINK1_MSI_ADDR_HIGH, + upper_32_bits(pcie->msi_phys)); + + regmap_read(pcie->syscon, REG_LINK1_MSI_ADDR_SIZE, &value); + value = (value & REG_LINK1_MSI_ADDR_SIZE_MASK) | MAX_MSI_IRQS; + regmap_write(pcie->syscon, REG_LINK1_MSI_ADDR_SIZE, value); + } else { + regmap_write(pcie->syscon, REG_LINK0_MSI_ADDR_LOW, + lower_32_bits(pcie->msi_phys)); + regmap_write(pcie->syscon, REG_LINK0_MSI_ADDR_HIGH, + upper_32_bits(pcie->msi_phys)); + + regmap_read(pcie->syscon, REG_LINK0_MSI_ADDR_SIZE, &value); + value = (value & REG_LINK0_MSI_ADDR_SIZE_MASK) | (MAX_MSI_IRQS << 16); + regmap_write(pcie->syscon, REG_LINK0_MSI_ADDR_SIZE, value); + } + + return 0; +} + +static irqreturn_t sg2042_pcie_msi_handle_irq(struct sg2042_pcie *pcie) +{ + u32 i, pos; + unsigned long val; + u32 status, num_vectors; + irqreturn_t ret = IRQ_NONE; + + num_vectors = pcie->num_applied_vecs; + for (i = 0; i <= num_vectors; i++) { + status = readl((void *)(pcie->msi_virt + i * BYTE_NUM_PER_MSI_VEC)); + if (!status) + continue; + + ret = IRQ_HANDLED; + val = status; + pos = 0; + while ((pos = find_next_bit(&val, MAX_MSI_IRQS_PER_CTRL, + pos)) != MAX_MSI_IRQS_PER_CTRL) { + generic_handle_domain_irq(pcie->msi_domain, + (i * MAX_MSI_IRQS_PER_CTRL) + + pos); + pos++; + } + writel(0, ((void *)(pcie->msi_virt) + i * BYTE_NUM_PER_MSI_VEC)); + } + return ret; +} + +static void sg2042_pcie_msi_chained_isr(struct irq_desc *desc) +{ + struct irq_chip *chip = irq_desc_get_chip(desc); + u32 status, st_msi_in_bit; + struct sg2042_pcie *pcie; + + chained_irq_enter(chip, desc); + + pcie = irq_desc_get_handler_data(desc); + if (pcie->link_id == 1) + st_msi_in_bit = REG_STATUS_LINK1_BIT; + else + st_msi_in_bit = REG_STATUS_LINK0_BIT; + + regmap_read(pcie->syscon, REG_STATUS, &status); + if ((status >> st_msi_in_bit) & 0x1) { + sg2042_pcie_msi_clear_status(pcie); + + sg2042_pcie_msi_handle_irq(pcie); + } + + chained_irq_exit(chip, desc); +} + +#define SG2042_PCIE_MSI_FLAGS_REQUIRED (MSI_FLAG_USE_DEF_DOM_OPS | \ + MSI_FLAG_USE_DEF_CHIP_OPS) + +#define SG2042_PCIE_MSI_FLAGS_SUPPORTED MSI_GENERIC_FLAGS_MASK + +static struct msi_parent_ops sg2042_pcie_msi_parent_ops = { + .required_flags = SG2042_PCIE_MSI_FLAGS_REQUIRED, + .supported_flags = SG2042_PCIE_MSI_FLAGS_SUPPORTED, + .bus_select_mask = MATCH_PCI_MSI, + .bus_select_token = DOMAIN_BUS_NEXUS, + .prefix = "SG2042-", + .init_dev_msi_info = msi_lib_init_dev_msi_info, +}; + +static int sg2042_pcie_setup_msi(struct sg2042_pcie *pcie, + struct device_node *msi_node) +{ + struct device *dev = pcie->cdns_pcie->dev; + struct fwnode_handle *fwnode = of_node_to_fwnode(dev->of_node); + struct irq_domain *parent_domain; + int ret = 0; + + if (!of_property_read_bool(msi_node, "msi-controller")) + return -ENODEV; + + ret = of_irq_get_byname(msi_node, "msi"); + if (ret <= 0) { + dev_err(dev, "%pOF: failed to get MSI irq\n", msi_node); + return ret; + } + pcie->msi_irq = ret; + + irq_set_chained_handler_and_data(pcie->msi_irq, + sg2042_pcie_msi_chained_isr, pcie); + + parent_domain = irq_domain_create_linear(fwnode, MSI_DEF_NUM_VECTORS, + &sg2042_pcie_msi_domain_ops, pcie); + if (!parent_domain) { + dev_err(dev, "%pfw: Failed to create IRQ domain\n", fwnode); + return -ENOMEM; + } + irq_domain_update_bus_token(parent_domain, DOMAIN_BUS_NEXUS); + + parent_domain->flags |= IRQ_DOMAIN_FLAG_MSI_PARENT; + parent_domain->msi_parent_ops = &sg2042_pcie_msi_parent_ops; + + pcie->msi_domain = parent_domain; + + ret = sg2042_pcie_init_msi_data(pcie); + if (ret) { + dev_err(dev, "Failed to initialize MSI data!\n"); + return ret; + } + + return 0; +} + +static void sg2042_pcie_free_msi(struct sg2042_pcie *pcie) +{ + struct device *dev = pcie->cdns_pcie->dev; + + if (pcie->msi_irq) + irq_set_chained_handler_and_data(pcie->msi_irq, NULL, NULL); + + if (pcie->msi_virt) + dma_free_coherent(dev, BYTE_NUM_PER_MSI_VEC * MAX_MSI_IRQS, + pcie->msi_virt, pcie->msi_phys); +} + +/* + * SG2042 only support 4-byte aligned access, so for the rootbus (i.e. to read + * the Root Port itself, read32 is required. For non-rootbus (i.e. to read + * the PCIe peripheral registers, supports 1/2/4 byte aligned access, so + * directly using read should be fine. + * + * The same is true for write. + */ +static int sg2042_pcie_config_read(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 *value) +{ + if (pci_is_root_bus(bus)) + return pci_generic_config_read32(bus, devfn, where, size, + value); + + return pci_generic_config_read(bus, devfn, where, size, value); +} + +static int sg2042_pcie_config_write(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 value) +{ + if (pci_is_root_bus(bus)) + return pci_generic_config_write32(bus, devfn, where, size, + value); + + return pci_generic_config_write(bus, devfn, where, size, value); +} + +static struct pci_ops sg2042_pcie_host_ops = { + .map_bus = cdns_pci_map_bus, + .read = sg2042_pcie_config_read, + .write = sg2042_pcie_config_write, +}; + +/* Dummy ops which will be assigned to cdns_pcie.ops, which must be !NULL. */ +static const struct cdns_pcie_ops sg2042_cdns_pcie_ops = {}; + +static int sg2042_pcie_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + struct pci_host_bridge *bridge; + struct device_node *np_syscon; + struct device_node *msi_node; + struct cdns_pcie *cdns_pcie; + struct sg2042_pcie *pcie; + struct cdns_pcie_rc *rc; + struct regmap *syscon; + int ret; + + pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); + if (!pcie) + return -ENOMEM; + + bridge = devm_pci_alloc_host_bridge(dev, sizeof(*rc)); + if (!bridge) { + dev_err(dev, "Failed to alloc host bridge!\n"); + return -ENOMEM; + } + + bridge->ops = &sg2042_pcie_host_ops; + + rc = pci_host_bridge_priv(bridge); + cdns_pcie = &rc->pcie; + cdns_pcie->dev = dev; + cdns_pcie->ops = &sg2042_cdns_pcie_ops; + pcie->cdns_pcie = cdns_pcie; + + np_syscon = of_parse_phandle(np, "sophgo,syscon-pcie-ctrl", 0); + if (!np_syscon) { + dev_err(dev, "Failed to get syscon node\n"); + return -ENOMEM; + } + syscon = syscon_node_to_regmap(np_syscon); + if (IS_ERR(syscon)) { + dev_err(dev, "Failed to get regmap for syscon\n"); + return -ENOMEM; + } + pcie->syscon = syscon; + + if (of_property_read_u32(np, "sophgo,link-id", &pcie->link_id)) { + dev_err(dev, "Unable to parse sophgo,link-id\n"); + return -EINVAL; + } + + platform_set_drvdata(pdev, pcie); + + pm_runtime_enable(dev); + + ret = pm_runtime_get_sync(dev); + if (ret < 0) { + dev_err(dev, "pm_runtime_get_sync failed\n"); + goto err_get_sync; + } + + msi_node = of_parse_phandle(dev->of_node, "msi-parent", 0); + if (!msi_node) { + dev_err(dev, "Failed to get msi-parent!\n"); + return -1; + } + + if (of_device_is_compatible(msi_node, "sophgo,sg2042-pcie-msi")) { + ret = sg2042_pcie_setup_msi(pcie, msi_node); + if (ret < 0) + goto err_setup_msi; + } + + ret = cdns_pcie_init_phy(dev, cdns_pcie); + if (ret) { + dev_err(dev, "Failed to init phy!\n"); + goto err_setup_msi; + } + + ret = cdns_pcie_host_setup(rc); + if (ret < 0) { + dev_err(dev, "Failed to setup host!\n"); + goto err_host_setup; + } + + return 0; + +err_host_setup: + cdns_pcie_disable_phy(cdns_pcie); + +err_setup_msi: + sg2042_pcie_free_msi(pcie); + +err_get_sync: + pm_runtime_put(dev); + pm_runtime_disable(dev); + + return ret; +} + +static void sg2042_pcie_shutdown(struct platform_device *pdev) +{ + struct sg2042_pcie *pcie = platform_get_drvdata(pdev); + struct cdns_pcie *cdns_pcie = pcie->cdns_pcie; + struct device *dev = &pdev->dev; + + sg2042_pcie_free_msi(pcie); + + cdns_pcie_disable_phy(cdns_pcie); + + pm_runtime_put(dev); + pm_runtime_disable(dev); +} + +static const struct of_device_id sg2042_pcie_of_match[] = { + { .compatible = "sophgo,sg2042-pcie-host" }, + {}, +}; + +static struct platform_driver sg2042_pcie_driver = { + .driver = { + .name = "sg2042-pcie", + .of_match_table = sg2042_pcie_of_match, + .pm = &cdns_pcie_pm_ops, + }, + .probe = sg2042_pcie_probe, + .shutdown = sg2042_pcie_shutdown, +}; +builtin_platform_driver(sg2042_pcie_driver); From fe5df3d2bace249fdae84e641f2ac6ac302f6e64 Mon Sep 17 00:00:00 2001 From: Chen Wang Date: Wed, 4 Jun 2025 21:00:43 +0800 Subject: [PATCH 03/34] FROMLIST: dt-bindings: mfd: syscon: Add sg2042 pcie ctrl compatible Document SOPHGO SG2042 compatible for PCIe control registers. These registers are shared by PCIe controller nodes. Signed-off-by: Chen Wang Acked-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/a9b213536c5bbc20de649afae69d2898a75924e4.1736923025.git.unicorn_wang@outlook.com Signed-off-by: Han Gao --- Documentation/devicetree/bindings/mfd/syscon.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml index c6bbb19c3e3e22..7bde197ab0ed5c 100644 --- a/Documentation/devicetree/bindings/mfd/syscon.yaml +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml @@ -112,6 +112,7 @@ select: - rockchip,rk3576-qos - rockchip,rk3588-qos - rockchip,rv1126-qos + - sophgo,sg2042-pcie-ctrl - st,spear1340-misc - stericsson,nomadik-pmu - starfive,jh7100-sysmain @@ -215,6 +216,7 @@ properties: - rockchip,rk3576-qos - rockchip,rk3588-qos - rockchip,rv1126-qos + - sophgo,sg2042-pcie-ctrl - st,spear1340-misc - stericsson,nomadik-pmu - starfive,jh7100-sysmain From b0b0320f7398b1268ce9d5a67c4d73d0513e8025 Mon Sep 17 00:00:00 2001 From: Chen Wang Date: Wed, 4 Jun 2025 21:00:49 +0800 Subject: [PATCH 04/34] FROMLIST: riscv: sophgo: dts: add pcie controllers for SG2042 Add PCIe controller nodes in DTS for Sophgo SG2042. Default they are disabled. Signed-off-by: Chen Wang Link: https://lore.kernel.org/r/4a1f23e5426bfb56cad9c07f90d4efaad5eab976.1736923025.git.unicorn_wang@outlook.com Signed-off-by: Han Gao --- arch/riscv/boot/dts/sophgo/sg2042.dtsi | 89 ++++++++++++++++++++++++++ 1 file changed, 89 insertions(+) diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi index aa8b7fcc125d71..1aec826ef3e5fa 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi @@ -214,6 +214,95 @@ #clock-cells = <1>; }; + pcie_rc0: pcie@7060000000 { + compatible = "sophgo,sg2042-pcie-host"; + device_type = "pci"; + reg = <0x70 0x60000000 0x0 0x02000000>, + <0x40 0x00000000 0x0 0x00001000>; + reg-names = "reg", "cfg"; + linux,pci-domain = <0>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0xc0000000 0x40 0xc0000000 0x0 0x00400000>, + <0x42000000 0x0 0xd0000000 0x40 0xd0000000 0x0 0x10000000>, + <0x02000000 0x0 0xe0000000 0x40 0xe0000000 0x0 0x20000000>, + <0x43000000 0x42 0x00000000 0x42 0x00000000 0x2 0x00000000>, + <0x03000000 0x41 0x00000000 0x41 0x00000000 0x1 0x00000000>; + bus-range = <0x0 0xff>; + vendor-id = <0x1f1c>; + device-id = <0x2042>; + cdns,no-bar-match-nbits = <48>; + sophgo,link-id = <0>; + sophgo,syscon-pcie-ctrl = <&cdns_pcie0_ctrl>; + msi-parent = <&msi>; + status = "disabled"; + }; + + cdns_pcie0_ctrl: syscon@7061800000 { + compatible = "sophgo,sg2042-pcie-ctrl", "syscon"; + reg = <0x70 0x61800000 0x0 0x800000>; + }; + + pcie_rc1: pcie@7062000000 { + compatible = "sophgo,sg2042-pcie-host"; + device_type = "pci"; + reg = <0x70 0x62000000 0x0 0x00800000>, + <0x48 0x00000000 0x0 0x00001000>; + reg-names = "reg", "cfg"; + linux,pci-domain = <1>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0xc0800000 0x48 0xc0800000 0x0 0x00400000>, + <0x42000000 0x0 0xd0000000 0x48 0xd0000000 0x0 0x10000000>, + <0x02000000 0x0 0xe0000000 0x48 0xe0000000 0x0 0x20000000>, + <0x03000000 0x49 0x00000000 0x49 0x00000000 0x1 0x00000000>, + <0x43000000 0x4a 0x00000000 0x4a 0x00000000 0x2 0x00000000>; + bus-range = <0x0 0xff>; + vendor-id = <0x1f1c>; + device-id = <0x2042>; + cdns,no-bar-match-nbits = <48>; + sophgo,link-id = <0>; + sophgo,syscon-pcie-ctrl = <&cdns_pcie1_ctrl>; + msi-parent = <&msi_pcie>; + status = "disabled"; + msi_pcie: msi { + compatible = "sophgo,sg2042-pcie-msi"; + msi-controller; + interrupt-parent = <&intc>; + interrupts = <123 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi"; + }; + }; + + pcie_rc2: pcie@7062800000 { + compatible = "sophgo,sg2042-pcie-host"; + device_type = "pci"; + reg = <0x70 0x62800000 0x0 0x00800000>, + <0x4c 0x00000000 0x0 0x00001000>; + reg-names = "reg", "cfg"; + linux,pci-domain = <2>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0xc0c00000 0x4c 0xc0c00000 0x0 0x00400000>, + <0x42000000 0x0 0xf8000000 0x4c 0xf8000000 0x0 0x04000000>, + <0x02000000 0x0 0xfc000000 0x4c 0xfc000000 0x0 0x04000000>, + <0x43000000 0x4e 0x00000000 0x4e 0x00000000 0x2 0x00000000>, + <0x03000000 0x4d 0x00000000 0x4d 0x00000000 0x1 0x00000000>; + bus-range = <0x0 0xff>; + vendor-id = <0x1f1c>; + device-id = <0x2042>; + cdns,no-bar-match-nbits = <48>; + sophgo,link-id = <1>; + sophgo,syscon-pcie-ctrl = <&cdns_pcie1_ctrl>; + msi-parent = <&msi>; + status = "disabled"; + }; + + cdns_pcie1_ctrl: syscon@7063800000 { + compatible = "sophgo,sg2042-pcie-ctrl", "syscon"; + reg = <0x70 0x63800000 0x0 0x800000>; + }; + clint_mswi: interrupt-controller@7094000000 { compatible = "sophgo,sg2042-aclint-mswi", "thead,c900-aclint-mswi"; reg = <0x00000070 0x94000000 0x00000000 0x00004000>; From 7e5c394a0d4004670cb9484b92b1b29e1bac2f84 Mon Sep 17 00:00:00 2001 From: Chen Wang Date: Wed, 4 Jun 2025 21:00:55 +0800 Subject: [PATCH 05/34] FROMLIST: riscv: sophgo: dts: enable pcie for PioneerBox Enable pcie controllers for PioneerBox, which uses SG2042 SoC. Signed-off-by: Chen Wang Link: https://lore.kernel.org/r/eb2e8c619a4dd53f9bb1aa33add4f85d4ffa7d79.1736923025.git.unicorn_wang@outlook.com Signed-off-by: Han Gao --- arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts index 34645a5f603838..d1cc91150c919c 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts +++ b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts @@ -60,6 +60,18 @@ }; }; +&pcie_rc0 { + status = "okay"; +}; + +&pcie_rc1 { + status = "okay"; +}; + +&pcie_rc2 { + status = "okay"; +}; + &sd { bus-width = <4>; no-sdio; From 1b8cc1f7a7fefb6ac5e187de3640b0634964694f Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Tue, 11 Feb 2025 13:17:56 +0800 Subject: [PATCH 06/34] UPSTREAM: riscv: dts: sophgo: sg2042: add pinctrl support Add pinctrl node and related pin configuration for SG2042 SoC. Link: https://lore.kernel.org/r/20250211051801.470800-9-inochiama@gmail.com Signed-off-by: Inochi Amaoto Signed-off-by: Chen Wang Signed-off-by: Chen Wang (cherry picked from commit 1cb666ec5a216c12d5aa1fb5225802b6090c4c57) Signed-off-by: Han Gao --- .../boot/dts/sophgo/sg2042-milkv-pioneer.dts | 72 +++++++++++++++++++ arch/riscv/boot/dts/sophgo/sg2042.dtsi | 6 ++ 2 files changed, 78 insertions(+) diff --git a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts index d1cc91150c919c..b5b8d4879549ed 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts +++ b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts @@ -42,6 +42,8 @@ }; &emmc { + pinctrl-0 = <&emmc_cfg>; + pinctrl-names = "default"; bus-width = <4>; no-sdio; no-sd; @@ -51,6 +53,8 @@ }; &i2c1 { + pinctrl-0 = <&i2c1_cfg>; + pinctrl-names = "default"; status = "okay"; mcu: syscon@17 { @@ -72,7 +76,73 @@ status = "okay"; }; +&pinctrl { + emmc_cfg: sdhci-emmc-cfg { + sdhci-emmc-wp-pins { + pinmux = ; + bias-disable; + drive-strength-microamp = <26800>; + input-schmitt-disable; + }; + + sdhci-emmc-cd-pins { + pinmux = ; + bias-pull-up; + drive-strength-microamp = <26800>; + input-schmitt-enable; + }; + + sdhci-emmc-rst-pwr-pins { + pinmux = , + ; + bias-disable; + drive-strength-microamp = <26800>; + input-schmitt-disable; + }; + }; + + i2c1_cfg: i2c1-cfg { + i2c1-pins { + pinmux = , + ; + bias-pull-up; + drive-strength-microamp = <26800>; + input-schmitt-enable; + }; + }; + + sd_cfg: sdhci-sd-cfg { + sdhci-sd-cd-wp-pins { + pinmux = , + ; + bias-pull-up; + drive-strength-microamp = <26800>; + input-schmitt-enable; + }; + + sdhci-sd-rst-pwr-pins { + pinmux = , + ; + bias-disable; + drive-strength-microamp = <26800>; + input-schmitt-disable; + }; + }; + + uart0_cfg: uart0-cfg { + uart0-rx-pins { + pinmux = , + ; + bias-pull-up; + drive-strength-microamp = <26800>; + input-schmitt-enable; + }; + }; +}; + &sd { + pinctrl-0 = <&sd_cfg>; + pinctrl-names = "default"; bus-width = <4>; no-sdio; no-mmc; @@ -81,6 +151,8 @@ }; &uart0 { + pinctrl-0 = <&uart0_cfg>; + pinctrl-names = "default"; status = "okay"; }; diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi index 1aec826ef3e5fa..2ed381846f14b1 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include #include #include "sg2042-cpus.dtsi" @@ -200,6 +201,11 @@ #clock-cells = <1>; }; + pinctrl: pinctrl@7030011000 { + compatible = "sophgo,sg2042-pinctrl"; + reg = <0x70 0x30011000 0x0 0x1000>; + }; + clkgen: clock-controller@7030012000 { compatible = "sophgo,sg2042-clkgen"; reg = <0x70 0x30012000 0x0 0x1000>; From 8e36c96d55ca0291a962824d649fb6044f636b14 Mon Sep 17 00:00:00 2001 From: Zixian Zeng Date: Wed, 4 Jun 2025 21:07:12 +0800 Subject: [PATCH 07/34] UPSTREAM: riscv: sophgo: dts: Add spi controller for SG2042 Add spi controllers for SG2042. SG2042 uses the upstreamed Synopsys DW SPI IP. Signed-off-by: Zixian Zeng Link: https://lore.kernel.org/r/20250425-sfg-spi-v6-3-2dbe7bb46013@gmail.com Signed-off-by: Inochi Amaoto Signed-off-by: Chen Wang Signed-off-by: Chen Wang (cherry picked from commit 73ab31a8f3fbd4dfb45e5ca3aea97f71f90774cb) Signed-off-by: Han Gao --- arch/riscv/boot/dts/sophgo/sg2042.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi index 2ed381846f14b1..ff337a89adb4c1 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi @@ -632,6 +632,32 @@ status = "disabled"; }; + spi0: spi@7040004000 { + compatible = "sophgo,sg2042-spi", "snps,dw-apb-ssi"; + reg = <0x70 0x40004000 0x00 0x1000>; + clocks = <&clkgen GATE_CLK_APB_SPI>; + interrupt-parent = <&intc>; + interrupts = <110 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + num-cs = <2>; + resets = <&rstgen RST_SPI0>; + status = "disabled"; + }; + + spi1: spi@7040005000 { + compatible = "sophgo,sg2042-spi", "snps,dw-apb-ssi"; + reg = <0x70 0x40005000 0x00 0x1000>; + clocks = <&clkgen GATE_CLK_APB_SPI>; + interrupt-parent = <&intc>; + interrupts = <111 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + num-cs = <2>; + resets = <&rstgen RST_SPI1>; + status = "disabled"; + }; + emmc: mmc@704002a000 { compatible = "sophgo,sg2042-dwcmshc"; reg = <0x70 0x4002a000 0x0 0x1000>; From 588773e023bd2b862a60832963596b1888ded4d8 Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Wed, 4 Jun 2025 21:09:19 +0800 Subject: [PATCH 08/34] FROMLIST: dt-bindings: net: sophgo,sg2044-dwmac: Add support for Sophgo SG2042 dwmac The GMAC IP on SG2042 is a standard Synopsys DesignWare MAC (version 5.00a) with tx clock. Add necessary compatible string for this device. Signed-off-by: Inochi Amaoto Tested-by: Han Gao Link: https://lore.kernel.org/r/20250506093256.1107770-2-inochiama@gmail.com Signed-off-by: Han Gao --- Documentation/devicetree/bindings/net/snps,dwmac.yaml | 4 ++++ .../devicetree/bindings/net/sophgo,sg2044-dwmac.yaml | 11 ++++++++--- 2 files changed, 12 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/net/snps,dwmac.yaml b/Documentation/devicetree/bindings/net/snps,dwmac.yaml index 78b3030dc56d27..f16b49da6dbf57 100644 --- a/Documentation/devicetree/bindings/net/snps,dwmac.yaml +++ b/Documentation/devicetree/bindings/net/snps,dwmac.yaml @@ -30,6 +30,7 @@ select: - snps,dwmac-4.00 - snps,dwmac-4.10a - snps,dwmac-4.20a + - snps,dwmac-5.00a - snps,dwmac-5.10a - snps,dwmac-5.20 - snps,dwmac-5.30a @@ -97,11 +98,13 @@ properties: - snps,dwmac-4.00 - snps,dwmac-4.10a - snps,dwmac-4.20a + - snps,dwmac-5.00a - snps,dwmac-5.10a - snps,dwmac-5.20 - snps,dwmac-5.30a - snps,dwxgmac - snps,dwxgmac-2.10 + - sophgo,sg2042-dwmac - sophgo,sg2044-dwmac - starfive,jh7100-dwmac - starfive,jh7110-dwmac @@ -634,6 +637,7 @@ allOf: - snps,dwmac-4.00 - snps,dwmac-4.10a - snps,dwmac-4.20a + - snps,dwmac-5.00a - snps,dwmac-5.10a - snps,dwmac-5.20 - snps,dwmac-5.30a diff --git a/Documentation/devicetree/bindings/net/sophgo,sg2044-dwmac.yaml b/Documentation/devicetree/bindings/net/sophgo,sg2044-dwmac.yaml index 4dd2dc9c678b70..112b0b2a15249e 100644 --- a/Documentation/devicetree/bindings/net/sophgo,sg2044-dwmac.yaml +++ b/Documentation/devicetree/bindings/net/sophgo,sg2044-dwmac.yaml @@ -15,14 +15,19 @@ select: contains: enum: - sophgo,sg2044-dwmac + - sophgo,sg2042-dwmac required: - compatible properties: compatible: - items: - - const: sophgo,sg2044-dwmac - - const: snps,dwmac-5.30a + oneOf: + - items: + - const: sophgo,sg2042-dwmac + - const: snps,dwmac-5.00a + - items: + - const: sophgo,sg2044-dwmac + - const: snps,dwmac-5.30a reg: maxItems: 1 From 189ed9f2ecf0d8d0679d8f82861fc04c83158ae5 Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Wed, 4 Jun 2025 21:09:40 +0800 Subject: [PATCH 09/34] FROMLIST: net: stmmac: dwmac-sophgo: Add support for Sophgo SG2042 SoC Adds device id of the ethernet controller on the Sophgo SG2042 SoC. Signed-off-by: Inochi Amaoto Tested-by: Han Gao Link: https://lore.kernel.org/r/20250506093256.1107770-3-inochiama@gmail.com Signed-off-by: Han Gao --- drivers/net/ethernet/stmicro/stmmac/dwmac-sophgo.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sophgo.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sophgo.c index 3303784cbbf8e3..3b7947a7a7ba70 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sophgo.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sophgo.c @@ -54,6 +54,7 @@ static int sophgo_dwmac_probe(struct platform_device *pdev) } static const struct of_device_id sophgo_dwmac_match[] = { + { .compatible = "sophgo,sg2042-dwmac" }, { .compatible = "sophgo,sg2044-dwmac" }, { /* sentinel */ } }; From 62fcb41aafa667b9f6a604689bb9eaa1a66d357d Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Wed, 4 Jun 2025 21:09:47 +0800 Subject: [PATCH 10/34] FROMLIST: net: stmmac: platform: Add snps,dwmac-5.00a IP compatible string Add "snps,dwmac-5.30a" compatible string for 5.00a version that can avoid to define some platform data in the glue layer. Signed-off-by: Inochi Amaoto Tested-by: Han Gao Link: https://lore.kernel.org/r/20250506093256.1107770-4-inochiama@gmail.com Signed-off-by: Han Gao --- drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c index c73eff6a56b87a..de3098a773ba68 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c @@ -410,6 +410,7 @@ static const char * const stmmac_gmac4_compats[] = { "snps,dwmac-4.00", "snps,dwmac-4.10a", "snps,dwmac-4.20a", + "snps,dwmac-5.00a", "snps,dwmac-5.10a", "snps,dwmac-5.20", "snps,dwmac-5.30a", From a265b9d673f6c9e5d7ae1259fdcd0bd4f8acc0a8 Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Wed, 4 Jun 2025 21:09:54 +0800 Subject: [PATCH 11/34] FROMLIST: riscv: dts: sophgo: add ethernet GMAC device for sg2042 Add ethernet GMAC device node for the sg2042. Signed-off-by: Inochi Amaoto Tested-by: Han Gao Link: https://lore.kernel.org/r/20250506093256.1107770-5-inochiama@gmail.com Signed-off-by: Han Gao --- arch/riscv/boot/dts/sophgo/sg2042.dtsi | 61 ++++++++++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi index ff337a89adb4c1..c206f315283974 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi @@ -658,6 +658,67 @@ status = "disabled"; }; + gmac0: ethernet@7040026000 { + compatible = "sophgo,sg2042-dwmac", "snps,dwmac-5.00a"; + reg = <0x70 0x40026000 0x0 0x4000>; + clocks = <&clkgen GATE_CLK_AXI_ETH0>, + <&clkgen GATE_CLK_PTP_REF_I_ETH0>, + <&clkgen GATE_CLK_TX_ETH0>; + clock-names = "stmmaceth", "ptp_ref", "tx"; + dma-noncoherent; + interrupt-parent = <&intc>; + interrupts = <132 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + resets = <&rstgen RST_ETH0>; + reset-names = "stmmaceth"; + snps,multicast-filter-bins = <0>; + snps,perfect-filter-entries = <1>; + snps,aal; + snps,tso; + snps,txpbl = <32>; + snps,rxpbl = <32>; + snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; + snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; + snps,axi-config = <&gmac0_stmmac_axi_setup>; + status = "disabled"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + }; + + gmac0_mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <8>; + queue0 {}; + queue1 {}; + queue2 {}; + queue3 {}; + queue4 {}; + queue5 {}; + queue6 {}; + queue7 {}; + }; + + gmac0_mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <8>; + queue0 {}; + queue1 {}; + queue2 {}; + queue3 {}; + queue4 {}; + queue5 {}; + queue6 {}; + queue7 {}; + }; + + gmac0_stmmac_axi_setup: stmmac-axi-config { + snps,blen = <16 8 4 0 0 0 0>; + snps,wr_osr_lmt = <1>; + snps,rd_osr_lmt = <2>; + }; + }; + emmc: mmc@704002a000 { compatible = "sophgo,sg2042-dwcmshc"; reg = <0x70 0x4002a000 0x0 0x1000>; From bf4830d6572df3e68a73227cd34cdd5f8178813a Mon Sep 17 00:00:00 2001 From: Guo Ren Date: Wed, 4 Jun 2025 21:11:24 +0800 Subject: [PATCH 12/34] FROMLIST: riscv: Move vendor errata definitions into vendorid_list.h Move vendor errata definitions into vendorid_list and make it re-useable for other header files. Signed-off-by: Guo Ren Signed-off-by: Guo Ren Tested-by: Inochi Amaoto Link: https://lore.kernel.org/r/20241214143039.4139398-2-guoren@kernel.org Signed-off-by: Han Gao --- arch/riscv/include/asm/errata_list.h | 18 ------------------ arch/riscv/include/asm/vendorid_list.h | 18 ++++++++++++++++++ 2 files changed, 18 insertions(+), 18 deletions(-) diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h index 6e426ed7919a4a..589a3ebe2ae261 100644 --- a/arch/riscv/include/asm/errata_list.h +++ b/arch/riscv/include/asm/errata_list.h @@ -11,24 +11,6 @@ #include #include -#ifdef CONFIG_ERRATA_ANDES -#define ERRATA_ANDES_NO_IOCP 0 -#define ERRATA_ANDES_NUMBER 1 -#endif - -#ifdef CONFIG_ERRATA_SIFIVE -#define ERRATA_SIFIVE_CIP_453 0 -#define ERRATA_SIFIVE_CIP_1200 1 -#define ERRATA_SIFIVE_NUMBER 2 -#endif - -#ifdef CONFIG_ERRATA_THEAD -#define ERRATA_THEAD_MAE 0 -#define ERRATA_THEAD_PMU 1 -#define ERRATA_THEAD_GHOSTWRITE 2 -#define ERRATA_THEAD_NUMBER 3 -#endif - #ifdef __ASSEMBLY__ #define ALT_INSN_FAULT(x) \ diff --git a/arch/riscv/include/asm/vendorid_list.h b/arch/riscv/include/asm/vendorid_list.h index a5150cdf34d87f..d9fed9bcedeb4b 100644 --- a/arch/riscv/include/asm/vendorid_list.h +++ b/arch/riscv/include/asm/vendorid_list.h @@ -10,4 +10,22 @@ #define SIFIVE_VENDOR_ID 0x489 #define THEAD_VENDOR_ID 0x5b7 +#ifdef CONFIG_ERRATA_ANDES +#define ERRATA_ANDES_NO_IOCP 0 +#define ERRATA_ANDES_NUMBER 1 +#endif + +#ifdef CONFIG_ERRATA_SIFIVE +#define ERRATA_SIFIVE_CIP_453 0 +#define ERRATA_SIFIVE_CIP_1200 1 +#define ERRATA_SIFIVE_NUMBER 2 +#endif + +#ifdef CONFIG_ERRATA_THEAD +#define ERRATA_THEAD_MAE 0 +#define ERRATA_THEAD_PMU 1 +#define ERRATA_THEAD_GHOSTWRITE 2 +#define ERRATA_THEAD_NUMBER 3 +#endif + #endif From 3529cdf2abb8d2cbbe923d93368fda2f9ce0a563 Mon Sep 17 00:00:00 2001 From: Guo Ren Date: Wed, 4 Jun 2025 21:11:35 +0800 Subject: [PATCH 13/34] FROMLIST: riscv: qspinlock: errata: Add ERRATA_THEAD_WRITE_ONCE fixup The early version of T-Head C9xx cores has a store merge buffer delay problem. The store merge buffer could improve the store queue performance by merging multi-store requests, but when there are not continued store requests, the prior single store request would be waiting in the store queue for a long time. That would cause significant problems for communication between multi-cores. This problem was found on sg2042 & th1520 platforms with the qspinlock lock torture test. So appending a fence w.o could immediately flush the store merge buffer and let other cores see the write result. This will apply the WRITE_ONCE errata to handle the non-standard behavior via appending a fence w.o instruction for WRITE_ONCE(). This problem is only observed on the sg2042 hardware platform by running the lock_torture test program for half an hour. The problem was not found in the user space application, because interrupt can break the livelock. Reviewed-by: Leonardo Bras Signed-off-by: Guo Ren Signed-off-by: Guo Ren Tested-by: Inochi Amaoto Link: https://lore.kernel.org/r/20241214143039.4139398-3-guoren@kernel.org Signed-off-by: Han Gao --- arch/riscv/Kconfig.errata | 19 +++++++++++++++ arch/riscv/errata/thead/errata.c | 20 ++++++++++++++++ arch/riscv/include/asm/rwonce.h | 33 ++++++++++++++++++++++++++ arch/riscv/include/asm/vendorid_list.h | 3 ++- include/asm-generic/rwonce.h | 2 ++ 5 files changed, 76 insertions(+), 1 deletion(-) create mode 100644 arch/riscv/include/asm/rwonce.h diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata index e318119d570de0..fdd8b7de377cb2 100644 --- a/arch/riscv/Kconfig.errata +++ b/arch/riscv/Kconfig.errata @@ -130,4 +130,23 @@ config ERRATA_THEAD_GHOSTWRITE If you don't know what to do here, say "Y". +config ERRATA_THEAD_WRITE_ONCE + bool "Apply T-Head WRITE_ONCE errata" + depends on ERRATA_THEAD + default y + help + The early version of T-Head C9xx cores of sg2042 & th1520 have a store + merge buffer delay problem. The store merge buffer could improve the + store queue performance by merging multi-store requests, but when there + are no continued store requests, the prior single store request would be + waiting in the store queue for a long time. That would cause signifi- + cant problems for communication between multi-cores. Appending a + fence w.o could immediately flush the store merge buffer and let other + cores see the write result. + + This will apply the WRITE_ONCE errata to handle the non-standard beh- + avior via appending a fence w.o instruction for WRITE_ONCE(). + + If you don't know what to do here, say "Y". + endmenu # "CPU errata selection" diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c index 0b942183f708fe..fbe46f2fa8fbbd 100644 --- a/arch/riscv/errata/thead/errata.c +++ b/arch/riscv/errata/thead/errata.c @@ -168,6 +168,23 @@ static bool errata_probe_ghostwrite(unsigned int stage, return true; } +static bool errata_probe_write_once(unsigned int stage, + unsigned long arch_id, unsigned long impid) +{ + if (!IS_ENABLED(CONFIG_ERRATA_THEAD_WRITE_ONCE)) + return false; + + /* target-c9xx cores report arch_id and impid as 0 */ + if (arch_id != 0 || impid != 0) + return false; + + if (stage == RISCV_ALTERNATIVES_BOOT || + stage == RISCV_ALTERNATIVES_MODULE) + return true; + + return false; +} + static u32 thead_errata_probe(unsigned int stage, unsigned long archid, unsigned long impid) { @@ -183,6 +200,9 @@ static u32 thead_errata_probe(unsigned int stage, errata_probe_ghostwrite(stage, archid, impid); + if (errata_probe_write_once(stage, archid, impid)) + cpu_req_errata |= BIT(ERRATA_THEAD_WRITE_ONCE); + return cpu_req_errata; } diff --git a/arch/riscv/include/asm/rwonce.h b/arch/riscv/include/asm/rwonce.h new file mode 100644 index 00000000000000..756586746a4ff6 --- /dev/null +++ b/arch/riscv/include/asm/rwonce.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef __ASM_RWONCE_H +#define __ASM_RWONCE_H + +#include +#include +#include + +#if defined(CONFIG_ERRATA_THEAD_WRITE_ONCE) && !defined(NO_ALTERNATIVE) + +#define write_once_fence() \ +do { \ + asm volatile(ALTERNATIVE( \ + "nop", \ + "fence w, o", \ + THEAD_VENDOR_ID, \ + ERRATA_THEAD_WRITE_ONCE, \ + CONFIG_ERRATA_THEAD_WRITE_ONCE) \ + : : : "memory"); \ +} while (0) + +#define __WRITE_ONCE(x, val) \ +do { \ + *(volatile typeof(x) *)&(x) = (val); \ + write_once_fence(); \ +} while (0) + +#endif /* defined(CONFIG_ERRATA_THEAD_WRITE_ONCE) && !defined(NO_ALTERNATIVE) */ + +#include + +#endif /* __ASM_RWONCE_H */ diff --git a/arch/riscv/include/asm/vendorid_list.h b/arch/riscv/include/asm/vendorid_list.h index d9fed9bcedeb4b..da73440748eadc 100644 --- a/arch/riscv/include/asm/vendorid_list.h +++ b/arch/riscv/include/asm/vendorid_list.h @@ -25,7 +25,8 @@ #define ERRATA_THEAD_MAE 0 #define ERRATA_THEAD_PMU 1 #define ERRATA_THEAD_GHOSTWRITE 2 -#define ERRATA_THEAD_NUMBER 3 +#define ERRATA_THEAD_WRITE_ONCE 3 +#define ERRATA_THEAD_NUMBER 4 #endif #endif diff --git a/include/asm-generic/rwonce.h b/include/asm-generic/rwonce.h index 52b969c7cef935..4e2d941f15a11b 100644 --- a/include/asm-generic/rwonce.h +++ b/include/asm-generic/rwonce.h @@ -50,10 +50,12 @@ __READ_ONCE(x); \ }) +#ifndef __WRITE_ONCE #define __WRITE_ONCE(x, val) \ do { \ *(volatile typeof(x) *)&(x) = (val); \ } while (0) +#endif #define WRITE_ONCE(x, val) \ do { \ From 9320d35f9e25d06d113ce0b469a173e6adc1b231 Mon Sep 17 00:00:00 2001 From: Han Gao Date: Wed, 4 Jun 2025 21:12:25 +0800 Subject: [PATCH 14/34] FROMLIST: riscv: dts: sophgo: Add xtheadvector to the sg2042 devicetree The sg2042 SoCs support xtheadvector [1] so it can be included in the devicetree. Also include vlenb for the cpu. And set vlenb=16 [2]. This can be tested by passing the "mitigations=off" kernel parameter. Link: https://lore.kernel.org/linux-riscv/20241113-xtheadvector-v11-4-236c22791ef9@rivosinc.com/ [1] Link: https://lore.kernel.org/linux-riscv/aCO44SAoS2kIP61r@ghost/ [2] Reviewed-by: Inochi Amaoto Link: https://lore.kernel.org/r/8ea337dfd3458a5dc39a3b1892b4825899b74df3.1747235487.git.rabenda.cn@gmail.com Signed-off-by: Han Gao --- arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 192 +++++++++++++------- 1 file changed, 128 insertions(+), 64 deletions(-) diff --git a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi index b136b6c4128c05..dcc984965b6b87 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi @@ -260,7 +260,8 @@ riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <0>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -285,7 +286,8 @@ riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <1>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -310,7 +312,8 @@ riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <2>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -335,7 +338,8 @@ riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <3>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -360,7 +364,8 @@ riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <4>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -385,7 +390,8 @@ riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <5>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -410,7 +416,8 @@ riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <6>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -435,7 +442,8 @@ riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <7>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -460,7 +468,8 @@ riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <8>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -485,7 +494,8 @@ riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <9>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -510,7 +520,8 @@ riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <10>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -535,7 +546,8 @@ riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <11>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -560,7 +572,8 @@ riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <12>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -585,7 +598,8 @@ riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <13>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -610,7 +624,8 @@ riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <14>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -635,7 +650,8 @@ riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <15>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -660,7 +676,8 @@ riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <16>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -685,7 +702,8 @@ riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <17>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -710,7 +728,8 @@ riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <18>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -735,7 +754,8 @@ riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <19>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -760,7 +780,8 @@ riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <20>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -785,7 +806,8 @@ riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <21>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -810,7 +832,8 @@ riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <22>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -835,7 +858,8 @@ riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <23>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -860,7 +884,8 @@ riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <24>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -885,7 +910,8 @@ riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <25>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -910,7 +936,8 @@ riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <26>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -935,7 +962,8 @@ riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <27>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -960,7 +988,8 @@ riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <28>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -985,7 +1014,8 @@ riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <29>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1010,7 +1040,8 @@ riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <30>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1035,7 +1066,8 @@ riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <31>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1060,7 +1092,8 @@ riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <32>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1085,7 +1118,8 @@ riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <33>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1110,7 +1144,8 @@ riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <34>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1135,7 +1170,8 @@ riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <35>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1160,7 +1196,8 @@ riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <36>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1185,7 +1222,8 @@ riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <37>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1210,7 +1248,8 @@ riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <38>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1235,7 +1274,8 @@ riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <39>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1260,7 +1300,8 @@ riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <40>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1285,7 +1326,8 @@ riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <41>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1310,7 +1352,8 @@ riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <42>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1335,7 +1378,8 @@ riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <43>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1360,7 +1404,8 @@ riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <44>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1385,7 +1430,8 @@ riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <45>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1410,7 +1456,8 @@ riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <46>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1435,7 +1482,8 @@ riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <47>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1460,7 +1508,8 @@ riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <48>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1485,7 +1534,8 @@ riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <49>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1510,7 +1560,8 @@ riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <50>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1535,7 +1586,8 @@ riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <51>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1560,7 +1612,8 @@ riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <52>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1585,7 +1638,8 @@ riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <53>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1610,7 +1664,8 @@ riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <54>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1635,7 +1690,8 @@ riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <55>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1660,7 +1716,8 @@ riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <56>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1685,7 +1742,8 @@ riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <57>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1710,7 +1768,8 @@ riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <58>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1735,7 +1794,8 @@ riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <59>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1760,7 +1820,8 @@ riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <60>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1785,7 +1846,8 @@ riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <61>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1810,7 +1872,8 @@ riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <62>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1835,7 +1898,8 @@ riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadvector"; + thead,vlenb = <16>; reg = <63>; i-cache-block-size = <64>; i-cache-size = <65536>; From b831f19480553971c586e0de9016cd317b350d1e Mon Sep 17 00:00:00 2001 From: Han Gao Date: Wed, 4 Jun 2025 21:12:49 +0800 Subject: [PATCH 15/34] FROMLIST: riscv: dts: sophgo: add ziccrse for sg2042 sg2042 support Ziccrse ISA extension [1]. Link: https://lore.kernel.org/all/20241103145153.105097-12-alexghiti@rivosinc.com/ [1] Reviewed-by: Inochi Amaoto Link: https://lore.kernel.org/r/158b561a96e12c1d45a6b96d2039e03448ebea62.1747235487.git.rabenda.cn@gmail.com Signed-off-by: Han Gao --- arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 320 ++++++++++++-------- 1 file changed, 192 insertions(+), 128 deletions(-) diff --git a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi index dcc984965b6b87..f483f62ab0c4b2 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi @@ -259,8 +259,9 @@ riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <0>; i-cache-block-size = <64>; @@ -285,8 +286,9 @@ riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <1>; i-cache-block-size = <64>; @@ -311,8 +313,9 @@ riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <2>; i-cache-block-size = <64>; @@ -337,8 +340,9 @@ riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <3>; i-cache-block-size = <64>; @@ -363,8 +367,9 @@ riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <4>; i-cache-block-size = <64>; @@ -389,8 +394,9 @@ riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <5>; i-cache-block-size = <64>; @@ -415,8 +421,9 @@ riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <6>; i-cache-block-size = <64>; @@ -441,8 +448,9 @@ riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <7>; i-cache-block-size = <64>; @@ -467,8 +475,9 @@ riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <8>; i-cache-block-size = <64>; @@ -493,8 +502,9 @@ riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <9>; i-cache-block-size = <64>; @@ -519,8 +529,9 @@ riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <10>; i-cache-block-size = <64>; @@ -545,8 +556,9 @@ riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <11>; i-cache-block-size = <64>; @@ -571,8 +583,9 @@ riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <12>; i-cache-block-size = <64>; @@ -597,8 +610,9 @@ riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <13>; i-cache-block-size = <64>; @@ -623,8 +637,9 @@ riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <14>; i-cache-block-size = <64>; @@ -649,8 +664,9 @@ riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <15>; i-cache-block-size = <64>; @@ -675,8 +691,9 @@ riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <16>; i-cache-block-size = <64>; @@ -701,8 +718,9 @@ riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <17>; i-cache-block-size = <64>; @@ -727,8 +745,9 @@ riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <18>; i-cache-block-size = <64>; @@ -753,8 +772,9 @@ riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <19>; i-cache-block-size = <64>; @@ -779,8 +799,9 @@ riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <20>; i-cache-block-size = <64>; @@ -805,8 +826,9 @@ riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <21>; i-cache-block-size = <64>; @@ -831,8 +853,9 @@ riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <22>; i-cache-block-size = <64>; @@ -857,8 +880,9 @@ riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <23>; i-cache-block-size = <64>; @@ -883,8 +907,9 @@ riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <24>; i-cache-block-size = <64>; @@ -909,8 +934,9 @@ riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <25>; i-cache-block-size = <64>; @@ -935,8 +961,9 @@ riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <26>; i-cache-block-size = <64>; @@ -961,8 +988,9 @@ riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <27>; i-cache-block-size = <64>; @@ -987,8 +1015,9 @@ riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <28>; i-cache-block-size = <64>; @@ -1013,8 +1042,9 @@ riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <29>; i-cache-block-size = <64>; @@ -1039,8 +1069,9 @@ riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <30>; i-cache-block-size = <64>; @@ -1065,8 +1096,9 @@ riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <31>; i-cache-block-size = <64>; @@ -1091,8 +1123,9 @@ riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <32>; i-cache-block-size = <64>; @@ -1117,8 +1150,9 @@ riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <33>; i-cache-block-size = <64>; @@ -1143,8 +1177,9 @@ riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <34>; i-cache-block-size = <64>; @@ -1169,8 +1204,9 @@ riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <35>; i-cache-block-size = <64>; @@ -1195,8 +1231,9 @@ riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <36>; i-cache-block-size = <64>; @@ -1221,8 +1258,9 @@ riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <37>; i-cache-block-size = <64>; @@ -1247,8 +1285,9 @@ riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <38>; i-cache-block-size = <64>; @@ -1273,8 +1312,9 @@ riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <39>; i-cache-block-size = <64>; @@ -1299,8 +1339,9 @@ riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <40>; i-cache-block-size = <64>; @@ -1325,8 +1366,9 @@ riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <41>; i-cache-block-size = <64>; @@ -1351,8 +1393,9 @@ riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <42>; i-cache-block-size = <64>; @@ -1377,8 +1420,9 @@ riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <43>; i-cache-block-size = <64>; @@ -1403,8 +1447,9 @@ riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <44>; i-cache-block-size = <64>; @@ -1429,8 +1474,9 @@ riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <45>; i-cache-block-size = <64>; @@ -1455,8 +1501,9 @@ riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <46>; i-cache-block-size = <64>; @@ -1481,8 +1528,9 @@ riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <47>; i-cache-block-size = <64>; @@ -1507,8 +1555,9 @@ riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <48>; i-cache-block-size = <64>; @@ -1533,8 +1582,9 @@ riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <49>; i-cache-block-size = <64>; @@ -1559,8 +1609,9 @@ riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <50>; i-cache-block-size = <64>; @@ -1585,8 +1636,9 @@ riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <51>; i-cache-block-size = <64>; @@ -1611,8 +1663,9 @@ riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <52>; i-cache-block-size = <64>; @@ -1637,8 +1690,9 @@ riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <53>; i-cache-block-size = <64>; @@ -1663,8 +1717,9 @@ riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <54>; i-cache-block-size = <64>; @@ -1689,8 +1744,9 @@ riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <55>; i-cache-block-size = <64>; @@ -1715,8 +1771,9 @@ riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <56>; i-cache-block-size = <64>; @@ -1741,8 +1798,9 @@ riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <57>; i-cache-block-size = <64>; @@ -1767,8 +1825,9 @@ riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <58>; i-cache-block-size = <64>; @@ -1793,8 +1852,9 @@ riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <59>; i-cache-block-size = <64>; @@ -1819,8 +1879,9 @@ riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <60>; i-cache-block-size = <64>; @@ -1845,8 +1906,9 @@ riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <61>; i-cache-block-size = <64>; @@ -1871,8 +1933,9 @@ riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <62>; i-cache-block-size = <64>; @@ -1897,8 +1960,9 @@ riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xtheadvector"; + "ziccrse", "zicntr", "zicsr", + "zifencei", "zihpm", + "xtheadvector"; thead,vlenb = <16>; reg = <63>; i-cache-block-size = <64>; From 695ca3ac51df373b16dd4e031cc222392dfe5765 Mon Sep 17 00:00:00 2001 From: Han Gao Date: Wed, 4 Jun 2025 21:12:56 +0800 Subject: [PATCH 16/34] FROMLIST: riscv: dts: sophgo: add zfh for sg2042 sg2042 support Zfh ISA extension [1]. Link: https://occ-oss-prod.oss-cn-hangzhou.aliyuncs.com/resource//1737721869472/%E7%8E%84%E9%93%81C910%E4%B8%8EC920R1S6%E7%94%A8%E6%88%B7%E6%89%8B%E5%86%8C%28xrvm%29_20250124.pdf [1] Reviewed-by: Inochi Amaoto Link: https://lore.kernel.org/r/104dde6002c268a39fab6fcf469adc26d49ba364.1747235487.git.rabenda.cn@gmail.com Signed-off-by: Han Gao --- arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 256 ++++++++++---------- 1 file changed, 128 insertions(+), 128 deletions(-) diff --git a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi index f483f62ab0c4b2..8dd1a3c60bc436 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi @@ -256,11 +256,11 @@ cpu0: cpu@0 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <0>; @@ -283,11 +283,11 @@ cpu1: cpu@1 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <1>; @@ -310,11 +310,11 @@ cpu2: cpu@2 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <2>; @@ -337,11 +337,11 @@ cpu3: cpu@3 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <3>; @@ -364,11 +364,11 @@ cpu4: cpu@4 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <4>; @@ -391,11 +391,11 @@ cpu5: cpu@5 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <5>; @@ -418,11 +418,11 @@ cpu6: cpu@6 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <6>; @@ -445,11 +445,11 @@ cpu7: cpu@7 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <7>; @@ -472,11 +472,11 @@ cpu8: cpu@8 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <8>; @@ -499,11 +499,11 @@ cpu9: cpu@9 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <9>; @@ -526,11 +526,11 @@ cpu10: cpu@10 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <10>; @@ -553,11 +553,11 @@ cpu11: cpu@11 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <11>; @@ -580,11 +580,11 @@ cpu12: cpu@12 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <12>; @@ -607,11 +607,11 @@ cpu13: cpu@13 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <13>; @@ -634,11 +634,11 @@ cpu14: cpu@14 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <14>; @@ -661,11 +661,11 @@ cpu15: cpu@15 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <15>; @@ -688,11 +688,11 @@ cpu16: cpu@16 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <16>; @@ -715,11 +715,11 @@ cpu17: cpu@17 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <17>; @@ -742,11 +742,11 @@ cpu18: cpu@18 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <18>; @@ -769,11 +769,11 @@ cpu19: cpu@19 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <19>; @@ -796,11 +796,11 @@ cpu20: cpu@20 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <20>; @@ -823,11 +823,11 @@ cpu21: cpu@21 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <21>; @@ -850,11 +850,11 @@ cpu22: cpu@22 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <22>; @@ -877,11 +877,11 @@ cpu23: cpu@23 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <23>; @@ -904,11 +904,11 @@ cpu24: cpu@24 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <24>; @@ -931,11 +931,11 @@ cpu25: cpu@25 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <25>; @@ -958,11 +958,11 @@ cpu26: cpu@26 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <26>; @@ -985,11 +985,11 @@ cpu27: cpu@27 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <27>; @@ -1012,11 +1012,11 @@ cpu28: cpu@28 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <28>; @@ -1039,11 +1039,11 @@ cpu29: cpu@29 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <29>; @@ -1066,11 +1066,11 @@ cpu30: cpu@30 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <30>; @@ -1093,11 +1093,11 @@ cpu31: cpu@31 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <31>; @@ -1120,11 +1120,11 @@ cpu32: cpu@32 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <32>; @@ -1147,11 +1147,11 @@ cpu33: cpu@33 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <33>; @@ -1174,11 +1174,11 @@ cpu34: cpu@34 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <34>; @@ -1201,11 +1201,11 @@ cpu35: cpu@35 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <35>; @@ -1228,11 +1228,11 @@ cpu36: cpu@36 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <36>; @@ -1255,11 +1255,11 @@ cpu37: cpu@37 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <37>; @@ -1282,11 +1282,11 @@ cpu38: cpu@38 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <38>; @@ -1309,11 +1309,11 @@ cpu39: cpu@39 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <39>; @@ -1336,11 +1336,11 @@ cpu40: cpu@40 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <40>; @@ -1363,11 +1363,11 @@ cpu41: cpu@41 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <41>; @@ -1390,11 +1390,11 @@ cpu42: cpu@42 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <42>; @@ -1417,11 +1417,11 @@ cpu43: cpu@43 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <43>; @@ -1444,11 +1444,11 @@ cpu44: cpu@44 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <44>; @@ -1471,11 +1471,11 @@ cpu45: cpu@45 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <45>; @@ -1498,11 +1498,11 @@ cpu46: cpu@46 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <46>; @@ -1525,11 +1525,11 @@ cpu47: cpu@47 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <47>; @@ -1552,11 +1552,11 @@ cpu48: cpu@48 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <48>; @@ -1579,11 +1579,11 @@ cpu49: cpu@49 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <49>; @@ -1606,11 +1606,11 @@ cpu50: cpu@50 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <50>; @@ -1633,11 +1633,11 @@ cpu51: cpu@51 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <51>; @@ -1660,11 +1660,11 @@ cpu52: cpu@52 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <52>; @@ -1687,11 +1687,11 @@ cpu53: cpu@53 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <53>; @@ -1714,11 +1714,11 @@ cpu54: cpu@54 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <54>; @@ -1741,11 +1741,11 @@ cpu55: cpu@55 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <55>; @@ -1768,11 +1768,11 @@ cpu56: cpu@56 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <56>; @@ -1795,11 +1795,11 @@ cpu57: cpu@57 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <57>; @@ -1822,11 +1822,11 @@ cpu58: cpu@58 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <58>; @@ -1849,11 +1849,11 @@ cpu59: cpu@59 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <59>; @@ -1876,11 +1876,11 @@ cpu60: cpu@60 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <60>; @@ -1903,11 +1903,11 @@ cpu61: cpu@61 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <61>; @@ -1930,11 +1930,11 @@ cpu62: cpu@62 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <62>; @@ -1957,11 +1957,11 @@ cpu63: cpu@63 { compatible = "thead,c920", "riscv"; device_type = "cpu"; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zfh"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "ziccrse", "zicntr", "zicsr", - "zifencei", "zihpm", + "zifencei", "zihpm", "zfh", "xtheadvector"; thead,vlenb = <16>; reg = <63>; From 24861641669708047a8107c20a5e459816bd78e8 Mon Sep 17 00:00:00 2001 From: Han Gao Date: Wed, 4 Jun 2025 21:14:22 +0800 Subject: [PATCH 17/34] FROMLIST: dt-bindings: riscv: add Sophgo SG2042_EVB_V1.X bindings Add DT binding documentation for the Sophgo SG2042_EVB_V1.X board [1]. Link: https://github.com/sophgo/sophgo-hardware/tree/master/SG2042/SG2042-x8-EVB [1] Acked-by: Conor Dooley Link: https://lore.kernel.org/r/b538e2b24eab8b740091d80ca76b20ef6014a4e5.1747231254.git.rabenda.cn@gmail.com Signed-off-by: Han Gao --- Documentation/devicetree/bindings/riscv/sophgo.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/riscv/sophgo.yaml b/Documentation/devicetree/bindings/riscv/sophgo.yaml index a14cb10ff3f074..6c82f89b56caa2 100644 --- a/Documentation/devicetree/bindings/riscv/sophgo.yaml +++ b/Documentation/devicetree/bindings/riscv/sophgo.yaml @@ -34,6 +34,7 @@ properties: - items: - enum: - milkv,pioneer + - sophgo,sg2042-evb-v1 - const: sophgo,sg2042 additionalProperties: true From a0446d8f4b0467b6669470f2d04fe932c2e152e8 Mon Sep 17 00:00:00 2001 From: Han Gao Date: Wed, 4 Jun 2025 21:14:30 +0800 Subject: [PATCH 18/34] FROMLIST: riscv: dts: sophgo: add Sophgo SG2042_EVB_V1.X board device tree Sophgo SG2042_EVB_V1.X [1] is a prototype development board based on SG2042 Currently supports serial port, sdcard/emmc, pwm, fan speed control. Link: https://github.com/sophgo/sophgo-hardware/tree/master/SG2042/SG2042-x8-EVB [1] Link: https://lore.kernel.org/r/4f5eaf5285dbeb0de1c8aa4700ca0910273e7674.1747231254.git.rabenda.cn@gmail.com Signed-off-by: Han Gao --- arch/riscv/boot/dts/sophgo/Makefile | 1 + arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts | 247 +++++++++++++++++++ 2 files changed, 248 insertions(+) create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts diff --git a/arch/riscv/boot/dts/sophgo/Makefile b/arch/riscv/boot/dts/sophgo/Makefile index 47d4243a8f35a7..2470e30ae901fb 100644 --- a/arch/riscv/boot/dts/sophgo/Makefile +++ b/arch/riscv/boot/dts/sophgo/Makefile @@ -3,3 +3,4 @@ dtb-$(CONFIG_ARCH_SOPHGO) += cv1800b-milkv-duo.dtb dtb-$(CONFIG_ARCH_SOPHGO) += cv1812h-huashan-pi.dtb dtb-$(CONFIG_ARCH_SOPHGO) += sg2002-licheerv-nano-b.dtb dtb-$(CONFIG_ARCH_SOPHGO) += sg2042-milkv-pioneer.dtb +dtb-$(CONFIG_ARCH_SOPHGO) += sg2042-evb-v1.dtb diff --git a/arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts b/arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts new file mode 100644 index 00000000000000..4f39a2575b8eec --- /dev/null +++ b/arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts @@ -0,0 +1,247 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2025 Sophgo Technology Inc. All rights reserved. + */ + +#include "sg2042.dtsi" + +#include +#include + +/ { + model = "Sophgo SG2042 EVB V1.X"; + compatible = "sophgo,sg2042-evb-v1", "sophgo,sg2042"; + + chosen { + stdout-path = "serial0"; + }; + + gpio-power { + compatible = "gpio-keys"; + + key-power { + label = "Power Key"; + linux,code = ; + gpios = <&port0a 22 GPIO_ACTIVE_HIGH>; + linux,input-type = ; + debounce-interval = <100>; + }; + }; +}; + +&cgi_main { + clock-frequency = <25000000>; +}; + +&cgi_dpll0 { + clock-frequency = <25000000>; +}; + +&cgi_dpll1 { + clock-frequency = <25000000>; +}; + +&emmc { + pinctrl-0 = <&emmc_cfg>; + pinctrl-names = "default"; + bus-width = <4>; + no-sdio; + no-sd; + non-removable; + wp-inverted; + status = "okay"; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_cfg>; + pinctrl-names = "default"; + status = "okay"; + + mcu: syscon@17 { + compatible = "sophgo,sg2042-hwmon-mcu"; + reg = <0x17>; + #thermal-sensor-cells = <1>; + }; +}; + +&gmac0 { + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + status = "okay"; + + mdio { + phy0: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + reset-gpios = <&port0a 27 GPIO_ACTIVE_LOW>; + reset-assert-us = <100000>; + reset-deassert-us = <100000>; + }; + }; +}; + +&pinctrl { + emmc_cfg: sdhci-emmc-cfg { + sdhci-emmc-wp-pins { + pinmux = ; + bias-disable; + drive-strength-microamp = <26800>; + input-schmitt-disable; + }; + + sdhci-emmc-cd-pins { + pinmux = ; + bias-pull-up; + drive-strength-microamp = <26800>; + input-schmitt-enable; + }; + + sdhci-emmc-rst-pwr-pins { + pinmux = , + ; + bias-disable; + drive-strength-microamp = <26800>; + input-schmitt-disable; + }; + }; + + i2c1_cfg: i2c1-cfg { + i2c1-pins { + pinmux = , + ; + bias-pull-up; + drive-strength-microamp = <26800>; + input-schmitt-enable; + }; + }; + + sd_cfg: sdhci-sd-cfg { + sdhci-sd-cd-wp-pins { + pinmux = , + ; + bias-pull-up; + drive-strength-microamp = <26800>; + input-schmitt-enable; + }; + + sdhci-sd-rst-pwr-pins { + pinmux = , + ; + bias-disable; + drive-strength-microamp = <26800>; + input-schmitt-disable; + }; + }; + + uart0_cfg: uart0-cfg { + uart0-rx-pins { + pinmux = , + ; + bias-pull-up; + drive-strength-microamp = <26800>; + input-schmitt-enable; + }; + }; +}; + +&sd { + pinctrl-0 = <&sd_cfg>; + pinctrl-names = "default"; + bus-width = <4>; + no-sdio; + no-mmc; + wp-inverted; + status = "okay"; +}; + +&uart0 { + pinctrl-0 = <&uart0_cfg>; + pinctrl-names = "default"; + status = "okay"; +}; + +/ { + pwmfan: pwm-fan { + compatible = "pwm-fan"; + cooling-levels = <103 128 179 230 255>; + pwms = <&pwm 0 40000 0>; + #cooling-cells = <2>; + }; + + thermal-zones { + soc-thermal { + polling-delay-passive = <1000>; + polling-delay = <1000>; + thermal-sensors = <&mcu 0>; + + trips { + soc_active1: soc-active1 { + temperature = <30000>; + hysteresis = <8000>; + type = "active"; + }; + + soc_active2: soc-active2 { + temperature = <58000>; + hysteresis = <12000>; + type = "active"; + }; + + soc_active3: soc-active3 { + temperature = <70000>; + hysteresis = <10000>; + type = "active"; + }; + + soc_hot: soc-hot { + temperature = <80000>; + hysteresis = <5000>; + type = "hot"; + }; + }; + + cooling-maps { + map0 { + trip = <&soc_active1>; + cooling-device = <&pwmfan 0 1>; + }; + + map1 { + trip = <&soc_active2>; + cooling-device = <&pwmfan 1 2>; + }; + + map2 { + trip = <&soc_active3>; + cooling-device = <&pwmfan 2 3>; + }; + + map3 { + trip = <&soc_hot>; + cooling-device = <&pwmfan 3 4>; + }; + }; + }; + + board-thermal { + polling-delay-passive = <1000>; + polling-delay = <1000>; + thermal-sensors = <&mcu 1>; + + trips { + board_active: board-active { + temperature = <75000>; + hysteresis = <8000>; + type = "active"; + }; + }; + + cooling-maps { + map4 { + trip = <&board_active>; + cooling-device = <&pwmfan 3 4>; + }; + }; + }; + }; +}; From c9c9ce0fcac41135a4f54b64d534fbf09986f84c Mon Sep 17 00:00:00 2001 From: Han Gao Date: Wed, 4 Jun 2025 21:14:38 +0800 Subject: [PATCH 19/34] FROMLIST: dt-bindings: riscv: add Sophgo SG2042_EVB_V2.0 bindings Add DT binding documentation for the Sophgo SG2042_EVB_V2.0 board [1]. Link: https://github.com/sophgo/sophgo-hardware/tree/master/SG2042/SG2042-x4-EVB [1] Link: https://lore.kernel.org/r/dddabd3bb2c718a506d2b6669a8252cfe3872fa9.1747231254.git.rabenda.cn@gmail.com Signed-off-by: Han Gao --- Documentation/devicetree/bindings/riscv/sophgo.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/riscv/sophgo.yaml b/Documentation/devicetree/bindings/riscv/sophgo.yaml index 6c82f89b56caa2..cbfd07cc053df1 100644 --- a/Documentation/devicetree/bindings/riscv/sophgo.yaml +++ b/Documentation/devicetree/bindings/riscv/sophgo.yaml @@ -35,6 +35,7 @@ properties: - enum: - milkv,pioneer - sophgo,sg2042-evb-v1 + - sophgo,sg2042-evb-v2 - const: sophgo,sg2042 additionalProperties: true From b0f236201d35610e16e5468b77f1a8195160f094 Mon Sep 17 00:00:00 2001 From: Han Gao Date: Wed, 4 Jun 2025 21:14:45 +0800 Subject: [PATCH 20/34] FROMLIST: riscv: dts: sophgo: add Sophgo SG2042_EVB_V2.0 board device tree Sophgo SG2042_EVB_V2.0 [1] is a prototype development board based on SG2042 Currently supports serial port, sdcard/emmc, pwm, fan speed control. Link: https://github.com/sophgo/sophgo-hardware/tree/master/SG2042/SG2042-x4-EVB [1] Link: https://lore.kernel.org/r/53a9a794641af697be9170e6d0af464a39d862ae.1747231254.git.rabenda.cn@gmail.com Signed-off-by: Han Gao --- arch/riscv/boot/dts/sophgo/Makefile | 1 + arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts | 235 +++++++++++++++++++ 2 files changed, 236 insertions(+) create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts diff --git a/arch/riscv/boot/dts/sophgo/Makefile b/arch/riscv/boot/dts/sophgo/Makefile index 2470e30ae901fb..31fa46ef3bf69d 100644 --- a/arch/riscv/boot/dts/sophgo/Makefile +++ b/arch/riscv/boot/dts/sophgo/Makefile @@ -4,3 +4,4 @@ dtb-$(CONFIG_ARCH_SOPHGO) += cv1812h-huashan-pi.dtb dtb-$(CONFIG_ARCH_SOPHGO) += sg2002-licheerv-nano-b.dtb dtb-$(CONFIG_ARCH_SOPHGO) += sg2042-milkv-pioneer.dtb dtb-$(CONFIG_ARCH_SOPHGO) += sg2042-evb-v1.dtb +dtb-$(CONFIG_ARCH_SOPHGO) += sg2042-evb-v2.dtb diff --git a/arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts b/arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts new file mode 100644 index 00000000000000..8eba1a4ab1eeff --- /dev/null +++ b/arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts @@ -0,0 +1,235 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2025 Sophgo Technology Inc. All rights reserved. + */ + +#include "sg2042.dtsi" + +#include +#include + +/ { + model = "Sophgo SG2042 EVB V2.0"; + compatible = "sophgo,sg2042-evb-v2", "sophgo,sg2042"; + + chosen { + stdout-path = "serial0"; + }; +}; + +&cgi_main { + clock-frequency = <25000000>; +}; + +&cgi_dpll0 { + clock-frequency = <25000000>; +}; + +&cgi_dpll1 { + clock-frequency = <25000000>; +}; + +&emmc { + pinctrl-0 = <&emmc_cfg>; + pinctrl-names = "default"; + bus-width = <4>; + no-sdio; + no-sd; + non-removable; + wp-inverted; + status = "okay"; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_cfg>; + pinctrl-names = "default"; + status = "okay"; + + mcu: syscon@17 { + compatible = "sophgo,sg2042-hwmon-mcu"; + reg = <0x17>; + #thermal-sensor-cells = <1>; + }; +}; + +&gmac0 { + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + status = "okay"; + + mdio { + phy0: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + reset-gpios = <&port0a 27 GPIO_ACTIVE_LOW>; + reset-assert-us = <100000>; + reset-deassert-us = <100000>; + }; + }; +}; + +&pinctrl { + emmc_cfg: sdhci-emmc-cfg { + sdhci-emmc-wp-pins { + pinmux = ; + bias-disable; + drive-strength-microamp = <26800>; + input-schmitt-disable; + }; + + sdhci-emmc-cd-pins { + pinmux = ; + bias-pull-up; + drive-strength-microamp = <26800>; + input-schmitt-enable; + }; + + sdhci-emmc-rst-pwr-pins { + pinmux = , + ; + bias-disable; + drive-strength-microamp = <26800>; + input-schmitt-disable; + }; + }; + + i2c1_cfg: i2c1-cfg { + i2c1-pins { + pinmux = , + ; + bias-pull-up; + drive-strength-microamp = <26800>; + input-schmitt-enable; + }; + }; + + sd_cfg: sdhci-sd-cfg { + sdhci-sd-cd-wp-pins { + pinmux = , + ; + bias-pull-up; + drive-strength-microamp = <26800>; + input-schmitt-enable; + }; + + sdhci-sd-rst-pwr-pins { + pinmux = , + ; + bias-disable; + drive-strength-microamp = <26800>; + input-schmitt-disable; + }; + }; + + uart0_cfg: uart0-cfg { + uart0-rx-pins { + pinmux = , + ; + bias-pull-up; + drive-strength-microamp = <26800>; + input-schmitt-enable; + }; + }; +}; + +&sd { + pinctrl-0 = <&sd_cfg>; + pinctrl-names = "default"; + bus-width = <4>; + no-sdio; + no-mmc; + wp-inverted; + status = "okay"; +}; + +&uart0 { + pinctrl-0 = <&uart0_cfg>; + pinctrl-names = "default"; + status = "okay"; +}; + +/ { + pwmfan: pwm-fan { + compatible = "pwm-fan"; + cooling-levels = <103 128 179 230 255>; + pwms = <&pwm 0 40000 0>; + #cooling-cells = <2>; + }; + + thermal-zones { + soc-thermal { + polling-delay-passive = <1000>; + polling-delay = <1000>; + thermal-sensors = <&mcu 0>; + + trips { + soc_active1: soc-active1 { + temperature = <30000>; + hysteresis = <8000>; + type = "active"; + }; + + soc_active2: soc-active2 { + temperature = <58000>; + hysteresis = <12000>; + type = "active"; + }; + + soc_active3: soc-active3 { + temperature = <70000>; + hysteresis = <10000>; + type = "active"; + }; + + soc_hot: soc-hot { + temperature = <80000>; + hysteresis = <5000>; + type = "hot"; + }; + }; + + cooling-maps { + map0 { + trip = <&soc_active1>; + cooling-device = <&pwmfan 0 1>; + }; + + map1 { + trip = <&soc_active2>; + cooling-device = <&pwmfan 1 2>; + }; + + map2 { + trip = <&soc_active3>; + cooling-device = <&pwmfan 2 3>; + }; + + map3 { + trip = <&soc_hot>; + cooling-device = <&pwmfan 3 4>; + }; + }; + }; + + board-thermal { + polling-delay-passive = <1000>; + polling-delay = <1000>; + thermal-sensors = <&mcu 1>; + + trips { + board_active: board-active { + temperature = <75000>; + hysteresis = <8000>; + type = "active"; + }; + }; + + cooling-maps { + map4 { + trip = <&board_active>; + cooling-device = <&pwmfan 3 4>; + }; + }; + }; + }; +}; From 17b8671656e244c9588dd32a72934107b179ef64 Mon Sep 17 00:00:00 2001 From: Han Gao Date: Wed, 4 Jun 2025 21:15:05 +0800 Subject: [PATCH 21/34] FROMLIST: riscv: vector: Fix context save/restore with xtheadvector Previously only v0-v7 were correctly saved/restored, and the context of v8-v31 are damanged. Correctly save/restore v8-v31 to avoid breaking userspace. Fixes: d863910eabaf ("riscv: vector: Support xtheadvector save/restore") Tested-by: Xiongchuan Tan Reviewed-by: Charlie Jenkins Reviewed-by: Yanteng Si Reviewed-by: Andy Chiu Link: https://lore.kernel.org/r/9b9eb2337f3d5336ce813721f8ebea51e0b2b553.1747994822.git.rabenda.cn@gmail.com Signed-off-by: Han Gao --- arch/riscv/include/asm/vector.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h index e8a83f55be2ba5..7df6355023a30a 100644 --- a/arch/riscv/include/asm/vector.h +++ b/arch/riscv/include/asm/vector.h @@ -200,11 +200,11 @@ static inline void __riscv_v_vstate_save(struct __riscv_v_ext_state *save_to, THEAD_VSETVLI_T4X0E8M8D1 THEAD_VSB_V_V0T0 "add t0, t0, t4\n\t" - THEAD_VSB_V_V0T0 + THEAD_VSB_V_V8T0 "add t0, t0, t4\n\t" - THEAD_VSB_V_V0T0 + THEAD_VSB_V_V16T0 "add t0, t0, t4\n\t" - THEAD_VSB_V_V0T0 + THEAD_VSB_V_V24T0 : : "r" (datap) : "memory", "t0", "t4"); } else { asm volatile ( @@ -236,11 +236,11 @@ static inline void __riscv_v_vstate_restore(struct __riscv_v_ext_state *restore_ THEAD_VSETVLI_T4X0E8M8D1 THEAD_VLB_V_V0T0 "add t0, t0, t4\n\t" - THEAD_VLB_V_V0T0 + THEAD_VLB_V_V8T0 "add t0, t0, t4\n\t" - THEAD_VLB_V_V0T0 + THEAD_VLB_V_V16T0 "add t0, t0, t4\n\t" - THEAD_VLB_V_V0T0 + THEAD_VLB_V_V24T0 : : "r" (datap) : "memory", "t0", "t4"); } else { asm volatile ( From 74fa4669a5fea1d7851f3f006c1608d559657587 Mon Sep 17 00:00:00 2001 From: Zixian Zeng Date: Wed, 4 Jun 2025 21:16:06 +0800 Subject: [PATCH 22/34] FROMLIST: spi: dt-bindings: spi-sg2044-nor: Add SOPHGO SG2042 Add bindings for the SOPHGO SG2042 SPI-NOR flash controller, which is compatible with SOPHGO SG2044. Signed-off-by: Zixian Zeng Reviewed-by: Chen Wang Link: https://lore.kernel.org/r/20250525-sfg-spifmc-v2-1-a3732b6f5ab4@gmail.com Signed-off-by: Han Gao --- Documentation/devicetree/bindings/spi/spi-sg2044-nor.yaml | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/spi/spi-sg2044-nor.yaml b/Documentation/devicetree/bindings/spi/spi-sg2044-nor.yaml index 948ff7a096433a..66e54dedab140a 100644 --- a/Documentation/devicetree/bindings/spi/spi-sg2044-nor.yaml +++ b/Documentation/devicetree/bindings/spi/spi-sg2044-nor.yaml @@ -14,7 +14,12 @@ allOf: properties: compatible: - const: sophgo,sg2044-spifmc-nor + oneOf: + - const: sophgo,sg2044-spifmc-nor + - items: + - enum: + - sophgo,sg2042-spifmc-nor + - const: sophgo,sg2044-spifmc-nor reg: maxItems: 1 From dbfcc8d1b03b506ef7fd33a095bc0f1a3e213ccc Mon Sep 17 00:00:00 2001 From: Zixian Zeng Date: Wed, 4 Jun 2025 21:16:17 +0800 Subject: [PATCH 23/34] FROMLIST: mtd: spi-nor: Add GD25LB512ME GigaDevice flash_info Add GD25LB512ME SPI-NOR flash information. The following SFDP dump was generated after applying the current commit. ------------------------------------------------------------------------ This flash is populated on the SG2042 Pioneer board and was tested at 100MHz frequency using the spi-sg2044-nor SPI controller. root@localhost ~ # cat /sys/bus/spi/devices/spi0.0/spi-nor/partname gd25lb512me root@localhost ~ # cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id c8671a root@localhost ~ # cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer gigadevice root@localhost ~ # xxd -p /sys/bus/spi/devices/spi0.0/spi-nor/sfdp 53464450060102ff00060110300000ffc8000103900000ff84000102c000 00ffffffffffffffffffffffffffffffffffe520eaffffffff1f44eb086b 003b00bbfeffffffffff00ffffff44eb0c200f5210d800ffd531b1fe83d6 1458ec6006337a757a7504bdd55c2906740008500001ffffffffffffffff ffffffffffffffffffffffffffffffffffffffffffffffff002050169df9 8156d9c8ffffffffffffffffffffffffffffffffffffffffffffffffffff fffffffffffffffffffffffff38ff0ff215cdcff root@localhost ~ # sha256sum /sys/bus/spi/devices/spi0.0/spi-nor/sfdp 859eb314b0500aa3e3dc5a1ad514f1013387c7aaa40147ed2d616ffc4b6d851c /sys/bus/spi/devices/spi0.0/spi-nor/sfdp root@localhost ~ # #Dump debugfs data root@localhost ~ # cat /sys/kernel/debug/spi-nor/spi0.0/capabilities Supported read modes by the flash 1S-1S-1S opcode 0x13 mode cycles 0 dummy cycles 0 1S-1S-4S opcode 0x6c mode cycles 0 dummy cycles 8 1S-4S-4S opcode 0xec mode cycles 2 dummy cycles 4 4S-4S-4S opcode 0xec mode cycles 2 dummy cycles 4 Supported page program modes by the flash 1S-1S-1S opcode 0x12 1S-1S-4S opcode 0x34 1S-4S-4S opcode 0x3e root@localhost ~ # cat /sys/kernel/debug/spi-nor/spi0.0/params name gd25lb512me id c8 67 1a ff c8 67 size 64.0 MiB write size 1 page size 256 address nbytes 4 flags HAS_SR_TB | 4B_OPCODES | HAS_4BAIT | HAS_LOCK | HAS_16BIT_SR | SOFT_RESET opcodes read 0x13 dummy cycles 0 erase 0x21 program 0x12 8D extension none protocols read 1S-1S-1S write 1S-1S-1S register 1S-1S-1S erase commands 21 (4.00 KiB) [1] 5c (32.0 KiB) [2] dc (64.0 KiB) [3] c7 (64.0 MiB) sector map region (in hex) | erase mask | overlaid ------------------+------------+---------- 00000000-03ffffff | [ 1 ] | no root@localhost ~ # dd if=/dev/urandom of=./spi_test bs=1M count=2 2+0 records in 2+0 records out 2097152 bytes (2.1 MB, 2.0 MiB) copied, 0.0279486 s, 75.0 MB/s root@localhost ~ # mtd_debug erase /dev/mtd0 0 2097152 Erased 2097152 bytes from address 0x00000000 in flash root@localhost ~ # mtd_debug read /dev/mtd0 0 2097152 spi_read Copied 2097152 bytes from address 0x00000000 in flash to spi_read root@localhost ~ # hexdump spi_read 0000000 ffff ffff ffff ffff ffff ffff ffff ffff * 0200000 root@localhost ~ # sha256sum spi_read 4bda3a28f4ffe603c0ec1258c0034d65a1a0d35ab7bd523a834608adabf03cc5 spi_read root@localhost ~ # mtd_debug write /dev/mtd0 0 2097152 spi_test Copied 2097152 bytes from spi_test to address 0x00000000 in flash root@localhost ~ # mtd_debug read /dev/mtd0 0 2097152 spi_read Copied 2097152 bytes from address 0x00000000 in flash to spi_read root@localhost ~ # sha256sum spi* a2ebfaebe38974847a4efb628b29a72f1d50e78c17318869d8954b033dc32e5d spi_read a2ebfaebe38974847a4efb628b29a72f1d50e78c17318869d8954b033dc32e5d spi_test root@localhost ~ # mtd_debug info /dev/mtd0 mtd.type = MTD_NORFLASH mtd.flags = MTD_CAP_NORFLASH mtd.size = 67108864 (64M) mtd.erasesize = 4096 (4K) mtd.writesize = 1 mtd.oobsize = 0 regions = 0 Signed-off-by: Zixian Zeng Link: https://lore.kernel.org/r/20250525-sfg-spifmc-v2-2-a3732b6f5ab4@gmail.com Signed-off-by: Han Gao --- drivers/mtd/spi-nor/gigadevice.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/mtd/spi-nor/gigadevice.c b/drivers/mtd/spi-nor/gigadevice.c index ef1edd0add70e6..223b2f598ecd65 100644 --- a/drivers/mtd/spi-nor/gigadevice.c +++ b/drivers/mtd/spi-nor/gigadevice.c @@ -33,6 +33,15 @@ static const struct spi_nor_fixups gd25q256_fixups = { .post_bfpt = gd25q256_post_bfpt, }; +static void gd25lb512me_default_init(struct spi_nor *nor) +{ + nor->params->quad_enable = spi_nor_sr1_bit6_quad_enable; +} + +static const struct spi_nor_fixups gd25lb512me_fixups = { + .default_init = gd25lb512me_default_init, +}; + static const struct flash_info gigadevice_nor_parts[] = { { .id = SNOR_ID(0xc8, 0x40, 0x15), @@ -82,6 +91,14 @@ static const struct flash_info gigadevice_nor_parts[] = { .size = SZ_16M, .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB, .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, + }, { + .id = SNOR_ID(0xc8, 0x67, 0x1a), + .name = "gd25lb512me", + .size = SZ_64M, + .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB, + .no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ, + .fixups = &gd25lb512me_fixups, + .fixup_flags = SPI_NOR_4B_OPCODES, }, }; From 56bb2bda59fc05e1b3d119c129db79ce3c3df56c Mon Sep 17 00:00:00 2001 From: Zixian Zeng Date: Wed, 4 Jun 2025 21:16:24 +0800 Subject: [PATCH 24/34] FROMLIST: riscv: dts: sophgo: Add SPI NOR node for SG2042 Add SPI-NOR controller and flash nodes to device tree for SG2042. Signed-off-by: Zixian Zeng Reviewed-by: Chen Wang Link: https://lore.kernel.org/r/20250525-sfg-spifmc-v2-3-a3732b6f5ab4@gmail.com Signed-off-by: Han Gao --- .../boot/dts/sophgo/sg2042-milkv-pioneer.dts | 18 ++++++++++++++ arch/riscv/boot/dts/sophgo/sg2042.dtsi | 24 +++++++++++++++++++ 2 files changed, 42 insertions(+) diff --git a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts index b5b8d4879549ed..3a100fe94e5a29 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts +++ b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts @@ -150,6 +150,24 @@ status = "okay"; }; +&spifmc0 { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + }; +}; + +&spifmc1 { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + }; +}; + &uart0 { pinctrl-0 = <&uart0_cfg>; pinctrl-names = "default"; diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi index c206f315283974..5b85a01ae6e78d 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi @@ -48,6 +48,30 @@ interrupt-parent = <&intc>; ranges; + spifmc0: spi@7000180000 { + compatible = "sophgo,sg2042-spifmc-nor", "sophgo,sg2044-spifmc-nor"; + reg = <0x70 0x00180000 0x0 0x1000000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clkgen GATE_CLK_AHB_SF>; + interrupt-parent = <&intc>; + interrupts = <108 IRQ_TYPE_LEVEL_HIGH>; + resets = <&rstgen RST_SF0>; + status = "disabled"; + }; + + spifmc1: spi@7002180000 { + compatible = "sophgo,sg2042-spifmc-nor", "sophgo,sg2044-spifmc-nor"; + reg = <0x70 0x02180000 0x0 0x1000000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clkgen GATE_CLK_AHB_SF>; + interrupt-parent = <&intc>; + interrupts = <109 IRQ_TYPE_LEVEL_HIGH>; + resets = <&rstgen RST_SF1>; + status = "disabled"; + }; + i2c0: i2c@7030005000 { compatible = "snps,designware-i2c"; reg = <0x70 0x30005000 0x0 0x1000>; From 87eadda207296e2f042b934666aa3cb19a1adcaa Mon Sep 17 00:00:00 2001 From: "xiaoguang.xing" Date: Wed, 4 Jun 2025 21:20:12 +0800 Subject: [PATCH 25/34] SOPHGO: riscv: kexec: Add image loader for kexec file FROM: https://github.com/sophgo/linux-riscv/commit/03fc4f7ede860864b27b63a1ff62de1ae71a1d3e Signed-off-by: Han Gao Tested-by: Han Gao --- arch/riscv/Kconfig | 2 +- arch/riscv/include/asm/kexec.h | 1 + arch/riscv/kernel/Makefile | 2 +- arch/riscv/kernel/image_kexec.c | 306 +++++++++++++++++++++++++ arch/riscv/kernel/machine_kexec_file.c | 1 + arch/riscv/mm/init.c | 2 +- 6 files changed, 311 insertions(+), 3 deletions(-) create mode 100644 arch/riscv/kernel/image_kexec.c diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index bbec87b7930999..b4b3a1385edfcb 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -57,7 +57,7 @@ config RISCV select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST select ARCH_HAS_UBSAN select ARCH_HAS_VDSO_ARCH_DATA if GENERIC_VDSO_DATA_STORE - select ARCH_KEEP_MEMBLOCK if ACPI + select ARCH_KEEP_MEMBLOCK select ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE if 64BIT && MMU select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT diff --git a/arch/riscv/include/asm/kexec.h b/arch/riscv/include/asm/kexec.h index 2b56769cb530cb..62f3ddc7c49833 100644 --- a/arch/riscv/include/asm/kexec.h +++ b/arch/riscv/include/asm/kexec.h @@ -56,6 +56,7 @@ extern riscv_kexec_method riscv_kexec_norelocate; #ifdef CONFIG_KEXEC_FILE extern const struct kexec_file_ops elf_kexec_ops; +extern const struct kexec_file_ops image_kexec_ops; struct purgatory_info; int arch_kexec_apply_relocations_add(struct purgatory_info *pi, diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile index f7480c9c6f8d73..95354939765297 100644 --- a/arch/riscv/kernel/Makefile +++ b/arch/riscv/kernel/Makefile @@ -107,7 +107,7 @@ obj-$(CONFIG_HOTPLUG_CPU) += cpu-hotplug.o obj-$(CONFIG_PARAVIRT) += paravirt.o obj-$(CONFIG_KGDB) += kgdb.o obj-$(CONFIG_KEXEC_CORE) += kexec_relocate.o crash_save_regs.o machine_kexec.o -obj-$(CONFIG_KEXEC_FILE) += elf_kexec.o machine_kexec_file.o +obj-$(CONFIG_KEXEC_FILE) += elf_kexec.o image_kexec.o machine_kexec_file.o obj-$(CONFIG_CRASH_DUMP) += crash_dump.o obj-$(CONFIG_VMCORE_INFO) += vmcore_info.o diff --git a/arch/riscv/kernel/image_kexec.c b/arch/riscv/kernel/image_kexec.c new file mode 100644 index 00000000000000..859b0d067962bf --- /dev/null +++ b/arch/riscv/kernel/image_kexec.c @@ -0,0 +1,306 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Kexec image loader + + * Adapted from arch/arm64/kernel/kexec_image.c + * Copyright (C) 2018 Linaro Limited + * Author: AKASHI Takahiro + */ +#define pr_fmt(fmt) "kexec_file(Image): " fmt + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static int prepare_elf_headers(void **addr, unsigned long *sz) +{ + struct crash_mem *cmem; + unsigned int nr_ranges; + int ret; + u64 i; + phys_addr_t start, end; + + nr_ranges = 2; /* for exclusion of crashkernel region */ + for_each_mem_range(i, &start, &end) + nr_ranges++; + + cmem = kmalloc(struct_size(cmem, ranges, nr_ranges), GFP_KERNEL); + if (!cmem) + return -ENOMEM; + + cmem->max_nr_ranges = nr_ranges; + cmem->nr_ranges = 0; + for_each_mem_range(i, &start, &end) { + cmem->ranges[cmem->nr_ranges].start = start; + cmem->ranges[cmem->nr_ranges].end = end - 1; + cmem->nr_ranges++; + } + + /* Exclude crashkernel region */ + ret = crash_exclude_mem_range(cmem, crashk_res.start, crashk_res.end); + if (ret) + goto out; + + if (crashk_low_res.end) { + ret = crash_exclude_mem_range(cmem, crashk_low_res.start, crashk_low_res.end); + if (ret) + goto out; + } + + ret = crash_prepare_elf64_headers(cmem, true, addr, sz); + +out: + kfree(cmem); + return ret; +} + +/* + * Tries to add the initrd and DTB to the image. If it is not possible to find + * valid locations, this function will undo changes to the image and return non + * zero. + */ +static int load_other_segments(struct kimage *image, + unsigned long kernel_load_addr, + unsigned long kernel_size, + char *initrd, unsigned long initrd_len, + char *cmdline) +{ + struct kexec_buf kbuf; + void *headers, *fdt = NULL; + unsigned long headers_sz, initrd_load_addr = 0, + orig_segments = image->nr_segments; + int ret = 0; + + kbuf.image = image; + /* not allocate anything below the kernel */ + kbuf.buf_min = kernel_load_addr + kernel_size; + + /* load elf core header */ + if (image->type == KEXEC_TYPE_CRASH) { + ret = prepare_elf_headers(&headers, &headers_sz); + if (ret) { + pr_err("Preparing elf core header failed\n"); + goto out_err; + } + + kbuf.buffer = headers; + kbuf.bufsz = headers_sz; + kbuf.mem = KEXEC_BUF_MEM_UNKNOWN; + kbuf.memsz = headers_sz; + kbuf.buf_align = PAGE_SIZE; + kbuf.buf_max = ULONG_MAX; + kbuf.top_down = true; + + ret = kexec_add_buffer(&kbuf); + if (ret) { + vfree(headers); + goto out_err; + } + image->elf_headers = headers; + image->elf_load_addr = kbuf.mem; + image->elf_headers_sz = headers_sz; + + pr_debug("Loaded elf core header at 0x%lx bufsz=0x%lx memsz=0x%lx\n", + image->elf_load_addr, kbuf.bufsz, kbuf.memsz); + } + + /* load initrd */ + if (initrd) { + kbuf.buffer = initrd; + kbuf.bufsz = initrd_len; + kbuf.mem = KEXEC_BUF_MEM_UNKNOWN; + kbuf.memsz = initrd_len; + kbuf.buf_align = PAGE_SIZE; + /* avoid to overlap kernel address */ + kbuf.buf_min = round_up(kernel_load_addr, SZ_1G); + kbuf.buf_max = ULONG_MAX; + kbuf.top_down = false; + + ret = kexec_add_buffer(&kbuf); + if (ret) + goto out_err; + initrd_load_addr = kbuf.mem; + + pr_debug("Loaded initrd at 0x%lx bufsz=0x%lx memsz=0x%lx\n", + initrd_load_addr, kbuf.bufsz, kbuf.memsz); + } + + /* load dtb */ + fdt = of_kexec_alloc_and_setup_fdt(image, initrd_load_addr, + initrd_len, cmdline, 0); + if (!fdt) { + pr_err("Preparing for new dtb failed\n"); + ret = -EINVAL; + goto out_err; + } + + /* trim it */ + fdt_pack(fdt); + kbuf.buffer = fdt; + kbuf.bufsz = kbuf.memsz = fdt_totalsize(fdt); + kbuf.buf_align = PAGE_SIZE; + kbuf.buf_max = ULONG_MAX; + kbuf.mem = KEXEC_BUF_MEM_UNKNOWN; + kbuf.top_down = false; + + ret = kexec_add_buffer(&kbuf); + if (ret) + goto out_err; + /* Cache the fdt buffer address for memory cleanup */ + image->arch.fdt = fdt; + image->arch.fdt_addr = kbuf.mem; + + pr_debug("Loaded dtb at 0x%lx bufsz=0x%lx memsz=0x%lx\n", + kbuf.mem, kbuf.bufsz, kbuf.memsz); + + return 0; + +out_err: + image->nr_segments = orig_segments; + kvfree(fdt); + return ret; +} + +static int image_probe(const char *kernel_buf, unsigned long kernel_len) +{ + const struct riscv_image_header *h = + (const struct riscv_image_header *)(kernel_buf); + + if (!h || (kernel_len < sizeof(*h))) + return -EINVAL; + + if (memcmp(&h->magic2, RISCV_IMAGE_MAGIC2, sizeof(h->magic2))) + return -EINVAL; + + return 0; +} + +static void *image_load(struct kimage *image, + char *kernel, unsigned long kernel_len, + char *initrd, unsigned long initrd_len, + char *cmdline, unsigned long cmdline_len) +{ + struct riscv_image_header *h; + u64 flags; + bool be_image, be_kernel; + struct kexec_buf kbuf; + unsigned long text_offset, kernel_segment_number; + unsigned long kernel_start; + struct kexec_segment *kernel_segment; + int ret; + + h = (struct riscv_image_header *)kernel; + if (!h->image_size) + return ERR_PTR(-EINVAL); + + /* Check cpu features */ + flags = le64_to_cpu(h->flags); + be_image = __HEAD_FLAG(BE); + be_kernel = IS_ENABLED(CONFIG_CPU_BIG_ENDIAN); + if (be_image != be_kernel) + return ERR_PTR(-EINVAL); + + /* Load the kernel */ + kbuf.image = image; + kbuf.buf_min = 0; + kbuf.buf_max = ULONG_MAX; + kbuf.top_down = false; + + kbuf.buffer = kernel; + kbuf.bufsz = kernel_len; + kbuf.mem = KEXEC_BUF_MEM_UNKNOWN; + kbuf.memsz = le64_to_cpu(h->image_size); + text_offset = le64_to_cpu(h->text_offset); + kbuf.buf_align = PMD_SIZE; + + /* Adjust kernel segment with TEXT_OFFSET */ + kbuf.memsz += text_offset; + + kernel_segment_number = image->nr_segments; + + /* + * The location of the kernel segment may make it impossible to satisfy + * the other segment requirements, so we try repeatedly to find a + * location that will work. + */ + while ((ret = kexec_add_buffer(&kbuf)) == 0) { + /* Try to load additional data */ + kernel_segment = &image->segment[kernel_segment_number]; + ret = load_other_segments(image, kernel_segment->mem, + kernel_segment->memsz, initrd, + initrd_len, cmdline); + if (!ret) + break; + + /* + * We couldn't find space for the other segments; erase the + * kernel segment and try the next available hole. + */ + image->nr_segments -= 1; + kbuf.buf_min = kernel_segment->mem + kernel_segment->memsz; + kbuf.mem = KEXEC_BUF_MEM_UNKNOWN; + } + + if (ret) { + pr_err("Could not find any suitable kernel location!"); + return ERR_PTR(ret); + } + + kernel_segment = &image->segment[kernel_segment_number]; + kernel_segment->mem += text_offset; + kernel_segment->memsz -= text_offset; + kernel_start = kernel_segment->mem; + image->start = kernel_start; + + + pr_debug("Loaded kernel at 0x%lx bufsz=0x%lx memsz=0x%lx\n", + kernel_segment->mem, kbuf.bufsz, + kernel_segment->memsz); + +#ifdef CONFIG_ARCH_SUPPORTS_KEXEC_PURGATORY + /* Add purgatory to the image */ + kbuf.top_down = true; + kbuf.mem = KEXEC_BUF_MEM_UNKNOWN; + ret = kexec_load_purgatory(image, &kbuf); + if (ret) { + pr_err("Error loading purgatory ret=%d\n", ret); + return ERR_PTR(ret); + } + ret = kexec_purgatory_get_set_symbol(image, "riscv_kernel_entry", + &kernel_start, + sizeof(kernel_start), 0); + if (ret) + pr_err("Error update purgatory ret=%d\n", ret); +#endif /* CONFIG_ARCH_SUPPORTS_KEXEC_PURGATORY */ + + return ret ? ERR_PTR(ret) : NULL; +} + +#ifdef CONFIG_KEXEC_IMAGE_VERIFY_SIG +static int image_verify_sig(const char *kernel, unsigned long kernel_len) +{ + return verify_pefile_signature(kernel, kernel_len, NULL, + VERIFYING_KEXEC_PE_SIGNATURE); +} +#endif + +const struct kexec_file_ops image_kexec_ops = { + .probe = image_probe, + .load = image_load, +#ifdef CONFIG_KEXEC_IMAGE_VERIFY_SIG + .verify_sig = image_verify_sig, +#endif +}; diff --git a/arch/riscv/kernel/machine_kexec_file.c b/arch/riscv/kernel/machine_kexec_file.c index b0bf8c1722c0cc..401edfd1774fad 100644 --- a/arch/riscv/kernel/machine_kexec_file.c +++ b/arch/riscv/kernel/machine_kexec_file.c @@ -9,6 +9,7 @@ #include const struct kexec_file_ops * const kexec_file_loaders[] = { + &image_kexec_ops, &elf_kexec_ops, NULL }; diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c index ab475ec6ca429e..6d9f02874fb47c 100644 --- a/arch/riscv/mm/init.c +++ b/arch/riscv/mm/init.c @@ -1307,7 +1307,7 @@ static void __init create_linear_mapping_page_table(void) __pa(PAGE_OFFSET) < end) start = __pa(PAGE_OFFSET); - create_linear_mapping_range(start, end, 0, NULL); + create_linear_mapping_range(start, end, PMD_SIZE, NULL); } #ifdef CONFIG_STRICT_KERNEL_RWX From f35d9cabadf8eafefe425e5090401c4b8fe75699 Mon Sep 17 00:00:00 2001 From: Han Gao Date: Wed, 4 Jun 2025 21:21:04 +0800 Subject: [PATCH 26/34] REVYOS: pcie: sg2042: pcie_rc1 use msi as msi-parent Signed-off-by: Han Gao --- arch/riscv/boot/dts/sophgo/sg2042.dtsi | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi index 5b85a01ae6e78d..761cba7babba7e 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi @@ -293,15 +293,8 @@ cdns,no-bar-match-nbits = <48>; sophgo,link-id = <0>; sophgo,syscon-pcie-ctrl = <&cdns_pcie1_ctrl>; - msi-parent = <&msi_pcie>; + msi-parent = <&msi>; status = "disabled"; - msi_pcie: msi { - compatible = "sophgo,sg2042-pcie-msi"; - msi-controller; - interrupt-parent = <&intc>; - interrupts = <123 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "msi"; - }; }; pcie_rc2: pcie@7062800000 { From 776811524950a9db8660b1c6cb454cddbeb9b772 Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Wed, 4 Jun 2025 21:22:44 +0800 Subject: [PATCH 27/34] REVYOS: dts: sophgo: sg2042: move pcie domain config into board devicetree Signed-off-by: Inochi Amaoto Signed-off-by: Han Gao --- .../boot/dts/sophgo/sg2042-milkv-pioneer.dts | 22 +++++++++++++++++-- arch/riscv/boot/dts/sophgo/sg2042.dtsi | 22 ++----------------- 2 files changed, 22 insertions(+), 22 deletions(-) diff --git a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts index 3a100fe94e5a29..b165249db0a559 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts +++ b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts @@ -65,14 +65,32 @@ }; &pcie_rc0 { + reg = <0x70 0x60000000 0x0 0x02000000>, + <0x40 0x00000000 0x0 0x00001000>; + linux,pci-domain = <0>; + bus-range = <0x00 0x7f>; + vendor-id = <0x1f1c>; + device-id = <0x2042>; status = "okay"; }; -&pcie_rc1 { +&pcie_rc2 { + reg = <0x70 0x62000000 0x0 0x00800000>, + <0x48 0x00000000 0x0 0x00001000>; + linux,pci-domain = <1>; + bus-range = <0x80 0xbf>; + vendor-id = <0x1f1c>; + device-id = <0x2042>; status = "okay"; }; -&pcie_rc2 { +&pcie_rc3 { + reg = <0x70 0x62800000 0x0 0x00800000>, + <0x4c 0x00000000 0x0 0x00001000>; + linux,pci-domain = <2>; + bus-range = <0xc0 0xff>; + vendor-id = <0x1f1c>; + device-id = <0x2042>; status = "okay"; }; diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi index 761cba7babba7e..80958dabfce34a 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi @@ -247,10 +247,7 @@ pcie_rc0: pcie@7060000000 { compatible = "sophgo,sg2042-pcie-host"; device_type = "pci"; - reg = <0x70 0x60000000 0x0 0x02000000>, - <0x40 0x00000000 0x0 0x00001000>; reg-names = "reg", "cfg"; - linux,pci-domain = <0>; #address-cells = <3>; #size-cells = <2>; ranges = <0x01000000 0x0 0xc0000000 0x40 0xc0000000 0x0 0x00400000>, @@ -258,9 +255,6 @@ <0x02000000 0x0 0xe0000000 0x40 0xe0000000 0x0 0x20000000>, <0x43000000 0x42 0x00000000 0x42 0x00000000 0x2 0x00000000>, <0x03000000 0x41 0x00000000 0x41 0x00000000 0x1 0x00000000>; - bus-range = <0x0 0xff>; - vendor-id = <0x1f1c>; - device-id = <0x2042>; cdns,no-bar-match-nbits = <48>; sophgo,link-id = <0>; sophgo,syscon-pcie-ctrl = <&cdns_pcie0_ctrl>; @@ -273,13 +267,10 @@ reg = <0x70 0x61800000 0x0 0x800000>; }; - pcie_rc1: pcie@7062000000 { + pcie_rc2: pcie@7062000000 { compatible = "sophgo,sg2042-pcie-host"; device_type = "pci"; - reg = <0x70 0x62000000 0x0 0x00800000>, - <0x48 0x00000000 0x0 0x00001000>; reg-names = "reg", "cfg"; - linux,pci-domain = <1>; #address-cells = <3>; #size-cells = <2>; ranges = <0x01000000 0x0 0xc0800000 0x48 0xc0800000 0x0 0x00400000>, @@ -287,9 +278,6 @@ <0x02000000 0x0 0xe0000000 0x48 0xe0000000 0x0 0x20000000>, <0x03000000 0x49 0x00000000 0x49 0x00000000 0x1 0x00000000>, <0x43000000 0x4a 0x00000000 0x4a 0x00000000 0x2 0x00000000>; - bus-range = <0x0 0xff>; - vendor-id = <0x1f1c>; - device-id = <0x2042>; cdns,no-bar-match-nbits = <48>; sophgo,link-id = <0>; sophgo,syscon-pcie-ctrl = <&cdns_pcie1_ctrl>; @@ -297,13 +285,10 @@ status = "disabled"; }; - pcie_rc2: pcie@7062800000 { + pcie_rc3: pcie@7062800000 { compatible = "sophgo,sg2042-pcie-host"; device_type = "pci"; - reg = <0x70 0x62800000 0x0 0x00800000>, - <0x4c 0x00000000 0x0 0x00001000>; reg-names = "reg", "cfg"; - linux,pci-domain = <2>; #address-cells = <3>; #size-cells = <2>; ranges = <0x01000000 0x0 0xc0c00000 0x4c 0xc0c00000 0x0 0x00400000>, @@ -311,9 +296,6 @@ <0x02000000 0x0 0xfc000000 0x4c 0xfc000000 0x0 0x04000000>, <0x43000000 0x4e 0x00000000 0x4e 0x00000000 0x2 0x00000000>, <0x03000000 0x4d 0x00000000 0x4d 0x00000000 0x1 0x00000000>; - bus-range = <0x0 0xff>; - vendor-id = <0x1f1c>; - device-id = <0x2042>; cdns,no-bar-match-nbits = <48>; sophgo,link-id = <1>; sophgo,syscon-pcie-ctrl = <&cdns_pcie1_ctrl>; From 6c4c38f4244138565da016e3d8335a8c596c0c3a Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Wed, 4 Jun 2025 21:22:59 +0800 Subject: [PATCH 28/34] REVYOS: dts: sophgo: sg2042: add pcie port for sg2042 EVB V1.X/V2.0 Signed-off-by: Inochi Amaoto Signed-off-by: Han Gao --- arch/riscv/boot/dts/sophgo/sg2042.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi index 80958dabfce34a..3134fa59a02072 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi @@ -262,6 +262,24 @@ status = "disabled"; }; + pcie_rc1: pcie@7060800000 { + compatible = "sophgo,sg2042-pcie-host"; + device_type = "pci"; + reg-names = "reg", "cfg"; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0xc0400000 0x44 0xc0400000 0x0 0x00400000>, + <0x42000000 0x0 0xd0000000 0x44 0xd0000000 0x0 0x10000000>, + <0x02000000 0x0 0xe0000000 0x44 0xe0000000 0x0 0x20000000>, + <0x43000000 0x46 0x00000000 0x46 0x00000000 0x2 0x00000000>, + <0x03000000 0x45 0x00000000 0x45 0x00000000 0x1 0x00000000>; + cdns,no-bar-match-nbits = <48>; + sophgo,link-id = <1>; + sophgo,syscon-pcie-ctrl = <&cdns_pcie0_ctrl>; + msi-parent = <&msi>; + status = "disabled"; + }; + cdns_pcie0_ctrl: syscon@7061800000 { compatible = "sophgo,sg2042-pcie-ctrl", "syscon"; reg = <0x70 0x61800000 0x0 0x800000>; From 3eb11eb58788bb597412482e7a47bac202fd4bc2 Mon Sep 17 00:00:00 2001 From: Han Gao Date: Wed, 4 Jun 2025 21:23:09 +0800 Subject: [PATCH 29/34] REVYOS: riscv: dts: sophgo: enable pcie_rc for Sophgo SG2042_EVB_V1.X Signed-off-by: Han Gao --- arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts | 30 ++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts b/arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts index 4f39a2575b8eec..775d1443a49521 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts +++ b/arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts @@ -80,6 +80,36 @@ }; }; +&pcie_rc0 { + reg = <0x70 0x60000000 0x0 0x00800000>, + <0x40 0x00000000 0x0 0x00001000>; + linux,pci-domain = <0>; + bus-range = <0x00 0x3f>; + vendor-id = <0x1f1c>; + device-id = <0x2042>; + status = "okay"; +}; + +&pcie_rc1 { + reg = <0x70 0x60800000 0x0 0x00800000>, + <0x44 0x00000000 0x0 0x00001000>; + linux,pci-domain = <1>; + bus-range = <0x40 0x7f>; + vendor-id = <0x1f1c>; + device-id = <0x2042>; + status = "okay"; +}; + +&pcie_rc2 { + reg = <0x70 0x62000000 0x0 0x02000000>, + <0x48 0x00000000 0x0 0x00001000>; + linux,pci-domain = <2>; + bus-range = <0x80 0xff>; + vendor-id = <0x1f1c>; + device-id = <0x2042>; + status = "okay"; +}; + &pinctrl { emmc_cfg: sdhci-emmc-cfg { sdhci-emmc-wp-pins { From 805efed49a4d2c62548a1842117f06103b518f5f Mon Sep 17 00:00:00 2001 From: Han Gao Date: Wed, 4 Jun 2025 21:23:18 +0800 Subject: [PATCH 30/34] REVYOS: riscv: dts: sophgo: enable pcie_rc for Sophgo SG2042_EVB_V2.0 Signed-off-by: Han Gao --- arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts | 30 ++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts b/arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts index 8eba1a4ab1eeff..8b834abd9e95ed 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts +++ b/arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts @@ -68,6 +68,36 @@ }; }; +&pcie_rc0 { + reg = <0x70 0x60000000 0x0 0x00800000>, + <0x40 0x00000000 0x0 0x00001000>; + linux,pci-domain = <0>; + bus-range = <0x00 0x3f>; + vendor-id = <0x1f1c>; + device-id = <0x2042>; + status = "okay"; +}; + +&pcie_rc1 { + reg = <0x70 0x60800000 0x0 0x00800000>, + <0x44 0x00000000 0x0 0x00001000>; + linux,pci-domain = <1>; + bus-range = <0x40 0x7f>; + vendor-id = <0x1f1c>; + device-id = <0x2042>; + status = "okay"; +}; + +&pcie_rc2 { + reg = <0x70 0x62000000 0x0 0x02000000>, + <0x48 0x00000000 0x0 0x00001000>; + linux,pci-domain = <2>; + bus-range = <0x80 0xff>; + vendor-id = <0x1f1c>; + device-id = <0x2042>; + status = "okay"; +}; + &pinctrl { emmc_cfg: sdhci-emmc-cfg { sdhci-emmc-wp-pins { From af08386ba9c32e30f56e29f116b6af6385680730 Mon Sep 17 00:00:00 2001 From: Han Gao Date: Wed, 4 Jun 2025 21:23:27 +0800 Subject: [PATCH 31/34] REVYOS: riscv: dts: sophgo: Enable SPI NOR node for SG2042_EVB_V1/V2 Signed-off-by: Han Gao --- arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts | 18 ++++++++++++++++++ arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts | 9 +++++++++ 2 files changed, 27 insertions(+) diff --git a/arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts b/arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts index 775d1443a49521..35c662beb5f004 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts +++ b/arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts @@ -184,6 +184,24 @@ status = "okay"; }; +&spifmc0 { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + }; +}; + +&spifmc1 { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + }; +}; + &uart0 { pinctrl-0 = <&uart0_cfg>; pinctrl-names = "default"; diff --git a/arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts b/arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts index 8b834abd9e95ed..c1c7f619099df3 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts +++ b/arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts @@ -172,6 +172,15 @@ status = "okay"; }; +&spifmc1 { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + }; +}; + &uart0 { pinctrl-0 = <&uart0_cfg>; pinctrl-names = "default"; From 43234a6814364208407baad01cd3c396eba11318 Mon Sep 17 00:00:00 2001 From: Han Gao Date: Wed, 4 Jun 2025 21:33:42 +0800 Subject: [PATCH 32/34] RISCV64: REVYOS: dts: sophgo: sg2042: sync old kernel numa-id Signed-off-by: Han Gao --- arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 64 +++++++++++++++++++++ arch/riscv/boot/dts/sophgo/sg2042.dtsi | 20 +++++++ 2 files changed, 84 insertions(+) diff --git a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi index 8dd1a3c60bc436..b5d6da7f284392 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi @@ -272,6 +272,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache0>; mmu-type = "riscv,sv39"; + numa-node-id = <0>; cpu0_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -299,6 +300,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache0>; mmu-type = "riscv,sv39"; + numa-node-id = <0>; cpu1_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -326,6 +328,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache0>; mmu-type = "riscv,sv39"; + numa-node-id = <0>; cpu2_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -353,6 +356,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache0>; mmu-type = "riscv,sv39"; + numa-node-id = <0>; cpu3_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -380,6 +384,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache1>; mmu-type = "riscv,sv39"; + numa-node-id = <0>; cpu4_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -407,6 +412,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache1>; mmu-type = "riscv,sv39"; + numa-node-id = <0>; cpu5_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -434,6 +440,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache1>; mmu-type = "riscv,sv39"; + numa-node-id = <0>; cpu6_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -461,6 +468,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache1>; mmu-type = "riscv,sv39"; + numa-node-id = <0>; cpu7_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -488,6 +496,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache4>; mmu-type = "riscv,sv39"; + numa-node-id = <1>; cpu8_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -515,6 +524,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache4>; mmu-type = "riscv,sv39"; + numa-node-id = <1>; cpu9_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -542,6 +552,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache4>; mmu-type = "riscv,sv39"; + numa-node-id = <1>; cpu10_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -569,6 +580,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache4>; mmu-type = "riscv,sv39"; + numa-node-id = <1>; cpu11_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -596,6 +608,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache5>; mmu-type = "riscv,sv39"; + numa-node-id = <1>; cpu12_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -623,6 +636,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache5>; mmu-type = "riscv,sv39"; + numa-node-id = <1>; cpu13_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -650,6 +664,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache5>; mmu-type = "riscv,sv39"; + numa-node-id = <1>; cpu14_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -677,6 +692,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache5>; mmu-type = "riscv,sv39"; + numa-node-id = <1>; cpu15_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -704,6 +720,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache2>; mmu-type = "riscv,sv39"; + numa-node-id = <0>; cpu16_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -731,6 +748,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache2>; mmu-type = "riscv,sv39"; + numa-node-id = <0>; cpu17_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -758,6 +776,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache2>; mmu-type = "riscv,sv39"; + numa-node-id = <0>; cpu18_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -785,6 +804,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache2>; mmu-type = "riscv,sv39"; + numa-node-id = <0>; cpu19_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -812,6 +832,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache3>; mmu-type = "riscv,sv39"; + numa-node-id = <0>; cpu20_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -839,6 +860,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache3>; mmu-type = "riscv,sv39"; + numa-node-id = <0>; cpu21_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -866,6 +888,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache3>; mmu-type = "riscv,sv39"; + numa-node-id = <0>; cpu22_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -893,6 +916,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache3>; mmu-type = "riscv,sv39"; + numa-node-id = <0>; cpu23_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -920,6 +944,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache6>; mmu-type = "riscv,sv39"; + numa-node-id = <1>; cpu24_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -947,6 +972,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache6>; mmu-type = "riscv,sv39"; + numa-node-id = <1>; cpu25_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -974,6 +1000,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache6>; mmu-type = "riscv,sv39"; + numa-node-id = <1>; cpu26_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1001,6 +1028,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache6>; mmu-type = "riscv,sv39"; + numa-node-id = <1>; cpu27_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1028,6 +1056,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache7>; mmu-type = "riscv,sv39"; + numa-node-id = <1>; cpu28_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1055,6 +1084,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache7>; mmu-type = "riscv,sv39"; + numa-node-id = <1>; cpu29_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1082,6 +1112,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache7>; mmu-type = "riscv,sv39"; + numa-node-id = <1>; cpu30_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1109,6 +1140,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache7>; mmu-type = "riscv,sv39"; + numa-node-id = <1>; cpu31_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1136,6 +1168,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache8>; mmu-type = "riscv,sv39"; + numa-node-id = <2>; cpu32_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1163,6 +1196,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache8>; mmu-type = "riscv,sv39"; + numa-node-id = <2>; cpu33_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1190,6 +1224,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache8>; mmu-type = "riscv,sv39"; + numa-node-id = <2>; cpu34_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1217,6 +1252,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache8>; mmu-type = "riscv,sv39"; + numa-node-id = <2>; cpu35_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1244,6 +1280,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache9>; mmu-type = "riscv,sv39"; + numa-node-id = <2>; cpu36_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1271,6 +1308,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache9>; mmu-type = "riscv,sv39"; + numa-node-id = <2>; cpu37_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1298,6 +1336,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache9>; mmu-type = "riscv,sv39"; + numa-node-id = <2>; cpu38_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1325,6 +1364,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache9>; mmu-type = "riscv,sv39"; + numa-node-id = <2>; cpu39_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1352,6 +1392,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache12>; mmu-type = "riscv,sv39"; + numa-node-id = <3>; cpu40_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1379,6 +1420,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache12>; mmu-type = "riscv,sv39"; + numa-node-id = <3>; cpu41_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1406,6 +1448,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache12>; mmu-type = "riscv,sv39"; + numa-node-id = <3>; cpu42_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1433,6 +1476,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache12>; mmu-type = "riscv,sv39"; + numa-node-id = <3>; cpu43_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1460,6 +1504,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache13>; mmu-type = "riscv,sv39"; + numa-node-id = <3>; cpu44_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1487,6 +1532,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache13>; mmu-type = "riscv,sv39"; + numa-node-id = <3>; cpu45_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1514,6 +1560,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache13>; mmu-type = "riscv,sv39"; + numa-node-id = <3>; cpu46_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1541,6 +1588,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache13>; mmu-type = "riscv,sv39"; + numa-node-id = <3>; cpu47_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1568,6 +1616,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache10>; mmu-type = "riscv,sv39"; + numa-node-id = <2>; cpu48_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1595,6 +1644,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache10>; mmu-type = "riscv,sv39"; + numa-node-id = <2>; cpu49_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1622,6 +1672,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache10>; mmu-type = "riscv,sv39"; + numa-node-id = <2>; cpu50_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1649,6 +1700,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache10>; mmu-type = "riscv,sv39"; + numa-node-id = <2>; cpu51_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1676,6 +1728,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache11>; mmu-type = "riscv,sv39"; + numa-node-id = <2>; cpu52_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1703,6 +1756,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache11>; mmu-type = "riscv,sv39"; + numa-node-id = <2>; cpu53_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1730,6 +1784,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache11>; mmu-type = "riscv,sv39"; + numa-node-id = <2>; cpu54_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1757,6 +1812,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache11>; mmu-type = "riscv,sv39"; + numa-node-id = <2>; cpu55_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1784,6 +1840,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache14>; mmu-type = "riscv,sv39"; + numa-node-id = <3>; cpu56_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1811,6 +1868,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache14>; mmu-type = "riscv,sv39"; + numa-node-id = <3>; cpu57_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1838,6 +1896,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache14>; mmu-type = "riscv,sv39"; + numa-node-id = <3>; cpu58_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1865,6 +1924,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache14>; mmu-type = "riscv,sv39"; + numa-node-id = <3>; cpu59_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1892,6 +1952,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache15>; mmu-type = "riscv,sv39"; + numa-node-id = <3>; cpu60_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1919,6 +1980,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache15>; mmu-type = "riscv,sv39"; + numa-node-id = <3>; cpu61_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1946,6 +2008,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache15>; mmu-type = "riscv,sv39"; + numa-node-id = <3>; cpu62_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1973,6 +2036,7 @@ d-cache-sets = <512>; next-level-cache = <&l2_cache15>; mmu-type = "riscv,sv39"; + numa-node-id = <3>; cpu63_intc: interrupt-controller { compatible = "riscv,cpu-intc"; diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi index 3134fa59a02072..40f0f02f708053 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi @@ -19,6 +19,26 @@ #size-cells = <2>; dma-noncoherent; + distance-map { + compatible = "numa-distance-map-v1"; + distance-matrix = <0 0 10>, + <0 1 15>, + <0 2 25>, + <0 3 30>, + <1 0 15>, + <1 1 10>, + <1 2 30>, + <1 3 25>, + <2 0 25>, + <2 1 30>, + <2 2 10>, + <2 3 15>, + <3 0 30>, + <3 1 25>, + <3 2 15>, + <3 3 10>; + }; + aliases { serial0 = &uart0; }; From a6f977706fb649b477ab0211ea4a7facbc8e642d Mon Sep 17 00:00:00 2001 From: Han Gao Date: Wed, 4 Jun 2025 21:33:52 +0800 Subject: [PATCH 33/34] RISCV64: REVYOS: Revert "riscv: Enable pcpu page first chunk allocator" This reverts commit 6b9f29b81b155af023da95f560f738f29722b306. --- arch/riscv/Kconfig | 2 -- arch/riscv/mm/kasan_init.c | 8 -------- 2 files changed, 10 deletions(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index b4b3a1385edfcb..abaac5cc5b994d 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -491,9 +491,7 @@ config NUMA depends on SMP && MMU select ARCH_SUPPORTS_NUMA_BALANCING select GENERIC_ARCH_NUMA - select HAVE_SETUP_PER_CPU_AREA select NEED_PER_CPU_EMBED_FIRST_CHUNK - select NEED_PER_CPU_PAGE_FIRST_CHUNK select OF_NUMA select USE_PERCPU_NUMA_NODE_ID help diff --git a/arch/riscv/mm/kasan_init.c b/arch/riscv/mm/kasan_init.c index 41c635d6aca4e9..b4988c36362a76 100644 --- a/arch/riscv/mm/kasan_init.c +++ b/arch/riscv/mm/kasan_init.c @@ -441,14 +441,6 @@ static void __init kasan_shallow_populate(void *start, void *end) kasan_shallow_populate_pgd(vaddr, vend); } -#ifdef CONFIG_KASAN_VMALLOC -void __init kasan_populate_early_vm_area_shadow(void *start, unsigned long size) -{ - kasan_populate(kasan_mem_to_shadow(start), - kasan_mem_to_shadow(start + size)); -} -#endif - static void __init create_tmp_mapping(void) { void *ptr; From a20a0b785225a3b7436a1fac0a5fa90479bdfbcd Mon Sep 17 00:00:00 2001 From: Han Gao Date: Wed, 4 Jun 2025 21:34:08 +0800 Subject: [PATCH 34/34] RISCV64: REVYOS: Revert "NUMA: early use of cpu_to_node() returns 0 instead of the correct node id" This reverts commit f9899c028151468d8c4af0bcbb3d5e87619b0973. --- init/main.c | 14 -------------- 1 file changed, 14 deletions(-) diff --git a/init/main.c b/init/main.c index 7f0a2a3dbd290a..82f508534df8cc 100644 --- a/init/main.c +++ b/init/main.c @@ -879,19 +879,6 @@ static void __init print_unknown_bootoptions(void) memblock_free(unknown_options, len); } -static void __init early_numa_node_init(void) -{ -#ifdef CONFIG_USE_PERCPU_NUMA_NODE_ID -#ifndef cpu_to_node - int cpu; - - /* The early_cpu_to_node() should be ready here. */ - for_each_possible_cpu(cpu) - set_cpu_numa_node(cpu, early_cpu_to_node(cpu)); -#endif -#endif -} - asmlinkage __visible __init __no_sanitize_address __noreturn __no_stack_protector void start_kernel(void) { @@ -925,7 +912,6 @@ void start_kernel(void) setup_nr_cpu_ids(); setup_per_cpu_areas(); smp_prepare_boot_cpu(); /* arch-specific boot-cpu hooks */ - early_numa_node_init(); boot_cpu_hotplug_init(); pr_notice("Kernel command line: %s\n", saved_command_line);