diff --git a/.gitignore b/.gitignore index 1bc5ac4ba..160e2acc3 100644 --- a/.gitignore +++ b/.gitignore @@ -14,5 +14,5 @@ *.pyc obj/ lib/ - +.DS_Store examples/HiFive1/zfp-hifive1/ diff --git a/arch/ARM/SAM/devices/sam-device.adb b/arch/ARM/SAM/devices/sam-device.adb new file mode 100644 index 000000000..ba6183c07 --- /dev/null +++ b/arch/ARM/SAM/devices/sam-device.adb @@ -0,0 +1,7 @@ +with SAM; use SAM; + +package body SAM.Device is + + + +end SAM.Device; diff --git a/arch/ARM/SAM/devices/sam-device.ads b/arch/ARM/SAM/devices/sam-device.ads new file mode 100644 index 000000000..f2bf04400 --- /dev/null +++ b/arch/ARM/SAM/devices/sam-device.ads @@ -0,0 +1,197 @@ +with SAM_SVD; use SAM_SVD; + +with SAM.GPIO; use SAM.GPIO; +with SAM.SPI; use SAM.SPI; + +package SAM.Device is + pragma Elaborate_Body; + + Unknown_Device : exception; + -- Raised by the routines below for a device passed as an actual parameter + -- when that device is not present on the given hardware instance. + + GPIO_A : aliased GPIO_Port with Import, Volatile, Address => PIOA_Base; + GPIO_B : aliased GPIO_Port with Import, Volatile, Address => PIOB_Base; + GPIO_C : aliased GPIO_Port with Import, Volatile, Address => PIOC_Base; + GPIO_D : aliased GPIO_Port with Import, Volatile, Address => PIOD_Base; + GPIO_E : aliased GPIO_Port with Import, Volatile, Address => PIOE_Base; + + PA0 : aliased GPIO_Point := (GPIO_A'Access, 0); + PA1 : aliased GPIO_Point := (GPIO_A'Access, 1); + PA2 : aliased GPIO_Point := (GPIO_A'Access, 2); + PA3 : aliased GPIO_Point := (GPIO_A'Access, 3); + PA4 : aliased GPIO_Point := (GPIO_A'Access, 4); + PA5 : aliased GPIO_Point := (GPIO_A'Access, 5); + PA6 : aliased GPIO_Point := (GPIO_A'Access, 6); + PA7 : aliased GPIO_Point := (GPIO_A'Access, 7); + PA8 : aliased GPIO_Point := (GPIO_A'Access, 8); + PA9 : aliased GPIO_Point := (GPIO_A'Access, 9); + PA10 : aliased GPIO_Point := (GPIO_A'Access, 10); + PA11 : aliased GPIO_Point := (GPIO_A'Access, 11); + PA12 : aliased GPIO_Point := (GPIO_A'Access, 12); + PA13 : aliased GPIO_Point := (GPIO_A'Access, 13); + PA14 : aliased GPIO_Point := (GPIO_A'Access, 14); + PA15 : aliased GPIO_Point := (GPIO_A'Access, 15); + PA16 : aliased GPIO_Point := (GPIO_A'Access, 16); + PA17 : aliased GPIO_Point := (GPIO_A'Access, 17); + PA18 : aliased GPIO_Point := (GPIO_A'Access, 18); + PA19 : aliased GPIO_Point := (GPIO_A'Access, 19); + PA20 : aliased GPIO_Point := (GPIO_A'Access, 20); + PA21 : aliased GPIO_Point := (GPIO_A'Access, 21); + PA22 : aliased GPIO_Point := (GPIO_A'Access, 22); + PA23 : aliased GPIO_Point := (GPIO_A'Access, 23); + PA24 : aliased GPIO_Point := (GPIO_A'Access, 24); + PA25 : aliased GPIO_Point := (GPIO_A'Access, 25); + PA26 : aliased GPIO_Point := (GPIO_A'Access, 26); + PA27 : aliased GPIO_Point := (GPIO_A'Access, 27); + PA28 : aliased GPIO_Point := (GPIO_A'Access, 28); + PA29 : aliased GPIO_Point := (GPIO_A'Access, 29); + PA30 : aliased GPIO_Point := (GPIO_A'Access, 30); + PA31 : aliased GPIO_Point := (GPIO_A'Access, 31); + + PB0 : aliased GPIO_Point := (GPIO_B'Access, 0); + PB1 : aliased GPIO_Point := (GPIO_B'Access, 1); + PB2 : aliased GPIO_Point := (GPIO_B'Access, 2); + PB3 : aliased GPIO_Point := (GPIO_B'Access, 3); + PB4 : aliased GPIO_Point := (GPIO_B'Access, 4); + PB5 : aliased GPIO_Point := (GPIO_B'Access, 5); + PB6 : aliased GPIO_Point := (GPIO_B'Access, 6); + PB7 : aliased GPIO_Point := (GPIO_B'Access, 7); + PB8 : aliased GPIO_Point := (GPIO_B'Access, 8); + PB9 : aliased GPIO_Point := (GPIO_B'Access, 9); + PB10 : aliased GPIO_Point := (GPIO_B'Access, 10); + PB11 : aliased GPIO_Point := (GPIO_B'Access, 11); + PB12 : aliased GPIO_Point := (GPIO_B'Access, 12); + PB13 : aliased GPIO_Point := (GPIO_B'Access, 13); + PB14 : aliased GPIO_Point := (GPIO_B'Access, 14); + PB15 : aliased GPIO_Point := (GPIO_B'Access, 15); + PB16 : aliased GPIO_Point := (GPIO_B'Access, 16); + PB17 : aliased GPIO_Point := (GPIO_B'Access, 17); + PB18 : aliased GPIO_Point := (GPIO_B'Access, 18); + PB19 : aliased GPIO_Point := (GPIO_B'Access, 19); + PB20 : aliased GPIO_Point := (GPIO_B'Access, 20); + PB21 : aliased GPIO_Point := (GPIO_B'Access, 21); + PB22 : aliased GPIO_Point := (GPIO_B'Access, 22); + PB23 : aliased GPIO_Point := (GPIO_B'Access, 23); + PB24 : aliased GPIO_Point := (GPIO_B'Access, 24); + PB25 : aliased GPIO_Point := (GPIO_B'Access, 25); + PB26 : aliased GPIO_Point := (GPIO_B'Access, 26); + PB27 : aliased GPIO_Point := (GPIO_B'Access, 27); + PB28 : aliased GPIO_Point := (GPIO_B'Access, 28); + PB29 : aliased GPIO_Point := (GPIO_B'Access, 29); + PB30 : aliased GPIO_Point := (GPIO_B'Access, 30); + PB31 : aliased GPIO_Point := (GPIO_B'Access, 31); + + PC0 : aliased GPIO_Point := (GPIO_C'Access, 0); + PC1 : aliased GPIO_Point := (GPIO_C'Access, 1); + PC2 : aliased GPIO_Point := (GPIO_C'Access, 2); + PC3 : aliased GPIO_Point := (GPIO_C'Access, 3); + PC4 : aliased GPIO_Point := (GPIO_C'Access, 4); + PC5 : aliased GPIO_Point := (GPIO_C'Access, 5); + PC6 : aliased GPIO_Point := (GPIO_C'Access, 6); + PC7 : aliased GPIO_Point := (GPIO_C'Access, 7); + PC8 : aliased GPIO_Point := (GPIO_C'Access, 8); + PC9 : aliased GPIO_Point := (GPIO_C'Access, 9); + PC10 : aliased GPIO_Point := (GPIO_C'Access, 10); + PC11 : aliased GPIO_Point := (GPIO_C'Access, 11); + PC12 : aliased GPIO_Point := (GPIO_C'Access, 12); + PC13 : aliased GPIO_Point := (GPIO_C'Access, 13); + PC14 : aliased GPIO_Point := (GPIO_C'Access, 14); + PC15 : aliased GPIO_Point := (GPIO_C'Access, 15); + PC16 : aliased GPIO_Point := (GPIO_C'Access, 16); + PC17 : aliased GPIO_Point := (GPIO_C'Access, 17); + PC18 : aliased GPIO_Point := (GPIO_C'Access, 18); + PC19 : aliased GPIO_Point := (GPIO_C'Access, 19); + PC20 : aliased GPIO_Point := (GPIO_C'Access, 20); + PC21 : aliased GPIO_Point := (GPIO_C'Access, 21); + PC22 : aliased GPIO_Point := (GPIO_C'Access, 22); + PC23 : aliased GPIO_Point := (GPIO_C'Access, 23); + PC24 : aliased GPIO_Point := (GPIO_C'Access, 24); + PC25 : aliased GPIO_Point := (GPIO_C'Access, 25); + PC26 : aliased GPIO_Point := (GPIO_C'Access, 26); + PC27 : aliased GPIO_Point := (GPIO_C'Access, 27); + PC28 : aliased GPIO_Point := (GPIO_C'Access, 28); + PC29 : aliased GPIO_Point := (GPIO_C'Access, 29); + PC30 : aliased GPIO_Point := (GPIO_C'Access, 30); + PC31 : aliased GPIO_Point := (GPIO_C'Access, 31); + + PD0 : aliased GPIO_Point := (GPIO_D'Access, 0); + PD1 : aliased GPIO_Point := (GPIO_D'Access, 1); + PD2 : aliased GPIO_Point := (GPIO_D'Access, 2); + PD3 : aliased GPIO_Point := (GPIO_D'Access, 3); + PD4 : aliased GPIO_Point := (GPIO_D'Access, 4); + PD5 : aliased GPIO_Point := (GPIO_D'Access, 5); + PD6 : aliased GPIO_Point := (GPIO_D'Access, 6); + PD7 : aliased GPIO_Point := (GPIO_D'Access, 7); + PD8 : aliased GPIO_Point := (GPIO_D'Access, 8); + PD9 : aliased GPIO_Point := (GPIO_D'Access, 9); + PD10 : aliased GPIO_Point := (GPIO_D'Access, 10); + PD11 : aliased GPIO_Point := (GPIO_D'Access, 11); + PD12 : aliased GPIO_Point := (GPIO_D'Access, 12); + PD13 : aliased GPIO_Point := (GPIO_D'Access, 13); + PD14 : aliased GPIO_Point := (GPIO_D'Access, 14); + PD15 : aliased GPIO_Point := (GPIO_D'Access, 15); + PD16 : aliased GPIO_Point := (GPIO_D'Access, 16); + PD17 : aliased GPIO_Point := (GPIO_D'Access, 17); + PD18 : aliased GPIO_Point := (GPIO_D'Access, 18); + PD19 : aliased GPIO_Point := (GPIO_D'Access, 19); + PD20 : aliased GPIO_Point := (GPIO_D'Access, 20); + PD21 : aliased GPIO_Point := (GPIO_D'Access, 21); + PD22 : aliased GPIO_Point := (GPIO_D'Access, 22); + PD23 : aliased GPIO_Point := (GPIO_D'Access, 23); + PD24 : aliased GPIO_Point := (GPIO_D'Access, 24); + PD25 : aliased GPIO_Point := (GPIO_D'Access, 25); + PD26 : aliased GPIO_Point := (GPIO_D'Access, 26); + PD27 : aliased GPIO_Point := (GPIO_D'Access, 27); + PD28 : aliased GPIO_Point := (GPIO_D'Access, 28); + PD29 : aliased GPIO_Point := (GPIO_D'Access, 29); + PD30 : aliased GPIO_Point := (GPIO_D'Access, 30); + PD31 : aliased GPIO_Point := (GPIO_D'Access, 31); + + PE0 : aliased GPIO_Point := (GPIO_E'Access, 0); + PE1 : aliased GPIO_Point := (GPIO_E'Access, 1); + PE2 : aliased GPIO_Point := (GPIO_E'Access, 2); + PE3 : aliased GPIO_Point := (GPIO_E'Access, 3); + PE4 : aliased GPIO_Point := (GPIO_E'Access, 4); + PE5 : aliased GPIO_Point := (GPIO_E'Access, 5); + PE6 : aliased GPIO_Point := (GPIO_E'Access, 6); + PE7 : aliased GPIO_Point := (GPIO_E'Access, 7); + PE8 : aliased GPIO_Point := (GPIO_E'Access, 8); + PE9 : aliased GPIO_Point := (GPIO_E'Access, 9); + PE10 : aliased GPIO_Point := (GPIO_E'Access, 10); + PE11 : aliased GPIO_Point := (GPIO_E'Access, 11); + PE12 : aliased GPIO_Point := (GPIO_E'Access, 12); + PE13 : aliased GPIO_Point := (GPIO_E'Access, 13); + PE14 : aliased GPIO_Point := (GPIO_E'Access, 14); + PE15 : aliased GPIO_Point := (GPIO_E'Access, 15); + PE16 : aliased GPIO_Point := (GPIO_E'Access, 16); + PE17 : aliased GPIO_Point := (GPIO_E'Access, 17); + PE18 : aliased GPIO_Point := (GPIO_E'Access, 18); + PE19 : aliased GPIO_Point := (GPIO_E'Access, 19); + PE20 : aliased GPIO_Point := (GPIO_E'Access, 20); + PE21 : aliased GPIO_Point := (GPIO_E'Access, 21); + PE22 : aliased GPIO_Point := (GPIO_E'Access, 22); + PE23 : aliased GPIO_Point := (GPIO_E'Access, 23); + PE24 : aliased GPIO_Point := (GPIO_E'Access, 24); + PE25 : aliased GPIO_Point := (GPIO_E'Access, 25); + PE26 : aliased GPIO_Point := (GPIO_E'Access, 26); + PE27 : aliased GPIO_Point := (GPIO_E'Access, 27); + PE28 : aliased GPIO_Point := (GPIO_E'Access, 28); + PE29 : aliased GPIO_Point := (GPIO_E'Access, 29); + PE30 : aliased GPIO_Point := (GPIO_E'Access, 30); + PE31 : aliased GPIO_Point := (GPIO_E'Access, 31); + + Internal_SPI_0 : aliased Internal_SPI_Port with Import, Volatile, Address => SPI0_Base; + Internal_SPI_1 : aliased Internal_SPI_Port with Import, Volatile, Address => SPI1_Base; + + SPI_0_Cs0 : aliased SPI_Port (Internal_SPI_0'Access, 0); + SPI_0_Cs1 : aliased SPI_Port (Internal_SPI_0'Access, 1); + SPI_0_Cs2 : aliased SPI_Port (Internal_SPI_0'Access, 2); + SPI_0_Cs3 : aliased SPI_Port (Internal_SPI_0'Access, 3); + + SPI_1_Cs0 : aliased SPI_Port (Internal_SPI_1'Access, 0); + SPI_1_Cs1 : aliased SPI_Port (Internal_SPI_1'Access, 1); + SPI_1_Cs2 : aliased SPI_Port (Internal_SPI_1'Access, 2); + SPI_1_Cs3 : aliased SPI_Port (Internal_SPI_1'Access, 3); + +end SAM.Device; diff --git a/arch/ARM/SAM/driver_demos/atmel_samv71_xplained_ultra.cfg b/arch/ARM/SAM/driver_demos/atmel_samv71_xplained_ultra.cfg new file mode 100644 index 000000000..ab9c2a354 --- /dev/null +++ b/arch/ARM/SAM/driver_demos/atmel_samv71_xplained_ultra.cfg @@ -0,0 +1,13 @@ +# +# Atmel SAMV71 Xplained Ultra evaluation kit. +# http://www.atmel.com/tools/ATSAMV71-XULT.aspx +# +# To connect using the EDBG chip on the dev kit over USB, you will +# first need to source [find interface/cmsis-dap.cfg] +# however, since this board also has a SWD+ETM connector, we don't +# automatically source that file here. + +set CHIPNAME samv71 + +source [find interface/cmsis-dap.cfg] +source [find target/atsamv.cfg] \ No newline at end of file diff --git a/arch/ARM/SAM/driver_demos/demo_gpio_leds/.gdbinit b/arch/ARM/SAM/driver_demos/demo_gpio_leds/.gdbinit new file mode 100644 index 000000000..618b9ce81 --- /dev/null +++ b/arch/ARM/SAM/driver_demos/demo_gpio_leds/.gdbinit @@ -0,0 +1,24 @@ +# This command file will cause a Cortex-M3 or -M4 board to automatically +# reset immediately after a GDB "load" command executes. Note that GPS +# issues that command as part of the Debug->Init menu invocation. Manual +# "load" command invocations will also trigger the action. +# +# The reset is achieved by writing to the "Application Interrupt and Reset +# Control" register located at address 0xE000ED0C. +# +# Both the processor and the peripherals can be reset by writing a value +# of 0x05FA0004. That value will write to the SYSRESETREQ bit. If you want +# to avoid resetting the peripherals, change the value to 0x05FA0001. That +# value will write to the VECTRESET bit. Do *not* use a value that sets both +# bits. +# +# In both cases, any on-board debug hardware is not reset. +# +# See the book "The Definitive Guide to the ARM Cortex-M3 and Cortex-M4 +# Processors" by Joseph Yiu, 3rd edition, pp 262-263 for further details. + +define hookpost-load +echo Resetting the processor and peripherals...\n +set *0xE000ED0C := 0x05FA0004 +echo Reset complete\n +end \ No newline at end of file diff --git a/arch/ARM/SAM/driver_demos/demo_gpio_leds/README.md b/arch/ARM/SAM/driver_demos/demo_gpio_leds/README.md new file mode 100644 index 000000000..30a15deae --- /dev/null +++ b/arch/ARM/SAM/driver_demos/demo_gpio_leds/README.md @@ -0,0 +1,7 @@ +This program demonstrates using the GPIO driver and interrupt +configuration to blink the four LEDs on the STM32F4 Discovery board. + +The LEDs blink in a circular pattern, initially rotating clockwise. When +the blue user button is pressed the rotation direction changes. Button +presses generate interrupts that signal state changes that can then be +queried by application code. diff --git a/arch/ARM/SAM/driver_demos/demo_gpio_leds/demo_gpio.gpr b/arch/ARM/SAM/driver_demos/demo_gpio_leds/demo_gpio.gpr new file mode 100644 index 000000000..447a70c76 --- /dev/null +++ b/arch/ARM/SAM/driver_demos/demo_gpio_leds/demo_gpio.gpr @@ -0,0 +1,54 @@ +with "../../../../../boards/samv71_xplained/samv71_xplained_full.gpr"; + +project Demo_GPIO extends "../../../../../examples/shared/common/common.gpr" is + + for Languages use ("Ada"); + for Main use ("demo_gpio"); + for Source_Dirs use ("src"); + for Object_Dir use "obj/" & SAMV71_XPLAINED_Full.Build; + for Runtime ("Ada") use SAMV71_XPLAINED_Full'Runtime("Ada"); + for Create_Missing_Dirs use "true"; + + package Builder is + for Global_Configuration_Pragmas use "gnat.adc"; + end Builder; + + type App_Builds is ("Debug", "Production"); + App_Build : App_Builds := external ("APP_BUILD", "Production"); + + for Object_Dir use "obj/" & App_Build; + + package Compiler is + case App_Build is + when "Debug" => + for Default_Switches ("ada") use + ("-g", + -- "-gnatwa", + "-gnata", -- enable pre/postconditions + "-gnatQ", + "-gnatw.X", -- disable warnings about exceptions and LCH + "-ffunction-sections", + "-fdata-sections"); + + when "Production" => + for Default_Switches ("ada") use ( + "-g", + "-O2", + "-gnatp", + "-gnatn2", -- honor Inline requests + "-Winline", -- warn if cannot honor Inline aspect/pragma + "-gnatw.X", + "-ffunction-sections", + "-fdata-sections"); + end case; + end Compiler; + + package Ide is + for Connection_Tool use "openocd"; + for Connection_Config_File use "../atmel_samv71_xplained_ultra.cfg"; + for Program_Host use "localhsot:4242"; + for Communication_Protocol use "remote"; + end Ide; + +end Demo_GPIO; + diff --git a/arch/ARM/SAM/driver_demos/demo_gpio_leds/gnat.adc b/arch/ARM/SAM/driver_demos/demo_gpio_leds/gnat.adc new file mode 100644 index 000000000..ba680210b --- /dev/null +++ b/arch/ARM/SAM/driver_demos/demo_gpio_leds/gnat.adc @@ -0,0 +1,2 @@ +pragma Partition_Elaboration_Policy (Sequential); + diff --git a/arch/ARM/SAM/driver_demos/demo_gpio_leds/src/demo_gpio.adb b/arch/ARM/SAM/driver_demos/demo_gpio_leds/src/demo_gpio.adb new file mode 100644 index 000000000..e92a60bc0 --- /dev/null +++ b/arch/ARM/SAM/driver_demos/demo_gpio_leds/src/demo_gpio.adb @@ -0,0 +1,77 @@ +with SAM.Device; use SAM.Device; +with SAM.GPIO; use SAM.GPIO; + +-- with HAL.GPIO; use HAL.GPIO; +with Ada.Numerics.Discrete_Random; +with Ada.Real_Time; use Ada.Real_Time; + +procedure Demo_GPIO is + + LED0 : GPIO_Point renames PA23; + LED1 : GPIO_Point renames PC9; + + procedure Initialize_LEDs is + begin + Enable_Clock (GPIO_A); + Enable_Clock (GPIO_B); + + LED0.Configure_IO + (Config => GPIO_Port_Configuration'(Mode => Mode_Out, + Resistors => <>, + Output_Type => Push_Pull)); + LED1.Configure_IO + (Config => GPIO_Port_Configuration'(Mode => Mode_Out, + Resistors => <>, + Output_Type => Push_Pull)); + end Initialize_LEDs; + + procedure Wait (Period : Time_Span) + is + begin + delay until (Period + Clock); + end Wait; + + procedure Flip_Coin + is + type Coin is (Heads, Tails); + + package Random_Coin is new Ada.Numerics.Discrete_Random (Coin); + use Random_Coin; + G : Generator; + begin + Reset (G); + loop + -- simulate flipping + for I in 1 .. 10 loop + LED0.Set; + LED1.Clear; + Wait (Period => Milliseconds (50)); + LED0.Clear; + LED1.Set; + Wait (Period => Milliseconds (50)); + end loop; + + -- Clear LEDS and delay + LED0.Clear; + LED1.Clear; + Wait (Period => Milliseconds (300)); + + -- check result + case Random (G) is + when Heads => + LED0.Set; + LED1.Clear; + when Tails => + LED0.Clear; + LED1.Set; + end case; + + -- delay and repeat + Wait (Period => Milliseconds (2000)); + end loop; + end Flip_Coin; + +begin + Initialize_LEDs; + Flip_Coin; +end Demo_GPIO; diff --git a/arch/ARM/SAM/driver_demos/demo_i2c/README.md b/arch/ARM/SAM/driver_demos/demo_i2c/README.md new file mode 100644 index 000000000..30a15deae --- /dev/null +++ b/arch/ARM/SAM/driver_demos/demo_i2c/README.md @@ -0,0 +1,7 @@ +This program demonstrates using the GPIO driver and interrupt +configuration to blink the four LEDs on the STM32F4 Discovery board. + +The LEDs blink in a circular pattern, initially rotating clockwise. When +the blue user button is pressed the rotation direction changes. Button +presses generate interrupts that signal state changes that can then be +queried by application code. diff --git a/arch/ARM/SAM/driver_demos/demo_i2c/demo_i2c.gpr b/arch/ARM/SAM/driver_demos/demo_i2c/demo_i2c.gpr new file mode 100644 index 000000000..d258b87be --- /dev/null +++ b/arch/ARM/SAM/driver_demos/demo_i2c/demo_i2c.gpr @@ -0,0 +1,55 @@ +with "../../../../../boards/samv71_xplained/samv71_xplained_full.gpr"; + +project Demo_I2C extends "../../../../../examples/shared/common/common.gpr" is + + for Languages use ("Ada"); + for Main use ("demo_i2c"); + for Source_Dirs use ("src"); + for Object_Dir use "obj/" & SAMV71_XPLAINED_Full.Build; + for Runtime ("Ada") use SAMV71_XPLAINED_Full'Runtime("Ada"); + for Create_Missing_Dirs use "true"; + + package Builder is + for Global_Configuration_Pragmas use "gnat.adc"; + end Builder; + + type App_Builds is ("Debug", "Production"); + App_Build : App_Builds := external ("APP_BUILD", "Production"); + + for Object_Dir use "obj/" & App_Build; + + package Compiler is + case App_Build is + when "Debug" => + for Default_Switches ("ada") use + ("-g", + -- "-gnatwa", + "-gnata", -- enable pre/postconditions + "-gnatQ", + "-gnatw.X", -- disable warnings about exceptions and LCH + "-ffunction-sections", + "-fdata-sections"); + + when "Production" => + for Default_Switches ("ada") use ( + "-g", + "-O2", + "-gnatp", + "-gnatn2", -- honor Inline requests + "-Winline", -- warn if cannot honor Inline aspect/pragma + "-gnatw.X", + "-ffunction-sections", + "-fdata-sections"); + end case; + end Compiler; + + package Ide is + for Gnatlist use "arm-eabi-gnatls"; + for Connection_Tool use "openocd"; + for Connection_Config_File use "../atmel_samv71_xplained_ultra.cfg"; + for Program_Host use "localhost:4242"; + for Communication_Protocol use "remote"; + end Ide; + +end Demo_I2C; + diff --git a/arch/ARM/SAM/driver_demos/demo_i2c/gnat.adc b/arch/ARM/SAM/driver_demos/demo_i2c/gnat.adc new file mode 100644 index 000000000..ba680210b --- /dev/null +++ b/arch/ARM/SAM/driver_demos/demo_i2c/gnat.adc @@ -0,0 +1,2 @@ +pragma Partition_Elaboration_Policy (Sequential); + diff --git a/arch/ARM/SAM/driver_demos/demo_i2c/src/demo_i2c.adb b/arch/ARM/SAM/driver_demos/demo_i2c/src/demo_i2c.adb new file mode 100644 index 000000000..8323fffbc --- /dev/null +++ b/arch/ARM/SAM/driver_demos/demo_i2c/src/demo_i2c.adb @@ -0,0 +1,79 @@ +with SAM.Device; use SAM.Device; + +with HAL; use HAL; +with HAL.GPIO; +with HAL.SPI; use HAL.SPI; + +with SAM.GPIO; use SAM.GPIO; +with SAM.SPI; + +with Ada.Real_Time; use Ada.Real_Time; +with Ada.Text_IO; use Ada.Text_IO; + +procedure Demo_I2C +is + Port : SAM.SPI.SPI_Port renames SPI_0_Cs1; + + MISO : SAM.GPIO.GPIO_Point renames PD20; + MOSI : SAM.GPIO.GPIO_Point renames PD21; + SPCK : SAM.GPIO.GPIO_Point renames PD22; + NPCS1 : SAM.GPIO.GPIO_Point renames PD25; + + Data_Stream : HAL.SPI.SPI_Data_8b (1 .. 8); + Status : HAL.SPI.SPI_Status; + + Counter : UInt8 := 0; + + Cfg : SAM.SPI.Configuration := (Baud => 250_000, + others => <>); + + procedure Wait (Period : Time_Span) + is + begin + delay until (Period + Clock); + end Wait; +begin + Put_Line ("Setting up..."); + Enable_Clock (GPIO_D); + MISO.Configure_IO (Config => (Mode => Mode_AF, + Resistors => <>, + AF_Output_Type => Open_Drain, + AF => Periph_B)); + MOSI.Configure_IO (Config => (Mode => Mode_AF, + Resistors => <>, + AF_Output_Type => Open_Drain, + AF => Periph_B)); + SPCK.Configure_IO (Config => (Mode => Mode_AF, + Resistors => <>, + AF_Output_Type => Open_Drain, + AF => Periph_B)); + NPCS1.Configure_IO (Config => (Mode => Mode_AF, + Resistors => <>, + AF_Output_Type => Open_Drain, + AF => Periph_B)); + + SAM.SPI.Configure (This => Port, + Cfg => Cfg); + Enable_Clock (This => Port); + + loop + Put ("Sending: "); + for I in Data_Stream'Range loop + Data_Stream (I) := Counter; + Put (Counter'Img); + Counter := Counter + 1; + end loop; + + SAM.SPI.Transmit (This => Port, + Data => Data_Stream, + Status => Status); + New_Line; + + if Status /= HAL.SPI.Ok then + Put_Line ("There was an error transmitting."); + return; + end if; + + Wait (Period => Milliseconds (1000)); + end loop; +end Demo_I2C; diff --git a/arch/ARM/SAM/driver_demos/demo_spi/.gdbinit b/arch/ARM/SAM/driver_demos/demo_spi/.gdbinit new file mode 100644 index 000000000..618b9ce81 --- /dev/null +++ b/arch/ARM/SAM/driver_demos/demo_spi/.gdbinit @@ -0,0 +1,24 @@ +# This command file will cause a Cortex-M3 or -M4 board to automatically +# reset immediately after a GDB "load" command executes. Note that GPS +# issues that command as part of the Debug->Init menu invocation. Manual +# "load" command invocations will also trigger the action. +# +# The reset is achieved by writing to the "Application Interrupt and Reset +# Control" register located at address 0xE000ED0C. +# +# Both the processor and the peripherals can be reset by writing a value +# of 0x05FA0004. That value will write to the SYSRESETREQ bit. If you want +# to avoid resetting the peripherals, change the value to 0x05FA0001. That +# value will write to the VECTRESET bit. Do *not* use a value that sets both +# bits. +# +# In both cases, any on-board debug hardware is not reset. +# +# See the book "The Definitive Guide to the ARM Cortex-M3 and Cortex-M4 +# Processors" by Joseph Yiu, 3rd edition, pp 262-263 for further details. + +define hookpost-load +echo Resetting the processor and peripherals...\n +set *0xE000ED0C := 0x05FA0004 +echo Reset complete\n +end \ No newline at end of file diff --git a/arch/ARM/SAM/driver_demos/demo_spi/README.md b/arch/ARM/SAM/driver_demos/demo_spi/README.md new file mode 100644 index 000000000..30a15deae --- /dev/null +++ b/arch/ARM/SAM/driver_demos/demo_spi/README.md @@ -0,0 +1,7 @@ +This program demonstrates using the GPIO driver and interrupt +configuration to blink the four LEDs on the STM32F4 Discovery board. + +The LEDs blink in a circular pattern, initially rotating clockwise. When +the blue user button is pressed the rotation direction changes. Button +presses generate interrupts that signal state changes that can then be +queried by application code. diff --git a/arch/ARM/SAM/driver_demos/demo_spi/demo_spi.gpr b/arch/ARM/SAM/driver_demos/demo_spi/demo_spi.gpr new file mode 100644 index 000000000..b14e66690 --- /dev/null +++ b/arch/ARM/SAM/driver_demos/demo_spi/demo_spi.gpr @@ -0,0 +1,51 @@ +with "../../../../../boards/samv71_xplained/samv71_xplained_full.gpr"; + +project Demo_SPI extends "../../../../../examples/shared/common/common.gpr" is + + for Languages use ("Ada"); + for Main use ("demo_spi"); + for Source_Dirs use ("src"); + for Object_Dir use "obj/" & Samv71_Xplained_Full.Build; + for Runtime ("ada") use Samv71_Xplained_Full'Runtime ("Ada"); + for Create_Missing_Dirs use "true"; + type App_Builds is + ("Debug", "Production"); + App_Build : App_Builds := external ("APP_BUILD", "Production"); + for Object_Dir use "obj/" & App_Build; + type Lch_Type is + ("led", "lcd"); + Lch : Lch_Type := external ("LCH"); + type Rts_Type is + ("ravenscar-sfp", "ravenscar-full"); + Rts_Profile : Rts_Type := external ("RTS_Profile"); + type Loader_Type is + ("RAM", "ROM"); + Loader : Loader_Type := external ("LOADER"); + type Build_Type is + ("Debug", "Production"); + Adl_Build : Build_Type := external ("ADL_BUILD"); + + for Target use "arm-eabi"; + + package Builder is + for Global_Configuration_Pragmas use "gnat.adc"; + for Switches ("ada") use ("-g", "-j0"); + end Builder; + + package Compiler is + for Default_Switches ("ada") use ("-O0", "-g"); + end Compiler; + + package Ide is + for Connection_Tool use "openocd"; + for Connection_Config_File use "../atmel_samv71_xplained_ultra.cfg"; + for Program_Host use "localhost:4242"; + for Communication_Protocol use "remote"; + end Ide; + + package Linker is + for Default_Switches ("ada") use ("-Wl,--print-memory-usage", "-g", "-Wl,--gc-sections"); + end Linker; + +end Demo_SPI; + diff --git a/arch/ARM/SAM/driver_demos/demo_spi/gnat.adc b/arch/ARM/SAM/driver_demos/demo_spi/gnat.adc new file mode 100644 index 000000000..ba680210b --- /dev/null +++ b/arch/ARM/SAM/driver_demos/demo_spi/gnat.adc @@ -0,0 +1,2 @@ +pragma Partition_Elaboration_Policy (Sequential); + diff --git a/arch/ARM/SAM/driver_demos/demo_spi/src/demo_spi.adb b/arch/ARM/SAM/driver_demos/demo_spi/src/demo_spi.adb new file mode 100644 index 000000000..c5418eda0 --- /dev/null +++ b/arch/ARM/SAM/driver_demos/demo_spi/src/demo_spi.adb @@ -0,0 +1,107 @@ +with SAM.Device; + +with HAL; use HAL; +with HAL.GPIO; +with HAL.SPI; use HAL.SPI; + +with SAM.GPIO; +with SAM.SPI; + +with Ada.Real_Time; use Ada.Real_Time; + +procedure Demo_Spi +is + + LED0 : SAM.GPIO.GPIO_Point renames SAM.Device.PA23; + LED1 : SAM.GPIO.GPIO_Point renames SAM.Device.PC9; + + Port : SAM.SPI.SPI_Port renames SAM.Device.SPI_0_Cs1; + + MISO : SAM.GPIO.GPIO_Point renames SAM.Device.PD20; + MOSI : SAM.GPIO.GPIO_Point renames SAM.Device.PD21; + SPCK : SAM.GPIO.GPIO_Point renames SAM.Device.PD22; + NPCS1 : SAM.GPIO.GPIO_Point renames SAM.Device.PD25; + + Data_Stream : HAL.SPI.SPI_Data_8b (1 .. 8); + Status : HAL.SPI.SPI_Status; + + Counter : UInt8 := 0; + + Cfg : SAM.SPI.Configuration := (Baud => 25_000_000, + Tx_On_Rx_Empty => False, + others => <>); + + procedure Wait (Period : Time_Span) + is + begin + delay until (Period + Clock); + end Wait; + + procedure Initialize_LEDs is + use SAM.GPIO; + begin + Enable_Clock (SAM.Device.GPIO_A); + Enable_Clock (SAM.Device.GPIO_B); + + LED0.Configure_IO + (Config => GPIO_Port_Configuration'(Mode => Mode_Out, + Resistors => <>, + Output_Type => Open_Drain)); + LED1.Configure_IO + (Config => GPIO_Port_Configuration'(Mode => Mode_Out, + Resistors => <>, + Output_Type => Open_Drain)); + end Initialize_LEDs; + + procedure Initialize_SPI is + use SAM.GPIO; + begin + MISO.Configure_IO (Config => (Mode => Mode_AF, + Resistors => <>, + AF_Output_Type => Push_Pull, + AF => Periph_B)); + MOSI.Configure_IO (Config => (Mode => Mode_AF, + Resistors => <>, + AF_Output_Type => Push_Pull, + AF => Periph_B)); + SPCK.Configure_IO (Config => (Mode => Mode_AF, + Resistors => <>, + AF_Output_Type => Push_Pull, + AF => Periph_B)); + NPCS1.Configure_IO (Config => (Mode => Mode_AF, + Resistors => <>, + AF_Output_Type => Push_Pull, + AF => Periph_B)); + + SAM.SPI.Configure (This => Port, + Cfg => Cfg); + end Initialize_SPI; +begin + + Initialize_LEDs; + Initialize_SPI; + loop + LED0.Set; + LED1.Set; + Wait (Period => Milliseconds (1000)); + LED0.Clear; + LED1.Clear; + + for I in Data_Stream'Range loop + Data_Stream (I) := Counter; + Counter := Counter + 1; + end loop; + + SAM.SPI.Transmit (This => Port, + Data => Data_Stream, + Status => Status); + + if Status /= HAL.SPI.Ok then + LED0.Set; + else + LED1.Set; + end if; + + Wait (Period => Milliseconds (1000)); + end loop; +end Demo_SPI; diff --git a/arch/ARM/SAM/drivers/sam-dma.ads.old.ads b/arch/ARM/SAM/drivers/sam-dma.ads.old.ads new file mode 100644 index 000000000..a08657ee6 --- /dev/null +++ b/arch/ARM/SAM/drivers/sam-dma.ads.old.ads @@ -0,0 +1,634 @@ +pragma Restrictions (No_Elaboration_Code); + +with System; use System; +with Ada.Real_Time; use Ada.Real_Time; + +-- private with SAM_SVD.XDMAC; + +package SAM.DMA is + +-- type DMA_Controller is limited private; + + type HW_Iface_Number is + (HSMCI_TXRX, + SPI0_TX, SPI0_RX, + SPI1_TX, SPI1_RX, + QSPI_TX, QSPI_RX, + USART0_TX, USART0_RX, + USART1_TX, USART1_RX, + USART2_TX, USART2_RX, + PWM0_TX, + TWIHS0_TX, TWIHS0_RX, + TWIHS1_TX, TWIHS1_RX, + TWIHS2_TX, TWIHS2_RX, + UART0_TX, UART0_RX, + UART1_TX, UART1_RX, + UART2_TX, UART2_RX, + UART3_TX, UART3_RX, + UART4_TX, UART4_RX, + DACC0_TX, + DACC1_TX, + SSC_TX, SSC_RX, + PIOA_RX, + AFEC0_RX, + AFEC1_RX, + AES_TX, AES_RX, + PWM1_TX, + TC0_RX, + TC3_RX, + TC6_RX, + TC9_RX, + I2SC0_TX_Left, I2SC0_RX_Left, + I2SC1_TX_Left, I2SC1_RX_Left, + I2SC0_TX_Right, I2SC0_RX_Right, + I2SC1_TX_Right, I2SC1_RX_Right); + + for HW_Iface_Number use + (HSMCI_TXRX => 0, + SPI0_TX => 1, + SPI0_RX => 2, + SPI1_TX => 3, + SPI1_RX => 4, + QSPI_TX => 5, + QSPI_RX => 6, + USART0_TX => 7, + USART0_RX => 8, + USART1_TX => 9, + USART1_RX => 10, + USART2_TX => 11, + USART2_RX => 12, + PWM0_TX => 13, + TWIHS0_TX => 14, + TWIHS0_RX => 15, + TWIHS1_TX => 16, + TWIHS1_RX => 17, + TWIHS2_TX => 18, + TWIHS2_RX => 19, + UART0_TX => 20, + UART0_RX => 21, + UART1_TX => 22, + UART1_RX => 23, + UART2_TX => 24, + UART2_RX => 25, + UART3_TX => 26, + UART3_RX => 27, + UART4_TX => 28, + UART4_RX => 29, + DACC0_TX => 30, + DACC1_TX => 31, + SSC_TX => 32, + SSC_RX => 33, + PIOA_RX => 34, + AFEC0_RX => 35, + AFEC1_RX => 36, + AES_TX => 37, + AES_RX => 38, + PWM1_TX => 39, + TC0_RX => 40, + TC3_RX => 41, + TC6_RX => 42, + TC9_RX => 43, + I2SC0_TX_Left => 44, + I2SC0_RX_Left => 45, + I2SC1_TX_Left => 46, + I2SC1_RX_Left => 47, + I2SC0_TX_Right => 48, + I2SC0_RX_Right => 49, + I2SC1_TX_Right => 50, + I2SC1_RX_Right => 51); + + -- Do not change the order of the enumerals in the types in this package. + -- The underlying canonical representation values are required. + + type DMA_Stream_Selector is + (Stream_0, + Stream_1, + Stream_2, + Stream_3, + Stream_4, + Stream_5, + Stream_6, + Stream_7); + + procedure Enable + (This : DMA_Controller; + Stream : DMA_Stream_Selector) + with Inline; + -- Before enabling a stream to start a new transfer, the event status flags + -- corresponding to the stream must be cleared. Note that the unit may not + -- be enabled by the time the call returns. + + procedure Disable + (This : DMA_Controller; + Stream : DMA_Stream_Selector) + with + Post => not Enabled (This, Stream), + Inline; + + function Enabled + (This : DMA_Controller; + Stream : DMA_Stream_Selector) + return Boolean with Inline; + + procedure Reset + (This : in out DMA_Controller; + Stream : DMA_Stream_Selector) + with + Post => + not Enabled (This, Stream) and + Operating_Mode (This, Stream) = Normal_Mode and + Current_NDT (This, Stream) = 0 and + Selected_Channel (This, Stream) = Channel_0 and + Transfer_Direction (This, Stream) = Peripheral_To_Memory and + not Double_Buffered (This, Stream) and + not Circular_Mode (This, Stream) and + Memory_Data_Width (This, Stream) = Bytes and + Peripheral_Data_Width (This, Stream) = Bytes and + Priority (This, Stream) = Priority_Low and + Current_Memory_Buffer (This, Stream) = Memory_Buffer_0 and + (for all Flag in DMA_Status_Flag => + not Status (This, Stream, Flag)) and + (for all Interrupt in DMA_Interrupt => + not Interrupt_Enabled (This, Stream, Interrupt)); + -- In addition, + -- M_Burst = Memory_Burst_Single and + -- P_Burst = Peripheral_Burst_Single and + -- P_Inc_Offset_Size = 0 and + -- M_Inc_Mode = False and + -- P_Inc_Mode = False + -- Also clears the FIFO control register bits except sets bits to show FIFO + -- is empty, and to set the FIFO filling threshold selection to 1/2 full. + + procedure Configure_Data_Flow + (This : DMA_Controller; + Stream : DMA_Stream_Selector; + Source : Address; + Destination : Address; + Data_Count : UInt16) + with + Pre => + not Enabled (This, Stream) and + Valid_Addresses (Source, Destination) and + Compatible_Alignments (This, Stream, Source, Destination); + -- Sets the source and destination arguments within the specified stream, + -- based on the direction previously specified by a call to procedure + -- Configure. + -- + -- Sets the number of data items to be transferred (from 0 to 65535) on + -- the specified stream in the next transfer. This is the volume of data to + -- be transferred from source to destination. The number specified depends + -- only on the peripheral data format, as specified by the record component + -- Peripheral_Data_Format passed to a call to Configure. The value to be + -- specified is computed as follows: + -- + -- If the peripheral data format is in units of bytes, the value is + -- equal to the total number of bytes contained in the data to be sent. + -- + -- If the peripheral data format is in units of half-words, the value is + -- 1/2 the total number of bytes contained in the data to be sent. + -- + -- If the peripheral data format is in units of words, the value is + -- 1/4 the total number of bytes contained in the data to be sent. + -- + -- For example, to send a sequence of characters to a USART, the USART + -- peripheral format will be in units of bytes so the Data_Count argument + -- will be the number of characters (bytes) in the string to be sent. + -- In contrast, on a memory-to-memory transfer the most efficient approach + -- is to work in units of words. One would therefore specify word units for + -- the source and destination formats and then specify 1/4 the total number + -- of bytes involved (assuming a four-UInt8 word). + + procedure Start_Transfer + (This : DMA_Controller; + Stream : DMA_Stream_Selector; + Source : Address; + Destination : Address; + Data_Count : UInt16) + with + Pre => + Valid_Addresses (Source, Destination) and + Compatible_Alignments (This, Stream, Source, Destination) and + (for all Flag in DMA_Status_Flag => + (not Status (This, Stream, Flag))); + -- Convenience routine: disables the stream, calls Configure_Data_Flow, + -- and then enables the stream to start the transfer. DMA interrupts are + -- not enabled by this routine, but could be enabled prior to the call. + -- The requirement to clear the flags first is due to the fact that + -- the transfer begins immediately at the end of this routine. The + -- value specified for Data_Count is as described for procedure + -- Configure_Data_Flow. + + type DMA_Interrupt is + (Direct_Mode_Error_Interrupt, + Transfer_Error_Interrupt, + Half_Transfer_Complete_Interrupt, + Transfer_Complete_Interrupt, + FIFO_Error_Interrupt); + + type Interrupt_Selections is array (DMA_Interrupt) of Boolean; + + procedure Start_Transfer_with_Interrupts + (This : DMA_Controller; + Stream : DMA_Stream_Selector; + Source : Address; + Destination : Address; + Data_Count : UInt16; + Enabled_Interrupts : Interrupt_Selections := (others => True)) + with + Pre => + Valid_Addresses (Source, Destination) and + Compatible_Alignments (This, Stream, Source, Destination) and + (for all Flag in DMA_Status_Flag => + (not Status (This, Stream, Flag))); + -- Convenience routine: disables the stream, calls Configure_Data_Flow, + -- enables the selected DMA interrupts (by default, all of them), and + -- then enables the stream to start the transfer. All the selected DMA + -- interrupts are enabled, all the others are left unchanged. Interrupts + -- are selected for enablement by having a True value in the array at their + -- index location. The requirement to clear the flags first is due to the + -- fact that the transfer begins immediately at the end of this routine. + -- The value specified for Data_Count is as described for procedure + -- Configure_Data_Flow. + + type DMA_Error_Code is + (DMA_No_Error, + DMA_Transfer_Error, + DMA_FIFO_Error, + DMA_Direct_Mode_Error, + DMA_Timeout_Error, + DMA_Device_Error); + + procedure Abort_Transfer + (This : DMA_Controller; + Stream : DMA_Stream_Selector; + Result : out DMA_Error_Code) + with Post => not Enabled (This, Stream); + -- Disables the specified stream and then waits until the request is + -- effective. If a stream is disabled while a data transfer is ongoing, the + -- current datum will be transferred and the stream will be disabled only + -- after the transfer of this single datum completes. + + type DMA_Transfer_Level is + (Full_Transfer, + Half_Transfer); + + procedure Poll_For_Completion + (This : in out DMA_Controller; + Stream : DMA_Stream_Selector; + Expected_Level : DMA_Transfer_Level; + Timeout : Time_Span; + Result : out DMA_Error_Code); + + procedure Set_NDT + (This : DMA_Controller; + Stream : DMA_Stream_Selector; + Data_Count : UInt16) + with + Pre => not Enabled (This, Stream), + Post => Current_NDT (This, Stream) = Data_Count, + Inline; + -- Sets the number of data items to be transferred on the stream. + -- The Data_Count parameter specifies the number of data items to be + -- transferred (from 0 to 65535) on the next transfer. The value is + -- as described for procedure Configure_Data_Flow. + + function Items_Transferred + (This : DMA_Controller; + Stream : DMA_Stream_Selector) + return UInt16; + -- returns the number of items transfetred + + function Current_NDT + (This : DMA_Controller; + Stream : DMA_Stream_Selector) + return UInt16 + with Inline; + -- Returns the value of the NDT register. Should not be used directly, + -- as the meaning changes depending on transfer mode. rather use + -- Items_Transferred() + + function Circular_Mode + (This : DMA_Controller; + Stream : DMA_Stream_Selector) + return Boolean + with Inline; + + procedure Enable_Interrupt + (This : DMA_Controller; + Stream : DMA_Stream_Selector; + Source : DMA_Interrupt) + with + Post => Interrupt_Enabled (This, Stream, Source); + -- The postcondition should not be relied upon completely because it is + -- possible, under just the wrong conditions, for the interrupt to be + -- disabled immediately, prior to return from this routine + + procedure Disable_Interrupt + (This : DMA_Controller; + Stream : DMA_Stream_Selector; + Source : DMA_Interrupt) + with + Post => not Interrupt_Enabled (This, Stream, Source); + + function Interrupt_Enabled + (This : DMA_Controller; + Stream : DMA_Stream_Selector; + Source : DMA_Interrupt) + return Boolean + with Inline; + + type DMA_Status_Flag is + (FIFO_Error_Indicated, + Direct_Mode_Error_Indicated, + Transfer_Error_Indicated, + Half_Transfer_Complete_Indicated, + Transfer_Complete_Indicated); + + procedure Clear_Status + (This : in out DMA_Controller; + Stream : DMA_Stream_Selector; + Flag : DMA_Status_Flag) + with + Post => not Status (This, Stream, Flag), + Inline; + + procedure Clear_All_Status + (This : in out DMA_Controller; + Stream : DMA_Stream_Selector) + with Post => + (for all Indicated in DMA_Status_Flag => + not Status (This, Stream, Indicated)); + + function Status + (This : DMA_Controller; + Stream : DMA_Stream_Selector; + Flag : DMA_Status_Flag) + return Boolean + with Inline; + -- Returns whether the specified status flag is indicated + + type DMA_Channel_Selector is + (Channel_0, + Channel_1, + Channel_2, + Channel_3, + Channel_4, + Channel_5, + Channel_6, + Channel_7); + + function Selected_Channel + (This : DMA_Controller; Stream : DMA_Stream_Selector) + return DMA_Channel_Selector + with Inline; + + type DMA_Data_Transfer_Direction is + (Peripheral_To_Memory, + Memory_To_Peripheral, + Memory_To_Memory); + -- Note that only DMA_2 is able to do Memory_To_Memory transfers, and that + -- in this direction the circular mode is not allowed and the internal FIFO + -- must be enabled. + + function Transfer_Direction + (This : DMA_Controller; Stream : DMA_Stream_Selector) + return DMA_Data_Transfer_Direction + with Inline; + + type DMA_Data_Transfer_Widths is + (Bytes, + HalfWords, + Words); + + function Peripheral_Data_Width + (This : DMA_Controller; Stream : DMA_Stream_Selector) + return DMA_Data_Transfer_Widths + with Inline; + + function Memory_Data_Width + (This : DMA_Controller; Stream : DMA_Stream_Selector) + return DMA_Data_Transfer_Widths + with Inline; + + type DMA_Mode is + (Normal_Mode, + Peripheral_Flow_Control_Mode, + Circular_Mode); + + function Operating_Mode + (This : DMA_Controller; Stream : DMA_Stream_Selector) + return DMA_Mode + with Inline; + + type DMA_Priority_Level is + (Priority_Low, + Priority_Medium, + Priority_High, + Priority_Very_High); + + function Priority + (This : DMA_Controller; Stream : DMA_Stream_Selector) + return DMA_Priority_Level + with Inline; + + type Memory_Buffer_Target is (Memory_Buffer_0, Memory_Buffer_1); + + function Current_Memory_Buffer + (This : DMA_Controller; Stream : DMA_Stream_Selector) + return Memory_Buffer_Target + with Inline; + + procedure Select_Current_Memory_Buffer + (This : DMA_Controller; + Stream : DMA_Stream_Selector; + Buffer : Memory_Buffer_Target) + with Inline; + + procedure Set_Memory_Buffer + (This : DMA_Controller; + Stream : DMA_Stream_Selector; + Buffer : Memory_Buffer_Target; + To : System.Address) + with Inline; + + procedure Configure_Double_Buffered_Mode + (This : DMA_Controller; + Stream : DMA_Stream_Selector; + Buffer_0_Value : Address; + Buffer_1_Value : Address; + First_Buffer_Used : Memory_Buffer_Target) + with + Pre => not Enabled (This, Stream), + Post => not Enabled (This, Stream) and + Current_Memory_Buffer (This, Stream) = First_Buffer_Used; + -- A convenience routine that in effect calls Set_Memory_Buffer + -- once each for Buffer_1_Value and Buffer_2_Value, and then calls + -- Select_Current_Memory_Buffer so that First_Buffer_Used is the + -- buffer used first when the stream is enabled. + + procedure Enable_Double_Buffered_Mode + (This : DMA_Controller; + Stream : DMA_Stream_Selector) + with + Pre => Circular_Mode (This, Stream) and + Transfer_Direction (This, Stream) /= Memory_To_Memory, + Post => Double_Buffered (This, Stream); + + procedure Disable_Double_Buffered_Mode + (This : DMA_Controller; + Stream : DMA_Stream_Selector) + with Post => not Double_Buffered (This, Stream); + + function Double_Buffered + (This : DMA_Controller; + Stream : DMA_Stream_Selector) + return Boolean + with Inline; + + type DMA_FIFO_Threshold_Level is + (FIFO_Threshold_1_Quart_Full_Configuration, + FIFO_Threshold_Half_Full_Configuration, + FIFO_Threshold_3_Quarts_Full_Configuration, + FIFO_Threshold_Full_Configuration); + + type DMA_FIFO_Filling_State is + (FIFO_Less1QuarterFull, -- less than 1 quarter full but not empty + FIFO_1QuarterFull, -- more than 1 quarter full + FIFO_HalfFull, -- more than 1 half full + FIFO_3QuartersFull, -- more than 3 quarters full + FIFO_Empty, + FIFO_Full); + + type DMA_Memory_Burst is + (Memory_Burst_Single, + Memory_Burst_Inc4, + Memory_Burst_Inc8, + Memory_Burst_Inc16); + + type DMA_Peripheral_Burst is + (Peripheral_Burst_Single, + Peripheral_Burst_Inc4, + Peripheral_Burst_Inc8, + Peripheral_Burst_Inc16); + + type DMA_Stream_Configuration is record + -- These are the static, non-varying properties of the transactions + -- occurring on the streams to which they are applied (by a call to + -- Configure). Other, varying, properties are specified procedurally. + -- + -- You are not required to specify a value for every component because + -- some are only referenced depending on the values for others. Note, + -- however, that the default values specified do not represent a valid + -- configuration as a whole. + + Channel : DMA_Channel_Selector := DMA_Channel_Selector'First; + -- The channel in the multiplexed connections of controllers, streams, + -- and peripherals. It is vital to note that not all peripherals can + -- be connected to all streams. The possibilities are organized by + -- channels, per controller, as specified by the ST Micro Reference + -- Manual in the "DMA Request Mapping" tables. + + Direction : DMA_Data_Transfer_Direction := DMA_Data_Transfer_Direction'First; + + Increment_Peripheral_Address : Boolean := False; + -- Whether the peripheral address value should be incremented + -- automatically after each transfer + + Increment_Memory_Address : Boolean := False; + -- Whether the memory address value should be incremented automatically + -- after each transfer + + Peripheral_Data_Format : DMA_Data_Transfer_Widths := DMA_Data_Transfer_Widths'First; + -- The units of data (the format) in which the peripheral side of the + -- transaction is expressed. For example, a USART would work in terms + -- of bytes. See the description in Configure_Data_Flow. + + Memory_Data_Format : DMA_Data_Transfer_Widths := DMA_Data_Transfer_Widths'First; + -- The units of data (the format) in which the memory side of the + -- transaction is expressed. See the description in Configure_Data_Flow. + + Operation_Mode : DMA_Mode := DMA_Mode'First; + -- Note that the circular buffer mode cannot be used if memory-to-memory + -- data transfer is configured on the selected Stream + + Priority : DMA_Priority_Level := DMA_Priority_Level'First; + -- The relative priority of the given stream to all other streams + + FIFO_Enabled : Boolean := False; + -- Specifies whether the internal FIFO will be used for the transactions + -- occurring on the specified stream. By default the FIFO is disabled by + -- the hardware, and so the unit works in the so-called "direct mode" + -- instead. Per the Application Note, enabling the FIFO is highly + -- advantageous. Note that the direct mode cannot be used if + -- memory-to-memory data transfer is configured. The threshold and + -- burst sizes are only considered if the FIFO is enabled, and the + -- corresponding values are highly dependent upon one another! + + FIFO_Threshold : DMA_FIFO_Threshold_Level := DMA_FIFO_Threshold_Level'First; + -- The threshold at which the FIFO is refilled. It is vital that the + -- threshold and burst sizes, if specified, are compatible. See the + -- Reference Manual and especially the Application Note. + + Memory_Burst_Size : DMA_Memory_Burst := DMA_Memory_Burst'First; + -- Specifies the amount of data to be transferred in a single non- + -- interruptible transaction. Note: The burst mode is possible only if + -- the address increment mode is enabled. + + Peripheral_Burst_Size : DMA_Peripheral_Burst := DMA_Peripheral_Burst'First; + -- Specifies the the amount of data to be transferred in + -- a single non-interruptible transaction. Note: The burst mode is + -- possible only if the address increment mode is enabled. + end record; + + procedure Configure + (This : DMA_Controller; + Stream : DMA_Stream_Selector; + Config : DMA_Stream_Configuration) + with Post => not Enabled (This, Stream); + -- This is the primary stream configuration facility. All the static + -- properties of the transfers for the given stream are specified here, + -- and in some cases, nowhere else (such as the channel). The required + -- relationships between the parameters specified in the record are + -- not checked, other than by the hardware itself. + -- + -- Note that not all required properties are specified here. In particular, + -- because they can vary per transfer, the source and destination + -- addresses, as well as the number of data items to be transferred, + -- are specified procedurally via calls to Configure_Data_Flow. + + function Valid_Addresses (Source, Destination : Address) return Boolean is + (Source /= Null_Address and Destination /= Null_Address and + Source /= Destination); + -- Basic sanity checking for the values + + function Aligned (This : Address; Width : DMA_Data_Transfer_Widths) + return Boolean with Inline; + -- Returns whether the address is aligned on a word, half-word, or UInt8 + -- boundary + + function Compatible_Alignments + (This : DMA_Controller; + Stream : DMA_Stream_Selector; + Source : Address; + Destination : Address) + return Boolean is + (case Transfer_Direction (This, Stream) is + when Peripheral_To_Memory | Memory_To_Memory => + Aligned (Source, Peripheral_Data_Width (This, Stream)) + and + Aligned (Destination, Memory_Data_Width (This, Stream)), + when Memory_To_Peripheral => + Aligned (Source, Memory_Data_Width (This, Stream)) + and + Aligned (Destination, Peripheral_Data_Width (This, Stream))); + -- Based on Ref Manual Table 44 and associated text, checks the alignments + -- of the addresses against the Peripheral_Data_Format (P_Data_Size) and + -- Memory_Data_Format (M_Data_Size) values for the given stream. We use an + -- expression function because the semantics are meant to be part of the + -- spec of the package, visible as a precondition. + +private + +-- type DMA_Controller is new STM32_SVD.DMA.DMA_Peripheral; + +end STM32.DMA; diff --git a/arch/ARM/SAM/drivers/sam-gpio.adb b/arch/ARM/SAM/drivers/sam-gpio.adb new file mode 100644 index 000000000..df1b2fe58 --- /dev/null +++ b/arch/ARM/SAM/drivers/sam-gpio.adb @@ -0,0 +1,329 @@ +with SAM; use SAM; +with SAM_SVD; use SAM_SVD; +with SAM_SVD.PIO; use SAM_SVD.PIO; + +with SAM.PMC; use SAM.PMC; + +package body SAM.GPIO is + + ---------- + -- Mode -- + ---------- + + overriding + function Mode (This : GPIO_Point) return HAL.GPIO.GPIO_Mode + is + begin + case Pin_IO_Mode (This) is + when Mode_Out => return HAL.GPIO.Output; + when Mode_In => return HAL.GPIO.Input; + when others => return HAL.GPIO.Unknown; + end case; + end Mode; + + ----------------- + -- Pin_IO_Mode -- + ----------------- + + function Pin_IO_Mode (This : GPIO_Point) return Pin_IO_Modes + is + Ret : Pin_IO_Modes; + begin + if This.Periph.PIO_PSR.Arr (This.Pin) then + -- peripheral is inactive + if This.Periph.PIO_OSR.Arr (This.Pin) then + -- output + Ret := Mode_Out; + else + -- input + Ret := Mode_In; + end if; + else + -- peripheral is active + Ret := Mode_AF; + end if; + return Ret; + end Pin_IO_Mode; + + -------------- + -- Set_Mode -- + -------------- + + overriding + function Set_Mode (This : in out GPIO_Point; + Mode : HAL.GPIO.GPIO_Config_Mode) + return Boolean + is + begin + case Mode is + when HAL.GPIO.Output => + This.Periph.PIO_OER.Arr (This.Pin) := True; + when HAL.GPIO.Input => + This.Periph.PIO_ODR.Arr (This.Pin) := True; +-- when others => +-- return False; + end case; + return True; + end Set_Mode; + + ------------------- + -- Pull_Resistor -- + ------------------- + + overriding + function Pull_Resistor (This : GPIO_Point) + return HAL.GPIO.GPIO_Pull_Resistor + is + begin + if This.Periph.PIO_PUSR.Arr (This.Pin) then + return HAL.GPIO.Pull_Up; + elsif This.Periph.PIO_PPDSR.Arr (This.Pin) then + return HAL.GPIO.Pull_Down; + else + return HAL.GPIO.Floating; + end if; + end Pull_Resistor; + + ----------------------- + -- Set_Pull_Resistor -- + ----------------------- + + overriding + function Set_Pull_Resistor (This : in out GPIO_Point; + Pull : HAL.GPIO.GPIO_Pull_Resistor) + return Boolean + is + begin + case Pull is + when HAL.GPIO.Floating => + This.Periph.PIO_PUDR.Arr (This.Pin) := True; + This.Periph.PIO_PPDDR.Arr (This.Pin) := True; + when HAL.GPIO.Pull_Up => + This.Periph.PIO_PUER.Arr (This.Pin) := True; + when HAL.GPIO.Pull_Down => + This.Periph.PIO_PPDER.Arr (This.Pin) := True; + end case; + return True; + end Set_Pull_Resistor; + + --------- + -- Set -- + --------- + + overriding + function Set (This : GPIO_Point) return Boolean + is + begin + return (This.Periph.PIO_PDSR.Arr (This.Pin)); + end Set; + + --------- + -- Set -- + --------- + + overriding + procedure Set (This : in out GPIO_Point) + is + begin + This.Periph.PIO_SODR.Arr (This.Pin) := True; + end Set; + + ----------- + -- Clear -- + ----------- + + overriding + procedure Clear (This : in out GPIO_Point) + is + begin + This.Periph.PIO_CODR.Arr (This.Pin) := True; + end Clear; + + ------------ + -- Toggle -- + ------------ + + overriding + procedure Toggle (This : in out GPIO_Point) + is + begin + if This.Periph.PIO_ODSR.Arr (This.Pin) then + This.Clear; + else + This.Set; + end if; + end Toggle; + + ----------- + -- Drive -- + ----------- + + procedure Drive (This : in out GPIO_Point; Condition : Boolean) + is + begin + if Condition then + This.Set; + else + This.Clear; + end if; + end Drive; + + ------------ + -- Locked -- + ------------ + + function Locked (This : GPIO_Point) return Boolean + is + begin + return (This.Periph.PIO_LOCKSR.Arr (This.Pin)); + end Locked; + + ------------------ + -- Configure_IO -- + ------------------ + + procedure Configure_IO (This : in out GPIO_Point; + Config : GPIO_Port_Configuration) + is + begin + -- Disable interrupts + This.Periph.PIO_IDR.Arr (This.Pin) := True; + + -- The PIO input logic requires the peripheral clock + if Config.Mode = Mode_In then + SAM.PMC.Configure_Peripheral (ID => Group_ID (GPIO => This), + Enable => True); + end if; + + -- Enable pull-up resistors as requested + -- Enable pull-down resistors as requested + if not Set_Pull_Resistor (This => This, + Pull => Config.Resistors) + then + raise GPIO_Exception; + end if; + + case Config.Mode is + when Mode_In => + This.Periph.PIO_PER.Arr (This.Pin) := True; + if not Set_Mode (This => This, + Mode => HAL.GPIO.Input) + then + raise GPIO_Exception; + end if; + + case Config.Filter_Type is + when None => + This.Periph.PIO_IFSCDR.Arr (This.Pin) := True; + This.Periph.PIO_IFDR.Arr (This.Pin) := True; + when Glitch => + This.Periph.PIO_IFSCDR.Arr (This.Pin) := True; + This.Periph.PIO_IFER.Arr (This.Pin) := True; + when Debounce => + This.Periph.PIO_IFSCER.Arr (This.Pin) := True; + This.Periph.PIO_SCDR.DIV := Config.Filter_Time; + end case; + This.Periph.PIO_SCHMITT.Arr (This.Pin) := Config.Schmitt_Trigger; + when Mode_Out => + This.Periph.PIO_PER.Arr (This.Pin) := True; + if not Set_Mode (This => This, + Mode => HAL.GPIO.Output) + then + raise GPIO_Exception; + end if; + + case Config.Output_Type is + when Push_Pull => + This.Periph.PIO_MDDR.Arr (This.Pin) := True; + when Open_Drain => + This.Periph.PIO_MDER.Arr (This.Pin) := True; + end case; + when Mode_AF => + case Config.AF_Output_Type is + when Push_Pull => + This.Periph.PIO_MDDR.Arr (This.Pin) := True; + when Open_Drain => + This.Periph.PIO_MDER.Arr (This.Pin) := True; + end case; + case Config.AF is + when Periph_A => + This.Periph.PIO_ABCDSR (0).Arr (This.Pin) := False; + This.Periph.PIO_ABCDSR (1).Arr (This.Pin) := False; + when Periph_B => + This.Periph.PIO_ABCDSR (0).Arr (This.Pin) := True; + This.Periph.PIO_ABCDSR (1).Arr (This.Pin) := False; + when Periph_C => + This.Periph.PIO_ABCDSR (0).Arr (This.Pin) := False; + This.Periph.PIO_ABCDSR (1).Arr (This.Pin) := True; + when Periph_D => + This.Periph.PIO_ABCDSR (0).Arr (This.Pin) := True; + This.Periph.PIO_ABCDSR (1).Arr (This.Pin) := True; + end case; + This.Periph.PIO_PDR.Arr (This.Pin) := True; + end case; + end Configure_IO; + + procedure Enable_Clock (Port : GPIO_Port) + is + begin + SAM.PMC.Enable_Peripheral_Clock (ID => Group_ID (Port => Port)); + end Enable_Clock; + + procedure Enable_Clock (Point : GPIO_Point) + is + begin + SAM.PMC.Enable_Peripheral_Clock (ID => Group_ID (GPIO => Point)); + end Enable_Clock; + + procedure Disable_Clock (Port : GPIO_Port) + is + begin + SAM.PMC.Disable_Peripheral_Clock (ID => Group_ID (Port => Port)); + end Disable_Clock; + + procedure Disable_Clock (Point : GPIO_Point) + is + begin + SAM.PMC.Disable_Peripheral_Clock (ID => Group_ID (GPIO => Point)); + end Disable_Clock; + + procedure Enable_Interrupt (This : GPIO_Point; + Trigger : Interrupt_Trigger_Type) + is + begin + This.Periph.PIO_IER.Arr (This.Pin) := True; + case Trigger is + when Rising_Edge => + This.Periph.PIO_AIMER.Arr (This.Pin) := True; + This.Periph.PIO_ESR.Arr (This.Pin) := True; + This.Periph.PIO_REHLSR.Arr (This.Pin) := True; + when Falling_Edge => + This.Periph.PIO_AIMER.Arr (This.Pin) := True; + This.Periph.PIO_ESR.Arr (This.Pin) := True; + This.Periph.PIO_FELLSR.Arr (This.Pin) := True; + when Low => + This.Periph.PIO_AIMER.Arr (This.Pin) := True; + This.Periph.PIO_LSR.Arr (This.Pin) := True; + This.Periph.PIO_FELLSR.Arr (This.Pin) := True; + when High => + This.Periph.PIO_AIMER.Arr (This.Pin) := True; + This.Periph.PIO_LSR.Arr (This.Pin) := True; + This.Periph.PIO_REHLSR.Arr (This.Pin) := True; + when Any_Edge => + This.Periph.PIO_AIMDR.Arr (This.Pin) := True; + end case; + end Enable_Interrupt; + + procedure Disable_Interrupt (This : GPIO_Point) + is + begin + This.Periph.PIO_IDR.Arr (This.Pin) := True; + end Disable_Interrupt; + + function Read_Interrupt_Status (This : GPIO_Point) return Boolean + is + begin + return This.Periph.PIO_ISR.Arr (This.Pin); + end Read_Interrupt_Status; + +end SAM.GPIO; diff --git a/arch/ARM/SAM/drivers/sam-gpio.ads b/arch/ARM/SAM/drivers/sam-gpio.ads new file mode 100644 index 000000000..3794d91ad --- /dev/null +++ b/arch/ARM/SAM/drivers/sam-gpio.ads @@ -0,0 +1,156 @@ +private with SAM_SVD.PIO; +private with System; + +with HAL.GPIO; + +package SAM.GPIO is + + GPIO_Exception : exception; + + type GPIO_Port is limited private; + + subtype GPIO_Pin is Integer range 0 .. 31; + + type Pin_IO_Modes is (Mode_In, Mode_Out, Mode_AF); + + type Pin_AF_Mode is (Periph_A, Periph_B, Periph_C, Periph_D); + + type Pin_Output_Types is (Push_Pull, Open_Drain); + + type Pin_Input_Filter_Type is (None, Glitch, Debounce); + + type GPIO_Port_Configuration (Mode : Pin_IO_Modes := Mode_In) is record + Resistors : HAL.GPIO.GPIO_Pull_Resistor := HAL.GPIO.Floating; + case Mode is + when Mode_In => + Filter_Type : Pin_Input_Filter_Type := None; + Filter_Time : UInt14 := 5; + Schmitt_Trigger : Boolean := False; + when Mode_Out => + Output_Type : Pin_Output_Types := Push_Pull; + when Mode_AF => + AF_Output_Type : Pin_Output_Types := Push_Pull; + AF : Pin_AF_Mode; + end case; + end record; + + type GPIO_Point is new HAL.GPIO.GPIO_Point with record + Periph : access GPIO_Port; + Pin : GPIO_Pin; + end record; + + type GPIO_Group is + (A, B, C, D, E); + + function Group (Port : GPIO_Port) return GPIO_Group; + + function Group (GPIO : GPIO_Point) return GPIO_Group is + (Group (Port => GPIO.Periph.all)); + + function Group_ID (Group : GPIO_Group) return Natural is + (case Group is + when A => PIOA_ID, + when B => PIOB_ID, + when C => PIOC_ID, + when D => PIOD_ID, + when E => PIOE_ID); + + function Group_ID (GPIO : GPIO_Point) return Natural is + (Group_ID (Group => Group (GPIO => GPIO))); + + function Group_ID (Port : GPIO_Port) return Natural is + (Group_ID (Group => Group (Port => Port))); + + overriding + function Mode (This : GPIO_Point) return HAL.GPIO.GPIO_Mode; + + overriding + function Set_Mode (This : in out GPIO_Point; + Mode : HAL.GPIO.GPIO_Config_Mode) return Boolean; + + overriding + function Pull_Resistor (This : GPIO_Point) + return HAL.GPIO.GPIO_Pull_Resistor; + + overriding + function Set_Pull_Resistor (This : in out GPIO_Point; + Pull : HAL.GPIO.GPIO_Pull_Resistor) + return Boolean; + + overriding + function Set (This : GPIO_Point) return Boolean with + Pre => Pin_IO_Mode (This) /= Mode_AF, + Inline; + -- Returns True if the bit specified by This.Pin is set (not zero) in the + -- input data register of This.Port.all; returns False otherwise. + + overriding + procedure Set (This : in out GPIO_Point) with + Inline; + -- For This.Port.all, sets the output data register bit specified by + -- This.Pin to one. Other pins are unaffected. + + overriding + procedure Clear (This : in out GPIO_Point) with + Inline; + -- For This.Port.all, sets the output data register bit specified by + -- This.Pin to zero. Other pins are unaffected. + + overriding + procedure Toggle (This : in out GPIO_Point) with + Inline; + -- For This.Port.all, negates the output data register bit specified by + -- This.Pin (one becomes zero and vice versa). Other pins are unaffected. + + procedure Drive (This : in out GPIO_Point; Condition : Boolean) with + Post => (This.Set = Condition), + Inline; + -- Drives This high or low (set or clear) based on the value of Condition + + function Locked (This : GPIO_Point) return Boolean + with Inline; + + procedure Configure_IO + (This : in out GPIO_Point; + Config : GPIO_Port_Configuration); + -- For Point.Pin on the Point.Port.all, configures the + -- characteristics specified by Config + + function Pin_IO_Mode (This : GPIO_Point) return Pin_IO_Modes with Inline; + + procedure Enable_Clock (Port : GPIO_Port); + procedure Enable_Clock (Point : GPIO_Point); + procedure Disable_Clock (Port : GPIO_Port); + procedure Disable_Clock (Point : GPIO_Point); + + type Interrupt_Trigger_Type is + (Any_Edge, Rising_Edge, Falling_Edge, Low, High); + + procedure Enable_Interrupt (This : GPIO_Point; + Trigger : Interrupt_Trigger_Type); + procedure Disable_Interrupt (This : GPIO_Point); + + function Read_Interrupt_Status (This : GPIO_Point) return Boolean; +private + + type GPIO_Port is new SAM_SVD.PIO.PIO_Peripheral; + + use System; + + Unknown_GPIO_Port : exception; + + function Group (Port : GPIO_Port) return GPIO_Group is + (if Port'Address = SAM_SVD.PIOA_Base then + A + elsif Port'Address = SAM_SVD.PIOB_Base then + B + elsif Port'Address = SAM_SVD.PIOC_Base then + C + elsif Port'Address = SAM_SVD.PIOD_Base then + D + elsif Port'Address = SAM_SVD.PIOE_Base then + E + else + raise Unknown_GPIO_Port); + +end SAM.GPIO; diff --git a/arch/ARM/SAM/drivers/sam-i2c.adb.hide.adb b/arch/ARM/SAM/drivers/sam-i2c.adb.hide.adb new file mode 100644 index 000000000..31869adda --- /dev/null +++ b/arch/ARM/SAM/drivers/sam-i2c.adb.hide.adb @@ -0,0 +1,187 @@ +with SAM.Device; + +with SAM_SVD.TWIHS; use SAM_SVD.TWIHS; + +package body SAM.I2C is + + I2C_FAST_MODE_SPEED : constant := 400_000; + LOW_LEVEL_TIME_LIMIT : constant := 384_000; + TWIHS_CLK_DIVIDER : constant := 2; + TWIHS_CLK_CALC_ARGU : constant := 3; + + --------------- + -- Configure -- + --------------- + + procedure Configure + (This : in out I2C_Port; + Conf : I2C_Configuration) + is + Status : SAM_SVD.TWIHS.TWIHS_TWIHS_SR_Register; + + Cl_Div, Ch_Div : UInt32; + + Ckdiv : UInt32 := 0; + begin + + -- disable twihs interrupts + This.Periph.TWIHS_IDR := (TXCOMP => True, + RXRDY => True, + TXRDY => True, + SVACC => True, + GACC => True, + OVRE => True, + UNRE => True, + NACK => True, + ARBLST => True, + SCL_WS => True, + EOSACC => True, + MCACK => True, + TOUT => True, + PECERR => True, + SMBDAM => True, + SMBHHM => True, + others => <>); + + -- dummy status register read + -- Status := This.Periph.TWIHS_SR; + + -- reset peripheral + This.Reset; + + -- enable master mode + This.Periph.TWIHS_CR.MSDIS := True; + This.Periph.TWIHS_CR.SVDIS := True; + + This.Periph.TWIHS_CR.MSEN := True; + + -- set clock speed + + -- fast mode can only be used in slave mode + if Conf.Clock_Speed > I2C_FAST_MODE_SPEED then + raise Program_Error with "Unsupported Clock Speed with configuration"; + end if; + + if Conf.Clock_Speed > LOW_LEVEL_TIME_LIMIT then + Cl_Div := SAM.Device.System_Clocks.MCK / + (LOW_LEVEL_TIME_LIMIT * TWIHS_CLK_DIVIDER) - TWIHS_CLK_CALC_ARGU; + Ch_Div := SAM.Device.System_Clocks.MCK / + ((Conf.Clock_Speed + + (Conf.Clock_Speed - LOW_LEVEL_TIME_LIMIT)) * + TWIHS_CLK_DIVIDER) - TWIHS_CLK_CALC_ARGU; + + while Cl_Div > UInt32 (TWIHS_TWIHS_CWGR_CLDIV_Field'Last) and + Ckdiv < UInt32 (TWIHS_TWIHS_CWGR_CKDIV_Field'Last) loop + Ckdiv := Ckdiv + 1; + Cl_Div := Cl_Div / TWIHS_CLK_DIVIDER; + end loop; + + while Ch_Div > UInt32 (TWIHS_TWIHS_CWGR_CHDIV_Field'Last) and + Ckdiv < UInt32 (TWIHS_TWIHS_CWGR_CKDIV_Field'Last) loop + Ckdiv := Ckdiv + 1; + Ch_Div := Ch_Div / TWIHS_CLK_DIVIDER; + end loop; + else + Cl_Div := SAM.Device.System_Clocks.MCK / + (Conf.Clock_Speed * TWIHS_CLK_DIVIDER) - TWIHS_CLK_CALC_ARGU; + + while Cl_Div > UInt32 (TWIHS_TWIHS_CWGR_CLDIV_Field'Last) and + Ckdiv < UInt32 (TWIHS_TWIHS_CWGR_CKDIV_Field'Last) loop + Ckdiv := Ckdiv + 1; + Cl_Div := Cl_Div / TWIHS_CLK_DIVIDER; + end loop; + + Ch_Div := Cl_Div; + end if; + + This.Periph.TWIHS_CWGR.CLDIV := UInt8 (Cl_Div); + This.Periph.TWIHS_CWGR.CHDIV := UInt8 (Ch_Div); + This.Periph.TWIHS_CWGR.CKDIV := UInt3 (Ckdiv); + + end Configure; + + --------------------- + -- Master_Transmit -- + --------------------- + + overriding procedure Master_Transmit + (This : in out I2C_Port; + Addr : HAL.I2C.I2C_Address; + Data : HAL.I2C.I2C_Data; + Status : out HAL.I2C.I2C_Status; + Timeout : Natural := 1000) + is + begin + -- Generated stub: replace with real body! + pragma Compile_Time_Warning (Standard.True, "Master_Transmit unimplemented"); + raise Program_Error with "Unimplemented procedure Master_Transmit"; + end Master_Transmit; + + -------------------- + -- Master_Receive -- + -------------------- + + overriding procedure Master_Receive + (This : in out I2C_Port; + Addr : HAL.I2C.I2C_Address; + Data : out HAL.I2C.I2C_Data; + Status : out HAL.I2C.I2C_Status; + Timeout : Natural := 1000) + is + begin + This.Periph.TWIHS_MMR.MREAD := 1; + This.Periph.TWIHS_MMR.IADRSZ := 1; + + case This.Config.Addressing_Mode is + when Addressing_Mode_7bit => + This.Periph.TWIHS_MMR.DADR := Addr; + when Addressing_Mode_10bit => + This.Periph.TWIHS_MMR.DADR := + end case; + end Master_Receive; + + --------------- + -- Mem_Write -- + --------------- + + overriding procedure Mem_Write + (This : in out I2C_Port; + Addr : HAL.I2C.I2C_Address; + Mem_Addr : UInt16; + Mem_Addr_Size : HAL.I2C.I2C_Memory_Address_Size; + Data : HAL.I2C.I2C_Data; + Status : out HAL.I2C.I2C_Status; + Timeout : Natural := 1000) + is + begin + -- Generated stub: replace with real body! + pragma Compile_Time_Warning (Standard.True, "Mem_Write unimplemented"); + raise Program_Error with "Unimplemented procedure Mem_Write"; + end Mem_Write; + + -------------- + -- Mem_Read -- + -------------- + + overriding procedure Mem_Read + (This : in out I2C_Port; + Addr : HAL.I2C.I2C_Address; + Mem_Addr : UInt16; + Mem_Addr_Size : HAL.I2C.I2C_Memory_Address_Size; + Data : out HAL.I2C.I2C_Data; + Status : out HAL.I2C.I2C_Status; + Timeout : Natural := 1000) + is + begin + -- Generated stub: replace with real body! + pragma Compile_Time_Warning (Standard.True, "Mem_Read unimplemented"); + raise Program_Error with "Unimplemented procedure Mem_Read"; + end Mem_Read; + + procedure Reset (This : in out I2C_Port) + is + begin + This.Periph.TWIHS_CR.SWRST := 1; + end Reset; + +end SAM.I2C; diff --git a/arch/ARM/SAM/drivers/sam-i2c.ads.hide.ads b/arch/ARM/SAM/drivers/sam-i2c.ads.hide.ads new file mode 100644 index 000000000..5eb02f9d6 --- /dev/null +++ b/arch/ARM/SAM/drivers/sam-i2c.ads.hide.ads @@ -0,0 +1,93 @@ +private with SAM_SVD.TWIHS; +with HAL.I2C; + +package SAM.I2C is + + type Internal_I2C_Port is private; + + type I2C_Port (Periph : not null access Internal_I2C_Port) is + limited new HAL.I2C.I2C_Port with private; + + type I2C_Device_Mode is + (I2C_Mode, + SMBusDevice_Mode, + SMBusHost_Mode); + + type I2C_Acknowledgement is (Ack_Disable, Ack_Enable); + + type I2C_Direction is (Transmitter, Receiver); + + type I2C_Addressing_Mode is + (Addressing_Mode_7bit, + Addressing_Mode_10bit); + + type I2C_Configuration is record + Clock_Speed : UInt32; + Mode : I2C_Device_Mode := I2C_Mode; + Addressing_Mode : I2C_Addressing_Mode; + end record; + + procedure Configure + (This : in out I2C_Port; + Conf : I2C_Configuration); + + + + overriding + procedure Master_Transmit + (This : in out I2C_Port; + Addr : HAL.I2C.I2C_Address; + Data : HAL.I2C.I2C_Data; + Status : out HAL.I2C.I2C_Status; + Timeout : Natural := 1000); + + overriding + procedure Master_Receive + (This : in out I2C_Port; + Addr : HAL.I2C.I2C_Address; + Data : out HAL.I2C.I2C_Data; + Status : out HAL.I2C.I2C_Status; + Timeout : Natural := 1000); + + overriding + procedure Mem_Write + (This : in out I2C_Port; + Addr : HAL.I2C.I2C_Address; + Mem_Addr : UInt16; + Mem_Addr_Size : HAL.I2C.I2C_Memory_Address_Size; + Data : HAL.I2C.I2C_Data; + Status : out HAL.I2C.I2C_Status; + Timeout : Natural := 1000); + + overriding + procedure Mem_Read + (This : in out I2C_Port; + Addr : HAL.I2C.I2C_Address; + Mem_Addr : UInt16; + Mem_Addr_Size : HAL.I2C.I2C_Memory_Address_Size; + Data : out HAL.I2C.I2C_Data; + Status : out HAL.I2C.I2C_Status; + Timeout : Natural := 1000); + +private + + type I2C_State is + (Reset, + Ready, + Master_Busy_Tx, + Master_Busy_Rx, + Mem_Busy_Tx, + Mem_Busy_Rx); + + type Internal_I2C_Port is new SAM_SVD.TWIHS.TWIHS_Peripheral; + + type I2C_Port (Periph : not null access Internal_I2C_Port) is + limited new HAL.I2C.I2C_Port with record + Config : I2C_Configuration; + State : I2C_State := Reset; + DMA_Enabled : Boolean := False; + end record; + + procedure Reset (This : in out I2C_Port); + +end SAM.I2C; diff --git a/arch/ARM/SAM/drivers/sam-pmc.adb b/arch/ARM/SAM/drivers/sam-pmc.adb new file mode 100644 index 000000000..334e17ad4 --- /dev/null +++ b/arch/ARM/SAM/drivers/sam-pmc.adb @@ -0,0 +1,279 @@ +with SAM_SVD.PMC; use SAM_SVD.PMC; +with SAM_SVD.SUPC; use SAM_SVD.SUPC; + +package body SAM.PMC is + + procedure Configure_Peripheral (ID : Natural; + Enable : Boolean) + is + begin + Disable_Peripheral (ID => ID); + -- TODO: configure gclk or periph_clk + if Enable then + Enable_Peripheral (ID => ID); + end if; + end Configure_Peripheral; + + procedure Enable_Peripheral (ID : Natural) + is + PCR_Reg : PMC_PMC_PCR_Register := PMC_Periph.PMC_PCR; + begin + PCR_Reg.PID := UInt7 (ID); + PCR_Reg.CMD := True; + PCR_Reg.EN := True; + + PMC_Periph.PMC_PCR := PCR_Reg; + end Enable_Peripheral; + + procedure Disable_Peripheral (ID : Natural) + is + PCR_Reg : PMC_PMC_PCR_Register := PMC_Periph.PMC_PCR; + begin + PCR_Reg.PID := UInt7 (ID); + PCR_Reg.CMD := True; + PCR_Reg.EN := False; + + PMC_Periph.PMC_PCR := PCR_Reg; + end Disable_Peripheral; + + procedure Enable_Peripheral_Clock (ID : Natural) + is + begin + if ID < 32 then + PMC_Periph.PMC_PCER0.PID.Arr (ID) := True; + elsif ID < 37 then + PMC_Periph.PMC_PCER1.PID.Arr (ID) := True; + elsif ID = 37 then + PMC_Periph.PMC_PCER1.PID37 := True; + elsif ID < 53 then + PMC_Periph.PMC_PCER1.PID_1.Arr (ID) := True; + else + PMC_Periph.PMC_PCER1.PID_2.Arr (ID) := True; + end if; + end Enable_Peripheral_Clock; + + procedure Disable_Peripheral_Clock (ID : Natural) + is + begin + if ID < 32 then + PMC_Periph.PMC_PCDR0.PID.Arr (ID) := True; + elsif ID < 37 then + PMC_Periph.PMC_PCDR1.PID.Arr (ID) := True; + elsif ID = 37 then + PMC_Periph.PMC_PCDR1.PID37 := True; + elsif ID < 53 then + PMC_Periph.PMC_PCDR1.PID_1.Arr (ID) := True; + else + PMC_Periph.PMC_PCDR1.PID_2.Arr (ID) := True; + end if; + end Disable_Peripheral_Clock; + + function Get_Peripheral_Clock (ID : Natural) return UInt32 + is + begin + if ID = UART0_ID or ID = UART1_ID or ID = UART2_ID or ID = UART3_ID or + ID = UART4_ID or ID = USART0_ID or ID = USART1_ID or ID = USART2_ID + then + return System_Clocks.PCK (4); + elsif ID = MCAN0_INT0_ID or ID = MCAN0_INT1_ID or ID = MCAN1_INT0_ID or + ID = MCAN1_INT1_ID + then + return System_Clocks.PCK (5); + elsif ID = TC1_CHANNEL0_ID or ID = TC1_CHANNEL1_ID or + ID = TC1_CHANNEL2_ID or ID = TC2_CHANNEL0_ID or ID = TC2_CHANNEL1_ID or + ID = TC2_CHANNEL2_ID or ID = TC3_CHANNEL0_ID or ID = TC3_CHANNEL1_ID or + ID = TC3_CHANNEL2_ID + then + return System_Clocks.PCK (6); + elsif ID = TC0_CHANNEL0_ID or ID = TC0_CHANNEL1_ID or + ID = TC0_CHANNEL2_ID + then + return System_Clocks.PCK (7); + elsif ID = I2SC0_ID or ID = I2SC1_ID then + return Get_GCLK (PID => UInt7 (ID)); + else + return System_Clocks.MCK; + end if; + + end Get_Peripheral_Clock; + + function Calc_PLLACK_Div return UInt32 + is + Div : constant UInt32 := UInt32 (PMC_Periph.CKGR_PLLAR.DIVA); + Mul : constant UInt32 := UInt32 (PMC_Periph.CKGR_PLLAR.MULA); + begin + if Div = 0 or Mul = 0 then + return 0; + end if; + + return ((Mul + 1) / Div); + end Calc_PLLACK_Div; + + function Calc_FCLK (In_Clk : UInt32) return UInt32 + is + Ret : UInt32; + begin + case PMC_Periph.PMC_MCKR.PRES is + when Clk_1 => + Ret := In_Clk / 1; + when Clk_2 => + Ret := In_Clk / 2; + when Clk_4 => + Ret := In_Clk / 4; + when Clk_8 => + Ret := In_Clk / 8; + when Clk_16 => + Ret := In_Clk / 16; + when Clk_32 => + Ret := In_Clk / 32; + when Clk_64 => + Ret := In_Clk / 64; + when Clk_3 => + Ret := In_Clk / 3; + end case; + + return Ret; + end Calc_FCLK; + + function Calc_USB_FS (Clocks : System_Clock_Map) return UInt32 + is + Clk : UInt32; + Div : constant UInt32 := UInt32 (PMC_Periph.PMC_USB.USBDIV) + 1; + begin + if not PMC_Periph.PMC_USB.USBS then + -- PLLA source + Clk := Clocks.PLLACK; + else + -- UPLL source + Clk := Clocks.UPLLCKDIV; + end if; + return (Clk / Div); + end Calc_USB_FS; + + function Calc_PCKx (X : Natural; + Clocks : System_Clock_Map) + return UInt32 + is + Clk : UInt32; + Pres : constant UInt32 := UInt32 (PMC_Periph.PMC_PCK (X).PRES) + 1; + begin + case PMC_Periph.PMC_PCK (X).CSS is + when Slow_Clk => + Clk := Clocks.SLCK; + when Main_Clk => + Clk := Clocks.MAINCK; + when Plla_Clk => + Clk := Clocks.PLLACK; + when Upll_Clk => + Clk := Clocks.UPLLCKDIV; + when Mck => + Clk := Clocks.MCK; + end case; + + return (Clk / Pres); + end Calc_PCKx; + + function Get_UPLLDIV2_Value return UInt32 + is (if PMC_Periph.PMC_MCKR.UPLLDIV2 then 2 else 1); + + function System_Clocks return System_Clock_Map + is + Clocks : System_Clock_Map; + begin + -- calculate SLOW_CLK + case SUPC_Periph.SUPC_SR.OSCSEL is + when Rc => + Clocks.SLCK := Slow_RC_Osc; + when Cryst => + Clocks.SLCK := Crystal_Osc_32k768; + end case; + + -- calculate MAINCK + if not PMC_Periph.CKGR_MOR.MOSCSEL then + -- main RC osc + case PMC_Periph.CKGR_MOR.MOSCRCF is + when Val_4_Mhz => + Clocks.MAINCK := 4_000_000; + when Val_8_Mhz => + Clocks.MAINCK := 8_000_000; + when Val_12_Mhz => + Clocks.MAINCK := 12_000_000; + end case; + else + -- main crystal osc + Clocks.MAINCK := Crystal_Osc_Main; + end if; + + -- calculate PLLACK + Clocks.PLLACK := Calc_PLLACK_Div * Clocks.MAINCK; + + -- calculate UTMI PLL + Clocks.UPLLCK := UPLLCK_480MHz; + Clocks.UPLLCKDIV := Clocks.UPLLCK / + (Get_UPLLDIV2_Value + 1); + + -- calc MCK & FCLK + case PMC_Periph.PMC_MCKR.CSS is + when Slow_Clk => + Clocks.FCLK := Calc_FCLK (In_Clk => Clocks.SLCK); + when Main_Clk => + Clocks.FCLK := Calc_FCLK (In_Clk => Clocks.MAINCK); + when Plla_Clk => + Clocks.FCLK := Calc_FCLK (In_Clk => Clocks.PLLACK); + when Upll_Clk => + Clocks.FCLK := Calc_FCLK (In_Clk => Clocks.UPLLCKDIV); + end case; + + case PMC_Periph.PMC_MCKR.MDIV is + when Eq_Pck => + Clocks.MCK := Clocks.FCLK / 1; + when Pck_Div2 => + Clocks.MCK := Clocks.FCLK / 2; + when Pck_Div4 => + Clocks.MCK := Clocks.FCLK / 4; + when Pck_Div3 => + Clocks.MCK := Clocks.FCLK / 3; + end case; + + Clocks.HCLK := Clocks.FCLK; + Clocks.SysTick := Clocks.FCLK / 8; + Clocks.USBCLK := Calc_USB_FS (Clocks => Clocks); + + for I in Clocks.PCK'Range loop + Clocks.PCK (I) := Calc_PCKx (X => I, + Clocks => Clocks); + end loop; + + Clocks.USBHS := Clocks.UPLLCK; + + return Clocks; + + end System_Clocks; + + function Get_GCLK (PID : HAL.UInt7) return UInt32 + is + Div : UInt32; + Clk : UInt32; + begin + PMC_Periph.PMC_PCR := (PID => PID, + CMD => False, + others => <>); + + Div := UInt32 (PMC_Periph.PMC_PCR.GCLKDIV) + 1; + case PMC_Periph.PMC_PCR.GCLKCSS is + when Slow_Clk => + Clk := System_Clocks.SLCK; + when Main_Clk => + Clk := System_Clocks.MAINCK; + when Plla_Clk => + Clk := System_Clocks.PLLACK; + when Upll_Clk => + Clk := System_Clocks.UPLLCKDIV; + when Mck_Clk => + Clk := System_Clocks.MCK; + end case; + + return (Clk / Div); + end Get_GCLK; + +end SAM.PMC; diff --git a/arch/ARM/SAM/drivers/sam-pmc.ads b/arch/ARM/SAM/drivers/sam-pmc.ads new file mode 100644 index 000000000..a05347724 --- /dev/null +++ b/arch/ARM/SAM/drivers/sam-pmc.ads @@ -0,0 +1,61 @@ +package SAM.PMC is + + procedure Configure_Peripheral (ID : Natural; + Enable : Boolean); + + procedure Enable_Peripheral (ID : Natural); + + procedure Disable_Peripheral (ID : Natural); + + procedure Enable_Peripheral_Clock (ID : Natural); + procedure Disable_Peripheral_Clock (ID : Natural); + + function Get_Peripheral_Clock (ID : Natural) return UInt32; + + type Peripheral_Clock_Array is array (0 .. 7) of UInt32; + + type System_Clock_Map is record + MAINCK : UInt32 := 0; -- Main CLock + SLCK : UInt32 := 0; -- Slow Clock + PLLACK : UInt32 := 0; -- PLLA Clock + UPLLCK : UInt32 := 0; -- UPLL Clock + UPLLCKDIV : UInt32 := 0; -- UPLL after divider Clock + MCK : UInt32 := 0; -- Master Clock + SysTick : UInt32 := 0; -- SysTick External Clock + HCLK : UInt32 := 0; -- Processor Clock + FCLK : UInt32 := 0; -- Free Running Clock + USBCLK : UInt32 := 0; -- USB FS Clock + USBHS : UInt32 := 0; -- USB HS Clock + PCK : Peripheral_Clock_Array := (others => 0); + end record; + + function System_Clocks return System_Clock_Map; + +private + + Slow_RC_Osc : constant := 32_768; + Crystal_Osc_32k768 : constant := 32_768; + + Crystal_Osc_Main : constant := 12_000_000; + + UPLLCK_480MHz : constant := 480_000_000; + + type GCLK_Source is + (SLCK, MAINCK, UPLLCKDIV, PLLACK, MCK); + + type GCLK_Divider is range 1 .. 256; + + function Calc_PLLACK_Div return UInt32; + function Calc_FCLK (In_Clk : UInt32) return UInt32; + function Calc_USB_FS (Clocks : System_Clock_Map) return UInt32; + function Calc_PCKx (X : Natural; + Clocks : System_Clock_Map) + return UInt32; + +-- procedure Set_GCLK (PID : UInt7; +-- Src : GCLK_Source; +-- Div : GCLK_Divider); + + function Get_GCLK (PID : UInt7) return UInt32; + +end SAM.PMC; diff --git a/arch/ARM/SAM/drivers/sam-spi.adb b/arch/ARM/SAM/drivers/sam-spi.adb new file mode 100644 index 000000000..36c8f0ff3 --- /dev/null +++ b/arch/ARM/SAM/drivers/sam-spi.adb @@ -0,0 +1,568 @@ +with SAM_SVD.SPI; use SAM_SVD.SPI; + +with SAM.PMC; + +with System; + +package body SAM.SPI is + + procedure Configure (This : in out SPI_Port; + Cfg : Configuration) + is + begin + Enable_Clock (This => This); + Unlock_Write_Protection (This => This); + Disable (This => This); + Reset (This => This); + + Set_Mode (This => This, + Md => Cfg.Md); + + Set_Variable_Peripheral_Select_Mode (This => This, + Enable => Cfg.Variable_Peripheral); + Set_Peripheral_Select_Decode (This => This, + Enable => Cfg.Select_Decode); + if not Cfg.Variable_Peripheral then + if not Cfg.Select_Decode then + Set_Peripheral_Chip_Select_Value (This => This, + Value => + Get_PCS (NPCS => This.CS)); + else + Set_Peripheral_Chip_Select_Value (This => This, + Value => UInt4 (This.CS)); + end if; + end if; + Set_Fault_Detect_Mode (This => This, + Enable => Cfg.Fault_Detect); + Set_Tx_On_Rx_Empty (This => This, + Enable => Cfg.Tx_On_Rx_Empty); + Set_Delay_Between_Chip_Select (This => This, + Value => Cfg.Dly_Btw_Cs); + Set_Clock_Polarity (This => This, + Pol => Cfg.Clk_Pol); + Set_Clock_Phase (This => This, + Phase => Cfg.Clk_Phase); + Configure_Cs_Behavior (This => This, + Behavior => Cfg.Cs_Beh); + Set_Bits_Per_Transfer (This => This, + Size => Cfg.BPT); + Set_Transfer_Delay (This => This, + Delay_Before_SPCK => Cfg.Dly_SPCK, + Delay_Between_Transfers => Cfg.Dly_Btw_Transfers); + Set_Baudrate (This => This, + Bitrate => Cfg.Baud); + Enable (This => This); + + end Configure; + + overriding + function Data_Size (This : SPI_Port) return HAL.SPI.SPI_Data_Size + is + Size : constant SPI_CSR_BITS_Field := + This.Periph.SPI_CSR (Integer (This.CS)).BITS; + begin + case Size is + when SAM_SVD.SPI.Val_8_Bit => + return HAL.SPI.Data_Size_8b; + when SAM_SVD.SPI.Val_16_Bit => + return HAL.SPI.Data_Size_16b; + when others => + null; + end case; + + -- EXECUTION FLOW CAN'T REACH HERE + raise Program_Error with "Unsupported Data Size"; + return HAL.SPI.Data_Size_8b; + end Data_Size; + + function Poll_For_TX_Ready (This : SPI_Port; + Timeout : Natural) + return Boolean + is + begin + for I in 1 .. Timeout loop + if Is_Tx_Ready (This => This) then + return True; + end if; + end loop; + + -- if execution gets here there was a timeout + return False; + end Poll_For_TX_Ready; + + overriding + procedure Transmit + (This : in out SPI_Port; + Data : HAL.SPI.SPI_Data_8b; + Status : out HAL.SPI.SPI_Status; + Timeout : Natural := SPI_Timeout) + is + PCS : UInt4; + begin + if not This.Periph.SPI_MR.PCSDEC then + PCS := Get_PCS (NPCS => This.CS); + else + PCS := UInt4 (This.CS); + end if; + + for I in Data'Range loop + if not Poll_For_TX_Ready (This => This, + Timeout => Timeout) + then + Status := HAL.SPI.Err_Timeout; + return; + end if; + + This.Periph.SPI_TDR := (TD => SPI_SPI_TDR_TD_Field (Data (I)), + PCS => PCS, + others => <>); + end loop; + This.Periph.SPI_CR.LASTXFER := True; + Status := HAL.SPI.Ok; + end Transmit; + + overriding + procedure Transmit + (This : in out SPI_Port; + Data : HAL.SPI.SPI_Data_16b; + Status : out HAL.SPI.SPI_Status; + Timeout : Natural := SPI_Timeout) + is + PCS : UInt4; + begin + if not This.Periph.SPI_MR.PCSDEC then + PCS := Get_PCS (NPCS => This.CS); + else + PCS := UInt4 (This.CS); + end if; + + for I in Data'Range loop + if not Poll_For_TX_Ready (This => This, + Timeout => Timeout) + then + Status := HAL.SPI.Err_Timeout; + return; + end if; + + This.Periph.SPI_TDR := (TD => SPI_SPI_TDR_TD_Field (Data (I)), + PCS => PCS, + others => <>); + end loop; + This.Periph.SPI_CR.LASTXFER := True; + Status := HAL.SPI.Ok; + end Transmit; + + function Poll_For_RX_Ready (This : SPI_Port; + Timeout : Natural) + return Boolean + is + begin + for I in 1 .. Timeout loop + if Is_Rx_Full (This => This) then + return True; + end if; + end loop; + + -- if execution gets here there was a timeout + return False; + end Poll_For_RX_Ready; + + overriding + procedure Receive + (This : in out SPI_Port; + Data : out HAL.SPI.SPI_Data_8b; + Status : out HAL.SPI.SPI_Status; + Timeout : Natural := SPI_Timeout) + is + begin + for I in Data'Range loop + if not Poll_For_RX_Ready (This => This, + Timeout => Timeout) + then + Status := HAL.SPI.Err_Timeout; + return; + end if; + Data (I) := HAL.UInt8 (This.Periph.SPI_RDR.RD); + end loop; + + Status := HAL.SPI.Ok; + end Receive; + + overriding + procedure Receive + (This : in out SPI_Port; + Data : out HAL.SPI.SPI_Data_16b; + Status : out HAL.SPI.SPI_Status; + Timeout : Natural := SPI_Timeout) + is + begin + for I in Data'Range loop + if not Poll_For_RX_Ready (This => This, + Timeout => Timeout) + then + Status := HAL.SPI.Err_Timeout; + return; + end if; + Data (I) := HAL.UInt16 (This.Periph.SPI_RDR.RD); + end loop; + + Status := HAL.SPI.Ok; + end Receive; + + overriding + procedure Transfer + (This : in out SPI_Port; + Tx_Data : HAL.SPI.SPI_Data_8b; + Rx_Data : out HAL.SPI.SPI_Data_8b; + Status : out HAL.SPI.SPI_Status; + Timeout : Natural := SPI_Timeout) + is + PCS : UInt4; + begin + if not This.Periph.SPI_MR.PCSDEC then + PCS := Get_PCS (NPCS => This.CS); + else + PCS := UInt4 (This.CS); + end if; + + -- Clear any pending RX's + if This.Poll_For_RX_Ready (Timeout => 10) then + Rx_Data (Rx_Data'First) := HAL.UInt8 (This.Periph.SPI_RDR.RD); + end if; + + for I in Tx_Data'Range loop + declare + Tx : HAL.SPI.SPI_Data_8b (1 .. 1) + with Address => Tx_Data (I)'Address; + Rx : HAL.SPI.SPI_Data_8b (1 .. 1) + with Address => Rx_Data (I)'Address; + + use HAL.SPI; + begin +-- This.Transmit (Data => Tx, +-- Status => Status, +-- Timeout => Timeout); +-- if Status /= Ok then +-- return; +-- end if; + + if not Poll_For_TX_Ready (This => This, + Timeout => Timeout) + then + Status := HAL.SPI.Err_Timeout; + return; + end if; + + This.Periph.SPI_TDR := (TD => SPI_SPI_TDR_TD_Field (Tx (1)), + PCS => PCS, + others => <>); + + This.Receive (Data => Rx, + Status => Status, + Timeout => Timeout); + if Status /= Ok then + return; + end if; + end; + end loop; + This.Periph.SPI_CR.LASTXFER := True; + end Transfer; + + ------------ + -- Enable -- + ------------ + + procedure Enable (This : in out SPI_Port) + is + begin + This.Periph.SPI_CR.SPIEN := True; + end Enable; + + ------------- + -- Disable -- + ------------- + + procedure Disable (This : in out SPI_Port) + is + begin + This.Periph.SPI_CR.SPIDIS := True; + end Disable; + + function Enabled (This : SPI_Port) return Boolean + is + begin + return (This.Periph.SPI_SR.SPIENS); + end Enabled; + + ----------- + -- Reset -- + ----------- + + procedure Reset (This : in out SPI_Port) + is + begin + This.Periph.SPI_CR.SWRST := True; + end Reset; + + procedure Set_Mode (This : in out SPI_Port; + Md : Mode) + is + begin + case Md is + when Master => + Set_Last_Xfer (This => This); + This.Periph.SPI_MR.MSTR := True; + when Slave => + This.Periph.SPI_MR.MSTR := False; + end case; + end Set_Mode; + + function Get_Mode (This : SPI_Port) return Mode + is + Ret : Mode; + begin + if This.Periph.SPI_MR.MSTR then + Ret := Master; + else + Ret := Slave; + end if; + + return Ret; + end Get_Mode; + + procedure Set_Variable_Peripheral_Select_Mode (This : in out SPI_Port; + Enable : Boolean) + is + begin + This.Periph.SPI_MR.PS := Enable; + end Set_Variable_Peripheral_Select_Mode; + + function Get_Variable_Peripheral_Select_Mode (This : SPI_Port) + return Boolean + is + begin + return (This.Periph.SPI_MR.PS); + end Get_Variable_Peripheral_Select_Mode; + + procedure Set_Peripheral_Select_Decode (This : in out SPI_Port; + Enable : Boolean) + is + begin + if Enable then + raise Program_Error with "Select decoding is not currently supported"; +-- This.Periph.SPI_MR.PCSDEC := 1; + else + This.Periph.SPI_MR.PCSDEC := False; + end if; + end Set_Peripheral_Select_Decode; + + function Get_Peripheral_Select_Decode (This : SPI_Port) + return Boolean + is + begin + return (This.Periph.SPI_MR.PCSDEC); + end Get_Peripheral_Select_Decode; + + procedure Set_Fault_Detect_Mode (This : in out SPI_Port; + Enable : Boolean) + is + begin + This.Periph.SPI_MR.MODFDIS := Enable; + end Set_Fault_Detect_Mode; + + function Get_Fault_Detect_Mode (This : SPI_Port) return Boolean + is + begin + return (This.Periph.SPI_MR.MODFDIS); + end Get_Fault_Detect_Mode; + + procedure Set_Tx_On_Rx_Empty (This : in out SPI_Port; + Enable : Boolean) + is + begin + This.Periph.SPI_MR.WDRBT := Enable; + end Set_Tx_On_Rx_Empty; + + function Get_Tx_In_Rx_Empty (This : SPI_Port) return Boolean + is + begin + return (This.Periph.SPI_MR.WDRBT); + end Get_Tx_In_Rx_Empty; + + procedure Set_Loopback (This : in out SPI_Port; + Enable : Boolean) + is + begin + This.Periph.SPI_MR.LLB := Enable; + end Set_Loopback; + + procedure Set_Clock_Polarity (This : in out SPI_Port; + Pol : Clock_Polarity) + is + begin + case Pol is + when Default_Hi => + This.Periph.SPI_CSR (Integer (This.CS)).CPOL := True; + when Default_Lo => + This.Periph.SPI_CSR (Integer (This.CS)).CPOL := False; + end case; + end Set_Clock_Polarity; + + procedure Set_Clock_Phase (This : in out SPI_Port; + Phase : Clock_Phase) + is + begin + case Phase is + when Cap_Rising => + This.Periph.SPI_CSR (Integer (This.CS)).NCPHA := True; + when Cap_Falling => + This.Periph.SPI_CSR (Integer (This.CS)).NCPHA := False; + end case; + end Set_Clock_Phase; + + procedure Configure_Cs_Behavior (This : in out SPI_Port; + Behavior : Cs_Behavior) + is + begin + case Behavior is + when Keep_Low => + This.Periph.SPI_CSR (Integer (This.CS)).CSAAT := True; + when Rise_No_Tx => + This.Periph.SPI_CSR (Integer (This.CS)).CSAAT := False; + This.Periph.SPI_CSR (Integer (This.CS)).CSNAAT := False; + when Rise_Forced => + This.Periph.SPI_CSR (Integer (This.CS)).CSAAT := False; + This.Periph.SPI_CSR (Integer (This.CS)).CSNAAT := True; + end case; + end Configure_Cs_Behavior; + + procedure Set_Bits_Per_Transfer (This : in out SPI_Port; + Size : HAL.SPI.SPI_Data_Size) + is + begin + case Size is + when HAL.SPI.Data_Size_8b => + This.Periph.SPI_CSR (Integer (This.CS)).BITS := Val_8_Bit; + when HAL.SPI.Data_Size_16b => + This.Periph.SPI_CSR (Integer (This.CS)).BITS := Val_16_Bit; + end case; + end Set_Bits_Per_Transfer; + + procedure Set_Transfer_Delay (This : in out SPI_Port; + Delay_Before_SPCK : Delay_Type; + Delay_Between_Transfers : Delay_Type) + is + begin + This.Periph.SPI_CSR (Integer (This.CS)).DLYBS := + SPI_SPI_CSR_DLYBS_Field (Delay_Before_SPCK); + This.Periph.SPI_CSR (Integer (This.CS)).DLYBCT := + SPI_SPI_CSR_DLYBCT_Field (Delay_Between_Transfers); + end Set_Transfer_Delay; + + procedure Set_Baudrate (This : in out SPI_Port; + Bitrate : UInt32) + is + MCK : constant UInt32 := SAM.PMC.System_Clocks.MCK; + SCBR : constant UInt32 := MCK / Bitrate; + begin + if SCBR = 0 then + raise Program_Error; + end if; + + if SCBR > UInt32 (UInt8'Last) then + raise Program_Error; + end if; + + This.Periph.SPI_CSR (Integer (This.CS)).SCBR := + UInt8 (SCBR); + end Set_Baudrate; + + procedure Set_Last_Xfer (This : in out SPI_Port) + is + begin + This.Periph.SPI_CR.LASTXFER := True; + end Set_Last_Xfer; + + procedure Set_Peripheral_Chip_Select_Value (This : in out SPI_Port; + Value : UInt4) + is + begin + This.Periph.SPI_MR.PCS := Value; + end Set_Peripheral_Chip_Select_Value; + + procedure Set_Delay_Between_Chip_Select (This : in out SPI_Port; + Value : Delay_Type) + is + begin + This.Periph.SPI_MR.DLYBCS := SPI_SPI_MR_DLYBCS_Field (Value); + end Set_Delay_Between_Chip_Select; + + function Calculate_Baud_Divider (Baud : Natural; + Mck : Natural) + return Divider_Type + is + Ret_Pre : Natural; + begin + Ret_Pre := Div_Ceil (Lhs => Mck, + Rhs => Baud); + if Ret_Pre > Natural (Divider_Type'Last) then + return Divider_Type'Last; + end if; + + return Divider_Type (Ret_Pre); + end Calculate_Baud_Divider; + + function Div_Ceil (Lhs, Rhs : Natural) return Natural + is + begin + return (1 + ((Lhs - 1) / Rhs)); + end Div_Ceil; + + procedure Enable_Clock (This : SPI_Port) + is + use System; + begin + if This.Periph.all'Address = SPI0_Base then + SAM.PMC.Enable_Peripheral_Clock (ID => SPI0_ID); + elsif This.Periph.all'Address = SPI1_Base then + SAM.PMC.Enable_Peripheral_Clock (ID => SPI1_ID); + else + raise Unknown_Port; + end if; + end Enable_Clock; + + + procedure Disable_Clock (This : SPI_Port) + is + use System; + begin + if This.Periph.all'Address = SPI0_Base then + SAM.PMC.Disable_Peripheral_Clock (ID => SPI0_ID); + elsif This.Periph.all'Address = SPI1_Base then + SAM.PMC.Disable_Peripheral_Clock (ID => SPI1_ID); + else + raise Unknown_Port; + end if; + end Disable_Clock; + + procedure Unlock_Write_Protection (This : in out SPI_Port) + is + begin + This.Periph.SPI_WPMR := (WPEN => False, + WPITEN => False, + WPCREN => False, + WPKEY => Passwd, + others => <>); + end Unlock_Write_Protection; + + procedure Lock_Write_Protection (This : in out SPI_Port) + is + begin + This.Periph.SPI_WPMR := (WPEN => True, + WPITEN => True, + WPCREN => True, + WPKEY => Passwd, + others => <>); + end Lock_Write_Protection; + +end SAM.SPI; diff --git a/arch/ARM/SAM/drivers/sam-spi.ads b/arch/ARM/SAM/drivers/sam-spi.ads new file mode 100644 index 000000000..1b940b779 --- /dev/null +++ b/arch/ARM/SAM/drivers/sam-spi.ads @@ -0,0 +1,226 @@ +private with SAM_SVD.SPI; + +with HAL.SPI; + +package SAM.SPI is + + SPI_Timeout : constant := 15000; + + type Chip_Select is new Integer range 0 .. 3 + with Size => 4; + + type Chip_Select_List is array (Integer range <>) of Chip_Select; + + type Internal_SPI_Port is private; + + type SPI_Port (Periph : not null access Internal_SPI_Port; + CS : Chip_Select) is + limited new HAL.SPI.SPI_Port with private; + + Unknown_Port : exception; + + type Mode is + (Master, Slave); + + type Delay_Type is new Natural range 0 .. 255; + + type Clock_Polarity is + (Default_Hi, Default_Lo); + + type Clock_Phase is + (Cap_Rising, Cap_Falling); + + -- SPI Chip Select behavior modes while transferring. + type Cs_Behavior is + (Keep_Low, -- CS does not rise until a new transfer is requested on different chip select + Rise_No_Tx, -- CS rises if there is no more data to transfer + Rise_Forced); -- CS is de-asserted systematically during a time DLYBCS. + + type Divider_Type is new Natural range 0 .. 255; + + type Configuration is record + Md : Mode := Master; + Variable_Peripheral : Boolean := False; + Select_Decode : Boolean := False; + Fault_Detect : Boolean := False; + Tx_On_Rx_Empty : Boolean := False; + Dly_Btw_Cs : Delay_Type := 6; + Clk_Pol : Clock_Polarity := Default_Lo; + Clk_Phase : Clock_Phase := Cap_Rising; + Cs_Beh : Cs_Behavior := Rise_No_Tx; + BPT : HAL.SPI.SPI_Data_Size := HAL.SPI.Data_Size_8b; + Dly_SPCK : Delay_Type := 0; + Dly_Btw_Transfers : Delay_Type := 0; + Baud : UInt32 := 1; + end record; + + procedure Configure (This : in out SPI_Port; + Cfg : Configuration); + + -- Enable SPI. + procedure Enable (This : in out SPI_Port) + with Inline; + + function Enabled (This : SPI_Port) return Boolean; + + -- Disable SPI + procedure Disable (This : in out SPI_Port) + with Inline; + + -- Reset SPI and set it to Slave mode + procedure Reset (This : in out SPI_Port) + with Inline; + + -- Set SPI to Master or Slave mode + procedure Set_Mode (This : in out SPI_Port; + Md : Mode); + + -- Get SPI work mode. + function Get_Mode (This : SPI_Port) return Mode; + + -- Set Peripheral Select mode. + -- Peripheral Chip Select can be controlled by SPI_TDR or SPI_MR. + procedure Set_Variable_Peripheral_Select_Mode (This : in out SPI_Port; + Enable : Boolean); + + -- Get Peripheral Select mode. + function Get_Variable_Peripheral_Select_Mode (This : SPI_Port) + return Boolean; + + procedure Set_Peripheral_Select_Decode (This : in out SPI_Port; + Enable : Boolean); + + function Get_Peripheral_Select_Decode (This : SPI_Port) + return Boolean; + + procedure Set_Fault_Detect_Mode (This : in out SPI_Port; + Enable : Boolean); + + function Get_Fault_Detect_Mode (This : SPI_Port) return Boolean; + + procedure Set_Tx_On_Rx_Empty (This : in out SPI_Port; + Enable : Boolean); + + function Get_Tx_In_Rx_Empty (This : SPI_Port) return Boolean; + + procedure Set_Delay_Between_Chip_Select (This : in out SPI_Port; + Value : Delay_Type); + + procedure Set_Loopback (This : in out SPI_Port; + Enable : Boolean); + + procedure Set_Clock_Polarity (This : in out SPI_Port; + Pol : Clock_Polarity); + + procedure Set_Clock_Phase (This : in out SPI_Port; + Phase : Clock_Phase); + + procedure Configure_Cs_Behavior (This : in out SPI_Port; + Behavior : Cs_Behavior); + + procedure Set_Bits_Per_Transfer (This : in out SPI_Port; + Size : HAL.SPI.SPI_Data_Size); + + procedure Set_Transfer_Delay (This : in out SPI_Port; + Delay_Before_SPCK : Delay_Type; + Delay_Between_Transfers : Delay_Type); + + procedure Set_Baudrate (This : in out SPI_Port; + Bitrate : UInt32) + with Pre => Bitrate /= 0; + + overriding + function Data_Size (This : SPI_Port) return HAL.SPI.SPI_Data_Size; + + overriding + procedure Transmit + (This : in out SPI_Port; + Data : HAL.SPI.SPI_Data_8b; + Status : out HAL.SPI.SPI_Status; + Timeout : Natural := SPI_Timeout); + + overriding + procedure Transmit + (This : in out SPI_Port; + Data : HAL.SPI.SPI_Data_16b; + Status : out HAL.SPI.SPI_Status; + Timeout : Natural := SPI_Timeout); + + overriding + procedure Receive + (This : in out SPI_Port; + Data : out HAL.SPI.SPI_Data_8b; + Status : out HAL.SPI.SPI_Status; + Timeout : Natural := SPI_Timeout); + + overriding + procedure Receive + (This : in out SPI_Port; + Data : out HAL.SPI.SPI_Data_16b; + Status : out HAL.SPI.SPI_Status; + Timeout : Natural := SPI_Timeout); + + overriding + procedure Transfer + (This : in out SPI_Port; + Tx_Data : HAL.SPI.SPI_Data_8b; + Rx_Data : out HAL.SPI.SPI_Data_8b; + Status : out HAL.SPI.SPI_Status; + Timeout : Natural := SPI_Timeout); + + procedure Enable_Clock (This : SPI_Port); + procedure Disable_Clock (This : SPI_Port); + +private + + use SAM_SVD; + + WPKEY : constant := 16#535049#; + + type Internal_SPI_Port is new SAM_SVD.SPI.SPI_Peripheral; + + type SPI_Port (Periph : not null access Internal_SPI_Port; + CS : Chip_Select) is + limited new HAL.SPI.SPI_Port with null record; + + -- Issue a LASTXFER command. + -- The next transfer is the last transfer and after that CS is de-asserted. + procedure Set_Last_Xfer (This : in out SPI_Port) + with Inline; + + procedure Set_Peripheral_Chip_Select_Value (This : in out SPI_Port; + Value : UInt4); + + function Get_PCS (NPCS : Chip_Select) return UInt4 is + ((2 ** Natural (NPCS)) - 1); + + function Is_Tx_Empty (This : SPI_Port) return Boolean is + (This.Periph.SPI_SR.TXEMPTY); + + function Is_Tx_Ready (This : SPI_Port) return Boolean is + (This.Periph.SPI_SR.TDRE); + + function Is_Rx_Full (This : SPI_Port) return Boolean is + (This.Periph.SPI_SR.RDRF); + + function Is_Rx_Ready (This : SPI_Port) return Boolean is + (Is_Tx_Empty (This) and then Is_Rx_Full (This)); + + function Calculate_Baud_Divider (Baud : Natural; + Mck : Natural) + return Divider_Type; + + function Div_Ceil (Lhs, Rhs : Natural) return Natural; + + function Poll_For_TX_Ready (This : SPI_Port; + Timeout : Natural) + return Boolean; + + function Poll_For_RX_Ready (This : SPI_Port; + Timeout : Natural) + return Boolean; + + procedure Unlock_Write_Protection (This : in out SPI_Port); + procedure Lock_Write_Protection (This : in out SPI_Port); + +end SAM.SPI; diff --git a/arch/ARM/SAM/drivers/sam.ads b/arch/ARM/SAM/drivers/sam.ads new file mode 100644 index 000000000..cc61f11e5 --- /dev/null +++ b/arch/ARM/SAM/drivers/sam.ads @@ -0,0 +1,85 @@ +pragma Warnings (Off); +with Interfaces; use Interfaces; +with HAL; use HAL; +pragma Warnings (On); + +package SAM is + pragma Pure; + + -- Peripheral Identifiers + SUPC_ID : constant := 0; + RSTC_ID : constant := 1; + RTC_ID : constant := 2; + RTT_ID : constant := 3; + WDT_ID : constant := 4; + PMC_ID : constant := 5; + EFC_ID : constant := 6; + UART0_ID : constant := 7; + UART1_ID : constant := 8; + SMC_ID : constant := 9; + PIOA_ID : constant := 10; + PIOB_ID : constant := 11; + PIOC_ID : constant := 12; + USART0_ID : constant := 13; + USART1_ID : constant := 14; + USART2_ID : constant := 15; + PIOD_ID : constant := 16; + PIOE_ID : constant := 17; + HSMCI_ID : constant := 18; + TWIHS0_ID : constant := 19; + TWIHS1_ID : constant := 20; + SPI0_ID : constant := 21; + SSC_ID : constant := 22; + TC0_CHANNEL0_ID : constant := 23; + TC0_CHANNEL1_ID : constant := 24; + TC0_CHANNEL2_ID : constant := 25; + TC1_CHANNEL0_ID : constant := 26; + TC1_CHANNEL1_ID : constant := 27; + TC1_CHANNEL2_ID : constant := 28; + AFEC0_ID : constant := 29; + DACC_ID : constant := 30; + PWM0_ID : constant := 31; + ICM_ID : constant := 32; + ACC_ID : constant := 33; + USBHS_ID : constant := 34; + MCAN0_INT0_ID : constant := 35; + MCAN0_INT1_ID : constant := 36; + MCAN1_INT0_ID : constant := 37; + MCAN1_INT1_ID : constant := 38; + GMAC_ID : constant := 39; + AFEC1_ID : constant := 40; + TWIHS2_ID : constant := 41; + SPI1_ID : constant := 42; + QSPI_ID : constant := 43; + UART2_ID : constant := 44; + UART3_ID : constant := 45; + UART4_ID : constant := 46; + TC2_CHANNEL0_ID : constant := 47; + TC2_CHANNEL1_ID : constant := 48; + TC2_CHANNEL2_ID : constant := 49; + TC3_CHANNEL0_ID : constant := 50; + TC3_CHANNEL1_ID : constant := 51; + TC3_CHANNEL2_ID : constant := 52; + MLB_0_ID : constant := 53; + MLB_1_ID : constant := 54; + + AES_ID : constant := 56; + TRNG_ID : constant := 57; + XDMAC_ID : constant := 58; + ISI_ID : constant := 59; + PWM1_ID : constant := 60; + ARM_FPU_ID : constant := 61; + SDRAMC_ID : constant := 62; + RSWDT_ID : constant := 63; + ARM_CCW_ID : constant := 64; + ARM_CCF_ID : constant := 65; + GMAC_Q1_ID : constant := 66; + GMAC_Q2_ID : constant := 67; + ARM_IXC_ID : constant := 68; + I2SC0_ID : constant := 69; + I2SC1_ID : constant := 70; + GMAC_Q3_ID : constant := 71; + GMAC_Q4_ID : constant := 72; + GMAC_Q5_ID : constant := 73; + +end SAM; diff --git a/arch/ARM/SAM/svd/atsamv71/sam_svd-acc.ads b/arch/ARM/SAM/svd/atsamv71/sam_svd-acc.ads new file mode 100644 index 000000000..9db0df283 --- /dev/null +++ b/arch/ARM/SAM/svd/atsamv71/sam_svd-acc.ads @@ -0,0 +1,412 @@ +-- This spec has been automatically generated from ATSAMV71Q21.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package SAM_SVD.ACC is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + -- Control Register + type ACC_ACC_CR_Register is record + -- Write-only. Software Reset + SWRST : Boolean := False; + -- unspecified + Reserved_1_31 : HAL.UInt31 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for ACC_ACC_CR_Register use record + SWRST at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + -- Selection for Minus Comparator Input + type ACC_MR_SELMINUS_Field is + ( + -- Select TS + Ts, + -- Select VREFP + Vrefp, + -- Select DAC0 + Dac0, + -- Select DAC1 + Dac1, + -- Select AFE0_AD0 + Afe0_Ad0, + -- Select AFE0_AD1 + Afe0_Ad1, + -- Select AFE0_AD2 + Afe0_Ad2, + -- Select AFE0_AD3 + Afe0_Ad3) + with Size => 3; + for ACC_MR_SELMINUS_Field use + (Ts => 0, + Vrefp => 1, + Dac0 => 2, + Dac1 => 3, + Afe0_Ad0 => 4, + Afe0_Ad1 => 5, + Afe0_Ad2 => 6, + Afe0_Ad3 => 7); + + -- Selection For Plus Comparator Input + type ACC_MR_SELPLUS_Field is + ( + -- Select AFE0_AD0 + Afe0_Ad0, + -- Select AFE0_AD1 + Afe0_Ad1, + -- Select AFE0_AD2 + Afe0_Ad2, + -- Select AFE0_AD3 + Afe0_Ad3, + -- Select AFE0_AD4 + Afe0_Ad4, + -- Select AFE0_AD5 + Afe0_Ad5, + -- Select AFE1_AD0 + Afe1_Ad0, + -- Select AFE1_AD1 + Afe1_Ad1) + with Size => 3; + for ACC_MR_SELPLUS_Field use + (Afe0_Ad0 => 0, + Afe0_Ad1 => 1, + Afe0_Ad2 => 2, + Afe0_Ad3 => 3, + Afe0_Ad4 => 4, + Afe0_Ad5 => 5, + Afe1_Ad0 => 6, + Afe1_Ad1 => 7); + + -- Analog Comparator Enable + type ACC_MR_ACEN_Field is + ( + -- Analog comparator disabled. + Dis, + -- Analog comparator enabled. + En) + with Size => 1; + for ACC_MR_ACEN_Field use + (Dis => 0, + En => 1); + + -- Edge Type + type ACC_MR_EDGETYP_Field is + ( + -- Only rising edge of comparator output + Rising, + -- Falling edge of comparator output + Falling, + -- Any edge of comparator output + Any) + with Size => 2; + for ACC_MR_EDGETYP_Field use + (Rising => 0, + Falling => 1, + Any => 2); + + -- Invert Comparator Output + type ACC_MR_INV_Field is + ( + -- Analog comparator output is directly processed. + Dis, + -- Analog comparator output is inverted prior to being processed. + En) + with Size => 1; + for ACC_MR_INV_Field use + (Dis => 0, + En => 1); + + -- Selection Of Fault Source + type ACC_MR_SELFS_Field is + ( + -- The CE flag is used to drive the FAULT output. + Ce, + -- The output of the analog comparator flag is used to drive the FAULT + -- output. + Output) + with Size => 1; + for ACC_MR_SELFS_Field use + (Ce => 0, + Output => 1); + + -- Fault Enable + type ACC_MR_FE_Field is + ( + -- The FAULT output is tied to 0. + Dis, + -- The FAULT output is driven by the signal defined by SELFS. + En) + with Size => 1; + for ACC_MR_FE_Field use + (Dis => 0, + En => 1); + + -- Mode Register + type ACC_ACC_MR_Register is record + -- Selection for Minus Comparator Input + SELMINUS : ACC_MR_SELMINUS_Field := SAM_SVD.ACC.Ts; + -- unspecified + Reserved_3_3 : HAL.Bit := 16#0#; + -- Selection For Plus Comparator Input + SELPLUS : ACC_MR_SELPLUS_Field := SAM_SVD.ACC.Afe0_Ad0; + -- unspecified + Reserved_7_7 : HAL.Bit := 16#0#; + -- Analog Comparator Enable + ACEN : ACC_MR_ACEN_Field := SAM_SVD.ACC.Dis; + -- Edge Type + EDGETYP : ACC_MR_EDGETYP_Field := SAM_SVD.ACC.Rising; + -- unspecified + Reserved_11_11 : HAL.Bit := 16#0#; + -- Invert Comparator Output + INV : ACC_MR_INV_Field := SAM_SVD.ACC.Dis; + -- Selection Of Fault Source + SELFS : ACC_MR_SELFS_Field := SAM_SVD.ACC.Ce; + -- Fault Enable + FE : ACC_MR_FE_Field := SAM_SVD.ACC.Dis; + -- unspecified + Reserved_15_31 : HAL.UInt17 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for ACC_ACC_MR_Register use record + SELMINUS at 0 range 0 .. 2; + Reserved_3_3 at 0 range 3 .. 3; + SELPLUS at 0 range 4 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + ACEN at 0 range 8 .. 8; + EDGETYP at 0 range 9 .. 10; + Reserved_11_11 at 0 range 11 .. 11; + INV at 0 range 12 .. 12; + SELFS at 0 range 13 .. 13; + FE at 0 range 14 .. 14; + Reserved_15_31 at 0 range 15 .. 31; + end record; + + -- Interrupt Enable Register + type ACC_ACC_IER_Register is record + -- Write-only. Comparison Edge + CE : Boolean := False; + -- unspecified + Reserved_1_31 : HAL.UInt31 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for ACC_ACC_IER_Register use record + CE at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + -- Interrupt Disable Register + type ACC_ACC_IDR_Register is record + -- Write-only. Comparison Edge + CE : Boolean := False; + -- unspecified + Reserved_1_31 : HAL.UInt31 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for ACC_ACC_IDR_Register use record + CE at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + -- Interrupt Mask Register + type ACC_ACC_IMR_Register is record + -- Read-only. Comparison Edge + CE : Boolean; + -- unspecified + Reserved_1_31 : HAL.UInt31; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for ACC_ACC_IMR_Register use record + CE at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + -- Interrupt Status Register + type ACC_ACC_ISR_Register is record + -- Read-only. Comparison Edge (cleared on read) + CE : Boolean; + -- Read-only. Synchronized Comparator Output + SCO : Boolean; + -- unspecified + Reserved_2_30 : HAL.UInt29; + -- Read-only. Flag Mask + MASK : Boolean; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for ACC_ACC_ISR_Register use record + CE at 0 range 0 .. 0; + SCO at 0 range 1 .. 1; + Reserved_2_30 at 0 range 2 .. 30; + MASK at 0 range 31 .. 31; + end record; + + -- Current Selection + type ACC_ACR_ISEL_Field is + ( + -- Low-power option. + Lopw, + -- High-speed option. + Hisp) + with Size => 1; + for ACC_ACR_ISEL_Field use + (Lopw => 0, + Hisp => 1); + + subtype ACC_ACC_ACR_HYST_Field is HAL.UInt2; + + -- Analog Control Register + type ACC_ACC_ACR_Register is record + -- Current Selection + ISEL : ACC_ACR_ISEL_Field := SAM_SVD.ACC.Lopw; + -- Hysteresis Selection + HYST : ACC_ACC_ACR_HYST_Field := 16#0#; + -- unspecified + Reserved_3_31 : HAL.UInt29 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for ACC_ACC_ACR_Register use record + ISEL at 0 range 0 .. 0; + HYST at 0 range 1 .. 2; + Reserved_3_31 at 0 range 3 .. 31; + end record; + + -- Write Protection Key + type ACC_WPMR_WPKEY_Field is + ( + -- Reset value for the field + Acc_Wpmr_Wpkey_Field_Reset, + -- Writing any other value in this field aborts the write operation of + -- the WPEN bit.Always reads as 0. + Passwd) + with Size => 24; + for ACC_WPMR_WPKEY_Field use + (Acc_Wpmr_Wpkey_Field_Reset => 0, + Passwd => 4277059); + + -- Write Protection Mode Register + type ACC_ACC_WPMR_Register is record + -- Write Protection Enable + WPEN : Boolean := False; + -- unspecified + Reserved_1_7 : HAL.UInt7 := 16#0#; + -- Write Protection Key + WPKEY : ACC_WPMR_WPKEY_Field := Acc_Wpmr_Wpkey_Field_Reset; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for ACC_ACC_WPMR_Register use record + WPEN at 0 range 0 .. 0; + Reserved_1_7 at 0 range 1 .. 7; + WPKEY at 0 range 8 .. 31; + end record; + + -- Write Protection Status Register + type ACC_ACC_WPSR_Register is record + -- Read-only. Write Protection Violation Status + WPVS : Boolean; + -- unspecified + Reserved_1_31 : HAL.UInt31; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for ACC_ACC_WPSR_Register use record + WPVS at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + subtype ACC_ACC_VER_VERSION_Field is HAL.UInt12; + subtype ACC_ACC_VER_MFN_Field is HAL.UInt3; + + -- Version Register + type ACC_ACC_VER_Register is record + -- Read-only. Version of the Hardware Module + VERSION : ACC_ACC_VER_VERSION_Field; + -- unspecified + Reserved_12_15 : HAL.UInt4; + -- Read-only. Metal Fix Number + MFN : ACC_ACC_VER_MFN_Field; + -- unspecified + Reserved_19_31 : HAL.UInt13; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for ACC_ACC_VER_Register use record + VERSION at 0 range 0 .. 11; + Reserved_12_15 at 0 range 12 .. 15; + MFN at 0 range 16 .. 18; + Reserved_19_31 at 0 range 19 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- Analog Comparator Controller + type ACC_Peripheral is record + -- Control Register + ACC_CR : aliased ACC_ACC_CR_Register; + -- Mode Register + ACC_MR : aliased ACC_ACC_MR_Register; + -- Interrupt Enable Register + ACC_IER : aliased ACC_ACC_IER_Register; + -- Interrupt Disable Register + ACC_IDR : aliased ACC_ACC_IDR_Register; + -- Interrupt Mask Register + ACC_IMR : aliased ACC_ACC_IMR_Register; + -- Interrupt Status Register + ACC_ISR : aliased ACC_ACC_ISR_Register; + -- Analog Control Register + ACC_ACR : aliased ACC_ACC_ACR_Register; + -- Write Protection Mode Register + ACC_WPMR : aliased ACC_ACC_WPMR_Register; + -- Write Protection Status Register + ACC_WPSR : aliased ACC_ACC_WPSR_Register; + -- Version Register + ACC_VER : aliased ACC_ACC_VER_Register; + end record + with Volatile; + + for ACC_Peripheral use record + ACC_CR at 16#0# range 0 .. 31; + ACC_MR at 16#4# range 0 .. 31; + ACC_IER at 16#24# range 0 .. 31; + ACC_IDR at 16#28# range 0 .. 31; + ACC_IMR at 16#2C# range 0 .. 31; + ACC_ISR at 16#30# range 0 .. 31; + ACC_ACR at 16#94# range 0 .. 31; + ACC_WPMR at 16#E4# range 0 .. 31; + ACC_WPSR at 16#E8# range 0 .. 31; + ACC_VER at 16#FC# range 0 .. 31; + end record; + + -- Analog Comparator Controller + ACC_Periph : aliased ACC_Peripheral + with Import, Address => System'To_Address (16#40044000#); + +end SAM_SVD.ACC; diff --git a/arch/ARM/SAM/svd/atsamv71/sam_svd-aes.ads b/arch/ARM/SAM/svd/atsamv71/sam_svd-aes.ads new file mode 100644 index 000000000..9147b0f7c --- /dev/null +++ b/arch/ARM/SAM/svd/atsamv71/sam_svd-aes.ads @@ -0,0 +1,558 @@ +-- This spec has been automatically generated from ATSAMV71Q21.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package SAM_SVD.AES is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + -- Control Register + type AES_AES_CR_Register is record + -- Write-only. Start Processing + START : Boolean := False; + -- unspecified + Reserved_1_7 : HAL.UInt7 := 16#0#; + -- Write-only. Software Reset + SWRST : Boolean := False; + -- unspecified + Reserved_9_15 : HAL.UInt7 := 16#0#; + -- Write-only. Random Number Generator Seed Loading + LOADSEED : Boolean := False; + -- unspecified + Reserved_17_31 : HAL.UInt15 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for AES_AES_CR_Register use record + START at 0 range 0 .. 0; + Reserved_1_7 at 0 range 1 .. 7; + SWRST at 0 range 8 .. 8; + Reserved_9_15 at 0 range 9 .. 15; + LOADSEED at 0 range 16 .. 16; + Reserved_17_31 at 0 range 17 .. 31; + end record; + + -- Dual Input Buffer + type AES_MR_DUALBUFF_Field is + ( + -- AES_IDATARx cannot be written during processing of previous block. + Inactive, + -- AES_IDATARx can be written during processing of previous block when + -- SMOD = 2. It speeds up the overall runtime of large files. + Active) + with Size => 1; + for AES_MR_DUALBUFF_Field use + (Inactive => 0, + Active => 1); + + subtype AES_AES_MR_PROCDLY_Field is HAL.UInt4; + + -- Start Mode + type AES_MR_SMOD_Field is + ( + -- Manual Mode + Manual_Start, + -- Auto Mode + Auto_Start, + -- AES_IDATAR0 access only Auto Mode (DMA) + Idatar0_Start) + with Size => 2; + for AES_MR_SMOD_Field use + (Manual_Start => 0, + Auto_Start => 1, + Idatar0_Start => 2); + + -- Key Size + type AES_MR_KEYSIZE_Field is + ( + -- AES Key Size is 128 bits + Aes128, + -- AES Key Size is 192 bits + Aes192, + -- AES Key Size is 256 bits + Aes256) + with Size => 2; + for AES_MR_KEYSIZE_Field use + (Aes128 => 0, + Aes192 => 1, + Aes256 => 2); + + -- Operating Mode + type AES_MR_OPMOD_Field is + ( + -- ECB: Electronic Code Book mode + Ecb, + -- CBC: Cipher Block Chaining mode + Cbc, + -- OFB: Output Feedback mode + Ofb, + -- CFB: Cipher Feedback mode + Cfb, + -- CTR: Counter mode (16-bit internal counter) + Ctr, + -- GCM: Galois/Counter mode + Gcm) + with Size => 3; + for AES_MR_OPMOD_Field use + (Ecb => 0, + Cbc => 1, + Ofb => 2, + Cfb => 3, + Ctr => 4, + Gcm => 5); + + -- Cipher Feedback Data Size + type AES_MR_CFBS_Field is + ( + -- 128-bit + Size_128Bit, + -- 64-bit + Size_64Bit, + -- 32-bit + Size_32Bit, + -- 16-bit + Size_16Bit, + -- 8-bit + Size_8Bit) + with Size => 3; + for AES_MR_CFBS_Field use + (Size_128Bit => 0, + Size_64Bit => 1, + Size_32Bit => 2, + Size_16Bit => 3, + Size_8Bit => 4); + + -- Countermeasure Key + type AES_MR_CKEY_Field is + ( + -- Reset value for the field + Aes_Mr_Ckey_Field_Reset, + -- This field must be written with 0xE to allow CMTYPx bit configuration + -- changes. Any other values will abort the write operation in CMTYPx + -- bits.Always reads as 0. + Passwd) + with Size => 4; + for AES_MR_CKEY_Field use + (Aes_Mr_Ckey_Field_Reset => 0, + Passwd => 14); + + -- Countermeasure Type 1 + type AES_MR_CMTYP1_Field is + ( + -- Countermeasure type 1 is disabled. + Noprot_Extkey, + -- Countermeasure type 1 is enabled. + Prot_Extkey) + with Size => 1; + for AES_MR_CMTYP1_Field use + (Noprot_Extkey => 0, + Prot_Extkey => 1); + + -- Countermeasure Type 2 + type AES_MR_CMTYP2_Field is + ( + -- Countermeasure type 2 is disabled. + No_Pause, + -- Countermeasure type 2 is enabled. + Pause) + with Size => 1; + for AES_MR_CMTYP2_Field use + (No_Pause => 0, + Pause => 1); + + -- Countermeasure Type 3 + type AES_MR_CMTYP3_Field is + ( + -- Countermeasure type 3 is disabled. + No_Dummy, + -- Countermeasure type 3 is enabled. + Dummy) + with Size => 1; + for AES_MR_CMTYP3_Field use + (No_Dummy => 0, + Dummy => 1); + + -- Countermeasure Type 4 + type AES_MR_CMTYP4_Field is + ( + -- Countermeasure type 4 is disabled. + No_Restart, + -- Countermeasure type 4 is enabled. + Restart) + with Size => 1; + for AES_MR_CMTYP4_Field use + (No_Restart => 0, + Restart => 1); + + -- Countermeasure Type 5 + type AES_MR_CMTYP5_Field is + ( + -- Countermeasure type 5 is disabled. + No_Addaccess, + -- Countermeasure type 5 is enabled. + Addaccess) + with Size => 1; + for AES_MR_CMTYP5_Field use + (No_Addaccess => 0, + Addaccess => 1); + + -- Countermeasure Type 6 + type AES_MR_CMTYP6_Field is + ( + -- Countermeasure type 6 is disabled. + No_Idlecurrent, + -- Countermeasure type 6 is enabled. + Idlecurrent) + with Size => 1; + for AES_MR_CMTYP6_Field use + (No_Idlecurrent => 0, + Idlecurrent => 1); + + -- Mode Register + type AES_AES_MR_Register is record + -- Processing Mode + CIPHER : Boolean := False; + -- GCM Automatic Tag Generation Enable + GTAGEN : Boolean := False; + -- unspecified + Reserved_2_2 : HAL.Bit := 16#0#; + -- Dual Input Buffer + DUALBUFF : AES_MR_DUALBUFF_Field := SAM_SVD.AES.Inactive; + -- Processing Delay + PROCDLY : AES_AES_MR_PROCDLY_Field := 16#0#; + -- Start Mode + SMOD : AES_MR_SMOD_Field := SAM_SVD.AES.Manual_Start; + -- Key Size + KEYSIZE : AES_MR_KEYSIZE_Field := SAM_SVD.AES.Aes128; + -- Operating Mode + OPMOD : AES_MR_OPMOD_Field := SAM_SVD.AES.Ecb; + -- Last Output Data Mode + LOD : Boolean := False; + -- Cipher Feedback Data Size + CFBS : AES_MR_CFBS_Field := SAM_SVD.AES.Size_128Bit; + -- unspecified + Reserved_19_19 : HAL.Bit := 16#0#; + -- Countermeasure Key + CKEY : AES_MR_CKEY_Field := Aes_Mr_Ckey_Field_Reset; + -- Countermeasure Type 1 + CMTYP1 : AES_MR_CMTYP1_Field := SAM_SVD.AES.Noprot_Extkey; + -- Countermeasure Type 2 + CMTYP2 : AES_MR_CMTYP2_Field := SAM_SVD.AES.No_Pause; + -- Countermeasure Type 3 + CMTYP3 : AES_MR_CMTYP3_Field := SAM_SVD.AES.No_Dummy; + -- Countermeasure Type 4 + CMTYP4 : AES_MR_CMTYP4_Field := SAM_SVD.AES.No_Restart; + -- Countermeasure Type 5 + CMTYP5 : AES_MR_CMTYP5_Field := SAM_SVD.AES.No_Addaccess; + -- Countermeasure Type 6 + CMTYP6 : AES_MR_CMTYP6_Field := SAM_SVD.AES.No_Idlecurrent; + -- unspecified + Reserved_30_31 : HAL.UInt2 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for AES_AES_MR_Register use record + CIPHER at 0 range 0 .. 0; + GTAGEN at 0 range 1 .. 1; + Reserved_2_2 at 0 range 2 .. 2; + DUALBUFF at 0 range 3 .. 3; + PROCDLY at 0 range 4 .. 7; + SMOD at 0 range 8 .. 9; + KEYSIZE at 0 range 10 .. 11; + OPMOD at 0 range 12 .. 14; + LOD at 0 range 15 .. 15; + CFBS at 0 range 16 .. 18; + Reserved_19_19 at 0 range 19 .. 19; + CKEY at 0 range 20 .. 23; + CMTYP1 at 0 range 24 .. 24; + CMTYP2 at 0 range 25 .. 25; + CMTYP3 at 0 range 26 .. 26; + CMTYP4 at 0 range 27 .. 27; + CMTYP5 at 0 range 28 .. 28; + CMTYP6 at 0 range 29 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + -- Interrupt Enable Register + type AES_AES_IER_Register is record + -- Write-only. Data Ready Interrupt Enable + DATRDY : Boolean := False; + -- unspecified + Reserved_1_7 : HAL.UInt7 := 16#0#; + -- Write-only. Unspecified Register Access Detection Interrupt Enable + URAD : Boolean := False; + -- unspecified + Reserved_9_15 : HAL.UInt7 := 16#0#; + -- Write-only. GCM Tag Ready Interrupt Enable + TAGRDY : Boolean := False; + -- unspecified + Reserved_17_31 : HAL.UInt15 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for AES_AES_IER_Register use record + DATRDY at 0 range 0 .. 0; + Reserved_1_7 at 0 range 1 .. 7; + URAD at 0 range 8 .. 8; + Reserved_9_15 at 0 range 9 .. 15; + TAGRDY at 0 range 16 .. 16; + Reserved_17_31 at 0 range 17 .. 31; + end record; + + -- Interrupt Disable Register + type AES_AES_IDR_Register is record + -- Write-only. Data Ready Interrupt Disable + DATRDY : Boolean := False; + -- unspecified + Reserved_1_7 : HAL.UInt7 := 16#0#; + -- Write-only. Unspecified Register Access Detection Interrupt Disable + URAD : Boolean := False; + -- unspecified + Reserved_9_15 : HAL.UInt7 := 16#0#; + -- Write-only. GCM Tag Ready Interrupt Disable + TAGRDY : Boolean := False; + -- unspecified + Reserved_17_31 : HAL.UInt15 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for AES_AES_IDR_Register use record + DATRDY at 0 range 0 .. 0; + Reserved_1_7 at 0 range 1 .. 7; + URAD at 0 range 8 .. 8; + Reserved_9_15 at 0 range 9 .. 15; + TAGRDY at 0 range 16 .. 16; + Reserved_17_31 at 0 range 17 .. 31; + end record; + + -- Interrupt Mask Register + type AES_AES_IMR_Register is record + -- Read-only. Data Ready Interrupt Mask + DATRDY : Boolean; + -- unspecified + Reserved_1_7 : HAL.UInt7; + -- Read-only. Unspecified Register Access Detection Interrupt Mask + URAD : Boolean; + -- unspecified + Reserved_9_15 : HAL.UInt7; + -- Read-only. GCM Tag Ready Interrupt Mask + TAGRDY : Boolean; + -- unspecified + Reserved_17_31 : HAL.UInt15; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for AES_AES_IMR_Register use record + DATRDY at 0 range 0 .. 0; + Reserved_1_7 at 0 range 1 .. 7; + URAD at 0 range 8 .. 8; + Reserved_9_15 at 0 range 9 .. 15; + TAGRDY at 0 range 16 .. 16; + Reserved_17_31 at 0 range 17 .. 31; + end record; + + -- Unspecified Register Access (cleared by writing SWRST in AES_CR) + type AES_ISR_URAT_Field is + ( + -- Input Data register written during the data processing when SMOD = + -- 0x2 mode. + Idr_Wr_Processing, + -- Output Data register read during the data processing. + Odr_Rd_Processing, + -- Mode register written during the data processing. + Mr_Wr_Processing, + -- Output Data register read during the sub-keys generation. + Odr_Rd_Subkgen, + -- Mode register written during the sub-keys generation. + Mr_Wr_Subkgen, + -- Write-only register read access. + Wor_Rd_Access) + with Size => 4; + for AES_ISR_URAT_Field use + (Idr_Wr_Processing => 0, + Odr_Rd_Processing => 1, + Mr_Wr_Processing => 2, + Odr_Rd_Subkgen => 3, + Mr_Wr_Subkgen => 4, + Wor_Rd_Access => 5); + + -- Interrupt Status Register + type AES_AES_ISR_Register is record + -- Read-only. Data Ready (cleared by setting bit START or bit SWRST in + -- AES_CR or by reading AES_ODATARx) + DATRDY : Boolean; + -- unspecified + Reserved_1_7 : HAL.UInt7; + -- Read-only. Unspecified Register Access Detection Status (cleared by + -- writing SWRST in AES_CR) + URAD : Boolean; + -- unspecified + Reserved_9_11 : HAL.UInt3; + -- Read-only. Unspecified Register Access (cleared by writing SWRST in + -- AES_CR) + URAT : AES_ISR_URAT_Field; + -- Read-only. GCM Tag Ready + TAGRDY : Boolean; + -- unspecified + Reserved_17_31 : HAL.UInt15; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for AES_AES_ISR_Register use record + DATRDY at 0 range 0 .. 0; + Reserved_1_7 at 0 range 1 .. 7; + URAD at 0 range 8 .. 8; + Reserved_9_11 at 0 range 9 .. 11; + URAT at 0 range 12 .. 15; + TAGRDY at 0 range 16 .. 16; + Reserved_17_31 at 0 range 17 .. 31; + end record; + + -- Key Word Register 0 + + -- Key Word Register 0 + type AES_AES_KEYWR_Registers is array (0 .. 7) of HAL.UInt32 + with Volatile; + + -- Input Data Register 0 + + -- Input Data Register 0 + type AES_AES_IDATAR_Registers is array (0 .. 3) of HAL.UInt32 + with Volatile; + + -- Output Data Register 0 + + -- Output Data Register 0 + type AES_AES_ODATAR_Registers is array (0 .. 3) of HAL.UInt32 + with Volatile; + + -- Initialization Vector Register 0 + + -- Initialization Vector Register 0 + type AES_AES_IVR_Registers is array (0 .. 3) of HAL.UInt32 + with Volatile; + + -- GCM Intermediate Hash Word Register 0 + + -- GCM Intermediate Hash Word Register 0 + type AES_AES_GHASHR_Registers is array (0 .. 3) of HAL.UInt32 + with Volatile; + + -- GCM Authentication Tag Word Register 0 + + -- GCM Authentication Tag Word Register 0 + type AES_AES_TAGR_Registers is array (0 .. 3) of HAL.UInt32 + with Volatile; + + -- GCM H Word Register 0 + + -- GCM H Word Register 0 + type AES_AES_GCMHR_Registers is array (0 .. 3) of HAL.UInt32 + with Volatile; + + subtype AES_AES_VERSION_VERSION_Field is HAL.UInt12; + subtype AES_AES_VERSION_MFN_Field is HAL.UInt3; + + -- Version Register + type AES_AES_VERSION_Register is record + -- Read-only. Version of the Hardware Module + VERSION : AES_AES_VERSION_VERSION_Field; + -- unspecified + Reserved_12_15 : HAL.UInt4; + -- Read-only. Metal Fix Number + MFN : AES_AES_VERSION_MFN_Field; + -- unspecified + Reserved_19_31 : HAL.UInt13; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for AES_AES_VERSION_Register use record + VERSION at 0 range 0 .. 11; + Reserved_12_15 at 0 range 12 .. 15; + MFN at 0 range 16 .. 18; + Reserved_19_31 at 0 range 19 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- Advanced Encryption Standard + type AES_Peripheral is record + -- Control Register + AES_CR : aliased AES_AES_CR_Register; + -- Mode Register + AES_MR : aliased AES_AES_MR_Register; + -- Interrupt Enable Register + AES_IER : aliased AES_AES_IER_Register; + -- Interrupt Disable Register + AES_IDR : aliased AES_AES_IDR_Register; + -- Interrupt Mask Register + AES_IMR : aliased AES_AES_IMR_Register; + -- Interrupt Status Register + AES_ISR : aliased AES_AES_ISR_Register; + -- Key Word Register 0 + AES_KEYWR : aliased AES_AES_KEYWR_Registers; + -- Input Data Register 0 + AES_IDATAR : aliased AES_AES_IDATAR_Registers; + -- Output Data Register 0 + AES_ODATAR : aliased AES_AES_ODATAR_Registers; + -- Initialization Vector Register 0 + AES_IVR : aliased AES_AES_IVR_Registers; + -- Additional Authenticated Data Length Register + AES_AADLENR : aliased HAL.UInt32; + -- Plaintext/Ciphertext Length Register + AES_CLENR : aliased HAL.UInt32; + -- GCM Intermediate Hash Word Register 0 + AES_GHASHR : aliased AES_AES_GHASHR_Registers; + -- GCM Authentication Tag Word Register 0 + AES_TAGR : aliased AES_AES_TAGR_Registers; + -- GCM Encryption Counter Value Register + AES_CTRR : aliased HAL.UInt32; + -- GCM H Word Register 0 + AES_GCMHR : aliased AES_AES_GCMHR_Registers; + -- Version Register + AES_VERSION : aliased AES_AES_VERSION_Register; + end record + with Volatile; + + for AES_Peripheral use record + AES_CR at 16#0# range 0 .. 31; + AES_MR at 16#4# range 0 .. 31; + AES_IER at 16#10# range 0 .. 31; + AES_IDR at 16#14# range 0 .. 31; + AES_IMR at 16#18# range 0 .. 31; + AES_ISR at 16#1C# range 0 .. 31; + AES_KEYWR at 16#20# range 0 .. 255; + AES_IDATAR at 16#40# range 0 .. 127; + AES_ODATAR at 16#50# range 0 .. 127; + AES_IVR at 16#60# range 0 .. 127; + AES_AADLENR at 16#70# range 0 .. 31; + AES_CLENR at 16#74# range 0 .. 31; + AES_GHASHR at 16#78# range 0 .. 127; + AES_TAGR at 16#88# range 0 .. 127; + AES_CTRR at 16#98# range 0 .. 31; + AES_GCMHR at 16#9C# range 0 .. 127; + AES_VERSION at 16#FC# range 0 .. 31; + end record; + + -- Advanced Encryption Standard + AES_Periph : aliased AES_Peripheral + with Import, Address => System'To_Address (16#4006C000#); + +end SAM_SVD.AES; diff --git a/arch/ARM/SAM/svd/atsamv71/sam_svd-afec.ads b/arch/ARM/SAM/svd/atsamv71/sam_svd-afec.ads new file mode 100644 index 000000000..0ef224256 --- /dev/null +++ b/arch/ARM/SAM/svd/atsamv71/sam_svd-afec.ads @@ -0,0 +1,1391 @@ +-- This spec has been automatically generated from ATSAMV71Q21.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package SAM_SVD.AFEC is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + -- AFEC Control Register + type AFEC_AFEC_CR_Register is record + -- Write-only. Software Reset + SWRST : Boolean := False; + -- Write-only. Start Conversion + START : Boolean := False; + -- unspecified + Reserved_2_31 : HAL.UInt30 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for AFEC_AFEC_CR_Register use record + SWRST at 0 range 0 .. 0; + START at 0 range 1 .. 1; + Reserved_2_31 at 0 range 2 .. 31; + end record; + + -- Trigger Enable + type AFEC_MR_TRGEN_Field is + ( + -- Hardware triggers are disabled. Starting a conversion is only + -- possible by software. + Dis, + -- Hardware trigger selected by TRGSEL field is enabled. + En) + with Size => 1; + for AFEC_MR_TRGEN_Field use + (Dis => 0, + En => 1); + + -- Trigger Selection + type AFEC_MR_TRGSEL_Field is + ( + -- AFE0_ADTRG for AFEC0 / AFE1_ADTRG for AFEC1 + Afec_Trig0, + -- TIOA Output of the Timer Counter Channel 0 for AFEC0/TIOA Output of + -- the Timer Counter Channel 3 for AFEC1 + Afec_Trig1, + -- TIOA Output of the Timer Counter Channel 1 for AFEC0/TIOA Output of + -- the Timer Counter Channel 4 for AFEC1 + Afec_Trig2, + -- TIOA Output of the Timer Counter Channel 2 for AFEC0/TIOA Output of + -- the Timer Counter Channel 5 for AFEC1 + Afec_Trig3, + -- PWM0 event line 0 for AFEC0 / PWM1 event line 0 for AFEC1 + Afec_Trig4, + -- PWM0 event line 1 for AFEC0 / PWM1 event line 1 for AFEC1 + Afec_Trig5, + -- Analog Comparator + Afec_Trig6) + with Size => 3; + for AFEC_MR_TRGSEL_Field use + (Afec_Trig0 => 0, + Afec_Trig1 => 1, + Afec_Trig2 => 2, + Afec_Trig3 => 3, + Afec_Trig4 => 4, + Afec_Trig5 => 5, + Afec_Trig6 => 6); + + -- Sleep Mode + type AFEC_MR_SLEEP_Field is + ( + -- Normal mode: The AFE and reference voltage circuitry are kept ON + -- between conversions. + Normal, + -- Sleep mode: The AFE and reference voltage circuitry are OFF between + -- conversions. + Sleep) + with Size => 1; + for AFEC_MR_SLEEP_Field use + (Normal => 0, + Sleep => 1); + + -- Fast Wakeup + type AFEC_MR_FWUP_Field is + ( + -- Normal Sleep mode: The sleep mode is defined by the SLEEP bit. + Off, + -- Fast akeup Sleep mode: The voltage reference is ON between + -- conversions and AFE is OFF. + On) + with Size => 1; + for AFEC_MR_FWUP_Field use + (Off => 0, + On => 1); + + -- Free Run Mode + type AFEC_MR_FREERUN_Field is + ( + -- Normal mode + Off, + -- Free Run mode: Never wait for any trigger. + On) + with Size => 1; + for AFEC_MR_FREERUN_Field use + (Off => 0, + On => 1); + + subtype AFEC_AFEC_MR_PRESCAL_Field is HAL.UInt8; + + -- Startup Time + type AFEC_MR_STARTUP_Field is + ( + -- 0 periods of AFE clock + Sut0, + -- 8 periods of AFE clock + Sut8, + -- 16 periods of AFE clock + Sut16, + -- 24 periods of AFE clock + Sut24, + -- 64 periods of AFE clock + Sut64, + -- 80 periods of AFE clock + Sut80, + -- 96 periods of AFE clock + Sut96, + -- 112 periods of AFE clock + Sut112, + -- 512 periods of AFE clock + Sut512, + -- 576 periods of AFE clock + Sut576, + -- 640 periods of AFE clock + Sut640, + -- 704 periods of AFE clock + Sut704, + -- 768 periods of AFE clock + Sut768, + -- 832 periods of AFE clock + Sut832, + -- 896 periods of AFE clock + Sut896, + -- 960 periods of AFE clock + Sut960) + with Size => 4; + for AFEC_MR_STARTUP_Field use + (Sut0 => 0, + Sut8 => 1, + Sut16 => 2, + Sut24 => 3, + Sut64 => 4, + Sut80 => 5, + Sut96 => 6, + Sut112 => 7, + Sut512 => 8, + Sut576 => 9, + Sut640 => 10, + Sut704 => 11, + Sut768 => 12, + Sut832 => 13, + Sut896 => 14, + Sut960 => 15); + + subtype AFEC_AFEC_MR_TRACKTIM_Field is HAL.UInt4; + subtype AFEC_AFEC_MR_TRANSFER_Field is HAL.UInt2; + + -- User Sequence Enable + type AFEC_MR_USEQ_Field is + ( + -- Normal mode: The controller converts channels in a simple numeric + -- order. + Num_Order, + -- User Sequence mode: The sequence respects what is defined in + -- AFEC_SEQ1R and AFEC_SEQ1R. + Reg_Order) + with Size => 1; + for AFEC_MR_USEQ_Field use + (Num_Order => 0, + Reg_Order => 1); + + -- AFEC Mode Register + type AFEC_AFEC_MR_Register is record + -- Trigger Enable + TRGEN : AFEC_MR_TRGEN_Field := SAM_SVD.AFEC.Dis; + -- Trigger Selection + TRGSEL : AFEC_MR_TRGSEL_Field := SAM_SVD.AFEC.Afec_Trig0; + -- unspecified + Reserved_4_4 : HAL.Bit := 16#0#; + -- Sleep Mode + SLEEP : AFEC_MR_SLEEP_Field := SAM_SVD.AFEC.Normal; + -- Fast Wakeup + FWUP : AFEC_MR_FWUP_Field := SAM_SVD.AFEC.Off; + -- Free Run Mode + FREERUN : AFEC_MR_FREERUN_Field := SAM_SVD.AFEC.Off; + -- Prescaler Rate Selection + PRESCAL : AFEC_AFEC_MR_PRESCAL_Field := 16#0#; + -- Startup Time + STARTUP : AFEC_MR_STARTUP_Field := SAM_SVD.AFEC.Sut0; + -- unspecified + Reserved_20_22 : HAL.UInt3 := 16#0#; + -- One + ONE : Boolean := False; + -- Tracking Time + TRACKTIM : AFEC_AFEC_MR_TRACKTIM_Field := 16#0#; + -- Transfer Period + TRANSFER : AFEC_AFEC_MR_TRANSFER_Field := 16#0#; + -- unspecified + Reserved_30_30 : HAL.Bit := 16#0#; + -- User Sequence Enable + USEQ : AFEC_MR_USEQ_Field := SAM_SVD.AFEC.Num_Order; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for AFEC_AFEC_MR_Register use record + TRGEN at 0 range 0 .. 0; + TRGSEL at 0 range 1 .. 3; + Reserved_4_4 at 0 range 4 .. 4; + SLEEP at 0 range 5 .. 5; + FWUP at 0 range 6 .. 6; + FREERUN at 0 range 7 .. 7; + PRESCAL at 0 range 8 .. 15; + STARTUP at 0 range 16 .. 19; + Reserved_20_22 at 0 range 20 .. 22; + ONE at 0 range 23 .. 23; + TRACKTIM at 0 range 24 .. 27; + TRANSFER at 0 range 28 .. 29; + Reserved_30_30 at 0 range 30 .. 30; + USEQ at 0 range 31 .. 31; + end record; + + -- Comparison Mode + type AFEC_EMR_CMPMODE_Field is + ( + -- Generates an event when the converted data is lower than the low + -- threshold of the window. + Low, + -- Generates an event when the converted data is higher than the high + -- threshold of the window. + High, + -- Generates an event when the converted data is in the comparison + -- window. + In_k, + -- Generates an event when the converted data is out of the comparison + -- window. + Out_k) + with Size => 2; + for AFEC_EMR_CMPMODE_Field use + (Low => 0, + High => 1, + In_k => 2, + Out_k => 3); + + subtype AFEC_AFEC_EMR_CMPSEL_Field is HAL.UInt5; + subtype AFEC_AFEC_EMR_CMPFILTER_Field is HAL.UInt2; + + -- Resolution + type AFEC_EMR_RES_Field is + ( + -- 12-bit resolution, AFE sample rate is maximum (no averaging). + No_Average, + -- 13-bit resolution, AFE sample rate divided by 4 (averaging). + Osr4, + -- 14-bit resolution, AFE sample rate divided by 16 (averaging). + Osr16, + -- 15-bit resolution, AFE sample rate divided by 64 (averaging). + Osr64, + -- 16-bit resolution, AFE sample rate divided by 256 (averaging). + Osr256) + with Size => 3; + for AFEC_EMR_RES_Field use + (No_Average => 0, + Osr4 => 2, + Osr16 => 3, + Osr64 => 4, + Osr256 => 5); + + -- Sign Mode + type AFEC_EMR_SIGNMODE_Field is + ( + -- Single-Ended channels: Unsigned conversions.Differential channels: + -- Signed conversions. + Se_Unsg_Df_Sign, + -- Single-Ended channels: Signed conversions.Differential channels: + -- Unsigned conversions. + Se_Sign_Df_Unsg, + -- All channels: Unsigned conversions. + All_Unsigned, + -- All channels: Signed conversions. + All_Signed) + with Size => 2; + for AFEC_EMR_SIGNMODE_Field use + (Se_Unsg_Df_Sign => 0, + Se_Sign_Df_Unsg => 1, + All_Unsigned => 2, + All_Signed => 3); + + -- AFEC Extended Mode Register + type AFEC_AFEC_EMR_Register is record + -- Comparison Mode + CMPMODE : AFEC_EMR_CMPMODE_Field := SAM_SVD.AFEC.Low; + -- unspecified + Reserved_2_2 : HAL.Bit := 16#0#; + -- Comparison Selected Channel + CMPSEL : AFEC_AFEC_EMR_CMPSEL_Field := 16#0#; + -- unspecified + Reserved_8_8 : HAL.Bit := 16#0#; + -- Compare All Channels + CMPALL : Boolean := False; + -- unspecified + Reserved_10_11 : HAL.UInt2 := 16#0#; + -- Compare Event Filtering + CMPFILTER : AFEC_AFEC_EMR_CMPFILTER_Field := 16#0#; + -- unspecified + Reserved_14_15 : HAL.UInt2 := 16#0#; + -- Resolution + RES : AFEC_EMR_RES_Field := SAM_SVD.AFEC.No_Average; + -- unspecified + Reserved_19_23 : HAL.UInt5 := 16#0#; + -- TAG of the AFEC_LDCR + TAG : Boolean := False; + -- Single Trigger Mode + STM : Boolean := False; + -- unspecified + Reserved_26_27 : HAL.UInt2 := 16#0#; + -- Sign Mode + SIGNMODE : AFEC_EMR_SIGNMODE_Field := + SAM_SVD.AFEC.Se_Unsg_Df_Sign; + -- unspecified + Reserved_30_31 : HAL.UInt2 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for AFEC_AFEC_EMR_Register use record + CMPMODE at 0 range 0 .. 1; + Reserved_2_2 at 0 range 2 .. 2; + CMPSEL at 0 range 3 .. 7; + Reserved_8_8 at 0 range 8 .. 8; + CMPALL at 0 range 9 .. 9; + Reserved_10_11 at 0 range 10 .. 11; + CMPFILTER at 0 range 12 .. 13; + Reserved_14_15 at 0 range 14 .. 15; + RES at 0 range 16 .. 18; + Reserved_19_23 at 0 range 19 .. 23; + TAG at 0 range 24 .. 24; + STM at 0 range 25 .. 25; + Reserved_26_27 at 0 range 26 .. 27; + SIGNMODE at 0 range 28 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + -- AFEC_AFEC_SEQ1R_USCH array element + subtype AFEC_AFEC_SEQ1R_USCH_Element is HAL.UInt4; + + -- AFEC_AFEC_SEQ1R_USCH array + type AFEC_AFEC_SEQ1R_USCH_Field_Array is array (0 .. 7) + of AFEC_AFEC_SEQ1R_USCH_Element + with Component_Size => 4, Size => 32; + + -- AFEC Channel Sequence 1 Register + type AFEC_AFEC_SEQ1R_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- USCH as a value + Val : HAL.UInt32; + when True => + -- USCH as an array + Arr : AFEC_AFEC_SEQ1R_USCH_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, + Bit_Order => System.Low_Order_First; + + for AFEC_AFEC_SEQ1R_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- AFEC_AFEC_SEQ2R_USCH array element + subtype AFEC_AFEC_SEQ2R_USCH_Element is HAL.UInt4; + + -- AFEC_AFEC_SEQ2R_USCH array + type AFEC_AFEC_SEQ2R_USCH_Field_Array is array (8 .. 11) + of AFEC_AFEC_SEQ2R_USCH_Element + with Component_Size => 4, Size => 16; + + -- Type definition for AFEC_AFEC_SEQ2R_USCH + type AFEC_AFEC_SEQ2R_USCH_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- USCH as a value + Val : HAL.UInt16; + when True => + -- USCH as an array + Arr : AFEC_AFEC_SEQ2R_USCH_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for AFEC_AFEC_SEQ2R_USCH_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- AFEC Channel Sequence 2 Register + type AFEC_AFEC_SEQ2R_Register is record + -- User Sequence Number 8 + USCH : AFEC_AFEC_SEQ2R_USCH_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for AFEC_AFEC_SEQ2R_Register use record + USCH at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + -- AFEC_AFEC_CHER_CH array + type AFEC_AFEC_CHER_CH_Field_Array is array (0 .. 11) of Boolean + with Component_Size => 1, Size => 12; + + -- Type definition for AFEC_AFEC_CHER_CH + type AFEC_AFEC_CHER_CH_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CH as a value + Val : HAL.UInt12; + when True => + -- CH as an array + Arr : AFEC_AFEC_CHER_CH_Field_Array; + end case; + end record + with Unchecked_Union, Size => 12; + + for AFEC_AFEC_CHER_CH_Field use record + Val at 0 range 0 .. 11; + Arr at 0 range 0 .. 11; + end record; + + -- AFEC Channel Enable Register + type AFEC_AFEC_CHER_Register is record + -- Write-only. Channel 0 Enable + CH : AFEC_AFEC_CHER_CH_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_12_31 : HAL.UInt20 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for AFEC_AFEC_CHER_Register use record + CH at 0 range 0 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + -- AFEC_AFEC_CHDR_CH array + type AFEC_AFEC_CHDR_CH_Field_Array is array (0 .. 11) of Boolean + with Component_Size => 1, Size => 12; + + -- Type definition for AFEC_AFEC_CHDR_CH + type AFEC_AFEC_CHDR_CH_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CH as a value + Val : HAL.UInt12; + when True => + -- CH as an array + Arr : AFEC_AFEC_CHDR_CH_Field_Array; + end case; + end record + with Unchecked_Union, Size => 12; + + for AFEC_AFEC_CHDR_CH_Field use record + Val at 0 range 0 .. 11; + Arr at 0 range 0 .. 11; + end record; + + -- AFEC Channel Disable Register + type AFEC_AFEC_CHDR_Register is record + -- Write-only. Channel 0 Disable + CH : AFEC_AFEC_CHDR_CH_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_12_31 : HAL.UInt20 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for AFEC_AFEC_CHDR_Register use record + CH at 0 range 0 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + -- AFEC_AFEC_CHSR_CH array + type AFEC_AFEC_CHSR_CH_Field_Array is array (0 .. 11) of Boolean + with Component_Size => 1, Size => 12; + + -- Type definition for AFEC_AFEC_CHSR_CH + type AFEC_AFEC_CHSR_CH_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CH as a value + Val : HAL.UInt12; + when True => + -- CH as an array + Arr : AFEC_AFEC_CHSR_CH_Field_Array; + end case; + end record + with Unchecked_Union, Size => 12; + + for AFEC_AFEC_CHSR_CH_Field use record + Val at 0 range 0 .. 11; + Arr at 0 range 0 .. 11; + end record; + + -- AFEC Channel Status Register + type AFEC_AFEC_CHSR_Register is record + -- Read-only. Channel 0 Status + CH : AFEC_AFEC_CHSR_CH_Field; + -- unspecified + Reserved_12_31 : HAL.UInt20; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for AFEC_AFEC_CHSR_Register use record + CH at 0 range 0 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + subtype AFEC_AFEC_LCDR_LDATA_Field is HAL.UInt16; + subtype AFEC_AFEC_LCDR_CHNB_Field is HAL.UInt4; + + -- AFEC Last Converted Data Register + type AFEC_AFEC_LCDR_Register is record + -- Read-only. Last Data Converted + LDATA : AFEC_AFEC_LCDR_LDATA_Field; + -- unspecified + Reserved_16_23 : HAL.UInt8; + -- Read-only. Channel Number + CHNB : AFEC_AFEC_LCDR_CHNB_Field; + -- unspecified + Reserved_28_31 : HAL.UInt4; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for AFEC_AFEC_LCDR_Register use record + LDATA at 0 range 0 .. 15; + Reserved_16_23 at 0 range 16 .. 23; + CHNB at 0 range 24 .. 27; + Reserved_28_31 at 0 range 28 .. 31; + end record; + + -- AFEC_AFEC_IER_EOC array + type AFEC_AFEC_IER_EOC_Field_Array is array (0 .. 11) of Boolean + with Component_Size => 1, Size => 12; + + -- Type definition for AFEC_AFEC_IER_EOC + type AFEC_AFEC_IER_EOC_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- EOC as a value + Val : HAL.UInt12; + when True => + -- EOC as an array + Arr : AFEC_AFEC_IER_EOC_Field_Array; + end case; + end record + with Unchecked_Union, Size => 12; + + for AFEC_AFEC_IER_EOC_Field use record + Val at 0 range 0 .. 11; + Arr at 0 range 0 .. 11; + end record; + + -- AFEC Interrupt Enable Register + type AFEC_AFEC_IER_Register is record + -- Write-only. End of Conversion Interrupt Enable 0 + EOC : AFEC_AFEC_IER_EOC_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_12_23 : HAL.UInt12 := 16#0#; + -- Write-only. Data Ready Interrupt Enable + DRDY : Boolean := False; + -- Write-only. General Overrun Error Interrupt Enable + GOVRE : Boolean := False; + -- Write-only. Comparison Event Interrupt Enable + COMPE : Boolean := False; + -- unspecified + Reserved_27_29 : HAL.UInt3 := 16#0#; + -- Write-only. Temperature Change Interrupt Enable + TEMPCHG : Boolean := False; + -- unspecified + Reserved_31_31 : HAL.Bit := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for AFEC_AFEC_IER_Register use record + EOC at 0 range 0 .. 11; + Reserved_12_23 at 0 range 12 .. 23; + DRDY at 0 range 24 .. 24; + GOVRE at 0 range 25 .. 25; + COMPE at 0 range 26 .. 26; + Reserved_27_29 at 0 range 27 .. 29; + TEMPCHG at 0 range 30 .. 30; + Reserved_31_31 at 0 range 31 .. 31; + end record; + + -- AFEC_AFEC_IDR_EOC array + type AFEC_AFEC_IDR_EOC_Field_Array is array (0 .. 11) of Boolean + with Component_Size => 1, Size => 12; + + -- Type definition for AFEC_AFEC_IDR_EOC + type AFEC_AFEC_IDR_EOC_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- EOC as a value + Val : HAL.UInt12; + when True => + -- EOC as an array + Arr : AFEC_AFEC_IDR_EOC_Field_Array; + end case; + end record + with Unchecked_Union, Size => 12; + + for AFEC_AFEC_IDR_EOC_Field use record + Val at 0 range 0 .. 11; + Arr at 0 range 0 .. 11; + end record; + + -- AFEC Interrupt Disable Register + type AFEC_AFEC_IDR_Register is record + -- Write-only. End of Conversion Interrupt Disable 0 + EOC : AFEC_AFEC_IDR_EOC_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_12_23 : HAL.UInt12 := 16#0#; + -- Write-only. Data Ready Interrupt Disable + DRDY : Boolean := False; + -- Write-only. General Overrun Error Interrupt Disable + GOVRE : Boolean := False; + -- Write-only. Comparison Event Interrupt Disable + COMPE : Boolean := False; + -- unspecified + Reserved_27_29 : HAL.UInt3 := 16#0#; + -- Write-only. Temperature Change Interrupt Disable + TEMPCHG : Boolean := False; + -- unspecified + Reserved_31_31 : HAL.Bit := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for AFEC_AFEC_IDR_Register use record + EOC at 0 range 0 .. 11; + Reserved_12_23 at 0 range 12 .. 23; + DRDY at 0 range 24 .. 24; + GOVRE at 0 range 25 .. 25; + COMPE at 0 range 26 .. 26; + Reserved_27_29 at 0 range 27 .. 29; + TEMPCHG at 0 range 30 .. 30; + Reserved_31_31 at 0 range 31 .. 31; + end record; + + -- AFEC_AFEC_IMR_EOC array + type AFEC_AFEC_IMR_EOC_Field_Array is array (0 .. 11) of Boolean + with Component_Size => 1, Size => 12; + + -- Type definition for AFEC_AFEC_IMR_EOC + type AFEC_AFEC_IMR_EOC_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- EOC as a value + Val : HAL.UInt12; + when True => + -- EOC as an array + Arr : AFEC_AFEC_IMR_EOC_Field_Array; + end case; + end record + with Unchecked_Union, Size => 12; + + for AFEC_AFEC_IMR_EOC_Field use record + Val at 0 range 0 .. 11; + Arr at 0 range 0 .. 11; + end record; + + -- AFEC Interrupt Mask Register + type AFEC_AFEC_IMR_Register is record + -- Read-only. End of Conversion Interrupt Mask 0 + EOC : AFEC_AFEC_IMR_EOC_Field; + -- unspecified + Reserved_12_23 : HAL.UInt12; + -- Read-only. Data Ready Interrupt Mask + DRDY : Boolean; + -- Read-only. General Overrun Error Interrupt Mask + GOVRE : Boolean; + -- Read-only. Comparison Event Interrupt Mask + COMPE : Boolean; + -- unspecified + Reserved_27_29 : HAL.UInt3; + -- Read-only. Temperature Change Interrupt Mask + TEMPCHG : Boolean; + -- unspecified + Reserved_31_31 : HAL.Bit; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for AFEC_AFEC_IMR_Register use record + EOC at 0 range 0 .. 11; + Reserved_12_23 at 0 range 12 .. 23; + DRDY at 0 range 24 .. 24; + GOVRE at 0 range 25 .. 25; + COMPE at 0 range 26 .. 26; + Reserved_27_29 at 0 range 27 .. 29; + TEMPCHG at 0 range 30 .. 30; + Reserved_31_31 at 0 range 31 .. 31; + end record; + + -- AFEC_AFEC_ISR_EOC array + type AFEC_AFEC_ISR_EOC_Field_Array is array (0 .. 11) of Boolean + with Component_Size => 1, Size => 12; + + -- Type definition for AFEC_AFEC_ISR_EOC + type AFEC_AFEC_ISR_EOC_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- EOC as a value + Val : HAL.UInt12; + when True => + -- EOC as an array + Arr : AFEC_AFEC_ISR_EOC_Field_Array; + end case; + end record + with Unchecked_Union, Size => 12; + + for AFEC_AFEC_ISR_EOC_Field use record + Val at 0 range 0 .. 11; + Arr at 0 range 0 .. 11; + end record; + + -- AFEC Interrupt Status Register + type AFEC_AFEC_ISR_Register is record + -- Read-only. End of Conversion 0 (cleared by reading AFEC_CDRx) + EOC : AFEC_AFEC_ISR_EOC_Field; + -- unspecified + Reserved_12_23 : HAL.UInt12; + -- Read-only. Data Ready (cleared by reading AFEC_LCDR) + DRDY : Boolean; + -- Read-only. General Overrun Error (cleared by reading AFEC_ISR) + GOVRE : Boolean; + -- Read-only. Comparison Error (cleared by reading AFEC_ISR) + COMPE : Boolean; + -- unspecified + Reserved_27_29 : HAL.UInt3; + -- Read-only. Temperature Change (cleared on read) + TEMPCHG : Boolean; + -- unspecified + Reserved_31_31 : HAL.Bit; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for AFEC_AFEC_ISR_Register use record + EOC at 0 range 0 .. 11; + Reserved_12_23 at 0 range 12 .. 23; + DRDY at 0 range 24 .. 24; + GOVRE at 0 range 25 .. 25; + COMPE at 0 range 26 .. 26; + Reserved_27_29 at 0 range 27 .. 29; + TEMPCHG at 0 range 30 .. 30; + Reserved_31_31 at 0 range 31 .. 31; + end record; + + -- AFEC_AFEC_OVER_OVRE array + type AFEC_AFEC_OVER_OVRE_Field_Array is array (0 .. 11) of Boolean + with Component_Size => 1, Size => 12; + + -- Type definition for AFEC_AFEC_OVER_OVRE + type AFEC_AFEC_OVER_OVRE_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- OVRE as a value + Val : HAL.UInt12; + when True => + -- OVRE as an array + Arr : AFEC_AFEC_OVER_OVRE_Field_Array; + end case; + end record + with Unchecked_Union, Size => 12; + + for AFEC_AFEC_OVER_OVRE_Field use record + Val at 0 range 0 .. 11; + Arr at 0 range 0 .. 11; + end record; + + -- AFEC Overrun Status Register + type AFEC_AFEC_OVER_Register is record + -- Read-only. Overrun Error 0 + OVRE : AFEC_AFEC_OVER_OVRE_Field; + -- unspecified + Reserved_12_31 : HAL.UInt20; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for AFEC_AFEC_OVER_Register use record + OVRE at 0 range 0 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + subtype AFEC_AFEC_CWR_LOWTHRES_Field is HAL.UInt16; + subtype AFEC_AFEC_CWR_HIGHTHRES_Field is HAL.UInt16; + + -- AFEC Compare Window Register + type AFEC_AFEC_CWR_Register is record + -- Low Threshold + LOWTHRES : AFEC_AFEC_CWR_LOWTHRES_Field := 16#0#; + -- High Threshold + HIGHTHRES : AFEC_AFEC_CWR_HIGHTHRES_Field := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for AFEC_AFEC_CWR_Register use record + LOWTHRES at 0 range 0 .. 15; + HIGHTHRES at 0 range 16 .. 31; + end record; + + -- AFEC_AFEC_CGR_GAIN array element + subtype AFEC_AFEC_CGR_GAIN_Element is HAL.UInt2; + + -- AFEC_AFEC_CGR_GAIN array + type AFEC_AFEC_CGR_GAIN_Field_Array is array (0 .. 11) + of AFEC_AFEC_CGR_GAIN_Element + with Component_Size => 2, Size => 24; + + -- Type definition for AFEC_AFEC_CGR_GAIN + type AFEC_AFEC_CGR_GAIN_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- GAIN as a value + Val : HAL.UInt24; + when True => + -- GAIN as an array + Arr : AFEC_AFEC_CGR_GAIN_Field_Array; + end case; + end record + with Unchecked_Union, Size => 24; + + for AFEC_AFEC_CGR_GAIN_Field use record + Val at 0 range 0 .. 23; + Arr at 0 range 0 .. 23; + end record; + + -- AFEC Channel Gain Register + type AFEC_AFEC_CGR_Register is record + -- Gain for Channel 0 + GAIN : AFEC_AFEC_CGR_GAIN_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for AFEC_AFEC_CGR_Register use record + GAIN at 0 range 0 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- AFEC_AFEC_DIFFR_DIFF array + type AFEC_AFEC_DIFFR_DIFF_Field_Array is array (0 .. 11) of Boolean + with Component_Size => 1, Size => 12; + + -- Type definition for AFEC_AFEC_DIFFR_DIFF + type AFEC_AFEC_DIFFR_DIFF_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- DIFF as a value + Val : HAL.UInt12; + when True => + -- DIFF as an array + Arr : AFEC_AFEC_DIFFR_DIFF_Field_Array; + end case; + end record + with Unchecked_Union, Size => 12; + + for AFEC_AFEC_DIFFR_DIFF_Field use record + Val at 0 range 0 .. 11; + Arr at 0 range 0 .. 11; + end record; + + -- AFEC Channel Differential Register + type AFEC_AFEC_DIFFR_Register is record + -- Differential inputs for channel 0 + DIFF : AFEC_AFEC_DIFFR_DIFF_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_12_31 : HAL.UInt20 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for AFEC_AFEC_DIFFR_Register use record + DIFF at 0 range 0 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + subtype AFEC_AFEC_CSELR_CSEL_Field is HAL.UInt4; + + -- AFEC Channel Selection Register + type AFEC_AFEC_CSELR_Register is record + -- Channel Selection + CSEL : AFEC_AFEC_CSELR_CSEL_Field := 16#0#; + -- unspecified + Reserved_4_31 : HAL.UInt28 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for AFEC_AFEC_CSELR_Register use record + CSEL at 0 range 0 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + subtype AFEC_AFEC_CDR_DATA_Field is HAL.UInt16; + + -- AFEC Channel Data Register + type AFEC_AFEC_CDR_Register is record + -- Read-only. Converted Data + DATA : AFEC_AFEC_CDR_DATA_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for AFEC_AFEC_CDR_Register use record + DATA at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype AFEC_AFEC_COCR_AOFF_Field is HAL.UInt10; + + -- AFEC Channel Offset Compensation Register + type AFEC_AFEC_COCR_Register is record + -- Analog Offset + AOFF : AFEC_AFEC_COCR_AOFF_Field := 16#0#; + -- unspecified + Reserved_10_31 : HAL.UInt22 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for AFEC_AFEC_COCR_Register use record + AOFF at 0 range 0 .. 9; + Reserved_10_31 at 0 range 10 .. 31; + end record; + + -- Temperature Comparison Mode + type AFEC_TEMPMR_TEMPCMPMOD_Field is + ( + -- Generates an event when the converted data is lower than the low + -- threshold of the window. + Low, + -- Generates an event when the converted data is higher than the high + -- threshold of the window. + High, + -- Generates an event when the converted data is in the comparison + -- window. + In_k, + -- Generates an event when the converted data is out of the comparison + -- window. + Out_k) + with Size => 2; + for AFEC_TEMPMR_TEMPCMPMOD_Field use + (Low => 0, + High => 1, + In_k => 2, + Out_k => 3); + + -- AFEC Temperature Sensor Mode Register + type AFEC_AFEC_TEMPMR_Register is record + -- Temperature Sensor RTC Trigger Mode + RTCT : Boolean := False; + -- unspecified + Reserved_1_3 : HAL.UInt3 := 16#0#; + -- Temperature Comparison Mode + TEMPCMPMOD : AFEC_TEMPMR_TEMPCMPMOD_Field := SAM_SVD.AFEC.Low; + -- unspecified + Reserved_6_31 : HAL.UInt26 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for AFEC_AFEC_TEMPMR_Register use record + RTCT at 0 range 0 .. 0; + Reserved_1_3 at 0 range 1 .. 3; + TEMPCMPMOD at 0 range 4 .. 5; + Reserved_6_31 at 0 range 6 .. 31; + end record; + + subtype AFEC_AFEC_TEMPCWR_TLOWTHRES_Field is HAL.UInt16; + subtype AFEC_AFEC_TEMPCWR_THIGHTHRES_Field is HAL.UInt16; + + -- AFEC Temperature Compare Window Register + type AFEC_AFEC_TEMPCWR_Register is record + -- Temperature Low Threshold + TLOWTHRES : AFEC_AFEC_TEMPCWR_TLOWTHRES_Field := 16#0#; + -- Temperature High Threshold + THIGHTHRES : AFEC_AFEC_TEMPCWR_THIGHTHRES_Field := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for AFEC_AFEC_TEMPCWR_Register use record + TLOWTHRES at 0 range 0 .. 15; + THIGHTHRES at 0 range 16 .. 31; + end record; + + subtype AFEC_AFEC_ACR_IBCTL_Field is HAL.UInt2; + + -- AFEC Analog Control Register + type AFEC_AFEC_ACR_Register is record + -- unspecified + Reserved_0_1 : HAL.UInt2 := 16#0#; + -- PGA0 Enable + PGA0EN : Boolean := False; + -- PGA1 Enable + PGA1EN : Boolean := False; + -- unspecified + Reserved_4_7 : HAL.UInt4 := 16#0#; + -- AFE Bias Current Control + IBCTL : AFEC_AFEC_ACR_IBCTL_Field := 16#0#; + -- unspecified + Reserved_10_31 : HAL.UInt22 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for AFEC_AFEC_ACR_Register use record + Reserved_0_1 at 0 range 0 .. 1; + PGA0EN at 0 range 2 .. 2; + PGA1EN at 0 range 3 .. 3; + Reserved_4_7 at 0 range 4 .. 7; + IBCTL at 0 range 8 .. 9; + Reserved_10_31 at 0 range 10 .. 31; + end record; + + -- AFEC_AFEC_SHMR_DUAL array + type AFEC_AFEC_SHMR_DUAL_Field_Array is array (0 .. 11) of Boolean + with Component_Size => 1, Size => 12; + + -- Type definition for AFEC_AFEC_SHMR_DUAL + type AFEC_AFEC_SHMR_DUAL_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- DUAL as a value + Val : HAL.UInt12; + when True => + -- DUAL as an array + Arr : AFEC_AFEC_SHMR_DUAL_Field_Array; + end case; + end record + with Unchecked_Union, Size => 12; + + for AFEC_AFEC_SHMR_DUAL_Field use record + Val at 0 range 0 .. 11; + Arr at 0 range 0 .. 11; + end record; + + -- AFEC Sample & Hold Mode Register + type AFEC_AFEC_SHMR_Register is record + -- Dual Sample & Hold for channel 0 + DUAL : AFEC_AFEC_SHMR_DUAL_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_12_31 : HAL.UInt20 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for AFEC_AFEC_SHMR_Register use record + DUAL at 0 range 0 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + -- AFEC Correction Select Register + type AFEC_AFEC_COSR_Register is record + -- Sample & Hold unit Correction Select + CSEL : Boolean := False; + -- unspecified + Reserved_1_31 : HAL.UInt31 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for AFEC_AFEC_COSR_Register use record + CSEL at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + subtype AFEC_AFEC_CVR_OFFSETCORR_Field is HAL.UInt16; + subtype AFEC_AFEC_CVR_GAINCORR_Field is HAL.UInt16; + + -- AFEC Correction Values Register + type AFEC_AFEC_CVR_Register is record + -- Offset Correction + OFFSETCORR : AFEC_AFEC_CVR_OFFSETCORR_Field := 16#0#; + -- Gain Correction + GAINCORR : AFEC_AFEC_CVR_GAINCORR_Field := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for AFEC_AFEC_CVR_Register use record + OFFSETCORR at 0 range 0 .. 15; + GAINCORR at 0 range 16 .. 31; + end record; + + -- AFEC_AFEC_CECR_ECORR array + type AFEC_AFEC_CECR_ECORR_Field_Array is array (0 .. 11) of Boolean + with Component_Size => 1, Size => 12; + + -- Type definition for AFEC_AFEC_CECR_ECORR + type AFEC_AFEC_CECR_ECORR_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- ECORR as a value + Val : HAL.UInt12; + when True => + -- ECORR as an array + Arr : AFEC_AFEC_CECR_ECORR_Field_Array; + end case; + end record + with Unchecked_Union, Size => 12; + + for AFEC_AFEC_CECR_ECORR_Field use record + Val at 0 range 0 .. 11; + Arr at 0 range 0 .. 11; + end record; + + -- AFEC Channel Error Correction Register + type AFEC_AFEC_CECR_Register is record + -- Error Correction Enable for channel 0 + ECORR : AFEC_AFEC_CECR_ECORR_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_12_31 : HAL.UInt20 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for AFEC_AFEC_CECR_Register use record + ECORR at 0 range 0 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + -- Write Protect KEY + type AFEC_WPMR_WPKEY_Field is + ( + -- Reset value for the field + Afec_Wpmr_Wpkey_Field_Reset, + -- Writing any other value in this field aborts the write operation of + -- the WPEN bit. Always reads as 0. + Passwd) + with Size => 24; + for AFEC_WPMR_WPKEY_Field use + (Afec_Wpmr_Wpkey_Field_Reset => 0, + Passwd => 4277315); + + -- AFEC Write Protection Mode Register + type AFEC_AFEC_WPMR_Register is record + -- Write Protection Enable + WPEN : Boolean := False; + -- unspecified + Reserved_1_7 : HAL.UInt7 := 16#0#; + -- Write Protect KEY + WPKEY : AFEC_WPMR_WPKEY_Field := Afec_Wpmr_Wpkey_Field_Reset; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for AFEC_AFEC_WPMR_Register use record + WPEN at 0 range 0 .. 0; + Reserved_1_7 at 0 range 1 .. 7; + WPKEY at 0 range 8 .. 31; + end record; + + subtype AFEC_AFEC_WPSR_WPVSRC_Field is HAL.UInt16; + + -- AFEC Write Protection Status Register + type AFEC_AFEC_WPSR_Register is record + -- Read-only. Write Protect Violation Status + WPVS : Boolean; + -- unspecified + Reserved_1_7 : HAL.UInt7; + -- Read-only. Write Protect Violation Source + WPVSRC : AFEC_AFEC_WPSR_WPVSRC_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for AFEC_AFEC_WPSR_Register use record + WPVS at 0 range 0 .. 0; + Reserved_1_7 at 0 range 1 .. 7; + WPVSRC at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype AFEC_AFEC_VERSION_VERSION_Field is HAL.UInt12; + subtype AFEC_AFEC_VERSION_MFN_Field is HAL.UInt3; + + -- AFEC Version Register + type AFEC_AFEC_VERSION_Register is record + -- Read-only. Version of the Hardware Module + VERSION : AFEC_AFEC_VERSION_VERSION_Field; + -- unspecified + Reserved_12_15 : HAL.UInt4; + -- Read-only. Metal Fix Number + MFN : AFEC_AFEC_VERSION_MFN_Field; + -- unspecified + Reserved_19_31 : HAL.UInt13; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for AFEC_AFEC_VERSION_Register use record + VERSION at 0 range 0 .. 11; + Reserved_12_15 at 0 range 12 .. 15; + MFN at 0 range 16 .. 18; + Reserved_19_31 at 0 range 19 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- Analog Front-End Controller + type AFEC_Peripheral is record + -- AFEC Control Register + AFEC_CR : aliased AFEC_AFEC_CR_Register; + -- AFEC Mode Register + AFEC_MR : aliased AFEC_AFEC_MR_Register; + -- AFEC Extended Mode Register + AFEC_EMR : aliased AFEC_AFEC_EMR_Register; + -- AFEC Channel Sequence 1 Register + AFEC_SEQ1R : aliased AFEC_AFEC_SEQ1R_Register; + -- AFEC Channel Sequence 2 Register + AFEC_SEQ2R : aliased AFEC_AFEC_SEQ2R_Register; + -- AFEC Channel Enable Register + AFEC_CHER : aliased AFEC_AFEC_CHER_Register; + -- AFEC Channel Disable Register + AFEC_CHDR : aliased AFEC_AFEC_CHDR_Register; + -- AFEC Channel Status Register + AFEC_CHSR : aliased AFEC_AFEC_CHSR_Register; + -- AFEC Last Converted Data Register + AFEC_LCDR : aliased AFEC_AFEC_LCDR_Register; + -- AFEC Interrupt Enable Register + AFEC_IER : aliased AFEC_AFEC_IER_Register; + -- AFEC Interrupt Disable Register + AFEC_IDR : aliased AFEC_AFEC_IDR_Register; + -- AFEC Interrupt Mask Register + AFEC_IMR : aliased AFEC_AFEC_IMR_Register; + -- AFEC Interrupt Status Register + AFEC_ISR : aliased AFEC_AFEC_ISR_Register; + -- AFEC Overrun Status Register + AFEC_OVER : aliased AFEC_AFEC_OVER_Register; + -- AFEC Compare Window Register + AFEC_CWR : aliased AFEC_AFEC_CWR_Register; + -- AFEC Channel Gain Register + AFEC_CGR : aliased AFEC_AFEC_CGR_Register; + -- AFEC Channel Differential Register + AFEC_DIFFR : aliased AFEC_AFEC_DIFFR_Register; + -- AFEC Channel Selection Register + AFEC_CSELR : aliased AFEC_AFEC_CSELR_Register; + -- AFEC Channel Data Register + AFEC_CDR : aliased AFEC_AFEC_CDR_Register; + -- AFEC Channel Offset Compensation Register + AFEC_COCR : aliased AFEC_AFEC_COCR_Register; + -- AFEC Temperature Sensor Mode Register + AFEC_TEMPMR : aliased AFEC_AFEC_TEMPMR_Register; + -- AFEC Temperature Compare Window Register + AFEC_TEMPCWR : aliased AFEC_AFEC_TEMPCWR_Register; + -- AFEC Analog Control Register + AFEC_ACR : aliased AFEC_AFEC_ACR_Register; + -- AFEC Sample & Hold Mode Register + AFEC_SHMR : aliased AFEC_AFEC_SHMR_Register; + -- AFEC Correction Select Register + AFEC_COSR : aliased AFEC_AFEC_COSR_Register; + -- AFEC Correction Values Register + AFEC_CVR : aliased AFEC_AFEC_CVR_Register; + -- AFEC Channel Error Correction Register + AFEC_CECR : aliased AFEC_AFEC_CECR_Register; + -- AFEC Write Protection Mode Register + AFEC_WPMR : aliased AFEC_AFEC_WPMR_Register; + -- AFEC Write Protection Status Register + AFEC_WPSR : aliased AFEC_AFEC_WPSR_Register; + -- AFEC Version Register + AFEC_VERSION : aliased AFEC_AFEC_VERSION_Register; + end record + with Volatile; + + for AFEC_Peripheral use record + AFEC_CR at 16#0# range 0 .. 31; + AFEC_MR at 16#4# range 0 .. 31; + AFEC_EMR at 16#8# range 0 .. 31; + AFEC_SEQ1R at 16#C# range 0 .. 31; + AFEC_SEQ2R at 16#10# range 0 .. 31; + AFEC_CHER at 16#14# range 0 .. 31; + AFEC_CHDR at 16#18# range 0 .. 31; + AFEC_CHSR at 16#1C# range 0 .. 31; + AFEC_LCDR at 16#20# range 0 .. 31; + AFEC_IER at 16#24# range 0 .. 31; + AFEC_IDR at 16#28# range 0 .. 31; + AFEC_IMR at 16#2C# range 0 .. 31; + AFEC_ISR at 16#30# range 0 .. 31; + AFEC_OVER at 16#4C# range 0 .. 31; + AFEC_CWR at 16#50# range 0 .. 31; + AFEC_CGR at 16#54# range 0 .. 31; + AFEC_DIFFR at 16#60# range 0 .. 31; + AFEC_CSELR at 16#64# range 0 .. 31; + AFEC_CDR at 16#68# range 0 .. 31; + AFEC_COCR at 16#6C# range 0 .. 31; + AFEC_TEMPMR at 16#70# range 0 .. 31; + AFEC_TEMPCWR at 16#74# range 0 .. 31; + AFEC_ACR at 16#94# range 0 .. 31; + AFEC_SHMR at 16#A0# range 0 .. 31; + AFEC_COSR at 16#D0# range 0 .. 31; + AFEC_CVR at 16#D4# range 0 .. 31; + AFEC_CECR at 16#D8# range 0 .. 31; + AFEC_WPMR at 16#E4# range 0 .. 31; + AFEC_WPSR at 16#E8# range 0 .. 31; + AFEC_VERSION at 16#FC# range 0 .. 31; + end record; + + -- Analog Front-End Controller + AFEC0_Periph : aliased AFEC_Peripheral + with Import, Address => System'To_Address (16#4003C000#); + + -- Analog Front-End Controller + AFEC1_Periph : aliased AFEC_Peripheral + with Import, Address => System'To_Address (16#40064000#); + +end SAM_SVD.AFEC; diff --git a/arch/ARM/SAM/svd/atsamv71/sam_svd-chipid.ads b/arch/ARM/SAM/svd/atsamv71/sam_svd-chipid.ads new file mode 100644 index 000000000..e7f7b80b5 --- /dev/null +++ b/arch/ARM/SAM/svd/atsamv71/sam_svd-chipid.ads @@ -0,0 +1,264 @@ +-- This spec has been automatically generated from ATSAMV71Q21.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package SAM_SVD.CHIPID is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + subtype CHIPID_CHIPID_CIDR_VERSION_Field is HAL.UInt5; + + -- Embedded Processor + type CHIPID_CIDR_EPROC_Field is + ( + -- Cortex-M7 + Samx7, + -- ARM946ES + Arm946Es, + -- ARM7TDMI + Arm7Tdmi, + -- Cortex-M3 + Cm3, + -- ARM920T + Arm920T, + -- ARM926EJS + Arm926Ejs, + -- Cortex-A5 + Ca5, + -- Cortex-M4 + Cm4) + with Size => 3; + for CHIPID_CIDR_EPROC_Field use + (Samx7 => 0, + Arm946Es => 1, + Arm7Tdmi => 2, + Cm3 => 3, + Arm920T => 4, + Arm926Ejs => 5, + Ca5 => 6, + Cm4 => 7); + + -- Nonvolatile Program Memory Size + type CHIPID_CIDR_NVPSIZ_Field is + ( + -- None + None, + -- 8 Kbytes + Val_8K, + -- 16 Kbytes + Val_16K, + -- 32 Kbytes + Val_32K, + -- 64 Kbytes + Val_64K, + -- 128 Kbytes + Val_128K, + -- 160 Kbytes + Val_160K, + -- 256 Kbytes + Val_256K, + -- 512 Kbytes + Val_512K, + -- 1024 Kbytes + Val_1024K, + -- 2048 Kbytes + Val_2048K) + with Size => 4; + for CHIPID_CIDR_NVPSIZ_Field use + (None => 0, + Val_8K => 1, + Val_16K => 2, + Val_32K => 3, + Val_64K => 5, + Val_128K => 7, + Val_160K => 8, + Val_256K => 9, + Val_512K => 10, + Val_1024K => 12, + Val_2048K => 14); + + -- Second Nonvolatile Program Memory Size + type CHIPID_CIDR_NVPSIZ2_Field is + ( + -- None + None, + -- 8 Kbytes + Val_8K, + -- 16 Kbytes + Val_16K, + -- 32 Kbytes + Val_32K, + -- 64 Kbytes + Val_64K, + -- 128 Kbytes + Val_128K, + -- 256 Kbytes + Val_256K, + -- 512 Kbytes + Val_512K, + -- 1024 Kbytes + Val_1024K, + -- 2048 Kbytes + Val_2048K) + with Size => 4; + for CHIPID_CIDR_NVPSIZ2_Field use + (None => 0, + Val_8K => 1, + Val_16K => 2, + Val_32K => 3, + Val_64K => 5, + Val_128K => 7, + Val_256K => 9, + Val_512K => 10, + Val_1024K => 12, + Val_2048K => 14); + + -- Internal SRAM Size + type CHIPID_CIDR_SRAMSIZ_Field is + ( + -- 48 Kbytes + Val_48K, + -- 192 Kbytes + Val_192K, + -- 384 Kbytes + Val_384K, + -- 6 Kbytes + Val_6K, + -- 24 Kbytes + Val_24K, + -- 4 Kbytes + Val_4K, + -- 80 Kbytes + Val_80K, + -- 160 Kbytes + Val_160K, + -- 8 Kbytes + Val_8K, + -- 16 Kbytes + Val_16K, + -- 32 Kbytes + Val_32K, + -- 64 Kbytes + Val_64K, + -- 128 Kbytes + Val_128K, + -- 256 Kbytes + Val_256K, + -- 96 Kbytes + Val_96K, + -- 512 Kbytes + Val_512K) + with Size => 4; + for CHIPID_CIDR_SRAMSIZ_Field use + (Val_48K => 0, + Val_192K => 1, + Val_384K => 2, + Val_6K => 3, + Val_24K => 4, + Val_4K => 5, + Val_80K => 6, + Val_160K => 7, + Val_8K => 8, + Val_16K => 9, + Val_32K => 10, + Val_64K => 11, + Val_128K => 12, + Val_256K => 13, + Val_96K => 14, + Val_512K => 15); + + -- Architecture Identifier + type CHIPID_CIDR_ARCH_Field is + ( + -- SAM V71 + Samv71) + with Size => 8; + for CHIPID_CIDR_ARCH_Field use + (Samv71 => 18); + + -- Nonvolatile Program Memory Type + type CHIPID_CIDR_NVPTYP_Field is + ( + -- ROM + Rom, + -- ROMless or on-chip Flash + Romless, + -- Embedded Flash Memory + Flash, + -- ROM and Embedded Flash Memory- NVPSIZ is ROM size- NVPSIZ2 is Flash + -- size + Rom_Flash, + -- SRAM emulating ROM + Sram) + with Size => 3; + for CHIPID_CIDR_NVPTYP_Field use + (Rom => 0, + Romless => 1, + Flash => 2, + Rom_Flash => 3, + Sram => 4); + + -- Chip ID Register + type CHIPID_CHIPID_CIDR_Register is record + -- Read-only. Version of the Device + VERSION : CHIPID_CHIPID_CIDR_VERSION_Field; + -- Read-only. Embedded Processor + EPROC : CHIPID_CIDR_EPROC_Field; + -- Read-only. Nonvolatile Program Memory Size + NVPSIZ : CHIPID_CIDR_NVPSIZ_Field; + -- Read-only. Second Nonvolatile Program Memory Size + NVPSIZ2 : CHIPID_CIDR_NVPSIZ2_Field; + -- Read-only. Internal SRAM Size + SRAMSIZ : CHIPID_CIDR_SRAMSIZ_Field; + -- Read-only. Architecture Identifier + ARCH : CHIPID_CIDR_ARCH_Field; + -- Read-only. Nonvolatile Program Memory Type + NVPTYP : CHIPID_CIDR_NVPTYP_Field; + -- Read-only. Extension Flag + EXT : Boolean; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for CHIPID_CHIPID_CIDR_Register use record + VERSION at 0 range 0 .. 4; + EPROC at 0 range 5 .. 7; + NVPSIZ at 0 range 8 .. 11; + NVPSIZ2 at 0 range 12 .. 15; + SRAMSIZ at 0 range 16 .. 19; + ARCH at 0 range 20 .. 27; + NVPTYP at 0 range 28 .. 30; + EXT at 0 range 31 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- Chip Identifier + type CHIPID_Peripheral is record + -- Chip ID Register + CHIPID_CIDR : aliased CHIPID_CHIPID_CIDR_Register; + -- Chip ID Extension Register + CHIPID_EXID : aliased HAL.UInt32; + end record + with Volatile; + + for CHIPID_Peripheral use record + CHIPID_CIDR at 16#0# range 0 .. 31; + CHIPID_EXID at 16#4# range 0 .. 31; + end record; + + -- Chip Identifier + CHIPID_Periph : aliased CHIPID_Peripheral + with Import, Address => System'To_Address (16#400E0940#); + +end SAM_SVD.CHIPID; diff --git a/arch/ARM/SAM/svd/atsamv71/sam_svd-dacc.ads b/arch/ARM/SAM/svd/atsamv71/sam_svd-dacc.ads new file mode 100644 index 000000000..dc58fa491 --- /dev/null +++ b/arch/ARM/SAM/svd/atsamv71/sam_svd-dacc.ads @@ -0,0 +1,963 @@ +-- This spec has been automatically generated from ATSAMV71Q21.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package SAM_SVD.DACC is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + -- Control Register + type DACC_DACC_CR_Register is record + -- Write-only. Software Reset + SWRST : Boolean := False; + -- unspecified + Reserved_1_31 : HAL.UInt31 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for DACC_DACC_CR_Register use record + SWRST at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + -- Max Speed Mode for Channel 0 + type DACC_MR_MAXS0_Field is + ( + -- Trigger mode or Free-running mode enabled. (See TRGENx.DACC_TRIGR.) + Trig_Event, + -- Max speed mode enabled. + Maximum) + with Size => 1; + for DACC_MR_MAXS0_Field use + (Trig_Event => 0, + Maximum => 1); + + -- DACC_DACC_MR_MAXS array + type DACC_DACC_MR_MAXS_Field_Array is array (0 .. 1) + of DACC_MR_MAXS0_Field + with Component_Size => 1, Size => 2; + + -- Type definition for DACC_DACC_MR_MAXS + type DACC_DACC_MR_MAXS_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- MAXS as a value + Val : HAL.UInt2; + when True => + -- MAXS as an array + Arr : DACC_DACC_MR_MAXS_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for DACC_DACC_MR_MAXS_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- Word Transfer Mode + type DACC_MR_WORD_Field is + ( + -- One data to convert is written to the FIFO per access to DACC. + Disabled, + -- Two data to convert are written to the FIFO per access to DACC + -- (reduces the number of requests to DMA and the number of system bus + -- accesses). + Enabled) + with Size => 1; + for DACC_MR_WORD_Field use + (Disabled => 0, + Enabled => 1); + + -- Differential Mode + type DACC_MR_DIFF_Field is + ( + -- DAC0 and DAC1 are single-ended outputs. + Disabled, + -- DACP and DACN are differential outputs. The differential level is + -- configured by the channel 0 value. + Enabled) + with Size => 1; + for DACC_MR_DIFF_Field use + (Disabled => 0, + Enabled => 1); + + subtype DACC_DACC_MR_PRESCALER_Field is HAL.UInt4; + + -- Mode Register + type DACC_DACC_MR_Register is record + -- Max Speed Mode for Channel 0 + MAXS : DACC_DACC_MR_MAXS_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_2_3 : HAL.UInt2 := 16#0#; + -- Word Transfer Mode + WORD : DACC_MR_WORD_Field := SAM_SVD.DACC.Disabled; + -- Must always be written to 0. + ZERO : Boolean := False; + -- unspecified + Reserved_6_22 : HAL.UInt17 := 16#0#; + -- Differential Mode + DIFF : DACC_MR_DIFF_Field := SAM_SVD.DACC.Disabled; + -- Peripheral Clock to DAC Clock Ratio + PRESCALER : DACC_DACC_MR_PRESCALER_Field := 16#0#; + -- unspecified + Reserved_28_31 : HAL.UInt4 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for DACC_DACC_MR_Register use record + MAXS at 0 range 0 .. 1; + Reserved_2_3 at 0 range 2 .. 3; + WORD at 0 range 4 .. 4; + ZERO at 0 range 5 .. 5; + Reserved_6_22 at 0 range 6 .. 22; + DIFF at 0 range 23 .. 23; + PRESCALER at 0 range 24 .. 27; + Reserved_28_31 at 0 range 28 .. 31; + end record; + + -- Trigger Enable of Channel 0 + type DACC_TRIGR_TRGEN0_Field is + ( + -- Trigger mode disabled. DACC is in Free-running mode or Max speed + -- mode. + Dis, + -- Trigger mode enabled. + En) + with Size => 1; + for DACC_TRIGR_TRGEN0_Field use + (Dis => 0, + En => 1); + + -- DACC_DACC_TRIGR_TRGEN array + type DACC_DACC_TRIGR_TRGEN_Field_Array is array (0 .. 1) + of DACC_TRIGR_TRGEN0_Field + with Component_Size => 1, Size => 2; + + -- Type definition for DACC_DACC_TRIGR_TRGEN + type DACC_DACC_TRIGR_TRGEN_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- TRGEN as a value + Val : HAL.UInt2; + when True => + -- TRGEN as an array + Arr : DACC_DACC_TRIGR_TRGEN_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for DACC_DACC_TRIGR_TRGEN_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- Trigger Selection of Channel 0 + type DACC_TRIGR_TRGSEL0_Field is + ( + -- DATRG + Trgsel0, + -- TC0 output + Trgsel1, + -- TC1 output + Trgsel2, + -- TC2 output + Trgsel3, + -- PWM0 event 0 + Trgsel4, + -- PWM0 event 1 + Trgsel5, + -- PWM1 event 0 + Trgsel6, + -- PWM1 event 1 + Trgsel7) + with Size => 3; + for DACC_TRIGR_TRGSEL0_Field use + (Trgsel0 => 0, + Trgsel1 => 1, + Trgsel2 => 2, + Trgsel3 => 3, + Trgsel4 => 4, + Trgsel5 => 5, + Trgsel6 => 6, + Trgsel7 => 7); + + -- Trigger Selection of Channel 1 + type DACC_TRIGR_TRGSEL1_Field is + ( + -- DATRG + Trgsel0, + -- TC0 output + Trgsel1, + -- TC1 output + Trgsel2, + -- TC2 output + Trgsel3, + -- PWM0 event 0 + Trgsel4, + -- PWM0 event 1 + Trgsel5, + -- PWM1 event 0 + Trgsel6, + -- PWM1 event 1 + Trgsel7) + with Size => 3; + for DACC_TRIGR_TRGSEL1_Field use + (Trgsel0 => 0, + Trgsel1 => 1, + Trgsel2 => 2, + Trgsel3 => 3, + Trgsel4 => 4, + Trgsel5 => 5, + Trgsel6 => 6, + Trgsel7 => 7); + + -- Over Sampling Ratio of Channel 0 + type DACC_TRIGR_OSR0_Field is + ( + -- OSR = 1 + Osr_1, + -- OSR = 2 + Osr_2, + -- OSR = 4 + Osr_4, + -- OSR = 8 + Osr_8, + -- OSR = 16 + Osr_16, + -- OSR = 32 + Osr_32) + with Size => 3; + for DACC_TRIGR_OSR0_Field use + (Osr_1 => 0, + Osr_2 => 1, + Osr_4 => 2, + Osr_8 => 3, + Osr_16 => 4, + Osr_32 => 5); + + -- Over Sampling Ratio of Channel 1 + type DACC_TRIGR_OSR1_Field is + ( + -- OSR = 1 + Osr_1, + -- OSR = 2 + Osr_2, + -- OSR = 4 + Osr_4, + -- OSR = 8 + Osr_8, + -- OSR = 16 + Osr_16, + -- OSR = 32 + Osr_32) + with Size => 3; + for DACC_TRIGR_OSR1_Field use + (Osr_1 => 0, + Osr_2 => 1, + Osr_4 => 2, + Osr_8 => 3, + Osr_16 => 4, + Osr_32 => 5); + + -- Trigger Register + type DACC_DACC_TRIGR_Register is record + -- Trigger Enable of Channel 0 + TRGEN : DACC_DACC_TRIGR_TRGEN_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_2_3 : HAL.UInt2 := 16#0#; + -- Trigger Selection of Channel 0 + TRGSEL0 : DACC_TRIGR_TRGSEL0_Field := SAM_SVD.DACC.Trgsel0; + -- unspecified + Reserved_7_7 : HAL.Bit := 16#0#; + -- Trigger Selection of Channel 1 + TRGSEL1 : DACC_TRIGR_TRGSEL1_Field := SAM_SVD.DACC.Trgsel0; + -- unspecified + Reserved_11_15 : HAL.UInt5 := 16#0#; + -- Over Sampling Ratio of Channel 0 + OSR0 : DACC_TRIGR_OSR0_Field := SAM_SVD.DACC.Osr_1; + -- unspecified + Reserved_19_19 : HAL.Bit := 16#0#; + -- Over Sampling Ratio of Channel 1 + OSR1 : DACC_TRIGR_OSR1_Field := SAM_SVD.DACC.Osr_1; + -- unspecified + Reserved_23_31 : HAL.UInt9 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for DACC_DACC_TRIGR_Register use record + TRGEN at 0 range 0 .. 1; + Reserved_2_3 at 0 range 2 .. 3; + TRGSEL0 at 0 range 4 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + TRGSEL1 at 0 range 8 .. 10; + Reserved_11_15 at 0 range 11 .. 15; + OSR0 at 0 range 16 .. 18; + Reserved_19_19 at 0 range 19 .. 19; + OSR1 at 0 range 20 .. 22; + Reserved_23_31 at 0 range 23 .. 31; + end record; + + -- DACC_DACC_CHER_CH array + type DACC_DACC_CHER_CH_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for DACC_DACC_CHER_CH + type DACC_DACC_CHER_CH_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CH as a value + Val : HAL.UInt2; + when True => + -- CH as an array + Arr : DACC_DACC_CHER_CH_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for DACC_DACC_CHER_CH_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- Channel Enable Register + type DACC_DACC_CHER_Register is record + -- Write-only. Channel 0 Enable + CH : DACC_DACC_CHER_CH_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_2_31 : HAL.UInt30 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for DACC_DACC_CHER_Register use record + CH at 0 range 0 .. 1; + Reserved_2_31 at 0 range 2 .. 31; + end record; + + -- DACC_DACC_CHDR_CH array + type DACC_DACC_CHDR_CH_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for DACC_DACC_CHDR_CH + type DACC_DACC_CHDR_CH_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CH as a value + Val : HAL.UInt2; + when True => + -- CH as an array + Arr : DACC_DACC_CHDR_CH_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for DACC_DACC_CHDR_CH_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- Channel Disable Register + type DACC_DACC_CHDR_Register is record + -- Write-only. Channel 0 Disable + CH : DACC_DACC_CHDR_CH_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_2_31 : HAL.UInt30 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for DACC_DACC_CHDR_Register use record + CH at 0 range 0 .. 1; + Reserved_2_31 at 0 range 2 .. 31; + end record; + + -- DACC_DACC_CHSR_CH array + type DACC_DACC_CHSR_CH_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for DACC_DACC_CHSR_CH + type DACC_DACC_CHSR_CH_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CH as a value + Val : HAL.UInt2; + when True => + -- CH as an array + Arr : DACC_DACC_CHSR_CH_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for DACC_DACC_CHSR_CH_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- DACC_DACC_CHSR_DACRDY array + type DACC_DACC_CHSR_DACRDY_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for DACC_DACC_CHSR_DACRDY + type DACC_DACC_CHSR_DACRDY_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- DACRDY as a value + Val : HAL.UInt2; + when True => + -- DACRDY as an array + Arr : DACC_DACC_CHSR_DACRDY_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for DACC_DACC_CHSR_DACRDY_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- Channel Status Register + type DACC_DACC_CHSR_Register is record + -- Read-only. Channel 0 Status + CH : DACC_DACC_CHSR_CH_Field; + -- unspecified + Reserved_2_7 : HAL.UInt6; + -- Read-only. DAC Ready Flag + DACRDY : DACC_DACC_CHSR_DACRDY_Field; + -- unspecified + Reserved_10_31 : HAL.UInt22; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for DACC_DACC_CHSR_Register use record + CH at 0 range 0 .. 1; + Reserved_2_7 at 0 range 2 .. 7; + DACRDY at 0 range 8 .. 9; + Reserved_10_31 at 0 range 10 .. 31; + end record; + + -- DACC_DACC_CDR_DATA array element + subtype DACC_DACC_CDR_DATA_Element is HAL.UInt16; + + -- DACC_DACC_CDR_DATA array + type DACC_DACC_CDR_DATA_Field_Array is array (0 .. 1) + of DACC_DACC_CDR_DATA_Element + with Component_Size => 16, Size => 32; + + -- Conversion Data Register 0 + type DACC_DACC_CDR_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- DATA as a value + Val : HAL.UInt32; + when True => + -- DATA as an array + Arr : DACC_DACC_CDR_DATA_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, + Bit_Order => System.Low_Order_First; + + for DACC_DACC_CDR_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- Conversion Data Register 0 + type DACC_DACC_CDR_Registers is array (0 .. 1) of DACC_DACC_CDR_Register + with Volatile; + + -- DACC_DACC_IER_TXRDY array + type DACC_DACC_IER_TXRDY_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for DACC_DACC_IER_TXRDY + type DACC_DACC_IER_TXRDY_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- TXRDY as a value + Val : HAL.UInt2; + when True => + -- TXRDY as an array + Arr : DACC_DACC_IER_TXRDY_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for DACC_DACC_IER_TXRDY_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- DACC_DACC_IER_EOC array + type DACC_DACC_IER_EOC_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for DACC_DACC_IER_EOC + type DACC_DACC_IER_EOC_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- EOC as a value + Val : HAL.UInt2; + when True => + -- EOC as an array + Arr : DACC_DACC_IER_EOC_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for DACC_DACC_IER_EOC_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- Interrupt Enable Register + type DACC_DACC_IER_Register is record + -- Write-only. Transmit Ready Interrupt Enable of channel 0 + TXRDY : DACC_DACC_IER_TXRDY_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_2_3 : HAL.UInt2 := 16#0#; + -- Write-only. End of Conversion Interrupt Enable of channel 0 + EOC : DACC_DACC_IER_EOC_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_6_31 : HAL.UInt26 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for DACC_DACC_IER_Register use record + TXRDY at 0 range 0 .. 1; + Reserved_2_3 at 0 range 2 .. 3; + EOC at 0 range 4 .. 5; + Reserved_6_31 at 0 range 6 .. 31; + end record; + + -- DACC_DACC_IDR_TXRDY array + type DACC_DACC_IDR_TXRDY_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for DACC_DACC_IDR_TXRDY + type DACC_DACC_IDR_TXRDY_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- TXRDY as a value + Val : HAL.UInt2; + when True => + -- TXRDY as an array + Arr : DACC_DACC_IDR_TXRDY_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for DACC_DACC_IDR_TXRDY_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- DACC_DACC_IDR_EOC array + type DACC_DACC_IDR_EOC_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for DACC_DACC_IDR_EOC + type DACC_DACC_IDR_EOC_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- EOC as a value + Val : HAL.UInt2; + when True => + -- EOC as an array + Arr : DACC_DACC_IDR_EOC_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for DACC_DACC_IDR_EOC_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- Interrupt Disable Register + type DACC_DACC_IDR_Register is record + -- Write-only. Transmit Ready Interrupt Disable of channel 0 + TXRDY : DACC_DACC_IDR_TXRDY_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_2_3 : HAL.UInt2 := 16#0#; + -- Write-only. End of Conversion Interrupt Disable of channel 0 + EOC : DACC_DACC_IDR_EOC_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_6_31 : HAL.UInt26 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for DACC_DACC_IDR_Register use record + TXRDY at 0 range 0 .. 1; + Reserved_2_3 at 0 range 2 .. 3; + EOC at 0 range 4 .. 5; + Reserved_6_31 at 0 range 6 .. 31; + end record; + + -- DACC_DACC_IMR_TXRDY array + type DACC_DACC_IMR_TXRDY_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for DACC_DACC_IMR_TXRDY + type DACC_DACC_IMR_TXRDY_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- TXRDY as a value + Val : HAL.UInt2; + when True => + -- TXRDY as an array + Arr : DACC_DACC_IMR_TXRDY_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for DACC_DACC_IMR_TXRDY_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- DACC_DACC_IMR_EOC array + type DACC_DACC_IMR_EOC_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for DACC_DACC_IMR_EOC + type DACC_DACC_IMR_EOC_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- EOC as a value + Val : HAL.UInt2; + when True => + -- EOC as an array + Arr : DACC_DACC_IMR_EOC_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for DACC_DACC_IMR_EOC_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- Interrupt Mask Register + type DACC_DACC_IMR_Register is record + -- Read-only. Transmit Ready Interrupt Mask of channel 0 + TXRDY : DACC_DACC_IMR_TXRDY_Field; + -- unspecified + Reserved_2_3 : HAL.UInt2; + -- Read-only. End of Conversion Interrupt Mask of channel 0 + EOC : DACC_DACC_IMR_EOC_Field; + -- unspecified + Reserved_6_31 : HAL.UInt26; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for DACC_DACC_IMR_Register use record + TXRDY at 0 range 0 .. 1; + Reserved_2_3 at 0 range 2 .. 3; + EOC at 0 range 4 .. 5; + Reserved_6_31 at 0 range 6 .. 31; + end record; + + -- DACC_DACC_ISR_TXRDY array + type DACC_DACC_ISR_TXRDY_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for DACC_DACC_ISR_TXRDY + type DACC_DACC_ISR_TXRDY_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- TXRDY as a value + Val : HAL.UInt2; + when True => + -- TXRDY as an array + Arr : DACC_DACC_ISR_TXRDY_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for DACC_DACC_ISR_TXRDY_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- DACC_DACC_ISR_EOC array + type DACC_DACC_ISR_EOC_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for DACC_DACC_ISR_EOC + type DACC_DACC_ISR_EOC_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- EOC as a value + Val : HAL.UInt2; + when True => + -- EOC as an array + Arr : DACC_DACC_ISR_EOC_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for DACC_DACC_ISR_EOC_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- Interrupt Status Register + type DACC_DACC_ISR_Register is record + -- Read-only. Transmit Ready Interrupt Flag of channel 0 + TXRDY : DACC_DACC_ISR_TXRDY_Field; + -- unspecified + Reserved_2_3 : HAL.UInt2; + -- Read-only. End of Conversion Interrupt Flag of channel 0 + EOC : DACC_DACC_ISR_EOC_Field; + -- unspecified + Reserved_6_31 : HAL.UInt26; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for DACC_DACC_ISR_Register use record + TXRDY at 0 range 0 .. 1; + Reserved_2_3 at 0 range 2 .. 3; + EOC at 0 range 4 .. 5; + Reserved_6_31 at 0 range 6 .. 31; + end record; + + -- DACC_DACC_ACR_IBCTLCH array element + subtype DACC_DACC_ACR_IBCTLCH_Element is HAL.UInt2; + + -- DACC_DACC_ACR_IBCTLCH array + type DACC_DACC_ACR_IBCTLCH_Field_Array is array (0 .. 1) + of DACC_DACC_ACR_IBCTLCH_Element + with Component_Size => 2, Size => 4; + + -- Type definition for DACC_DACC_ACR_IBCTLCH + type DACC_DACC_ACR_IBCTLCH_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- IBCTLCH as a value + Val : HAL.UInt4; + when True => + -- IBCTLCH as an array + Arr : DACC_DACC_ACR_IBCTLCH_Field_Array; + end case; + end record + with Unchecked_Union, Size => 4; + + for DACC_DACC_ACR_IBCTLCH_Field use record + Val at 0 range 0 .. 3; + Arr at 0 range 0 .. 3; + end record; + + -- Analog Current Register + type DACC_DACC_ACR_Register is record + -- Analog Output Current Control + IBCTLCH : DACC_DACC_ACR_IBCTLCH_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_4_31 : HAL.UInt28 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for DACC_DACC_ACR_Register use record + IBCTLCH at 0 range 0 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + -- Write Protect Key + type DACC_WPMR_WPKEY_Field is + ( + -- Reset value for the field + Dacc_Wpmr_Wpkey_Field_Reset, + -- Writing any other value in this field aborts the write operation of + -- bit WPEN.Always reads as 0. + Passwd) + with Size => 24; + for DACC_WPMR_WPKEY_Field use + (Dacc_Wpmr_Wpkey_Field_Reset => 0, + Passwd => 4473155); + + -- Write Protection Mode Register + type DACC_DACC_WPMR_Register is record + -- Write Protection Enable + WPEN : Boolean := False; + -- unspecified + Reserved_1_7 : HAL.UInt7 := 16#0#; + -- Write Protect Key + WPKEY : DACC_WPMR_WPKEY_Field := Dacc_Wpmr_Wpkey_Field_Reset; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for DACC_DACC_WPMR_Register use record + WPEN at 0 range 0 .. 0; + Reserved_1_7 at 0 range 1 .. 7; + WPKEY at 0 range 8 .. 31; + end record; + + subtype DACC_DACC_WPSR_WPVSRC_Field is HAL.UInt8; + + -- Write Protection Status Register + type DACC_DACC_WPSR_Register is record + -- Read-only. Write Protection Violation Status + WPVS : Boolean; + -- unspecified + Reserved_1_7 : HAL.UInt7; + -- Read-only. Write Protection Violation Source + WPVSRC : DACC_DACC_WPSR_WPVSRC_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for DACC_DACC_WPSR_Register use record + WPVS at 0 range 0 .. 0; + Reserved_1_7 at 0 range 1 .. 7; + WPVSRC at 0 range 8 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype DACC_DACC_VERSION_VERSION_Field is HAL.UInt12; + subtype DACC_DACC_VERSION_MFN_Field is HAL.UInt3; + + -- Version Register + type DACC_DACC_VERSION_Register is record + -- Read-only. Version + VERSION : DACC_DACC_VERSION_VERSION_Field; + -- unspecified + Reserved_12_15 : HAL.UInt4; + -- Read-only. Metal Fix Number + MFN : DACC_DACC_VERSION_MFN_Field; + -- unspecified + Reserved_19_31 : HAL.UInt13; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for DACC_DACC_VERSION_Register use record + VERSION at 0 range 0 .. 11; + Reserved_12_15 at 0 range 12 .. 15; + MFN at 0 range 16 .. 18; + Reserved_19_31 at 0 range 19 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- Digital-to-Analog Converter Controller + type DACC_Peripheral is record + -- Control Register + DACC_CR : aliased DACC_DACC_CR_Register; + -- Mode Register + DACC_MR : aliased DACC_DACC_MR_Register; + -- Trigger Register + DACC_TRIGR : aliased DACC_DACC_TRIGR_Register; + -- Channel Enable Register + DACC_CHER : aliased DACC_DACC_CHER_Register; + -- Channel Disable Register + DACC_CHDR : aliased DACC_DACC_CHDR_Register; + -- Channel Status Register + DACC_CHSR : aliased DACC_DACC_CHSR_Register; + -- Conversion Data Register 0 + DACC_CDR : aliased DACC_DACC_CDR_Registers; + -- Interrupt Enable Register + DACC_IER : aliased DACC_DACC_IER_Register; + -- Interrupt Disable Register + DACC_IDR : aliased DACC_DACC_IDR_Register; + -- Interrupt Mask Register + DACC_IMR : aliased DACC_DACC_IMR_Register; + -- Interrupt Status Register + DACC_ISR : aliased DACC_DACC_ISR_Register; + -- Analog Current Register + DACC_ACR : aliased DACC_DACC_ACR_Register; + -- Write Protection Mode Register + DACC_WPMR : aliased DACC_DACC_WPMR_Register; + -- Write Protection Status Register + DACC_WPSR : aliased DACC_DACC_WPSR_Register; + -- Version Register + DACC_VERSION : aliased DACC_DACC_VERSION_Register; + end record + with Volatile; + + for DACC_Peripheral use record + DACC_CR at 16#0# range 0 .. 31; + DACC_MR at 16#4# range 0 .. 31; + DACC_TRIGR at 16#8# range 0 .. 31; + DACC_CHER at 16#10# range 0 .. 31; + DACC_CHDR at 16#14# range 0 .. 31; + DACC_CHSR at 16#18# range 0 .. 31; + DACC_CDR at 16#1C# range 0 .. 63; + DACC_IER at 16#24# range 0 .. 31; + DACC_IDR at 16#28# range 0 .. 31; + DACC_IMR at 16#2C# range 0 .. 31; + DACC_ISR at 16#30# range 0 .. 31; + DACC_ACR at 16#94# range 0 .. 31; + DACC_WPMR at 16#E4# range 0 .. 31; + DACC_WPSR at 16#E8# range 0 .. 31; + DACC_VERSION at 16#FC# range 0 .. 31; + end record; + + -- Digital-to-Analog Converter Controller + DACC_Periph : aliased DACC_Peripheral + with Import, Address => System'To_Address (16#40040000#); + +end SAM_SVD.DACC; diff --git a/arch/ARM/SAM/svd/atsamv71/sam_svd-efc.ads b/arch/ARM/SAM/svd/atsamv71/sam_svd-efc.ads new file mode 100644 index 000000000..97b9614c9 --- /dev/null +++ b/arch/ARM/SAM/svd/atsamv71/sam_svd-efc.ads @@ -0,0 +1,289 @@ +-- This spec has been automatically generated from ATSAMV71Q21.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package SAM_SVD.EFC is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + subtype EFC_EEFC_FMR_FWS_Field is HAL.UInt4; + + -- EEFC Flash Mode Register + type EFC_EEFC_FMR_Register is record + -- Flash Ready Interrupt Enable + FRDY : Boolean := False; + -- unspecified + Reserved_1_7 : HAL.UInt7 := 16#0#; + -- Flash Wait State + FWS : EFC_EEFC_FMR_FWS_Field := 16#0#; + -- unspecified + Reserved_12_15 : HAL.UInt4 := 16#0#; + -- Sequential Code Optimization Disable + SCOD : Boolean := False; + -- unspecified + Reserved_17_25 : HAL.UInt9 := 16#0#; + -- Code Loop Optimization Enable + CLOE : Boolean := False; + -- unspecified + Reserved_27_31 : HAL.UInt5 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for EFC_EEFC_FMR_Register use record + FRDY at 0 range 0 .. 0; + Reserved_1_7 at 0 range 1 .. 7; + FWS at 0 range 8 .. 11; + Reserved_12_15 at 0 range 12 .. 15; + SCOD at 0 range 16 .. 16; + Reserved_17_25 at 0 range 17 .. 25; + CLOE at 0 range 26 .. 26; + Reserved_27_31 at 0 range 27 .. 31; + end record; + + -- Flash Command + type EEFC_FCR_FCMD_Field is + ( + -- Get Flash descriptor + Getd, + -- Write page + Wp, + -- Write page and lock + Wpl, + -- Erase page and write page + Ewp, + -- Erase page and write page then lock + Ewpl, + -- Erase all + Ea, + -- Erase pages + Epa, + -- Set lock bit + Slb, + -- Clear lock bit + Clb, + -- Get lock bit + Glb, + -- Set GPNVM bit + Sgpb, + -- Clear GPNVM bit + Cgpb, + -- Get GPNVM bit + Ggpb, + -- Start read unique identifier + Stui, + -- Stop read unique identifier + Spui, + -- Get CALIB bit + Gcalb, + -- Erase sector + Es, + -- Write user signature + Wus, + -- Erase user signature + Eus, + -- Start read user signature + Stus, + -- Stop read user signature + Spus) + with Size => 8; + for EEFC_FCR_FCMD_Field use + (Getd => 0, + Wp => 1, + Wpl => 2, + Ewp => 3, + Ewpl => 4, + Ea => 5, + Epa => 7, + Slb => 8, + Clb => 9, + Glb => 10, + Sgpb => 11, + Cgpb => 12, + Ggpb => 13, + Stui => 14, + Spui => 15, + Gcalb => 16, + Es => 17, + Wus => 18, + Eus => 19, + Stus => 20, + Spus => 21); + + subtype EFC_EEFC_FCR_FARG_Field is HAL.UInt16; + + -- Flash Writing Protection Key + type EEFC_FCR_FKEY_Field is + ( + -- Reset value for the field + Eefc_Fcr_Fkey_Field_Reset, + -- The 0x5A value enables the command defined by the bits of the + -- register. If the field is written with a different value, the write + -- is not performed and no action is started. + Passwd) + with Size => 8; + for EEFC_FCR_FKEY_Field use + (Eefc_Fcr_Fkey_Field_Reset => 0, + Passwd => 90); + + -- EEFC Flash Command Register + type EFC_EEFC_FCR_Register is record + -- Write-only. Flash Command + FCMD : EEFC_FCR_FCMD_Field := SAM_SVD.EFC.Getd; + -- Write-only. Flash Command Argument + FARG : EFC_EEFC_FCR_FARG_Field := 16#0#; + -- Write-only. Flash Writing Protection Key + FKEY : EEFC_FCR_FKEY_Field := Eefc_Fcr_Fkey_Field_Reset; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for EFC_EEFC_FCR_Register use record + FCMD at 0 range 0 .. 7; + FARG at 0 range 8 .. 23; + FKEY at 0 range 24 .. 31; + end record; + + -- EEFC Flash Status Register + type EFC_EEFC_FSR_Register is record + -- Read-only. Flash Ready Status (cleared when Flash is busy) + FRDY : Boolean; + -- Read-only. Flash Command Error Status (cleared on read or by writing + -- EEFC_FCR) + FCMDE : Boolean; + -- Read-only. Flash Lock Error Status (cleared on read) + FLOCKE : Boolean; + -- Read-only. Flash Error Status (cleared when a programming operation + -- starts) + FLERR : Boolean; + -- unspecified + Reserved_4_15 : HAL.UInt12; + -- Read-only. Unique ECC Error on LSB Part of the Memory Flash Data Bus + -- (cleared on read) + UECCELSB : Boolean; + -- Read-only. Multiple ECC Error on LSB Part of the Memory Flash Data + -- Bus (cleared on read) + MECCELSB : Boolean; + -- Read-only. Unique ECC Error on MSB Part of the Memory Flash Data Bus + -- (cleared on read) + UECCEMSB : Boolean; + -- Read-only. Multiple ECC Error on MSB Part of the Memory Flash Data + -- Bus (cleared on read) + MECCEMSB : Boolean; + -- unspecified + Reserved_20_31 : HAL.UInt12; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for EFC_EEFC_FSR_Register use record + FRDY at 0 range 0 .. 0; + FCMDE at 0 range 1 .. 1; + FLOCKE at 0 range 2 .. 2; + FLERR at 0 range 3 .. 3; + Reserved_4_15 at 0 range 4 .. 15; + UECCELSB at 0 range 16 .. 16; + MECCELSB at 0 range 17 .. 17; + UECCEMSB at 0 range 18 .. 18; + MECCEMSB at 0 range 19 .. 19; + Reserved_20_31 at 0 range 20 .. 31; + end record; + + subtype EFC_EEFC_VERSION_VERSION_Field is HAL.UInt12; + subtype EFC_EEFC_VERSION_MFN_Field is HAL.UInt3; + + -- EEFC Version Register + type EFC_EEFC_VERSION_Register is record + -- Read-only. Version of the Hardware Module + VERSION : EFC_EEFC_VERSION_VERSION_Field; + -- unspecified + Reserved_12_15 : HAL.UInt4; + -- Read-only. Metal Fix Number + MFN : EFC_EEFC_VERSION_MFN_Field; + -- unspecified + Reserved_19_31 : HAL.UInt13; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for EFC_EEFC_VERSION_Register use record + VERSION at 0 range 0 .. 11; + Reserved_12_15 at 0 range 12 .. 15; + MFN at 0 range 16 .. 18; + Reserved_19_31 at 0 range 19 .. 31; + end record; + + -- Write Protection Key + type EEFC_WPMR_WPKEY_Field is + ( + -- Reset value for the field + Eefc_Wpmr_Wpkey_Field_Reset, + -- Writing any other value in this field aborts the write + -- operation.Always reads as 0. + Passwd) + with Size => 24; + for EEFC_WPMR_WPKEY_Field use + (Eefc_Wpmr_Wpkey_Field_Reset => 0, + Passwd => 4539971); + + -- Write Protection Mode Register + type EFC_EEFC_WPMR_Register is record + -- Write Protection Enable + WPEN : Boolean := False; + -- unspecified + Reserved_1_7 : HAL.UInt7 := 16#0#; + -- Write Protection Key + WPKEY : EEFC_WPMR_WPKEY_Field := Eefc_Wpmr_Wpkey_Field_Reset; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for EFC_EEFC_WPMR_Register use record + WPEN at 0 range 0 .. 0; + Reserved_1_7 at 0 range 1 .. 7; + WPKEY at 0 range 8 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- Embedded Flash Controller + type EFC_Peripheral is record + -- EEFC Flash Mode Register + EEFC_FMR : aliased EFC_EEFC_FMR_Register; + -- EEFC Flash Command Register + EEFC_FCR : aliased EFC_EEFC_FCR_Register; + -- EEFC Flash Status Register + EEFC_FSR : aliased EFC_EEFC_FSR_Register; + -- EEFC Flash Result Register + EEFC_FRR : aliased HAL.UInt32; + -- EEFC Version Register + EEFC_VERSION : aliased EFC_EEFC_VERSION_Register; + -- Write Protection Mode Register + EEFC_WPMR : aliased EFC_EEFC_WPMR_Register; + end record + with Volatile; + + for EFC_Peripheral use record + EEFC_FMR at 16#0# range 0 .. 31; + EEFC_FCR at 16#4# range 0 .. 31; + EEFC_FSR at 16#8# range 0 .. 31; + EEFC_FRR at 16#C# range 0 .. 31; + EEFC_VERSION at 16#14# range 0 .. 31; + EEFC_WPMR at 16#E4# range 0 .. 31; + end record; + + -- Embedded Flash Controller + EFC_Periph : aliased EFC_Peripheral + with Import, Address => System'To_Address (16#400E0C00#); + +end SAM_SVD.EFC; diff --git a/arch/ARM/SAM/svd/atsamv71/sam_svd-fpu.ads b/arch/ARM/SAM/svd/atsamv71/sam_svd-fpu.ads new file mode 100644 index 000000000..90afb2d5b --- /dev/null +++ b/arch/ARM/SAM/svd/atsamv71/sam_svd-fpu.ads @@ -0,0 +1,146 @@ +-- This spec has been automatically generated from ATSAMV71Q21.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package SAM_SVD.FPU is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + -- Floating-point Context Control Register + type FPU_FPCCR_Register is record + -- Lazy state preservation is active. Floating-point stack frame has + -- been allocated but saving state to it has been deferred. + LSPACT : Boolean := False; + -- Privilege level was user when the floating-point stack frame was + -- allocated. + USER : Boolean := False; + -- unspecified + Reserved_2_2 : HAL.Bit := 16#0#; + -- Mode was Thread Mode when the floating-point stack frame was + -- allocated. + THREAD : Boolean := False; + -- Priority permitted setting the HardFault handler to the pending state + -- when the floating-point stack frame was allocated. + HFRDY : Boolean := False; + -- MemManage is enabled and priority permitted setting the MemManage + -- handler to the pending state when the floating-point stack frame was + -- allocated. + MMRDY : Boolean := False; + -- BusFault is enabled and priority permitted setting the BusFault + -- handler to the pending state when the floating-point stack frame was + -- allocated. + BFRDY : Boolean := False; + -- unspecified + Reserved_7_7 : HAL.Bit := 16#0#; + -- DebugMonitor is enabled and priority permits setting MON_PEND when + -- the floating-point stack frame was allocated. + MONRDY : Boolean := False; + -- unspecified + Reserved_9_29 : HAL.UInt21 := 16#0#; + -- Enable automatic lazy state preservation for floating-point context. + LSPEN : Boolean := False; + -- Enables CONTROL.FPCA setting on execution of a floating-point + -- instruction. This results in automatic hardware state preservation + -- and restoration, for floating-point context, on exception entry and + -- exit. + ASPEN : Boolean := False; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for FPU_FPCCR_Register use record + LSPACT at 0 range 0 .. 0; + USER at 0 range 1 .. 1; + Reserved_2_2 at 0 range 2 .. 2; + THREAD at 0 range 3 .. 3; + HFRDY at 0 range 4 .. 4; + MMRDY at 0 range 5 .. 5; + BFRDY at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + MONRDY at 0 range 8 .. 8; + Reserved_9_29 at 0 range 9 .. 29; + LSPEN at 0 range 30 .. 30; + ASPEN at 0 range 31 .. 31; + end record; + + subtype FPU_FPCAR_ADDRESS_Field is HAL.UInt29; + + -- Floating-point Context Address Register + type FPU_FPCAR_Register is record + -- unspecified + Reserved_0_2 : HAL.UInt3 := 16#0#; + -- The location of the unpopulated floating-point register space + -- allocated on an exception stack frame. + ADDRESS : FPU_FPCAR_ADDRESS_Field := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for FPU_FPCAR_Register use record + Reserved_0_2 at 0 range 0 .. 2; + ADDRESS at 0 range 3 .. 31; + end record; + + subtype FPU_FPDSCR_RMode_Field is HAL.UInt2; + + -- Floating-point Default Status Control Register + type FPU_FPDSCR_Register is record + -- unspecified + Reserved_0_21 : HAL.UInt22 := 16#0#; + -- Default value for FPSCR.RMode. + RMode : FPU_FPDSCR_RMode_Field := 16#0#; + -- Default value for FPSCR.FZ. + FZ : Boolean := False; + -- Default value for FPSCR.DN. + DN : Boolean := False; + -- Default value for FPSCR.AHP. + AHP : Boolean := False; + -- unspecified + Reserved_27_31 : HAL.UInt5 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for FPU_FPDSCR_Register use record + Reserved_0_21 at 0 range 0 .. 21; + RMode at 0 range 22 .. 23; + FZ at 0 range 24 .. 24; + DN at 0 range 25 .. 25; + AHP at 0 range 26 .. 26; + Reserved_27_31 at 0 range 27 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- Floating Point Unit Registers + type FPU_Peripheral is record + -- Floating-point Context Control Register + FPCCR : aliased FPU_FPCCR_Register; + -- Floating-point Context Address Register + FPCAR : aliased FPU_FPCAR_Register; + -- Floating-point Default Status Control Register + FPDSCR : aliased FPU_FPDSCR_Register; + end record + with Volatile; + + for FPU_Peripheral use record + FPCCR at 16#0# range 0 .. 31; + FPCAR at 16#4# range 0 .. 31; + FPDSCR at 16#8# range 0 .. 31; + end record; + + -- Floating Point Unit Registers + FPU_Periph : aliased FPU_Peripheral + with Import, Address => System'To_Address (16#E000EF34#); + +end SAM_SVD.FPU; diff --git a/arch/ARM/SAM/svd/atsamv71/sam_svd-gmac.ads b/arch/ARM/SAM/svd/atsamv71/sam_svd-gmac.ads new file mode 100644 index 000000000..7517a7d44 --- /dev/null +++ b/arch/ARM/SAM/svd/atsamv71/sam_svd-gmac.ads @@ -0,0 +1,2763 @@ +-- This spec has been automatically generated from ATSAMV71Q21.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package SAM_SVD.GMAC is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + -- Network Control Register + type GMAC_GMAC_NCR_Register is record + -- unspecified + Reserved_0_0 : HAL.Bit := 16#0#; + -- Loop Back Local + LBL : Boolean := False; + -- Receive Enable + RXEN : Boolean := False; + -- Transmit Enable + TXEN : Boolean := False; + -- Management Port Enable + MPE : Boolean := False; + -- Clear Statistics Registers + CLRSTAT : Boolean := False; + -- Increment Statistics Registers + INCSTAT : Boolean := False; + -- Write Enable for Statistics Registers + WESTAT : Boolean := False; + -- Back pressure + BP : Boolean := False; + -- Start Transmission + TSTART : Boolean := False; + -- Transmit Halt + THALT : Boolean := False; + -- Transmit Pause Frame + TXPF : Boolean := False; + -- Transmit Zero Quantum Pause Frame + TXZQPF : Boolean := False; + -- unspecified + Reserved_13_14 : HAL.UInt2 := 16#0#; + -- Store Receive Time Stamp to Memory + SRTSM : Boolean := False; + -- Enable PFC Priority-based Pause Reception + ENPBPR : Boolean := False; + -- Transmit PFC Priority-based Pause Frame + TXPBPF : Boolean := False; + -- Flush Next Packet + FNP : Boolean := False; + -- unspecified + Reserved_19_31 : HAL.UInt13 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for GMAC_GMAC_NCR_Register use record + Reserved_0_0 at 0 range 0 .. 0; + LBL at 0 range 1 .. 1; + RXEN at 0 range 2 .. 2; + TXEN at 0 range 3 .. 3; + MPE at 0 range 4 .. 4; + CLRSTAT at 0 range 5 .. 5; + INCSTAT at 0 range 6 .. 6; + WESTAT at 0 range 7 .. 7; + BP at 0 range 8 .. 8; + TSTART at 0 range 9 .. 9; + THALT at 0 range 10 .. 10; + TXPF at 0 range 11 .. 11; + TXZQPF at 0 range 12 .. 12; + Reserved_13_14 at 0 range 13 .. 14; + SRTSM at 0 range 15 .. 15; + ENPBPR at 0 range 16 .. 16; + TXPBPF at 0 range 17 .. 17; + FNP at 0 range 18 .. 18; + Reserved_19_31 at 0 range 19 .. 31; + end record; + + subtype GMAC_GMAC_NCFGR_RXBUFO_Field is HAL.UInt2; + + -- MDC CLock Division + type GMAC_NCFGR_CLK_Field is + ( + -- MCK divided by 8 (MCK up to 20 MHz) + Mck_8, + -- MCK divided by 16 (MCK up to 40 MHz) + Mck_16, + -- MCK divided by 32 (MCK up to 80 MHz) + Mck_32, + -- MCK divided by 48 (MCK up to 120 MHz) + Mck_48, + -- MCK divided by 64 (MCK up to 160 MHz) + Mck_64, + -- MCK divided by 96 (MCK up to 240 MHz) + Mck_96) + with Size => 3; + for GMAC_NCFGR_CLK_Field use + (Mck_8 => 0, + Mck_16 => 1, + Mck_32 => 2, + Mck_48 => 3, + Mck_64 => 4, + Mck_96 => 5); + + subtype GMAC_GMAC_NCFGR_DBW_Field is HAL.UInt2; + + -- Network Configuration Register + type GMAC_GMAC_NCFGR_Register is record + -- Speed + SPD : Boolean := False; + -- Full Duplex + FD : Boolean := False; + -- Discard Non-VLAN FRAMES + DNVLAN : Boolean := False; + -- Jumbo Frame Size + JFRAME : Boolean := False; + -- Copy All Frames + CAF : Boolean := False; + -- No Broadcast + NBC : Boolean := False; + -- Multicast Hash Enable + MTIHEN : Boolean := False; + -- Unicast Hash Enable + UNIHEN : Boolean := False; + -- 1536 Maximum Frame Size + MAXFS : Boolean := False; + -- unspecified + Reserved_9_11 : HAL.UInt3 := 16#0#; + -- Retry Test + RTY : Boolean := False; + -- Pause Enable + PEN : Boolean := False; + -- Receive Buffer Offset + RXBUFO : GMAC_GMAC_NCFGR_RXBUFO_Field := 16#0#; + -- Length Field Error Frame Discard + LFERD : Boolean := False; + -- Remove FCS + RFCS : Boolean := False; + -- MDC CLock Division + CLK : GMAC_NCFGR_CLK_Field := SAM_SVD.GMAC.Mck_8; + -- Data Bus Width + DBW : GMAC_GMAC_NCFGR_DBW_Field := 16#0#; + -- Disable Copy of Pause Frames + DCPF : Boolean := False; + -- Receive Checksum Offload Enable + RXCOEN : Boolean := False; + -- Enable Frames Received in Half Duplex + EFRHD : Boolean := False; + -- Ignore RX FCS + IRXFCS : Boolean := False; + -- unspecified + Reserved_27_27 : HAL.Bit := 16#0#; + -- IP Stretch Enable + IPGSEN : Boolean := False; + -- Receive Bad Preamble + RXBP : Boolean := False; + -- Ignore IPG GRXER + IRXER : Boolean := False; + -- unspecified + Reserved_31_31 : HAL.Bit := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for GMAC_GMAC_NCFGR_Register use record + SPD at 0 range 0 .. 0; + FD at 0 range 1 .. 1; + DNVLAN at 0 range 2 .. 2; + JFRAME at 0 range 3 .. 3; + CAF at 0 range 4 .. 4; + NBC at 0 range 5 .. 5; + MTIHEN at 0 range 6 .. 6; + UNIHEN at 0 range 7 .. 7; + MAXFS at 0 range 8 .. 8; + Reserved_9_11 at 0 range 9 .. 11; + RTY at 0 range 12 .. 12; + PEN at 0 range 13 .. 13; + RXBUFO at 0 range 14 .. 15; + LFERD at 0 range 16 .. 16; + RFCS at 0 range 17 .. 17; + CLK at 0 range 18 .. 20; + DBW at 0 range 21 .. 22; + DCPF at 0 range 23 .. 23; + RXCOEN at 0 range 24 .. 24; + EFRHD at 0 range 25 .. 25; + IRXFCS at 0 range 26 .. 26; + Reserved_27_27 at 0 range 27 .. 27; + IPGSEN at 0 range 28 .. 28; + RXBP at 0 range 29 .. 29; + IRXER at 0 range 30 .. 30; + Reserved_31_31 at 0 range 31 .. 31; + end record; + + -- Network Status Register + type GMAC_GMAC_NSR_Register is record + -- unspecified + Reserved_0_0 : HAL.Bit; + -- Read-only. MDIO Input Status + MDIO : Boolean; + -- Read-only. PHY Management Logic Idle + IDLE : Boolean; + -- unspecified + Reserved_3_31 : HAL.UInt29; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for GMAC_GMAC_NSR_Register use record + Reserved_0_0 at 0 range 0 .. 0; + MDIO at 0 range 1 .. 1; + IDLE at 0 range 2 .. 2; + Reserved_3_31 at 0 range 3 .. 31; + end record; + + -- User Register + type GMAC_GMAC_UR_Register is record + -- Reduced MII Mode + RMII : Boolean := False; + -- unspecified + Reserved_1_31 : HAL.UInt31 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for GMAC_GMAC_UR_Register use record + RMII at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + -- Fixed Burst Length for DMA Data Operations: + type GMAC_DCFGR_FBLDO_Field is + ( + -- Reset value for the field + Gmac_Dcfgr_Fbldo_Field_Reset, + -- 00001: Always use SINGLE AHB bursts + Single, + -- 001xx: Attempt to use INCR4 AHB bursts (Default) + Incr4, + -- 01xxx: Attempt to use INCR8 AHB bursts + Incr8, + -- 1xxxx: Attempt to use INCR16 AHB bursts + Incr16) + with Size => 5; + for GMAC_DCFGR_FBLDO_Field use + (Gmac_Dcfgr_Fbldo_Field_Reset => 0, + Single => 1, + Incr4 => 4, + Incr8 => 8, + Incr16 => 16); + + -- Receiver Packet Buffer Memory Size Select + type GMAC_DCFGR_RXBMS_Field is + ( + -- 4/8 Kbyte Memory Size + Eighth, + -- 4/4 Kbytes Memory Size + Quarter, + -- 4/2 Kbytes Memory Size + Half, + -- 4 Kbytes Memory Size + Full) + with Size => 2; + for GMAC_DCFGR_RXBMS_Field use + (Eighth => 0, + Quarter => 1, + Half => 2, + Full => 3); + + subtype GMAC_GMAC_DCFGR_DRBS_Field is HAL.UInt8; + + -- DMA Configuration Register + type GMAC_GMAC_DCFGR_Register is record + -- Fixed Burst Length for DMA Data Operations: + FBLDO : GMAC_DCFGR_FBLDO_Field := Gmac_Dcfgr_Fbldo_Field_Reset; + -- unspecified + Reserved_5_5 : HAL.Bit := 16#0#; + -- Endian Swap Mode Enable for Management Descriptor Accesses + ESMA : Boolean := False; + -- Endian Swap Mode Enable for Packet Data Accesses + ESPA : Boolean := False; + -- Receiver Packet Buffer Memory Size Select + RXBMS : GMAC_DCFGR_RXBMS_Field := SAM_SVD.GMAC.Eighth; + -- Transmitter Packet Buffer Memory Size Select + TXPBMS : Boolean := False; + -- Transmitter Checksum Generation Offload Enable + TXCOEN : Boolean := False; + -- unspecified + Reserved_12_15 : HAL.UInt4 := 16#0#; + -- DMA Receive Buffer Size + DRBS : GMAC_GMAC_DCFGR_DRBS_Field := 16#0#; + -- DMA Discard Receive Packets + DDRP : Boolean := False; + -- unspecified + Reserved_25_31 : HAL.UInt7 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for GMAC_GMAC_DCFGR_Register use record + FBLDO at 0 range 0 .. 4; + Reserved_5_5 at 0 range 5 .. 5; + ESMA at 0 range 6 .. 6; + ESPA at 0 range 7 .. 7; + RXBMS at 0 range 8 .. 9; + TXPBMS at 0 range 10 .. 10; + TXCOEN at 0 range 11 .. 11; + Reserved_12_15 at 0 range 12 .. 15; + DRBS at 0 range 16 .. 23; + DDRP at 0 range 24 .. 24; + Reserved_25_31 at 0 range 25 .. 31; + end record; + + -- Transmit Status Register + type GMAC_GMAC_TSR_Register is record + -- Used Bit Read + UBR : Boolean := False; + -- Collision Occurred + COL : Boolean := False; + -- Retry Limit Exceeded + RLE : Boolean := False; + -- Transmit Go + TXGO : Boolean := False; + -- Transmit Frame Corruption Due to AHB Error + TFC : Boolean := False; + -- Transmit Complete + TXCOMP : Boolean := False; + -- unspecified + Reserved_6_7 : HAL.UInt2 := 16#0#; + -- HRESP Not OK + HRESP : Boolean := False; + -- unspecified + Reserved_9_31 : HAL.UInt23 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for GMAC_GMAC_TSR_Register use record + UBR at 0 range 0 .. 0; + COL at 0 range 1 .. 1; + RLE at 0 range 2 .. 2; + TXGO at 0 range 3 .. 3; + TFC at 0 range 4 .. 4; + TXCOMP at 0 range 5 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + HRESP at 0 range 8 .. 8; + Reserved_9_31 at 0 range 9 .. 31; + end record; + + subtype GMAC_GMAC_RBQB_ADDR_Field is HAL.UInt30; + + -- Receive Buffer Queue Base Address Register + type GMAC_GMAC_RBQB_Register is record + -- unspecified + Reserved_0_1 : HAL.UInt2 := 16#0#; + -- Receive Buffer Queue Base Address + ADDR : GMAC_GMAC_RBQB_ADDR_Field := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for GMAC_GMAC_RBQB_Register use record + Reserved_0_1 at 0 range 0 .. 1; + ADDR at 0 range 2 .. 31; + end record; + + subtype GMAC_GMAC_TBQB_ADDR_Field is HAL.UInt30; + + -- Transmit Buffer Queue Base Address Register + type GMAC_GMAC_TBQB_Register is record + -- unspecified + Reserved_0_1 : HAL.UInt2 := 16#0#; + -- Transmit Buffer Queue Base Address + ADDR : GMAC_GMAC_TBQB_ADDR_Field := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for GMAC_GMAC_TBQB_Register use record + Reserved_0_1 at 0 range 0 .. 1; + ADDR at 0 range 2 .. 31; + end record; + + -- Receive Status Register + type GMAC_GMAC_RSR_Register is record + -- Buffer Not Available + BNA : Boolean := False; + -- Frame Received + REC : Boolean := False; + -- Receive Overrun + RXOVR : Boolean := False; + -- HRESP Not OK + HNO : Boolean := False; + -- unspecified + Reserved_4_31 : HAL.UInt28 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for GMAC_GMAC_RSR_Register use record + BNA at 0 range 0 .. 0; + REC at 0 range 1 .. 1; + RXOVR at 0 range 2 .. 2; + HNO at 0 range 3 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + -- Interrupt Status Register + type GMAC_GMAC_ISR_Register is record + -- Read-only. Management Frame Sent + MFS : Boolean; + -- Read-only. Receive Complete + RCOMP : Boolean; + -- Read-only. RX Used Bit Read + RXUBR : Boolean; + -- Read-only. TX Used Bit Read + TXUBR : Boolean; + -- Read-only. Transmit Underrun + TUR : Boolean; + -- Read-only. Retry Limit Exceeded + RLEX : Boolean; + -- Read-only. Transmit Frame Corruption Due to AHB Error + TFC : Boolean; + -- Read-only. Transmit Complete + TCOMP : Boolean; + -- unspecified + Reserved_8_9 : HAL.UInt2; + -- Read-only. Receive Overrun + ROVR : Boolean; + -- Read-only. HRESP Not OK + HRESP : Boolean; + -- Read-only. Pause Frame with Non-zero Pause Quantum Received + PFNZ : Boolean; + -- Read-only. Pause Time Zero + PTZ : Boolean; + -- Read-only. Pause Frame Transmitted + PFTR : Boolean; + -- unspecified + Reserved_15_17 : HAL.UInt3; + -- Read-only. PTP Delay Request Frame Received + DRQFR : Boolean; + -- Read-only. PTP Sync Frame Received + SFR : Boolean; + -- Read-only. PTP Delay Request Frame Transmitted + DRQFT : Boolean; + -- Read-only. PTP Sync Frame Transmitted + SFT : Boolean; + -- Read-only. PDelay Request Frame Received + PDRQFR : Boolean; + -- Read-only. PDelay Response Frame Received + PDRSFR : Boolean; + -- Read-only. PDelay Request Frame Transmitted + PDRQFT : Boolean; + -- Read-only. PDelay Response Frame Transmitted + PDRSFT : Boolean; + -- Read-only. TSU Seconds Register Increment + SRI : Boolean; + -- unspecified + Reserved_27_27 : HAL.Bit; + -- Read-only. Wake On LAN + WOL : Boolean; + -- unspecified + Reserved_29_31 : HAL.UInt3; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for GMAC_GMAC_ISR_Register use record + MFS at 0 range 0 .. 0; + RCOMP at 0 range 1 .. 1; + RXUBR at 0 range 2 .. 2; + TXUBR at 0 range 3 .. 3; + TUR at 0 range 4 .. 4; + RLEX at 0 range 5 .. 5; + TFC at 0 range 6 .. 6; + TCOMP at 0 range 7 .. 7; + Reserved_8_9 at 0 range 8 .. 9; + ROVR at 0 range 10 .. 10; + HRESP at 0 range 11 .. 11; + PFNZ at 0 range 12 .. 12; + PTZ at 0 range 13 .. 13; + PFTR at 0 range 14 .. 14; + Reserved_15_17 at 0 range 15 .. 17; + DRQFR at 0 range 18 .. 18; + SFR at 0 range 19 .. 19; + DRQFT at 0 range 20 .. 20; + SFT at 0 range 21 .. 21; + PDRQFR at 0 range 22 .. 22; + PDRSFR at 0 range 23 .. 23; + PDRQFT at 0 range 24 .. 24; + PDRSFT at 0 range 25 .. 25; + SRI at 0 range 26 .. 26; + Reserved_27_27 at 0 range 27 .. 27; + WOL at 0 range 28 .. 28; + Reserved_29_31 at 0 range 29 .. 31; + end record; + + -- Interrupt Enable Register + type GMAC_GMAC_IER_Register is record + -- Write-only. Management Frame Sent + MFS : Boolean := False; + -- Write-only. Receive Complete + RCOMP : Boolean := False; + -- Write-only. RX Used Bit Read + RXUBR : Boolean := False; + -- Write-only. TX Used Bit Read + TXUBR : Boolean := False; + -- Write-only. Transmit Underrun + TUR : Boolean := False; + -- Write-only. Retry Limit Exceeded or Late Collision + RLEX : Boolean := False; + -- Write-only. Transmit Frame Corruption Due to AHB Error + TFC : Boolean := False; + -- Write-only. Transmit Complete + TCOMP : Boolean := False; + -- unspecified + Reserved_8_9 : HAL.UInt2 := 16#0#; + -- Write-only. Receive Overrun + ROVR : Boolean := False; + -- Write-only. HRESP Not OK + HRESP : Boolean := False; + -- Write-only. Pause Frame with Non-zero Pause Quantum Received + PFNZ : Boolean := False; + -- Write-only. Pause Time Zero + PTZ : Boolean := False; + -- Write-only. Pause Frame Transmitted + PFTR : Boolean := False; + -- Write-only. External Interrupt + EXINT : Boolean := False; + -- unspecified + Reserved_16_17 : HAL.UInt2 := 16#0#; + -- Write-only. PTP Delay Request Frame Received + DRQFR : Boolean := False; + -- Write-only. PTP Sync Frame Received + SFR : Boolean := False; + -- Write-only. PTP Delay Request Frame Transmitted + DRQFT : Boolean := False; + -- Write-only. PTP Sync Frame Transmitted + SFT : Boolean := False; + -- Write-only. PDelay Request Frame Received + PDRQFR : Boolean := False; + -- Write-only. PDelay Response Frame Received + PDRSFR : Boolean := False; + -- Write-only. PDelay Request Frame Transmitted + PDRQFT : Boolean := False; + -- Write-only. PDelay Response Frame Transmitted + PDRSFT : Boolean := False; + -- Write-only. TSU Seconds Register Increment + SRI : Boolean := False; + -- Write-only. Enable RX LPI Indication + RXLPISBC : Boolean := False; + -- Write-only. Wake On LAN + WOL : Boolean := False; + -- Write-only. TSU Timer Comparison + TSUTIMCOMP : Boolean := False; + -- unspecified + Reserved_30_31 : HAL.UInt2 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for GMAC_GMAC_IER_Register use record + MFS at 0 range 0 .. 0; + RCOMP at 0 range 1 .. 1; + RXUBR at 0 range 2 .. 2; + TXUBR at 0 range 3 .. 3; + TUR at 0 range 4 .. 4; + RLEX at 0 range 5 .. 5; + TFC at 0 range 6 .. 6; + TCOMP at 0 range 7 .. 7; + Reserved_8_9 at 0 range 8 .. 9; + ROVR at 0 range 10 .. 10; + HRESP at 0 range 11 .. 11; + PFNZ at 0 range 12 .. 12; + PTZ at 0 range 13 .. 13; + PFTR at 0 range 14 .. 14; + EXINT at 0 range 15 .. 15; + Reserved_16_17 at 0 range 16 .. 17; + DRQFR at 0 range 18 .. 18; + SFR at 0 range 19 .. 19; + DRQFT at 0 range 20 .. 20; + SFT at 0 range 21 .. 21; + PDRQFR at 0 range 22 .. 22; + PDRSFR at 0 range 23 .. 23; + PDRQFT at 0 range 24 .. 24; + PDRSFT at 0 range 25 .. 25; + SRI at 0 range 26 .. 26; + RXLPISBC at 0 range 27 .. 27; + WOL at 0 range 28 .. 28; + TSUTIMCOMP at 0 range 29 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + -- Interrupt Disable Register + type GMAC_GMAC_IDR_Register is record + -- Write-only. Management Frame Sent + MFS : Boolean := False; + -- Write-only. Receive Complete + RCOMP : Boolean := False; + -- Write-only. RX Used Bit Read + RXUBR : Boolean := False; + -- Write-only. TX Used Bit Read + TXUBR : Boolean := False; + -- Write-only. Transmit Underrun + TUR : Boolean := False; + -- Write-only. Retry Limit Exceeded or Late Collision + RLEX : Boolean := False; + -- Write-only. Transmit Frame Corruption Due to AHB Error + TFC : Boolean := False; + -- Write-only. Transmit Complete + TCOMP : Boolean := False; + -- unspecified + Reserved_8_9 : HAL.UInt2 := 16#0#; + -- Write-only. Receive Overrun + ROVR : Boolean := False; + -- Write-only. HRESP Not OK + HRESP : Boolean := False; + -- Write-only. Pause Frame with Non-zero Pause Quantum Received + PFNZ : Boolean := False; + -- Write-only. Pause Time Zero + PTZ : Boolean := False; + -- Write-only. Pause Frame Transmitted + PFTR : Boolean := False; + -- Write-only. External Interrupt + EXINT : Boolean := False; + -- unspecified + Reserved_16_17 : HAL.UInt2 := 16#0#; + -- Write-only. PTP Delay Request Frame Received + DRQFR : Boolean := False; + -- Write-only. PTP Sync Frame Received + SFR : Boolean := False; + -- Write-only. PTP Delay Request Frame Transmitted + DRQFT : Boolean := False; + -- Write-only. PTP Sync Frame Transmitted + SFT : Boolean := False; + -- Write-only. PDelay Request Frame Received + PDRQFR : Boolean := False; + -- Write-only. PDelay Response Frame Received + PDRSFR : Boolean := False; + -- Write-only. PDelay Request Frame Transmitted + PDRQFT : Boolean := False; + -- Write-only. PDelay Response Frame Transmitted + PDRSFT : Boolean := False; + -- Write-only. TSU Seconds Register Increment + SRI : Boolean := False; + -- Write-only. Enable RX LPI Indication + RXLPISBC : Boolean := False; + -- Write-only. Wake On LAN + WOL : Boolean := False; + -- Write-only. TSU Timer Comparison + TSUTIMCOMP : Boolean := False; + -- unspecified + Reserved_30_31 : HAL.UInt2 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for GMAC_GMAC_IDR_Register use record + MFS at 0 range 0 .. 0; + RCOMP at 0 range 1 .. 1; + RXUBR at 0 range 2 .. 2; + TXUBR at 0 range 3 .. 3; + TUR at 0 range 4 .. 4; + RLEX at 0 range 5 .. 5; + TFC at 0 range 6 .. 6; + TCOMP at 0 range 7 .. 7; + Reserved_8_9 at 0 range 8 .. 9; + ROVR at 0 range 10 .. 10; + HRESP at 0 range 11 .. 11; + PFNZ at 0 range 12 .. 12; + PTZ at 0 range 13 .. 13; + PFTR at 0 range 14 .. 14; + EXINT at 0 range 15 .. 15; + Reserved_16_17 at 0 range 16 .. 17; + DRQFR at 0 range 18 .. 18; + SFR at 0 range 19 .. 19; + DRQFT at 0 range 20 .. 20; + SFT at 0 range 21 .. 21; + PDRQFR at 0 range 22 .. 22; + PDRSFR at 0 range 23 .. 23; + PDRQFT at 0 range 24 .. 24; + PDRSFT at 0 range 25 .. 25; + SRI at 0 range 26 .. 26; + RXLPISBC at 0 range 27 .. 27; + WOL at 0 range 28 .. 28; + TSUTIMCOMP at 0 range 29 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + -- Interrupt Mask Register + type GMAC_GMAC_IMR_Register is record + -- Management Frame Sent + MFS : Boolean := False; + -- Receive Complete + RCOMP : Boolean := False; + -- RX Used Bit Read + RXUBR : Boolean := False; + -- TX Used Bit Read + TXUBR : Boolean := False; + -- Transmit Underrun + TUR : Boolean := False; + -- Retry Limit Exceeded + RLEX : Boolean := False; + -- Transmit Frame Corruption Due to AHB Error + TFC : Boolean := False; + -- Transmit Complete + TCOMP : Boolean := False; + -- unspecified + Reserved_8_9 : HAL.UInt2 := 16#0#; + -- Receive Overrun + ROVR : Boolean := False; + -- HRESP Not OK + HRESP : Boolean := False; + -- Pause Frame with Non-zero Pause Quantum Received + PFNZ : Boolean := False; + -- Pause Time Zero + PTZ : Boolean := False; + -- Pause Frame Transmitted + PFTR : Boolean := False; + -- External Interrupt + EXINT : Boolean := False; + -- unspecified + Reserved_16_17 : HAL.UInt2 := 16#0#; + -- PTP Delay Request Frame Received + DRQFR : Boolean := False; + -- PTP Sync Frame Received + SFR : Boolean := False; + -- PTP Delay Request Frame Transmitted + DRQFT : Boolean := False; + -- PTP Sync Frame Transmitted + SFT : Boolean := False; + -- PDelay Request Frame Received + PDRQFR : Boolean := False; + -- PDelay Response Frame Received + PDRSFR : Boolean := False; + -- PDelay Request Frame Transmitted + PDRQFT : Boolean := False; + -- PDelay Response Frame Transmitted + PDRSFT : Boolean := False; + -- TSU Seconds Register Increment + SRI : Boolean := False; + -- Enable RX LPI Indication + RXLPISBC : Boolean := False; + -- Wake On LAN + WOL : Boolean := False; + -- TSU Timer Comparison + TSUTIMCOMP : Boolean := False; + -- unspecified + Reserved_30_31 : HAL.UInt2 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for GMAC_GMAC_IMR_Register use record + MFS at 0 range 0 .. 0; + RCOMP at 0 range 1 .. 1; + RXUBR at 0 range 2 .. 2; + TXUBR at 0 range 3 .. 3; + TUR at 0 range 4 .. 4; + RLEX at 0 range 5 .. 5; + TFC at 0 range 6 .. 6; + TCOMP at 0 range 7 .. 7; + Reserved_8_9 at 0 range 8 .. 9; + ROVR at 0 range 10 .. 10; + HRESP at 0 range 11 .. 11; + PFNZ at 0 range 12 .. 12; + PTZ at 0 range 13 .. 13; + PFTR at 0 range 14 .. 14; + EXINT at 0 range 15 .. 15; + Reserved_16_17 at 0 range 16 .. 17; + DRQFR at 0 range 18 .. 18; + SFR at 0 range 19 .. 19; + DRQFT at 0 range 20 .. 20; + SFT at 0 range 21 .. 21; + PDRQFR at 0 range 22 .. 22; + PDRSFR at 0 range 23 .. 23; + PDRQFT at 0 range 24 .. 24; + PDRSFT at 0 range 25 .. 25; + SRI at 0 range 26 .. 26; + RXLPISBC at 0 range 27 .. 27; + WOL at 0 range 28 .. 28; + TSUTIMCOMP at 0 range 29 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + subtype GMAC_GMAC_MAN_DATA_Field is HAL.UInt16; + subtype GMAC_GMAC_MAN_WTN_Field is HAL.UInt2; + subtype GMAC_GMAC_MAN_REGA_Field is HAL.UInt5; + subtype GMAC_GMAC_MAN_PHYA_Field is HAL.UInt5; + subtype GMAC_GMAC_MAN_OP_Field is HAL.UInt2; + + -- PHY Maintenance Register + type GMAC_GMAC_MAN_Register is record + -- PHY Data + DATA : GMAC_GMAC_MAN_DATA_Field := 16#0#; + -- Write Ten + WTN : GMAC_GMAC_MAN_WTN_Field := 16#0#; + -- Register Address + REGA : GMAC_GMAC_MAN_REGA_Field := 16#0#; + -- PHY Address + PHYA : GMAC_GMAC_MAN_PHYA_Field := 16#0#; + -- Operation + OP : GMAC_GMAC_MAN_OP_Field := 16#0#; + -- Clause 22 Operation + CLTTO : Boolean := False; + -- Write ZERO + WZO : Boolean := False; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for GMAC_GMAC_MAN_Register use record + DATA at 0 range 0 .. 15; + WTN at 0 range 16 .. 17; + REGA at 0 range 18 .. 22; + PHYA at 0 range 23 .. 27; + OP at 0 range 28 .. 29; + CLTTO at 0 range 30 .. 30; + WZO at 0 range 31 .. 31; + end record; + + subtype GMAC_GMAC_RPQ_RPQ_Field is HAL.UInt16; + + -- Received Pause Quantum Register + type GMAC_GMAC_RPQ_Register is record + -- Read-only. Received Pause Quantum + RPQ : GMAC_GMAC_RPQ_RPQ_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for GMAC_GMAC_RPQ_Register use record + RPQ at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype GMAC_GMAC_TPQ_TPQ_Field is HAL.UInt16; + + -- Transmit Pause Quantum Register + type GMAC_GMAC_TPQ_Register is record + -- Transmit Pause Quantum + TPQ : GMAC_GMAC_TPQ_TPQ_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for GMAC_GMAC_TPQ_Register use record + TPQ at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype GMAC_GMAC_TPSF_TPB1ADR_Field is HAL.UInt12; + + -- TX Partial Store and Forward Register + type GMAC_GMAC_TPSF_Register is record + -- Transmit Partial Store and Forward Address + TPB1ADR : GMAC_GMAC_TPSF_TPB1ADR_Field := 16#0#; + -- unspecified + Reserved_12_30 : HAL.UInt19 := 16#0#; + -- Enable TX Partial Store and Forward Operation + ENTXP : Boolean := False; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for GMAC_GMAC_TPSF_Register use record + TPB1ADR at 0 range 0 .. 11; + Reserved_12_30 at 0 range 12 .. 30; + ENTXP at 0 range 31 .. 31; + end record; + + subtype GMAC_GMAC_RPSF_RPB1ADR_Field is HAL.UInt12; + + -- RX Partial Store and Forward Register + type GMAC_GMAC_RPSF_Register is record + -- Receive Partial Store and Forward Address + RPB1ADR : GMAC_GMAC_RPSF_RPB1ADR_Field := 16#0#; + -- unspecified + Reserved_12_30 : HAL.UInt19 := 16#0#; + -- Enable RX Partial Store and Forward Operation + ENRXP : Boolean := False; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for GMAC_GMAC_RPSF_Register use record + RPB1ADR at 0 range 0 .. 11; + Reserved_12_30 at 0 range 12 .. 30; + ENRXP at 0 range 31 .. 31; + end record; + + subtype GMAC_GMAC_RJFML_FML_Field is HAL.UInt14; + + -- RX Jumbo Frame Max Length Register + type GMAC_GMAC_RJFML_Register is record + -- Frame Max Length + FML : GMAC_GMAC_RJFML_FML_Field := 16#0#; + -- unspecified + Reserved_14_31 : HAL.UInt18 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for GMAC_GMAC_RJFML_Register use record + FML at 0 range 0 .. 13; + Reserved_14_31 at 0 range 14 .. 31; + end record; + + -------------------------------------- + -- GMAC_GMAC_SA cluster's Registers -- + -------------------------------------- + + subtype GMAC_GMAC_SAT_GMAC_GMAC_SA_ADDR_Field is HAL.UInt16; + + -- Specific Address 1 Top Register + type GMAC_GMAC_SAT_GMAC_GMAC_SA_Register is record + -- Specific Address 1 + ADDR : GMAC_GMAC_SAT_GMAC_GMAC_SA_ADDR_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for GMAC_GMAC_SAT_GMAC_GMAC_SA_Register use record + ADDR at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + -- Specific Address 1 Bottom Register + type GMAC_GMAC_SA_Cluster is record + -- Specific Address 1 Bottom Register + GMAC_SAB : aliased HAL.UInt32; + -- Specific Address 1 Top Register + GMAC_SAT : aliased GMAC_GMAC_SAT_GMAC_GMAC_SA_Register; + end record + with Volatile, Size => 64; + + for GMAC_GMAC_SA_Cluster use record + GMAC_SAB at 16#0# range 0 .. 31; + GMAC_SAT at 16#4# range 0 .. 31; + end record; + + -- Specific Address 1 Bottom Register + type GMAC_GMAC_SA_Clusters is array (0 .. 3) of GMAC_GMAC_SA_Cluster; + + subtype GMAC_GMAC_TIDM1_TID_Field is HAL.UInt16; + + -- Type ID Match 1 Register + type GMAC_GMAC_TIDM1_Register is record + -- Type ID Match 1 + TID : GMAC_GMAC_TIDM1_TID_Field := 16#0#; + -- unspecified + Reserved_16_30 : HAL.UInt15 := 16#0#; + -- Enable Copying of TID Matched Frames + ENID1 : Boolean := False; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for GMAC_GMAC_TIDM1_Register use record + TID at 0 range 0 .. 15; + Reserved_16_30 at 0 range 16 .. 30; + ENID1 at 0 range 31 .. 31; + end record; + + subtype GMAC_GMAC_TIDM2_TID_Field is HAL.UInt16; + + -- Type ID Match 2 Register + type GMAC_GMAC_TIDM2_Register is record + -- Type ID Match 2 + TID : GMAC_GMAC_TIDM2_TID_Field := 16#0#; + -- unspecified + Reserved_16_30 : HAL.UInt15 := 16#0#; + -- Enable Copying of TID Matched Frames + ENID2 : Boolean := False; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for GMAC_GMAC_TIDM2_Register use record + TID at 0 range 0 .. 15; + Reserved_16_30 at 0 range 16 .. 30; + ENID2 at 0 range 31 .. 31; + end record; + + subtype GMAC_GMAC_TIDM3_TID_Field is HAL.UInt16; + + -- Type ID Match 3 Register + type GMAC_GMAC_TIDM3_Register is record + -- Type ID Match 3 + TID : GMAC_GMAC_TIDM3_TID_Field := 16#0#; + -- unspecified + Reserved_16_30 : HAL.UInt15 := 16#0#; + -- Enable Copying of TID Matched Frames + ENID3 : Boolean := False; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for GMAC_GMAC_TIDM3_Register use record + TID at 0 range 0 .. 15; + Reserved_16_30 at 0 range 16 .. 30; + ENID3 at 0 range 31 .. 31; + end record; + + subtype GMAC_GMAC_TIDM4_TID_Field is HAL.UInt16; + + -- Type ID Match 4 Register + type GMAC_GMAC_TIDM4_Register is record + -- Type ID Match 4 + TID : GMAC_GMAC_TIDM4_TID_Field := 16#0#; + -- unspecified + Reserved_16_30 : HAL.UInt15 := 16#0#; + -- Enable Copying of TID Matched Frames + ENID4 : Boolean := False; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for GMAC_GMAC_TIDM4_Register use record + TID at 0 range 0 .. 15; + Reserved_16_30 at 0 range 16 .. 30; + ENID4 at 0 range 31 .. 31; + end record; + + subtype GMAC_GMAC_WOL_IP_Field is HAL.UInt16; + + -- Wake on LAN Register + type GMAC_GMAC_WOL_Register is record + -- ARP Request IP Address + IP : GMAC_GMAC_WOL_IP_Field := 16#0#; + -- Magic Packet Event Enable + MAG : Boolean := False; + -- ARP Request IP Address + ARP : Boolean := False; + -- Specific Address Register 1 Event Enable + SA1 : Boolean := False; + -- Multicast Hash Event Enable + MTI : Boolean := False; + -- unspecified + Reserved_20_31 : HAL.UInt12 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for GMAC_GMAC_WOL_Register use record + IP at 0 range 0 .. 15; + MAG at 0 range 16 .. 16; + ARP at 0 range 17 .. 17; + SA1 at 0 range 18 .. 18; + MTI at 0 range 19 .. 19; + Reserved_20_31 at 0 range 20 .. 31; + end record; + + subtype GMAC_GMAC_IPGS_FL_Field is HAL.UInt16; + + -- IPG Stretch Register + type GMAC_GMAC_IPGS_Register is record + -- Frame Length + FL : GMAC_GMAC_IPGS_FL_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for GMAC_GMAC_IPGS_Register use record + FL at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype GMAC_GMAC_SVLAN_VLAN_TYPE_Field is HAL.UInt16; + + -- Stacked VLAN Register + type GMAC_GMAC_SVLAN_Register is record + -- User Defined VLAN_TYPE Field + VLAN_TYPE : GMAC_GMAC_SVLAN_VLAN_TYPE_Field := 16#0#; + -- unspecified + Reserved_16_30 : HAL.UInt15 := 16#0#; + -- Enable Stacked VLAN Processing Mode + ESVLAN : Boolean := False; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for GMAC_GMAC_SVLAN_Register use record + VLAN_TYPE at 0 range 0 .. 15; + Reserved_16_30 at 0 range 16 .. 30; + ESVLAN at 0 range 31 .. 31; + end record; + + subtype GMAC_GMAC_TPFCP_PEV_Field is HAL.UInt8; + subtype GMAC_GMAC_TPFCP_PQ_Field is HAL.UInt8; + + -- Transmit PFC Pause Register + type GMAC_GMAC_TPFCP_Register is record + -- Priority Enable Vector + PEV : GMAC_GMAC_TPFCP_PEV_Field := 16#0#; + -- Pause Quantum + PQ : GMAC_GMAC_TPFCP_PQ_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for GMAC_GMAC_TPFCP_Register use record + PEV at 0 range 0 .. 7; + PQ at 0 range 8 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype GMAC_GMAC_SAMT1_ADDR_Field is HAL.UInt16; + + -- Specific Address 1 Mask Top Register + type GMAC_GMAC_SAMT1_Register is record + -- Specific Address 1 Mask + ADDR : GMAC_GMAC_SAMT1_ADDR_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for GMAC_GMAC_SAMT1_Register use record + ADDR at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype GMAC_GMAC_NSC_NANOSEC_Field is HAL.UInt22; + + -- 1588 Timer Nanosecond Comparison Register + type GMAC_GMAC_NSC_Register is record + -- 1588 Timer Nanosecond Comparison Value + NANOSEC : GMAC_GMAC_NSC_NANOSEC_Field := 16#0#; + -- unspecified + Reserved_22_31 : HAL.UInt10 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for GMAC_GMAC_NSC_Register use record + NANOSEC at 0 range 0 .. 21; + Reserved_22_31 at 0 range 22 .. 31; + end record; + + subtype GMAC_GMAC_SCH_SEC_Field is HAL.UInt16; + + -- 1588 Timer Second Comparison High Register + type GMAC_GMAC_SCH_Register is record + -- 1588 Timer Second Comparison Value + SEC : GMAC_GMAC_SCH_SEC_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for GMAC_GMAC_SCH_Register use record + SEC at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype GMAC_GMAC_EFTSH_RUD_Field is HAL.UInt16; + + -- PTP Event Frame Transmitted Seconds High Register + type GMAC_GMAC_EFTSH_Register is record + -- Read-only. Register Update + RUD : GMAC_GMAC_EFTSH_RUD_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for GMAC_GMAC_EFTSH_Register use record + RUD at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype GMAC_GMAC_EFRSH_RUD_Field is HAL.UInt16; + + -- PTP Event Frame Received Seconds High Register + type GMAC_GMAC_EFRSH_Register is record + -- Read-only. Register Update + RUD : GMAC_GMAC_EFRSH_RUD_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for GMAC_GMAC_EFRSH_Register use record + RUD at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype GMAC_GMAC_PEFTSH_RUD_Field is HAL.UInt16; + + -- PTP Peer Event Frame Transmitted Seconds High Register + type GMAC_GMAC_PEFTSH_Register is record + -- Read-only. Register Update + RUD : GMAC_GMAC_PEFTSH_RUD_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for GMAC_GMAC_PEFTSH_Register use record + RUD at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype GMAC_GMAC_PEFRSH_RUD_Field is HAL.UInt16; + + -- PTP Peer Event Frame Received Seconds High Register + type GMAC_GMAC_PEFRSH_Register is record + -- Read-only. Register Update + RUD : GMAC_GMAC_PEFRSH_RUD_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for GMAC_GMAC_PEFRSH_Register use record + RUD at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype GMAC_GMAC_MID_MREV_Field is HAL.UInt16; + subtype GMAC_GMAC_MID_MID_Field is HAL.UInt16; + + -- Module ID Register + type GMAC_GMAC_MID_Register is record + -- Read-only. Module Revision + MREV : GMAC_GMAC_MID_MREV_Field; + -- Read-only. Module Identification Number + MID : GMAC_GMAC_MID_MID_Field; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for GMAC_GMAC_MID_Register use record + MREV at 0 range 0 .. 15; + MID at 0 range 16 .. 31; + end record; + + subtype GMAC_GMAC_OTHI_TXO_Field is HAL.UInt16; + + -- Octets Transmitted High Register + type GMAC_GMAC_OTHI_Register is record + -- Read-only. Transmitted Octets + TXO : GMAC_GMAC_OTHI_TXO_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for GMAC_GMAC_OTHI_Register use record + TXO at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype GMAC_GMAC_PFT_PFTX_Field is HAL.UInt16; + + -- Pause Frames Transmitted Register + type GMAC_GMAC_PFT_Register is record + -- Read-only. Pause Frames Transmitted Register + PFTX : GMAC_GMAC_PFT_PFTX_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for GMAC_GMAC_PFT_Register use record + PFTX at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype GMAC_GMAC_TUR_TXUNR_Field is HAL.UInt10; + + -- Transmit Underruns Register + type GMAC_GMAC_TUR_Register is record + -- Read-only. Transmit Underruns + TXUNR : GMAC_GMAC_TUR_TXUNR_Field; + -- unspecified + Reserved_10_31 : HAL.UInt22; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for GMAC_GMAC_TUR_Register use record + TXUNR at 0 range 0 .. 9; + Reserved_10_31 at 0 range 10 .. 31; + end record; + + subtype GMAC_GMAC_SCF_SCOL_Field is HAL.UInt18; + + -- Single Collision Frames Register + type GMAC_GMAC_SCF_Register is record + -- Read-only. Single Collision + SCOL : GMAC_GMAC_SCF_SCOL_Field; + -- unspecified + Reserved_18_31 : HAL.UInt14; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for GMAC_GMAC_SCF_Register use record + SCOL at 0 range 0 .. 17; + Reserved_18_31 at 0 range 18 .. 31; + end record; + + subtype GMAC_GMAC_MCF_MCOL_Field is HAL.UInt18; + + -- Multiple Collision Frames Register + type GMAC_GMAC_MCF_Register is record + -- Read-only. Multiple Collision + MCOL : GMAC_GMAC_MCF_MCOL_Field; + -- unspecified + Reserved_18_31 : HAL.UInt14; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for GMAC_GMAC_MCF_Register use record + MCOL at 0 range 0 .. 17; + Reserved_18_31 at 0 range 18 .. 31; + end record; + + subtype GMAC_GMAC_EC_XCOL_Field is HAL.UInt10; + + -- Excessive Collisions Register + type GMAC_GMAC_EC_Register is record + -- Read-only. Excessive Collisions + XCOL : GMAC_GMAC_EC_XCOL_Field; + -- unspecified + Reserved_10_31 : HAL.UInt22; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for GMAC_GMAC_EC_Register use record + XCOL at 0 range 0 .. 9; + Reserved_10_31 at 0 range 10 .. 31; + end record; + + subtype GMAC_GMAC_LC_LCOL_Field is HAL.UInt10; + + -- Late Collisions Register + type GMAC_GMAC_LC_Register is record + -- Read-only. Late Collisions + LCOL : GMAC_GMAC_LC_LCOL_Field; + -- unspecified + Reserved_10_31 : HAL.UInt22; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for GMAC_GMAC_LC_Register use record + LCOL at 0 range 0 .. 9; + Reserved_10_31 at 0 range 10 .. 31; + end record; + + subtype GMAC_GMAC_DTF_DEFT_Field is HAL.UInt18; + + -- Deferred Transmission Frames Register + type GMAC_GMAC_DTF_Register is record + -- Read-only. Deferred Transmission + DEFT : GMAC_GMAC_DTF_DEFT_Field; + -- unspecified + Reserved_18_31 : HAL.UInt14; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for GMAC_GMAC_DTF_Register use record + DEFT at 0 range 0 .. 17; + Reserved_18_31 at 0 range 18 .. 31; + end record; + + subtype GMAC_GMAC_CSE_CSR_Field is HAL.UInt10; + + -- Carrier Sense Errors Register + type GMAC_GMAC_CSE_Register is record + -- Read-only. Carrier Sense Error + CSR : GMAC_GMAC_CSE_CSR_Field; + -- unspecified + Reserved_10_31 : HAL.UInt22; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for GMAC_GMAC_CSE_Register use record + CSR at 0 range 0 .. 9; + Reserved_10_31 at 0 range 10 .. 31; + end record; + + subtype GMAC_GMAC_ORHI_RXO_Field is HAL.UInt16; + + -- Octets Received High Received Register + type GMAC_GMAC_ORHI_Register is record + -- Read-only. Received Octets + RXO : GMAC_GMAC_ORHI_RXO_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for GMAC_GMAC_ORHI_Register use record + RXO at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype GMAC_GMAC_PFR_PFRX_Field is HAL.UInt16; + + -- Pause Frames Received Register + type GMAC_GMAC_PFR_Register is record + -- Read-only. Pause Frames Received Register + PFRX : GMAC_GMAC_PFR_PFRX_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for GMAC_GMAC_PFR_Register use record + PFRX at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype GMAC_GMAC_UFR_UFRX_Field is HAL.UInt10; + + -- Undersize Frames Received Register + type GMAC_GMAC_UFR_Register is record + -- Read-only. Undersize Frames Received + UFRX : GMAC_GMAC_UFR_UFRX_Field; + -- unspecified + Reserved_10_31 : HAL.UInt22; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for GMAC_GMAC_UFR_Register use record + UFRX at 0 range 0 .. 9; + Reserved_10_31 at 0 range 10 .. 31; + end record; + + subtype GMAC_GMAC_OFR_OFRX_Field is HAL.UInt10; + + -- Oversize Frames Received Register + type GMAC_GMAC_OFR_Register is record + -- Read-only. Oversized Frames Received + OFRX : GMAC_GMAC_OFR_OFRX_Field; + -- unspecified + Reserved_10_31 : HAL.UInt22; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for GMAC_GMAC_OFR_Register use record + OFRX at 0 range 0 .. 9; + Reserved_10_31 at 0 range 10 .. 31; + end record; + + subtype GMAC_GMAC_JR_JRX_Field is HAL.UInt10; + + -- Jabbers Received Register + type GMAC_GMAC_JR_Register is record + -- Read-only. Jabbers Received + JRX : GMAC_GMAC_JR_JRX_Field; + -- unspecified + Reserved_10_31 : HAL.UInt22; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for GMAC_GMAC_JR_Register use record + JRX at 0 range 0 .. 9; + Reserved_10_31 at 0 range 10 .. 31; + end record; + + subtype GMAC_GMAC_FCSE_FCKR_Field is HAL.UInt10; + + -- Frame Check Sequence Errors Register + type GMAC_GMAC_FCSE_Register is record + -- Read-only. Frame Check Sequence Errors + FCKR : GMAC_GMAC_FCSE_FCKR_Field; + -- unspecified + Reserved_10_31 : HAL.UInt22; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for GMAC_GMAC_FCSE_Register use record + FCKR at 0 range 0 .. 9; + Reserved_10_31 at 0 range 10 .. 31; + end record; + + subtype GMAC_GMAC_LFFE_LFER_Field is HAL.UInt10; + + -- Length Field Frame Errors Register + type GMAC_GMAC_LFFE_Register is record + -- Read-only. Length Field Frame Errors + LFER : GMAC_GMAC_LFFE_LFER_Field; + -- unspecified + Reserved_10_31 : HAL.UInt22; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for GMAC_GMAC_LFFE_Register use record + LFER at 0 range 0 .. 9; + Reserved_10_31 at 0 range 10 .. 31; + end record; + + subtype GMAC_GMAC_RSE_RXSE_Field is HAL.UInt10; + + -- Receive Symbol Errors Register + type GMAC_GMAC_RSE_Register is record + -- Read-only. Receive Symbol Errors + RXSE : GMAC_GMAC_RSE_RXSE_Field; + -- unspecified + Reserved_10_31 : HAL.UInt22; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for GMAC_GMAC_RSE_Register use record + RXSE at 0 range 0 .. 9; + Reserved_10_31 at 0 range 10 .. 31; + end record; + + subtype GMAC_GMAC_AE_AER_Field is HAL.UInt10; + + -- Alignment Errors Register + type GMAC_GMAC_AE_Register is record + -- Read-only. Alignment Errors + AER : GMAC_GMAC_AE_AER_Field; + -- unspecified + Reserved_10_31 : HAL.UInt22; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for GMAC_GMAC_AE_Register use record + AER at 0 range 0 .. 9; + Reserved_10_31 at 0 range 10 .. 31; + end record; + + subtype GMAC_GMAC_RRE_RXRER_Field is HAL.UInt18; + + -- Receive Resource Errors Register + type GMAC_GMAC_RRE_Register is record + -- Read-only. Receive Resource Errors + RXRER : GMAC_GMAC_RRE_RXRER_Field; + -- unspecified + Reserved_18_31 : HAL.UInt14; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for GMAC_GMAC_RRE_Register use record + RXRER at 0 range 0 .. 17; + Reserved_18_31 at 0 range 18 .. 31; + end record; + + subtype GMAC_GMAC_ROE_RXOVR_Field is HAL.UInt10; + + -- Receive Overrun Register + type GMAC_GMAC_ROE_Register is record + -- Read-only. Receive Overruns + RXOVR : GMAC_GMAC_ROE_RXOVR_Field; + -- unspecified + Reserved_10_31 : HAL.UInt22; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for GMAC_GMAC_ROE_Register use record + RXOVR at 0 range 0 .. 9; + Reserved_10_31 at 0 range 10 .. 31; + end record; + + subtype GMAC_GMAC_IHCE_HCKER_Field is HAL.UInt8; + + -- IP Header Checksum Errors Register + type GMAC_GMAC_IHCE_Register is record + -- Read-only. IP Header Checksum Errors + HCKER : GMAC_GMAC_IHCE_HCKER_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for GMAC_GMAC_IHCE_Register use record + HCKER at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype GMAC_GMAC_TCE_TCKER_Field is HAL.UInt8; + + -- TCP Checksum Errors Register + type GMAC_GMAC_TCE_Register is record + -- Read-only. TCP Checksum Errors + TCKER : GMAC_GMAC_TCE_TCKER_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for GMAC_GMAC_TCE_Register use record + TCKER at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype GMAC_GMAC_UCE_UCKER_Field is HAL.UInt8; + + -- UDP Checksum Errors Register + type GMAC_GMAC_UCE_Register is record + -- Read-only. UDP Checksum Errors + UCKER : GMAC_GMAC_UCE_UCKER_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for GMAC_GMAC_UCE_Register use record + UCKER at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype GMAC_GMAC_TISUBN_LSBTIR_Field is HAL.UInt16; + + -- 1588 Timer Increment Sub-nanoseconds Register + type GMAC_GMAC_TISUBN_Register is record + -- Lower Significant Bits of Timer Increment Register + LSBTIR : GMAC_GMAC_TISUBN_LSBTIR_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for GMAC_GMAC_TISUBN_Register use record + LSBTIR at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype GMAC_GMAC_TSH_TCS_Field is HAL.UInt16; + + -- 1588 Timer Seconds High Register + type GMAC_GMAC_TSH_Register is record + -- Timer Count in Seconds + TCS : GMAC_GMAC_TSH_TCS_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for GMAC_GMAC_TSH_Register use record + TCS at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype GMAC_GMAC_TN_TNS_Field is HAL.UInt30; + + -- 1588 Timer Nanoseconds Register + type GMAC_GMAC_TN_Register is record + -- Timer Count in Nanoseconds + TNS : GMAC_GMAC_TN_TNS_Field := 16#0#; + -- unspecified + Reserved_30_31 : HAL.UInt2 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for GMAC_GMAC_TN_Register use record + TNS at 0 range 0 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + subtype GMAC_GMAC_TA_ITDT_Field is HAL.UInt30; + + -- 1588 Timer Adjust Register + type GMAC_GMAC_TA_Register is record + -- Write-only. Increment/Decrement + ITDT : GMAC_GMAC_TA_ITDT_Field := 16#0#; + -- unspecified + Reserved_30_30 : HAL.Bit := 16#0#; + -- Write-only. Adjust 1588 Timer + ADJ : Boolean := False; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for GMAC_GMAC_TA_Register use record + ITDT at 0 range 0 .. 29; + Reserved_30_30 at 0 range 30 .. 30; + ADJ at 0 range 31 .. 31; + end record; + + subtype GMAC_GMAC_TI_CNS_Field is HAL.UInt8; + subtype GMAC_GMAC_TI_ACNS_Field is HAL.UInt8; + subtype GMAC_GMAC_TI_NIT_Field is HAL.UInt8; + + -- 1588 Timer Increment Register + type GMAC_GMAC_TI_Register is record + -- Count Nanoseconds + CNS : GMAC_GMAC_TI_CNS_Field := 16#0#; + -- Alternative Count Nanoseconds + ACNS : GMAC_GMAC_TI_ACNS_Field := 16#0#; + -- Number of Increments + NIT : GMAC_GMAC_TI_NIT_Field := 16#0#; + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for GMAC_GMAC_TI_Register use record + CNS at 0 range 0 .. 7; + ACNS at 0 range 8 .. 15; + NIT at 0 range 16 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype GMAC_GMAC_EFTN_RUD_Field is HAL.UInt30; + + -- PTP Event Frame Transmitted Nanoseconds Register + type GMAC_GMAC_EFTN_Register is record + -- Read-only. Register Update + RUD : GMAC_GMAC_EFTN_RUD_Field; + -- unspecified + Reserved_30_31 : HAL.UInt2; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for GMAC_GMAC_EFTN_Register use record + RUD at 0 range 0 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + subtype GMAC_GMAC_EFRN_RUD_Field is HAL.UInt30; + + -- PTP Event Frame Received Nanoseconds Register + type GMAC_GMAC_EFRN_Register is record + -- Read-only. Register Update + RUD : GMAC_GMAC_EFRN_RUD_Field; + -- unspecified + Reserved_30_31 : HAL.UInt2; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for GMAC_GMAC_EFRN_Register use record + RUD at 0 range 0 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + subtype GMAC_GMAC_PEFTN_RUD_Field is HAL.UInt30; + + -- PTP Peer Event Frame Transmitted Nanoseconds Register + type GMAC_GMAC_PEFTN_Register is record + -- Read-only. Register Update + RUD : GMAC_GMAC_PEFTN_RUD_Field; + -- unspecified + Reserved_30_31 : HAL.UInt2; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for GMAC_GMAC_PEFTN_Register use record + RUD at 0 range 0 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + subtype GMAC_GMAC_PEFRN_RUD_Field is HAL.UInt30; + + -- PTP Peer Event Frame Received Nanoseconds Register + type GMAC_GMAC_PEFRN_Register is record + -- Read-only. Register Update + RUD : GMAC_GMAC_PEFRN_RUD_Field; + -- unspecified + Reserved_30_31 : HAL.UInt2; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for GMAC_GMAC_PEFRN_Register use record + RUD at 0 range 0 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + -- Interrupt Status Register Priority Queue (index = 1) 0 + type GMAC_GMAC_ISRPQ_Register is record + -- unspecified + Reserved_0_0 : HAL.Bit; + -- Read-only. Receive Complete + RCOMP : Boolean; + -- Read-only. RX Used Bit Read + RXUBR : Boolean; + -- unspecified + Reserved_3_4 : HAL.UInt2; + -- Read-only. Retry Limit Exceeded or Late Collision + RLEX : Boolean; + -- Read-only. Transmit Frame Corruption Due to AHB Error + TFC : Boolean; + -- Read-only. Transmit Complete + TCOMP : Boolean; + -- unspecified + Reserved_8_9 : HAL.UInt2; + -- Read-only. Receive Overrun + ROVR : Boolean; + -- Read-only. HRESP Not OK + HRESP : Boolean; + -- unspecified + Reserved_12_31 : HAL.UInt20; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for GMAC_GMAC_ISRPQ_Register use record + Reserved_0_0 at 0 range 0 .. 0; + RCOMP at 0 range 1 .. 1; + RXUBR at 0 range 2 .. 2; + Reserved_3_4 at 0 range 3 .. 4; + RLEX at 0 range 5 .. 5; + TFC at 0 range 6 .. 6; + TCOMP at 0 range 7 .. 7; + Reserved_8_9 at 0 range 8 .. 9; + ROVR at 0 range 10 .. 10; + HRESP at 0 range 11 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + -- Interrupt Status Register Priority Queue (index = 1) 0 + type GMAC_GMAC_ISRPQ_Registers is array (0 .. 1) + of GMAC_GMAC_ISRPQ_Register + with Volatile; + + subtype GMAC_GMAC_TBQBAPQ_TXBQBA_Field is HAL.UInt30; + + -- Transmit Buffer Queue Base Address Register Priority Queue (index = 1) 0 + type GMAC_GMAC_TBQBAPQ_Register is record + -- unspecified + Reserved_0_1 : HAL.UInt2 := 16#0#; + -- Transmit Buffer Queue Base Address + TXBQBA : GMAC_GMAC_TBQBAPQ_TXBQBA_Field := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for GMAC_GMAC_TBQBAPQ_Register use record + Reserved_0_1 at 0 range 0 .. 1; + TXBQBA at 0 range 2 .. 31; + end record; + + -- Transmit Buffer Queue Base Address Register Priority Queue (index = 1) 0 + type GMAC_GMAC_TBQBAPQ_Registers is array (0 .. 1) + of GMAC_GMAC_TBQBAPQ_Register + with Volatile; + + subtype GMAC_GMAC_RBQBAPQ_RXBQBA_Field is HAL.UInt30; + + -- Receive Buffer Queue Base Address Register Priority Queue (index = 1) 0 + type GMAC_GMAC_RBQBAPQ_Register is record + -- unspecified + Reserved_0_1 : HAL.UInt2 := 16#0#; + -- Receive Buffer Queue Base Address + RXBQBA : GMAC_GMAC_RBQBAPQ_RXBQBA_Field := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for GMAC_GMAC_RBQBAPQ_Register use record + Reserved_0_1 at 0 range 0 .. 1; + RXBQBA at 0 range 2 .. 31; + end record; + + -- Receive Buffer Queue Base Address Register Priority Queue (index = 1) 0 + type GMAC_GMAC_RBQBAPQ_Registers is array (0 .. 1) + of GMAC_GMAC_RBQBAPQ_Register + with Volatile; + + subtype GMAC_GMAC_RBSRPQ_RBS_Field is HAL.UInt16; + + -- Receive Buffer Size Register Priority Queue (index = 1) 0 + type GMAC_GMAC_RBSRPQ_Register is record + -- Receive Buffer Size + RBS : GMAC_GMAC_RBSRPQ_RBS_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for GMAC_GMAC_RBSRPQ_Register use record + RBS at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + -- Receive Buffer Size Register Priority Queue (index = 1) 0 + type GMAC_GMAC_RBSRPQ_Registers is array (0 .. 1) + of GMAC_GMAC_RBSRPQ_Register + with Volatile; + + -- Credit-Based Shaping Control Register + type GMAC_GMAC_CBSCR_Register is record + -- Queue B CBS Enable + QBE : Boolean := False; + -- Queue A CBS Enable + QAE : Boolean := False; + -- unspecified + Reserved_2_31 : HAL.UInt30 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for GMAC_GMAC_CBSCR_Register use record + QBE at 0 range 0 .. 0; + QAE at 0 range 1 .. 1; + Reserved_2_31 at 0 range 2 .. 31; + end record; + + subtype GMAC_GMAC_ST1RPQ_QNB_Field is HAL.UInt3; + subtype GMAC_GMAC_ST1RPQ_DSTCM_Field is HAL.UInt8; + subtype GMAC_GMAC_ST1RPQ_UDPM_Field is HAL.UInt16; + + -- Screening Type 1 Register Priority Queue (index = 0) 0 + type GMAC_GMAC_ST1RPQ_Register is record + -- Queue Number (0-2) + QNB : GMAC_GMAC_ST1RPQ_QNB_Field := 16#0#; + -- unspecified + Reserved_3_3 : HAL.Bit := 16#0#; + -- Differentiated Services or Traffic Class Match + DSTCM : GMAC_GMAC_ST1RPQ_DSTCM_Field := 16#0#; + -- UDP Port Match + UDPM : GMAC_GMAC_ST1RPQ_UDPM_Field := 16#0#; + -- Differentiated Services or Traffic Class Match Enable + DSTCE : Boolean := False; + -- UDP Port Match Enable + UDPE : Boolean := False; + -- unspecified + Reserved_30_31 : HAL.UInt2 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for GMAC_GMAC_ST1RPQ_Register use record + QNB at 0 range 0 .. 2; + Reserved_3_3 at 0 range 3 .. 3; + DSTCM at 0 range 4 .. 11; + UDPM at 0 range 12 .. 27; + DSTCE at 0 range 28 .. 28; + UDPE at 0 range 29 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + -- Screening Type 1 Register Priority Queue (index = 0) 0 + type GMAC_GMAC_ST1RPQ_Registers is array (0 .. 3) + of GMAC_GMAC_ST1RPQ_Register + with Volatile; + + subtype GMAC_GMAC_ST2RPQ_QNB_Field is HAL.UInt3; + subtype GMAC_GMAC_ST2RPQ_VLANP_Field is HAL.UInt3; + subtype GMAC_GMAC_ST2RPQ_I2ETH_Field is HAL.UInt3; + subtype GMAC_GMAC_ST2RPQ_COMPA_Field is HAL.UInt5; + subtype GMAC_GMAC_ST2RPQ_COMPB_Field is HAL.UInt5; + subtype GMAC_GMAC_ST2RPQ_COMPC_Field is HAL.UInt5; + + -- Screening Type 2 Register Priority Queue (index = 0) 0 + type GMAC_GMAC_ST2RPQ_Register is record + -- Queue Number (0-2) + QNB : GMAC_GMAC_ST2RPQ_QNB_Field := 16#0#; + -- unspecified + Reserved_3_3 : HAL.Bit := 16#0#; + -- VLAN Priority + VLANP : GMAC_GMAC_ST2RPQ_VLANP_Field := 16#0#; + -- unspecified + Reserved_7_7 : HAL.Bit := 16#0#; + -- VLAN Enable + VLANE : Boolean := False; + -- Index of Screening Type 2 EtherType register x + I2ETH : GMAC_GMAC_ST2RPQ_I2ETH_Field := 16#0#; + -- EtherType Enable + ETHE : Boolean := False; + -- Index of Screening Type 2 Compare Word 0/Word 1 register x + COMPA : GMAC_GMAC_ST2RPQ_COMPA_Field := 16#0#; + -- Compare A Enable + COMPAE : Boolean := False; + -- Index of Screening Type 2 Compare Word 0/Word 1 register x + COMPB : GMAC_GMAC_ST2RPQ_COMPB_Field := 16#0#; + -- Compare B Enable + COMPBE : Boolean := False; + -- Index of Screening Type 2 Compare Word 0/Word 1 register x + COMPC : GMAC_GMAC_ST2RPQ_COMPC_Field := 16#0#; + -- Compare C Enable + COMPCE : Boolean := False; + -- unspecified + Reserved_31_31 : HAL.Bit := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for GMAC_GMAC_ST2RPQ_Register use record + QNB at 0 range 0 .. 2; + Reserved_3_3 at 0 range 3 .. 3; + VLANP at 0 range 4 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + VLANE at 0 range 8 .. 8; + I2ETH at 0 range 9 .. 11; + ETHE at 0 range 12 .. 12; + COMPA at 0 range 13 .. 17; + COMPAE at 0 range 18 .. 18; + COMPB at 0 range 19 .. 23; + COMPBE at 0 range 24 .. 24; + COMPC at 0 range 25 .. 29; + COMPCE at 0 range 30 .. 30; + Reserved_31_31 at 0 range 31 .. 31; + end record; + + -- Screening Type 2 Register Priority Queue (index = 0) 0 + type GMAC_GMAC_ST2RPQ_Registers is array (0 .. 7) + of GMAC_GMAC_ST2RPQ_Register + with Volatile; + + -- Interrupt Enable Register Priority Queue (index = 1) 0 + type GMAC_GMAC_IERPQ_Register is record + -- unspecified + Reserved_0_0 : HAL.Bit := 16#0#; + -- Write-only. Receive Complete + RCOMP : Boolean := False; + -- Write-only. RX Used Bit Read + RXUBR : Boolean := False; + -- unspecified + Reserved_3_4 : HAL.UInt2 := 16#0#; + -- Write-only. Retry Limit Exceeded or Late Collision + RLEX : Boolean := False; + -- Write-only. Transmit Frame Corruption Due to AHB Error + TFC : Boolean := False; + -- Write-only. Transmit Complete + TCOMP : Boolean := False; + -- unspecified + Reserved_8_9 : HAL.UInt2 := 16#0#; + -- Write-only. Receive Overrun + ROVR : Boolean := False; + -- Write-only. HRESP Not OK + HRESP : Boolean := False; + -- unspecified + Reserved_12_31 : HAL.UInt20 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for GMAC_GMAC_IERPQ_Register use record + Reserved_0_0 at 0 range 0 .. 0; + RCOMP at 0 range 1 .. 1; + RXUBR at 0 range 2 .. 2; + Reserved_3_4 at 0 range 3 .. 4; + RLEX at 0 range 5 .. 5; + TFC at 0 range 6 .. 6; + TCOMP at 0 range 7 .. 7; + Reserved_8_9 at 0 range 8 .. 9; + ROVR at 0 range 10 .. 10; + HRESP at 0 range 11 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + -- Interrupt Enable Register Priority Queue (index = 1) 0 + type GMAC_GMAC_IERPQ_Registers is array (0 .. 1) + of GMAC_GMAC_IERPQ_Register + with Volatile; + + -- Interrupt Disable Register Priority Queue (index = 1) 0 + type GMAC_GMAC_IDRPQ_Register is record + -- unspecified + Reserved_0_0 : HAL.Bit := 16#0#; + -- Write-only. Receive Complete + RCOMP : Boolean := False; + -- Write-only. RX Used Bit Read + RXUBR : Boolean := False; + -- unspecified + Reserved_3_4 : HAL.UInt2 := 16#0#; + -- Write-only. Retry Limit Exceeded or Late Collision + RLEX : Boolean := False; + -- Write-only. Transmit Frame Corruption Due to AHB Error + TFC : Boolean := False; + -- Write-only. Transmit Complete + TCOMP : Boolean := False; + -- unspecified + Reserved_8_9 : HAL.UInt2 := 16#0#; + -- Write-only. Receive Overrun + ROVR : Boolean := False; + -- Write-only. HRESP Not OK + HRESP : Boolean := False; + -- unspecified + Reserved_12_31 : HAL.UInt20 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for GMAC_GMAC_IDRPQ_Register use record + Reserved_0_0 at 0 range 0 .. 0; + RCOMP at 0 range 1 .. 1; + RXUBR at 0 range 2 .. 2; + Reserved_3_4 at 0 range 3 .. 4; + RLEX at 0 range 5 .. 5; + TFC at 0 range 6 .. 6; + TCOMP at 0 range 7 .. 7; + Reserved_8_9 at 0 range 8 .. 9; + ROVR at 0 range 10 .. 10; + HRESP at 0 range 11 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + -- Interrupt Disable Register Priority Queue (index = 1) 0 + type GMAC_GMAC_IDRPQ_Registers is array (0 .. 1) + of GMAC_GMAC_IDRPQ_Register + with Volatile; + + -- Interrupt Mask Register Priority Queue (index = 1) 0 + type GMAC_GMAC_IMRPQ_Register is record + -- unspecified + Reserved_0_0 : HAL.Bit := 16#0#; + -- Receive Complete + RCOMP : Boolean := False; + -- RX Used Bit Read + RXUBR : Boolean := False; + -- unspecified + Reserved_3_4 : HAL.UInt2 := 16#0#; + -- Retry Limit Exceeded or Late Collision + RLEX : Boolean := False; + -- AHB Error + AHB : Boolean := False; + -- Transmit Complete + TCOMP : Boolean := False; + -- unspecified + Reserved_8_9 : HAL.UInt2 := 16#0#; + -- Receive Overrun + ROVR : Boolean := False; + -- HRESP Not OK + HRESP : Boolean := False; + -- unspecified + Reserved_12_31 : HAL.UInt20 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for GMAC_GMAC_IMRPQ_Register use record + Reserved_0_0 at 0 range 0 .. 0; + RCOMP at 0 range 1 .. 1; + RXUBR at 0 range 2 .. 2; + Reserved_3_4 at 0 range 3 .. 4; + RLEX at 0 range 5 .. 5; + AHB at 0 range 6 .. 6; + TCOMP at 0 range 7 .. 7; + Reserved_8_9 at 0 range 8 .. 9; + ROVR at 0 range 10 .. 10; + HRESP at 0 range 11 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + -- Interrupt Mask Register Priority Queue (index = 1) 0 + type GMAC_GMAC_IMRPQ_Registers is array (0 .. 1) + of GMAC_GMAC_IMRPQ_Register + with Volatile; + + subtype GMAC_GMAC_ST2ER_COMPVAL_Field is HAL.UInt16; + + -- Screening Type 2 Ethertype Register (index = 0) 0 + type GMAC_GMAC_ST2ER_Register is record + -- Ethertype Compare Value + COMPVAL : GMAC_GMAC_ST2ER_COMPVAL_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for GMAC_GMAC_ST2ER_Register use record + COMPVAL at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + -- Screening Type 2 Ethertype Register (index = 0) 0 + type GMAC_GMAC_ST2ER_Registers is array (0 .. 3) + of GMAC_GMAC_ST2ER_Register + with Volatile; + + subtype GMAC_ST2CW_MASKVAL_Field is HAL.UInt16; + subtype GMAC_ST2CW_COMPVAL_Field is HAL.UInt16; + + -- Screening Type 2 Compare Word 0 Register (index = 0) + type GMAC_ST2CW_Register is record + -- Mask Value + MASKVAL : GMAC_ST2CW_MASKVAL_Field := 16#0#; + -- Compare Value + COMPVAL : GMAC_ST2CW_COMPVAL_Field := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for GMAC_ST2CW_Register use record + MASKVAL at 0 range 0 .. 15; + COMPVAL at 0 range 16 .. 31; + end record; + + subtype GMAC_ST2CW_OFFSVAL_Field is HAL.UInt7; + + -- Ethernet Frame Offset Start + type GMAC_ST2CW10_OFFSSTRT_Field is + ( + -- Offset from the start of the frame + Framestart, + -- Offset from the byte after the EtherType field + Ethertype, + -- Offset from the byte after the IP header field + Ip, + -- Offset from the byte after the TCP/UDP header field + Tcp_Udp) + with Size => 2; + for GMAC_ST2CW10_OFFSSTRT_Field use + (Framestart => 0, + Ethertype => 1, + Ip => 2, + Tcp_Udp => 3); + + -- Screening Type 2 Compare Word 1 Register (index = 0) + type GMAC_ST2CW_Register_1 is record + -- Offset Value in Bytes + OFFSVAL : GMAC_ST2CW_OFFSVAL_Field := 16#0#; + -- Ethernet Frame Offset Start + OFFSSTRT : GMAC_ST2CW10_OFFSSTRT_Field := SAM_SVD.GMAC.Framestart; + -- unspecified + Reserved_9_31 : HAL.UInt23 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for GMAC_ST2CW_Register_1 use record + OFFSVAL at 0 range 0 .. 6; + OFFSSTRT at 0 range 7 .. 8; + Reserved_9_31 at 0 range 9 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- Gigabit Ethernet MAC + type GMAC_Peripheral is record + -- Network Control Register + GMAC_NCR : aliased GMAC_GMAC_NCR_Register; + -- Network Configuration Register + GMAC_NCFGR : aliased GMAC_GMAC_NCFGR_Register; + -- Network Status Register + GMAC_NSR : aliased GMAC_GMAC_NSR_Register; + -- User Register + GMAC_UR : aliased GMAC_GMAC_UR_Register; + -- DMA Configuration Register + GMAC_DCFGR : aliased GMAC_GMAC_DCFGR_Register; + -- Transmit Status Register + GMAC_TSR : aliased GMAC_GMAC_TSR_Register; + -- Receive Buffer Queue Base Address Register + GMAC_RBQB : aliased GMAC_GMAC_RBQB_Register; + -- Transmit Buffer Queue Base Address Register + GMAC_TBQB : aliased GMAC_GMAC_TBQB_Register; + -- Receive Status Register + GMAC_RSR : aliased GMAC_GMAC_RSR_Register; + -- Interrupt Status Register + GMAC_ISR : aliased GMAC_GMAC_ISR_Register; + -- Interrupt Enable Register + GMAC_IER : aliased GMAC_GMAC_IER_Register; + -- Interrupt Disable Register + GMAC_IDR : aliased GMAC_GMAC_IDR_Register; + -- Interrupt Mask Register + GMAC_IMR : aliased GMAC_GMAC_IMR_Register; + -- PHY Maintenance Register + GMAC_MAN : aliased GMAC_GMAC_MAN_Register; + -- Received Pause Quantum Register + GMAC_RPQ : aliased GMAC_GMAC_RPQ_Register; + -- Transmit Pause Quantum Register + GMAC_TPQ : aliased GMAC_GMAC_TPQ_Register; + -- TX Partial Store and Forward Register + GMAC_TPSF : aliased GMAC_GMAC_TPSF_Register; + -- RX Partial Store and Forward Register + GMAC_RPSF : aliased GMAC_GMAC_RPSF_Register; + -- RX Jumbo Frame Max Length Register + GMAC_RJFML : aliased GMAC_GMAC_RJFML_Register; + -- Hash Register Bottom + GMAC_HRB : aliased HAL.UInt32; + -- Hash Register Top + GMAC_HRT : aliased HAL.UInt32; + -- Specific Address 1 Bottom Register + GMAC_GMAC_SA : aliased GMAC_GMAC_SA_Clusters; + -- Type ID Match 1 Register + GMAC_TIDM1 : aliased GMAC_GMAC_TIDM1_Register; + -- Type ID Match 2 Register + GMAC_TIDM2 : aliased GMAC_GMAC_TIDM2_Register; + -- Type ID Match 3 Register + GMAC_TIDM3 : aliased GMAC_GMAC_TIDM3_Register; + -- Type ID Match 4 Register + GMAC_TIDM4 : aliased GMAC_GMAC_TIDM4_Register; + -- Wake on LAN Register + GMAC_WOL : aliased GMAC_GMAC_WOL_Register; + -- IPG Stretch Register + GMAC_IPGS : aliased GMAC_GMAC_IPGS_Register; + -- Stacked VLAN Register + GMAC_SVLAN : aliased GMAC_GMAC_SVLAN_Register; + -- Transmit PFC Pause Register + GMAC_TPFCP : aliased GMAC_GMAC_TPFCP_Register; + -- Specific Address 1 Mask Bottom Register + GMAC_SAMB1 : aliased HAL.UInt32; + -- Specific Address 1 Mask Top Register + GMAC_SAMT1 : aliased GMAC_GMAC_SAMT1_Register; + -- 1588 Timer Nanosecond Comparison Register + GMAC_NSC : aliased GMAC_GMAC_NSC_Register; + -- 1588 Timer Second Comparison Low Register + GMAC_SCL : aliased HAL.UInt32; + -- 1588 Timer Second Comparison High Register + GMAC_SCH : aliased GMAC_GMAC_SCH_Register; + -- PTP Event Frame Transmitted Seconds High Register + GMAC_EFTSH : aliased GMAC_GMAC_EFTSH_Register; + -- PTP Event Frame Received Seconds High Register + GMAC_EFRSH : aliased GMAC_GMAC_EFRSH_Register; + -- PTP Peer Event Frame Transmitted Seconds High Register + GMAC_PEFTSH : aliased GMAC_GMAC_PEFTSH_Register; + -- PTP Peer Event Frame Received Seconds High Register + GMAC_PEFRSH : aliased GMAC_GMAC_PEFRSH_Register; + -- Module ID Register + GMAC_MID : aliased GMAC_GMAC_MID_Register; + -- Octets Transmitted Low Register + GMAC_OTLO : aliased HAL.UInt32; + -- Octets Transmitted High Register + GMAC_OTHI : aliased GMAC_GMAC_OTHI_Register; + -- Frames Transmitted Register + GMAC_FT : aliased HAL.UInt32; + -- Broadcast Frames Transmitted Register + GMAC_BCFT : aliased HAL.UInt32; + -- Multicast Frames Transmitted Register + GMAC_MFT : aliased HAL.UInt32; + -- Pause Frames Transmitted Register + GMAC_PFT : aliased GMAC_GMAC_PFT_Register; + -- 64 Byte Frames Transmitted Register + GMAC_BFT64 : aliased HAL.UInt32; + -- 65 to 127 Byte Frames Transmitted Register + GMAC_TBFT127 : aliased HAL.UInt32; + -- 128 to 255 Byte Frames Transmitted Register + GMAC_TBFT255 : aliased HAL.UInt32; + -- 256 to 511 Byte Frames Transmitted Register + GMAC_TBFT511 : aliased HAL.UInt32; + -- 512 to 1023 Byte Frames Transmitted Register + GMAC_TBFT1023 : aliased HAL.UInt32; + -- 1024 to 1518 Byte Frames Transmitted Register + GMAC_TBFT1518 : aliased HAL.UInt32; + -- Greater Than 1518 Byte Frames Transmitted Register + GMAC_GTBFT1518 : aliased HAL.UInt32; + -- Transmit Underruns Register + GMAC_TUR : aliased GMAC_GMAC_TUR_Register; + -- Single Collision Frames Register + GMAC_SCF : aliased GMAC_GMAC_SCF_Register; + -- Multiple Collision Frames Register + GMAC_MCF : aliased GMAC_GMAC_MCF_Register; + -- Excessive Collisions Register + GMAC_EC : aliased GMAC_GMAC_EC_Register; + -- Late Collisions Register + GMAC_LC : aliased GMAC_GMAC_LC_Register; + -- Deferred Transmission Frames Register + GMAC_DTF : aliased GMAC_GMAC_DTF_Register; + -- Carrier Sense Errors Register + GMAC_CSE : aliased GMAC_GMAC_CSE_Register; + -- Octets Received Low Received Register + GMAC_ORLO : aliased HAL.UInt32; + -- Octets Received High Received Register + GMAC_ORHI : aliased GMAC_GMAC_ORHI_Register; + -- Frames Received Register + GMAC_FR : aliased HAL.UInt32; + -- Broadcast Frames Received Register + GMAC_BCFR : aliased HAL.UInt32; + -- Multicast Frames Received Register + GMAC_MFR : aliased HAL.UInt32; + -- Pause Frames Received Register + GMAC_PFR : aliased GMAC_GMAC_PFR_Register; + -- 64 Byte Frames Received Register + GMAC_BFR64 : aliased HAL.UInt32; + -- 65 to 127 Byte Frames Received Register + GMAC_TBFR127 : aliased HAL.UInt32; + -- 128 to 255 Byte Frames Received Register + GMAC_TBFR255 : aliased HAL.UInt32; + -- 256 to 511 Byte Frames Received Register + GMAC_TBFR511 : aliased HAL.UInt32; + -- 512 to 1023 Byte Frames Received Register + GMAC_TBFR1023 : aliased HAL.UInt32; + -- 1024 to 1518 Byte Frames Received Register + GMAC_TBFR1518 : aliased HAL.UInt32; + -- 1519 to Maximum Byte Frames Received Register + GMAC_TMXBFR : aliased HAL.UInt32; + -- Undersize Frames Received Register + GMAC_UFR : aliased GMAC_GMAC_UFR_Register; + -- Oversize Frames Received Register + GMAC_OFR : aliased GMAC_GMAC_OFR_Register; + -- Jabbers Received Register + GMAC_JR : aliased GMAC_GMAC_JR_Register; + -- Frame Check Sequence Errors Register + GMAC_FCSE : aliased GMAC_GMAC_FCSE_Register; + -- Length Field Frame Errors Register + GMAC_LFFE : aliased GMAC_GMAC_LFFE_Register; + -- Receive Symbol Errors Register + GMAC_RSE : aliased GMAC_GMAC_RSE_Register; + -- Alignment Errors Register + GMAC_AE : aliased GMAC_GMAC_AE_Register; + -- Receive Resource Errors Register + GMAC_RRE : aliased GMAC_GMAC_RRE_Register; + -- Receive Overrun Register + GMAC_ROE : aliased GMAC_GMAC_ROE_Register; + -- IP Header Checksum Errors Register + GMAC_IHCE : aliased GMAC_GMAC_IHCE_Register; + -- TCP Checksum Errors Register + GMAC_TCE : aliased GMAC_GMAC_TCE_Register; + -- UDP Checksum Errors Register + GMAC_UCE : aliased GMAC_GMAC_UCE_Register; + -- 1588 Timer Increment Sub-nanoseconds Register + GMAC_TISUBN : aliased GMAC_GMAC_TISUBN_Register; + -- 1588 Timer Seconds High Register + GMAC_TSH : aliased GMAC_GMAC_TSH_Register; + -- 1588 Timer Seconds Low Register + GMAC_TSL : aliased HAL.UInt32; + -- 1588 Timer Nanoseconds Register + GMAC_TN : aliased GMAC_GMAC_TN_Register; + -- 1588 Timer Adjust Register + GMAC_TA : aliased GMAC_GMAC_TA_Register; + -- 1588 Timer Increment Register + GMAC_TI : aliased GMAC_GMAC_TI_Register; + -- PTP Event Frame Transmitted Seconds Low Register + GMAC_EFTSL : aliased HAL.UInt32; + -- PTP Event Frame Transmitted Nanoseconds Register + GMAC_EFTN : aliased GMAC_GMAC_EFTN_Register; + -- PTP Event Frame Received Seconds Low Register + GMAC_EFRSL : aliased HAL.UInt32; + -- PTP Event Frame Received Nanoseconds Register + GMAC_EFRN : aliased GMAC_GMAC_EFRN_Register; + -- PTP Peer Event Frame Transmitted Seconds Low Register + GMAC_PEFTSL : aliased HAL.UInt32; + -- PTP Peer Event Frame Transmitted Nanoseconds Register + GMAC_PEFTN : aliased GMAC_GMAC_PEFTN_Register; + -- PTP Peer Event Frame Received Seconds Low Register + GMAC_PEFRSL : aliased HAL.UInt32; + -- PTP Peer Event Frame Received Nanoseconds Register + GMAC_PEFRN : aliased GMAC_GMAC_PEFRN_Register; + -- Interrupt Status Register Priority Queue (index = 1) 0 + GMAC_ISRPQ : aliased GMAC_GMAC_ISRPQ_Registers; + -- Transmit Buffer Queue Base Address Register Priority Queue (index = + -- 1) 0 + GMAC_TBQBAPQ : aliased GMAC_GMAC_TBQBAPQ_Registers; + -- Receive Buffer Queue Base Address Register Priority Queue (index = 1) + -- 0 + GMAC_RBQBAPQ : aliased GMAC_GMAC_RBQBAPQ_Registers; + -- Receive Buffer Size Register Priority Queue (index = 1) 0 + GMAC_RBSRPQ : aliased GMAC_GMAC_RBSRPQ_Registers; + -- Credit-Based Shaping Control Register + GMAC_CBSCR : aliased GMAC_GMAC_CBSCR_Register; + -- Credit-Based Shaping IdleSlope Register for Queue A + GMAC_CBSISQA : aliased HAL.UInt32; + -- Credit-Based Shaping IdleSlope Register for Queue B + GMAC_CBSISQB : aliased HAL.UInt32; + -- Screening Type 1 Register Priority Queue (index = 0) 0 + GMAC_ST1RPQ : aliased GMAC_GMAC_ST1RPQ_Registers; + -- Screening Type 2 Register Priority Queue (index = 0) 0 + GMAC_ST2RPQ : aliased GMAC_GMAC_ST2RPQ_Registers; + -- Interrupt Enable Register Priority Queue (index = 1) 0 + GMAC_IERPQ : aliased GMAC_GMAC_IERPQ_Registers; + -- Interrupt Disable Register Priority Queue (index = 1) 0 + GMAC_IDRPQ : aliased GMAC_GMAC_IDRPQ_Registers; + -- Interrupt Mask Register Priority Queue (index = 1) 0 + GMAC_IMRPQ : aliased GMAC_GMAC_IMRPQ_Registers; + -- Screening Type 2 Ethertype Register (index = 0) 0 + GMAC_ST2ER : aliased GMAC_GMAC_ST2ER_Registers; + -- Screening Type 2 Compare Word 0 Register (index = 0) + GMAC_ST2CW00 : aliased GMAC_ST2CW_Register; + -- Screening Type 2 Compare Word 1 Register (index = 0) + GMAC_ST2CW10 : aliased GMAC_ST2CW_Register_1; + -- Screening Type 2 Compare Word 0 Register (index = 1) + GMAC_ST2CW01 : aliased GMAC_ST2CW_Register; + -- Screening Type 2 Compare Word 1 Register (index = 1) + GMAC_ST2CW11 : aliased GMAC_ST2CW_Register_1; + -- Screening Type 2 Compare Word 0 Register (index = 2) + GMAC_ST2CW02 : aliased GMAC_ST2CW_Register; + -- Screening Type 2 Compare Word 1 Register (index = 2) + GMAC_ST2CW12 : aliased GMAC_ST2CW_Register_1; + -- Screening Type 2 Compare Word 0 Register (index = 3) + GMAC_ST2CW03 : aliased GMAC_ST2CW_Register; + -- Screening Type 2 Compare Word 1 Register (index = 3) + GMAC_ST2CW13 : aliased GMAC_ST2CW_Register_1; + -- Screening Type 2 Compare Word 0 Register (index = 4) + GMAC_ST2CW04 : aliased GMAC_ST2CW_Register; + -- Screening Type 2 Compare Word 1 Register (index = 4) + GMAC_ST2CW14 : aliased GMAC_ST2CW_Register_1; + -- Screening Type 2 Compare Word 0 Register (index = 5) + GMAC_ST2CW05 : aliased GMAC_ST2CW_Register; + -- Screening Type 2 Compare Word 1 Register (index = 5) + GMAC_ST2CW15 : aliased GMAC_ST2CW_Register_1; + -- Screening Type 2 Compare Word 0 Register (index = 6) + GMAC_ST2CW06 : aliased GMAC_ST2CW_Register; + -- Screening Type 2 Compare Word 1 Register (index = 6) + GMAC_ST2CW16 : aliased GMAC_ST2CW_Register_1; + -- Screening Type 2 Compare Word 0 Register (index = 7) + GMAC_ST2CW07 : aliased GMAC_ST2CW_Register; + -- Screening Type 2 Compare Word 1 Register (index = 7) + GMAC_ST2CW17 : aliased GMAC_ST2CW_Register_1; + -- Screening Type 2 Compare Word 0 Register (index = 8) + GMAC_ST2CW08 : aliased GMAC_ST2CW_Register; + -- Screening Type 2 Compare Word 1 Register (index = 8) + GMAC_ST2CW18 : aliased GMAC_ST2CW_Register_1; + -- Screening Type 2 Compare Word 0 Register (index = 9) + GMAC_ST2CW09 : aliased GMAC_ST2CW_Register; + -- Screening Type 2 Compare Word 1 Register (index = 9) + GMAC_ST2CW19 : aliased GMAC_ST2CW_Register_1; + -- Screening Type 2 Compare Word 0 Register (index = 10) + GMAC_ST2CW010 : aliased GMAC_ST2CW_Register; + -- Screening Type 2 Compare Word 1 Register (index = 10) + GMAC_ST2CW110 : aliased GMAC_ST2CW_Register_1; + -- Screening Type 2 Compare Word 0 Register (index = 11) + GMAC_ST2CW011 : aliased GMAC_ST2CW_Register; + -- Screening Type 2 Compare Word 1 Register (index = 11) + GMAC_ST2CW111 : aliased GMAC_ST2CW_Register_1; + -- Screening Type 2 Compare Word 0 Register (index = 12) + GMAC_ST2CW012 : aliased GMAC_ST2CW_Register; + -- Screening Type 2 Compare Word 1 Register (index = 12) + GMAC_ST2CW112 : aliased GMAC_ST2CW_Register_1; + -- Screening Type 2 Compare Word 0 Register (index = 13) + GMAC_ST2CW013 : aliased GMAC_ST2CW_Register; + -- Screening Type 2 Compare Word 1 Register (index = 13) + GMAC_ST2CW113 : aliased GMAC_ST2CW_Register_1; + -- Screening Type 2 Compare Word 0 Register (index = 14) + GMAC_ST2CW014 : aliased GMAC_ST2CW_Register; + -- Screening Type 2 Compare Word 1 Register (index = 14) + GMAC_ST2CW114 : aliased GMAC_ST2CW_Register_1; + -- Screening Type 2 Compare Word 0 Register (index = 15) + GMAC_ST2CW015 : aliased GMAC_ST2CW_Register; + -- Screening Type 2 Compare Word 1 Register (index = 15) + GMAC_ST2CW115 : aliased GMAC_ST2CW_Register_1; + -- Screening Type 2 Compare Word 0 Register (index = 16) + GMAC_ST2CW016 : aliased GMAC_ST2CW_Register; + -- Screening Type 2 Compare Word 1 Register (index = 16) + GMAC_ST2CW116 : aliased GMAC_ST2CW_Register_1; + -- Screening Type 2 Compare Word 0 Register (index = 17) + GMAC_ST2CW017 : aliased GMAC_ST2CW_Register; + -- Screening Type 2 Compare Word 1 Register (index = 17) + GMAC_ST2CW117 : aliased GMAC_ST2CW_Register_1; + -- Screening Type 2 Compare Word 0 Register (index = 18) + GMAC_ST2CW018 : aliased GMAC_ST2CW_Register; + -- Screening Type 2 Compare Word 1 Register (index = 18) + GMAC_ST2CW118 : aliased GMAC_ST2CW_Register_1; + -- Screening Type 2 Compare Word 0 Register (index = 19) + GMAC_ST2CW019 : aliased GMAC_ST2CW_Register; + -- Screening Type 2 Compare Word 1 Register (index = 19) + GMAC_ST2CW119 : aliased GMAC_ST2CW_Register_1; + -- Screening Type 2 Compare Word 0 Register (index = 20) + GMAC_ST2CW020 : aliased GMAC_ST2CW_Register; + -- Screening Type 2 Compare Word 1 Register (index = 20) + GMAC_ST2CW120 : aliased GMAC_ST2CW_Register_1; + -- Screening Type 2 Compare Word 0 Register (index = 21) + GMAC_ST2CW021 : aliased GMAC_ST2CW_Register; + -- Screening Type 2 Compare Word 1 Register (index = 21) + GMAC_ST2CW121 : aliased GMAC_ST2CW_Register_1; + -- Screening Type 2 Compare Word 0 Register (index = 22) + GMAC_ST2CW022 : aliased GMAC_ST2CW_Register; + -- Screening Type 2 Compare Word 1 Register (index = 22) + GMAC_ST2CW122 : aliased GMAC_ST2CW_Register_1; + -- Screening Type 2 Compare Word 0 Register (index = 23) + GMAC_ST2CW023 : aliased GMAC_ST2CW_Register; + -- Screening Type 2 Compare Word 1 Register (index = 23) + GMAC_ST2CW123 : aliased GMAC_ST2CW_Register_1; + end record + with Volatile; + + for GMAC_Peripheral use record + GMAC_NCR at 16#0# range 0 .. 31; + GMAC_NCFGR at 16#4# range 0 .. 31; + GMAC_NSR at 16#8# range 0 .. 31; + GMAC_UR at 16#C# range 0 .. 31; + GMAC_DCFGR at 16#10# range 0 .. 31; + GMAC_TSR at 16#14# range 0 .. 31; + GMAC_RBQB at 16#18# range 0 .. 31; + GMAC_TBQB at 16#1C# range 0 .. 31; + GMAC_RSR at 16#20# range 0 .. 31; + GMAC_ISR at 16#24# range 0 .. 31; + GMAC_IER at 16#28# range 0 .. 31; + GMAC_IDR at 16#2C# range 0 .. 31; + GMAC_IMR at 16#30# range 0 .. 31; + GMAC_MAN at 16#34# range 0 .. 31; + GMAC_RPQ at 16#38# range 0 .. 31; + GMAC_TPQ at 16#3C# range 0 .. 31; + GMAC_TPSF at 16#40# range 0 .. 31; + GMAC_RPSF at 16#44# range 0 .. 31; + GMAC_RJFML at 16#48# range 0 .. 31; + GMAC_HRB at 16#80# range 0 .. 31; + GMAC_HRT at 16#84# range 0 .. 31; + GMAC_GMAC_SA at 16#88# range 0 .. 255; + GMAC_TIDM1 at 16#A8# range 0 .. 31; + GMAC_TIDM2 at 16#AC# range 0 .. 31; + GMAC_TIDM3 at 16#B0# range 0 .. 31; + GMAC_TIDM4 at 16#B4# range 0 .. 31; + GMAC_WOL at 16#B8# range 0 .. 31; + GMAC_IPGS at 16#BC# range 0 .. 31; + GMAC_SVLAN at 16#C0# range 0 .. 31; + GMAC_TPFCP at 16#C4# range 0 .. 31; + GMAC_SAMB1 at 16#C8# range 0 .. 31; + GMAC_SAMT1 at 16#CC# range 0 .. 31; + GMAC_NSC at 16#DC# range 0 .. 31; + GMAC_SCL at 16#E0# range 0 .. 31; + GMAC_SCH at 16#E4# range 0 .. 31; + GMAC_EFTSH at 16#E8# range 0 .. 31; + GMAC_EFRSH at 16#EC# range 0 .. 31; + GMAC_PEFTSH at 16#F0# range 0 .. 31; + GMAC_PEFRSH at 16#F4# range 0 .. 31; + GMAC_MID at 16#FC# range 0 .. 31; + GMAC_OTLO at 16#100# range 0 .. 31; + GMAC_OTHI at 16#104# range 0 .. 31; + GMAC_FT at 16#108# range 0 .. 31; + GMAC_BCFT at 16#10C# range 0 .. 31; + GMAC_MFT at 16#110# range 0 .. 31; + GMAC_PFT at 16#114# range 0 .. 31; + GMAC_BFT64 at 16#118# range 0 .. 31; + GMAC_TBFT127 at 16#11C# range 0 .. 31; + GMAC_TBFT255 at 16#120# range 0 .. 31; + GMAC_TBFT511 at 16#124# range 0 .. 31; + GMAC_TBFT1023 at 16#128# range 0 .. 31; + GMAC_TBFT1518 at 16#12C# range 0 .. 31; + GMAC_GTBFT1518 at 16#130# range 0 .. 31; + GMAC_TUR at 16#134# range 0 .. 31; + GMAC_SCF at 16#138# range 0 .. 31; + GMAC_MCF at 16#13C# range 0 .. 31; + GMAC_EC at 16#140# range 0 .. 31; + GMAC_LC at 16#144# range 0 .. 31; + GMAC_DTF at 16#148# range 0 .. 31; + GMAC_CSE at 16#14C# range 0 .. 31; + GMAC_ORLO at 16#150# range 0 .. 31; + GMAC_ORHI at 16#154# range 0 .. 31; + GMAC_FR at 16#158# range 0 .. 31; + GMAC_BCFR at 16#15C# range 0 .. 31; + GMAC_MFR at 16#160# range 0 .. 31; + GMAC_PFR at 16#164# range 0 .. 31; + GMAC_BFR64 at 16#168# range 0 .. 31; + GMAC_TBFR127 at 16#16C# range 0 .. 31; + GMAC_TBFR255 at 16#170# range 0 .. 31; + GMAC_TBFR511 at 16#174# range 0 .. 31; + GMAC_TBFR1023 at 16#178# range 0 .. 31; + GMAC_TBFR1518 at 16#17C# range 0 .. 31; + GMAC_TMXBFR at 16#180# range 0 .. 31; + GMAC_UFR at 16#184# range 0 .. 31; + GMAC_OFR at 16#188# range 0 .. 31; + GMAC_JR at 16#18C# range 0 .. 31; + GMAC_FCSE at 16#190# range 0 .. 31; + GMAC_LFFE at 16#194# range 0 .. 31; + GMAC_RSE at 16#198# range 0 .. 31; + GMAC_AE at 16#19C# range 0 .. 31; + GMAC_RRE at 16#1A0# range 0 .. 31; + GMAC_ROE at 16#1A4# range 0 .. 31; + GMAC_IHCE at 16#1A8# range 0 .. 31; + GMAC_TCE at 16#1AC# range 0 .. 31; + GMAC_UCE at 16#1B0# range 0 .. 31; + GMAC_TISUBN at 16#1BC# range 0 .. 31; + GMAC_TSH at 16#1C0# range 0 .. 31; + GMAC_TSL at 16#1D0# range 0 .. 31; + GMAC_TN at 16#1D4# range 0 .. 31; + GMAC_TA at 16#1D8# range 0 .. 31; + GMAC_TI at 16#1DC# range 0 .. 31; + GMAC_EFTSL at 16#1E0# range 0 .. 31; + GMAC_EFTN at 16#1E4# range 0 .. 31; + GMAC_EFRSL at 16#1E8# range 0 .. 31; + GMAC_EFRN at 16#1EC# range 0 .. 31; + GMAC_PEFTSL at 16#1F0# range 0 .. 31; + GMAC_PEFTN at 16#1F4# range 0 .. 31; + GMAC_PEFRSL at 16#1F8# range 0 .. 31; + GMAC_PEFRN at 16#1FC# range 0 .. 31; + GMAC_ISRPQ at 16#3FC# range 0 .. 63; + GMAC_TBQBAPQ at 16#43C# range 0 .. 63; + GMAC_RBQBAPQ at 16#47C# range 0 .. 63; + GMAC_RBSRPQ at 16#49C# range 0 .. 63; + GMAC_CBSCR at 16#4BC# range 0 .. 31; + GMAC_CBSISQA at 16#4C0# range 0 .. 31; + GMAC_CBSISQB at 16#4C4# range 0 .. 31; + GMAC_ST1RPQ at 16#500# range 0 .. 127; + GMAC_ST2RPQ at 16#540# range 0 .. 255; + GMAC_IERPQ at 16#5FC# range 0 .. 63; + GMAC_IDRPQ at 16#61C# range 0 .. 63; + GMAC_IMRPQ at 16#63C# range 0 .. 63; + GMAC_ST2ER at 16#6E0# range 0 .. 127; + GMAC_ST2CW00 at 16#700# range 0 .. 31; + GMAC_ST2CW10 at 16#704# range 0 .. 31; + GMAC_ST2CW01 at 16#708# range 0 .. 31; + GMAC_ST2CW11 at 16#70C# range 0 .. 31; + GMAC_ST2CW02 at 16#710# range 0 .. 31; + GMAC_ST2CW12 at 16#714# range 0 .. 31; + GMAC_ST2CW03 at 16#718# range 0 .. 31; + GMAC_ST2CW13 at 16#71C# range 0 .. 31; + GMAC_ST2CW04 at 16#720# range 0 .. 31; + GMAC_ST2CW14 at 16#724# range 0 .. 31; + GMAC_ST2CW05 at 16#728# range 0 .. 31; + GMAC_ST2CW15 at 16#72C# range 0 .. 31; + GMAC_ST2CW06 at 16#730# range 0 .. 31; + GMAC_ST2CW16 at 16#734# range 0 .. 31; + GMAC_ST2CW07 at 16#738# range 0 .. 31; + GMAC_ST2CW17 at 16#73C# range 0 .. 31; + GMAC_ST2CW08 at 16#740# range 0 .. 31; + GMAC_ST2CW18 at 16#744# range 0 .. 31; + GMAC_ST2CW09 at 16#748# range 0 .. 31; + GMAC_ST2CW19 at 16#74C# range 0 .. 31; + GMAC_ST2CW010 at 16#750# range 0 .. 31; + GMAC_ST2CW110 at 16#754# range 0 .. 31; + GMAC_ST2CW011 at 16#758# range 0 .. 31; + GMAC_ST2CW111 at 16#75C# range 0 .. 31; + GMAC_ST2CW012 at 16#760# range 0 .. 31; + GMAC_ST2CW112 at 16#764# range 0 .. 31; + GMAC_ST2CW013 at 16#768# range 0 .. 31; + GMAC_ST2CW113 at 16#76C# range 0 .. 31; + GMAC_ST2CW014 at 16#770# range 0 .. 31; + GMAC_ST2CW114 at 16#774# range 0 .. 31; + GMAC_ST2CW015 at 16#778# range 0 .. 31; + GMAC_ST2CW115 at 16#77C# range 0 .. 31; + GMAC_ST2CW016 at 16#780# range 0 .. 31; + GMAC_ST2CW116 at 16#784# range 0 .. 31; + GMAC_ST2CW017 at 16#788# range 0 .. 31; + GMAC_ST2CW117 at 16#78C# range 0 .. 31; + GMAC_ST2CW018 at 16#790# range 0 .. 31; + GMAC_ST2CW118 at 16#794# range 0 .. 31; + GMAC_ST2CW019 at 16#798# range 0 .. 31; + GMAC_ST2CW119 at 16#79C# range 0 .. 31; + GMAC_ST2CW020 at 16#7A0# range 0 .. 31; + GMAC_ST2CW120 at 16#7A4# range 0 .. 31; + GMAC_ST2CW021 at 16#7A8# range 0 .. 31; + GMAC_ST2CW121 at 16#7AC# range 0 .. 31; + GMAC_ST2CW022 at 16#7B0# range 0 .. 31; + GMAC_ST2CW122 at 16#7B4# range 0 .. 31; + GMAC_ST2CW023 at 16#7B8# range 0 .. 31; + GMAC_ST2CW123 at 16#7BC# range 0 .. 31; + end record; + + -- Gigabit Ethernet MAC + GMAC_Periph : aliased GMAC_Peripheral + with Import, Address => System'To_Address (16#40050000#); + +end SAM_SVD.GMAC; diff --git a/arch/ARM/SAM/svd/atsamv71/sam_svd-gpbr.ads b/arch/ARM/SAM/svd/atsamv71/sam_svd-gpbr.ads new file mode 100644 index 000000000..6b122d89c --- /dev/null +++ b/arch/ARM/SAM/svd/atsamv71/sam_svd-gpbr.ads @@ -0,0 +1,42 @@ +-- This spec has been automatically generated from ATSAMV71Q21.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package SAM_SVD.GPBR is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + -- General Purpose Backup Register 0 + + -- General Purpose Backup Register 0 + type GPBR_SYS_GPBR_Registers is array (0 .. 7) of HAL.UInt32 + with Volatile; + + ----------------- + -- Peripherals -- + ----------------- + + -- General Purpose Backup Registers + type GPBR_Peripheral is record + -- General Purpose Backup Register 0 + SYS_GPBR : aliased GPBR_SYS_GPBR_Registers; + end record + with Volatile; + + for GPBR_Peripheral use record + SYS_GPBR at 0 range 0 .. 255; + end record; + + -- General Purpose Backup Registers + GPBR_Periph : aliased GPBR_Peripheral + with Import, Address => System'To_Address (16#400E1890#); + +end SAM_SVD.GPBR; diff --git a/arch/ARM/SAM/svd/atsamv71/sam_svd-hsmci.ads b/arch/ARM/SAM/svd/atsamv71/sam_svd-hsmci.ads new file mode 100644 index 000000000..2ab718b4c --- /dev/null +++ b/arch/ARM/SAM/svd/atsamv71/sam_svd-hsmci.ads @@ -0,0 +1,1078 @@ +-- This spec has been automatically generated from ATSAMV71Q21.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package SAM_SVD.HSMCI is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + -- Control Register + type HSMCI_HSMCI_CR_Register is record + -- Write-only. Multi-Media Interface Enable + MCIEN : Boolean := False; + -- Write-only. Multi-Media Interface Disable + MCIDIS : Boolean := False; + -- Write-only. Power Save Mode Enable + PWSEN : Boolean := False; + -- Write-only. Power Save Mode Disable + PWSDIS : Boolean := False; + -- unspecified + Reserved_4_6 : HAL.UInt3 := 16#0#; + -- Write-only. Software Reset + SWRST : Boolean := False; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for HSMCI_HSMCI_CR_Register use record + MCIEN at 0 range 0 .. 0; + MCIDIS at 0 range 1 .. 1; + PWSEN at 0 range 2 .. 2; + PWSDIS at 0 range 3 .. 3; + Reserved_4_6 at 0 range 4 .. 6; + SWRST at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype HSMCI_HSMCI_MR_CLKDIV_Field is HAL.UInt8; + subtype HSMCI_HSMCI_MR_PWSDIV_Field is HAL.UInt3; + + -- Mode Register + type HSMCI_HSMCI_MR_Register is record + -- Clock Divider + CLKDIV : HSMCI_HSMCI_MR_CLKDIV_Field := 16#0#; + -- Power Saving Divider + PWSDIV : HSMCI_HSMCI_MR_PWSDIV_Field := 16#0#; + -- Read Proof Enable + RDPROOF : Boolean := False; + -- Write Proof Enable + WRPROOF : Boolean := False; + -- Force Byte Transfer + FBYTE : Boolean := False; + -- Padding Value + PADV : Boolean := False; + -- unspecified + Reserved_15_15 : HAL.Bit := 16#0#; + -- Clock divider is odd + CLKODD : Boolean := False; + -- unspecified + Reserved_17_31 : HAL.UInt15 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for HSMCI_HSMCI_MR_Register use record + CLKDIV at 0 range 0 .. 7; + PWSDIV at 0 range 8 .. 10; + RDPROOF at 0 range 11 .. 11; + WRPROOF at 0 range 12 .. 12; + FBYTE at 0 range 13 .. 13; + PADV at 0 range 14 .. 14; + Reserved_15_15 at 0 range 15 .. 15; + CLKODD at 0 range 16 .. 16; + Reserved_17_31 at 0 range 17 .. 31; + end record; + + subtype HSMCI_HSMCI_DTOR_DTOCYC_Field is HAL.UInt4; + + -- Data Timeout Multiplier + type HSMCI_DTOR_DTOMUL_Field is + ( + -- DTOCYC + Val_1, + -- DTOCYC x 16 + Val_16, + -- DTOCYC x 128 + Val_128, + -- DTOCYC x 256 + Val_256, + -- DTOCYC x 1024 + Val_1024, + -- DTOCYC x 4096 + Val_4096, + -- DTOCYC x 65536 + Val_65536, + -- DTOCYC x 1048576 + Val_1048576) + with Size => 3; + for HSMCI_DTOR_DTOMUL_Field use + (Val_1 => 0, + Val_16 => 1, + Val_128 => 2, + Val_256 => 3, + Val_1024 => 4, + Val_4096 => 5, + Val_65536 => 6, + Val_1048576 => 7); + + -- Data Timeout Register + type HSMCI_HSMCI_DTOR_Register is record + -- Data Timeout Cycle Number + DTOCYC : HSMCI_HSMCI_DTOR_DTOCYC_Field := 16#0#; + -- Data Timeout Multiplier + DTOMUL : HSMCI_DTOR_DTOMUL_Field := SAM_SVD.HSMCI.Val_1; + -- unspecified + Reserved_7_31 : HAL.UInt25 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for HSMCI_HSMCI_DTOR_Register use record + DTOCYC at 0 range 0 .. 3; + DTOMUL at 0 range 4 .. 6; + Reserved_7_31 at 0 range 7 .. 31; + end record; + + -- SDCard/SDIO Slot + type HSMCI_SDCR_SDCSEL_Field is + ( + -- Slot A is selected. + Slota) + with Size => 2; + for HSMCI_SDCR_SDCSEL_Field use + (Slota => 0); + + -- SDCard/SDIO Bus Width + type HSMCI_SDCR_SDCBUS_Field is + ( + -- 1 bit + Val_1, + -- 4 bits + Val_4, + -- 8 bits + Val_8) + with Size => 2; + for HSMCI_SDCR_SDCBUS_Field use + (Val_1 => 0, + Val_4 => 2, + Val_8 => 3); + + -- SD/SDIO Card Register + type HSMCI_HSMCI_SDCR_Register is record + -- SDCard/SDIO Slot + SDCSEL : HSMCI_SDCR_SDCSEL_Field := SAM_SVD.HSMCI.Slota; + -- unspecified + Reserved_2_5 : HAL.UInt4 := 16#0#; + -- SDCard/SDIO Bus Width + SDCBUS : HSMCI_SDCR_SDCBUS_Field := SAM_SVD.HSMCI.Val_1; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for HSMCI_HSMCI_SDCR_Register use record + SDCSEL at 0 range 0 .. 1; + Reserved_2_5 at 0 range 2 .. 5; + SDCBUS at 0 range 6 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype HSMCI_HSMCI_CMDR_CMDNB_Field is HAL.UInt6; + + -- Response Type + type HSMCI_CMDR_RSPTYP_Field is + ( + -- No response + Noresp, + -- 48-bit response + Val_48_Bit, + -- 136-bit response + Val_136_Bit, + -- R1b response type + R1B) + with Size => 2; + for HSMCI_CMDR_RSPTYP_Field use + (Noresp => 0, + Val_48_Bit => 1, + Val_136_Bit => 2, + R1B => 3); + + -- Special Command + type HSMCI_CMDR_SPCMD_Field is + ( + -- Not a special CMD. + Std, + -- Initialization CMD: 74 clock cycles for initialization sequence. + Init, + -- Synchronized CMD: Wait for the end of the current data block transfer + -- before sending the pending command. + Sync, + -- CE-ATA Completion Signal disable Command. The host cancels the + -- ability for the device to return a command completion signal on the + -- command line. + Ce_Ata, + -- Interrupt command: Corresponds to the Interrupt Mode (CMD40). + It_Cmd, + -- Interrupt response: Corresponds to the Interrupt Mode (CMD40). + It_Resp, + -- Boot Operation Request. Start a boot operation mode, the host + -- processor can read boot data from the MMC device directly. + Bor, + -- End Boot Operation. This command allows the host processor to + -- terminate the boot operation mode. + Ebo) + with Size => 3; + for HSMCI_CMDR_SPCMD_Field use + (Std => 0, + Init => 1, + Sync => 2, + Ce_Ata => 3, + It_Cmd => 4, + It_Resp => 5, + Bor => 6, + Ebo => 7); + + -- Open Drain Command + type HSMCI_CMDR_OPDCMD_Field is + ( + -- Push pull command. + Pushpull, + -- Open drain command. + Opendrain) + with Size => 1; + for HSMCI_CMDR_OPDCMD_Field use + (Pushpull => 0, + Opendrain => 1); + + -- Max Latency for Command to Response + type HSMCI_CMDR_MAXLAT_Field is + ( + -- 5-cycle max latency. + Val_5, + -- 64-cycle max latency. + Val_64) + with Size => 1; + for HSMCI_CMDR_MAXLAT_Field use + (Val_5 => 0, + Val_64 => 1); + + -- Transfer Command + type HSMCI_CMDR_TRCMD_Field is + ( + -- No data transfer + No_Data, + -- Start data transfer + Start_Data, + -- Stop data transfer + Stop_Data) + with Size => 2; + for HSMCI_CMDR_TRCMD_Field use + (No_Data => 0, + Start_Data => 1, + Stop_Data => 2); + + -- Transfer Direction + type HSMCI_CMDR_TRDIR_Field is + ( + -- Write. + Write, + -- Read. + Read) + with Size => 1; + for HSMCI_CMDR_TRDIR_Field use + (Write => 0, + Read => 1); + + -- Transfer Type + type HSMCI_CMDR_TRTYP_Field is + ( + -- MMC/SD Card Single Block + Single, + -- MMC/SD Card Multiple Block + Multiple, + -- MMC Stream + Stream, + -- SDIO Byte + Byte, + -- SDIO Block + Block) + with Size => 3; + for HSMCI_CMDR_TRTYP_Field use + (Single => 0, + Multiple => 1, + Stream => 2, + Byte => 4, + Block => 5); + + -- SDIO Special Command + type HSMCI_CMDR_IOSPCMD_Field is + ( + -- Not an SDIO Special Command + Std, + -- SDIO Suspend Command + Suspend, + -- SDIO Resume Command + Resume) + with Size => 2; + for HSMCI_CMDR_IOSPCMD_Field use + (Std => 0, + Suspend => 1, + Resume => 2); + + -- ATA with Command Completion Signal + type HSMCI_CMDR_ATACS_Field is + ( + -- Normal operation mode. + Normal, + -- This bit indicates that a completion signal is expected within a + -- programmed amount of time (HSMCI_CSTOR). + Completion) + with Size => 1; + for HSMCI_CMDR_ATACS_Field use + (Normal => 0, + Completion => 1); + + -- Command Register + type HSMCI_HSMCI_CMDR_Register is record + -- Write-only. Command Number + CMDNB : HSMCI_HSMCI_CMDR_CMDNB_Field := 16#0#; + -- Write-only. Response Type + RSPTYP : HSMCI_CMDR_RSPTYP_Field := SAM_SVD.HSMCI.Noresp; + -- Write-only. Special Command + SPCMD : HSMCI_CMDR_SPCMD_Field := SAM_SVD.HSMCI.Std; + -- Write-only. Open Drain Command + OPDCMD : HSMCI_CMDR_OPDCMD_Field := SAM_SVD.HSMCI.Pushpull; + -- Write-only. Max Latency for Command to Response + MAXLAT : HSMCI_CMDR_MAXLAT_Field := SAM_SVD.HSMCI.Val_5; + -- unspecified + Reserved_13_15 : HAL.UInt3 := 16#0#; + -- Write-only. Transfer Command + TRCMD : HSMCI_CMDR_TRCMD_Field := SAM_SVD.HSMCI.No_Data; + -- Write-only. Transfer Direction + TRDIR : HSMCI_CMDR_TRDIR_Field := SAM_SVD.HSMCI.Write; + -- Write-only. Transfer Type + TRTYP : HSMCI_CMDR_TRTYP_Field := SAM_SVD.HSMCI.Single; + -- unspecified + Reserved_22_23 : HAL.UInt2 := 16#0#; + -- Write-only. SDIO Special Command + IOSPCMD : HSMCI_CMDR_IOSPCMD_Field := SAM_SVD.HSMCI.Std; + -- Write-only. ATA with Command Completion Signal + ATACS : HSMCI_CMDR_ATACS_Field := SAM_SVD.HSMCI.Normal; + -- Write-only. Boot Operation Acknowledge + BOOT_ACK : Boolean := False; + -- unspecified + Reserved_28_31 : HAL.UInt4 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for HSMCI_HSMCI_CMDR_Register use record + CMDNB at 0 range 0 .. 5; + RSPTYP at 0 range 6 .. 7; + SPCMD at 0 range 8 .. 10; + OPDCMD at 0 range 11 .. 11; + MAXLAT at 0 range 12 .. 12; + Reserved_13_15 at 0 range 13 .. 15; + TRCMD at 0 range 16 .. 17; + TRDIR at 0 range 18 .. 18; + TRTYP at 0 range 19 .. 21; + Reserved_22_23 at 0 range 22 .. 23; + IOSPCMD at 0 range 24 .. 25; + ATACS at 0 range 26 .. 26; + BOOT_ACK at 0 range 27 .. 27; + Reserved_28_31 at 0 range 28 .. 31; + end record; + + subtype HSMCI_HSMCI_BLKR_BCNT_Field is HAL.UInt16; + subtype HSMCI_HSMCI_BLKR_BLKLEN_Field is HAL.UInt16; + + -- Block Register + type HSMCI_HSMCI_BLKR_Register is record + -- MMC/SDIO Block Count - SDIO Byte Count + BCNT : HSMCI_HSMCI_BLKR_BCNT_Field := 16#0#; + -- Data Block Length + BLKLEN : HSMCI_HSMCI_BLKR_BLKLEN_Field := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for HSMCI_HSMCI_BLKR_Register use record + BCNT at 0 range 0 .. 15; + BLKLEN at 0 range 16 .. 31; + end record; + + subtype HSMCI_HSMCI_CSTOR_CSTOCYC_Field is HAL.UInt4; + + -- Completion Signal Timeout Multiplier + type HSMCI_CSTOR_CSTOMUL_Field is + ( + -- CSTOCYC x 1 + Val_1, + -- CSTOCYC x 16 + Val_16, + -- CSTOCYC x 128 + Val_128, + -- CSTOCYC x 256 + Val_256, + -- CSTOCYC x 1024 + Val_1024, + -- CSTOCYC x 4096 + Val_4096, + -- CSTOCYC x 65536 + Val_65536, + -- CSTOCYC x 1048576 + Val_1048576) + with Size => 3; + for HSMCI_CSTOR_CSTOMUL_Field use + (Val_1 => 0, + Val_16 => 1, + Val_128 => 2, + Val_256 => 3, + Val_1024 => 4, + Val_4096 => 5, + Val_65536 => 6, + Val_1048576 => 7); + + -- Completion Signal Timeout Register + type HSMCI_HSMCI_CSTOR_Register is record + -- Completion Signal Timeout Cycle Number + CSTOCYC : HSMCI_HSMCI_CSTOR_CSTOCYC_Field := 16#0#; + -- Completion Signal Timeout Multiplier + CSTOMUL : HSMCI_CSTOR_CSTOMUL_Field := SAM_SVD.HSMCI.Val_1; + -- unspecified + Reserved_7_31 : HAL.UInt25 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for HSMCI_HSMCI_CSTOR_Register use record + CSTOCYC at 0 range 0 .. 3; + CSTOMUL at 0 range 4 .. 6; + Reserved_7_31 at 0 range 7 .. 31; + end record; + + -- Response Register 0 + + -- Response Register 0 + type HSMCI_HSMCI_RSPR_Registers is array (0 .. 3) of HAL.UInt32 + with Volatile; + + -- Status Register + type HSMCI_HSMCI_SR_Register is record + -- Read-only. Command Ready (cleared by writing in HSMCI_CMDR) + CMDRDY : Boolean; + -- Read-only. Receiver Ready (cleared by reading HSMCI_RDR) + RXRDY : Boolean; + -- Read-only. Transmit Ready (cleared by writing in HSMCI_TDR) + TXRDY : Boolean; + -- Read-only. Data Block Ended (cleared on read) + BLKE : Boolean; + -- Read-only. Data Transfer in Progress (cleared at the end of CRC16 + -- calculation) + DTIP : Boolean; + -- Read-only. HSMCI Not Busy + NOTBUSY : Boolean; + -- unspecified + Reserved_6_7 : HAL.UInt2; + -- Read-only. SDIO Interrupt for Slot A (cleared on read) + SDIOIRQA : Boolean; + -- unspecified + Reserved_9_11 : HAL.UInt3; + -- Read-only. SDIO Read Wait Operation Status + SDIOWAIT : Boolean; + -- Read-only. CE-ATA Completion Signal Received (cleared on read) + CSRCV : Boolean; + -- unspecified + Reserved_14_15 : HAL.UInt2; + -- Read-only. Response Index Error (cleared by writing in HSMCI_CMDR) + RINDE : Boolean; + -- Read-only. Response Direction Error (cleared by writing in + -- HSMCI_CMDR) + RDIRE : Boolean; + -- Read-only. Response CRC Error (cleared by writing in HSMCI_CMDR) + RCRCE : Boolean; + -- Read-only. Response End Bit Error (cleared by writing in HSMCI_CMDR) + RENDE : Boolean; + -- Read-only. Response Time-out Error (cleared by writing in HSMCI_CMDR) + RTOE : Boolean; + -- Read-only. Data CRC Error (cleared on read) + DCRCE : Boolean; + -- Read-only. Data Time-out Error (cleared on read) + DTOE : Boolean; + -- Read-only. Completion Signal Time-out Error (cleared on read) + CSTOE : Boolean; + -- Read-only. DMA Block Overrun Error (cleared on read) + BLKOVRE : Boolean; + -- unspecified + Reserved_25_25 : HAL.Bit; + -- Read-only. FIFO empty flag + FIFOEMPTY : Boolean; + -- Read-only. Transfer Done flag + XFRDONE : Boolean; + -- Read-only. Boot Operation Acknowledge Received (cleared on read) + ACKRCV : Boolean; + -- Read-only. Boot Operation Acknowledge Error (cleared on read) + ACKRCVE : Boolean; + -- Read-only. Overrun (if FERRCTRL = 1, cleared by writing in HSMCI_CMDR + -- or cleared on read if FERRCTRL = 0) + OVRE : Boolean; + -- Read-only. Underrun (if FERRCTRL = 1, cleared by writing in + -- HSMCI_CMDR or cleared on read if FERRCTRL = 0) + UNRE : Boolean; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for HSMCI_HSMCI_SR_Register use record + CMDRDY at 0 range 0 .. 0; + RXRDY at 0 range 1 .. 1; + TXRDY at 0 range 2 .. 2; + BLKE at 0 range 3 .. 3; + DTIP at 0 range 4 .. 4; + NOTBUSY at 0 range 5 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + SDIOIRQA at 0 range 8 .. 8; + Reserved_9_11 at 0 range 9 .. 11; + SDIOWAIT at 0 range 12 .. 12; + CSRCV at 0 range 13 .. 13; + Reserved_14_15 at 0 range 14 .. 15; + RINDE at 0 range 16 .. 16; + RDIRE at 0 range 17 .. 17; + RCRCE at 0 range 18 .. 18; + RENDE at 0 range 19 .. 19; + RTOE at 0 range 20 .. 20; + DCRCE at 0 range 21 .. 21; + DTOE at 0 range 22 .. 22; + CSTOE at 0 range 23 .. 23; + BLKOVRE at 0 range 24 .. 24; + Reserved_25_25 at 0 range 25 .. 25; + FIFOEMPTY at 0 range 26 .. 26; + XFRDONE at 0 range 27 .. 27; + ACKRCV at 0 range 28 .. 28; + ACKRCVE at 0 range 29 .. 29; + OVRE at 0 range 30 .. 30; + UNRE at 0 range 31 .. 31; + end record; + + -- Interrupt Enable Register + type HSMCI_HSMCI_IER_Register is record + -- Write-only. Command Ready Interrupt Enable + CMDRDY : Boolean := False; + -- Write-only. Receiver Ready Interrupt Enable + RXRDY : Boolean := False; + -- Write-only. Transmit Ready Interrupt Enable + TXRDY : Boolean := False; + -- Write-only. Data Block Ended Interrupt Enable + BLKE : Boolean := False; + -- Write-only. Data Transfer in Progress Interrupt Enable + DTIP : Boolean := False; + -- Write-only. Data Not Busy Interrupt Enable + NOTBUSY : Boolean := False; + -- unspecified + Reserved_6_7 : HAL.UInt2 := 16#0#; + -- Write-only. SDIO Interrupt for Slot A Interrupt Enable + SDIOIRQA : Boolean := False; + -- unspecified + Reserved_9_11 : HAL.UInt3 := 16#0#; + -- Write-only. SDIO Read Wait Operation Status Interrupt Enable + SDIOWAIT : Boolean := False; + -- Write-only. Completion Signal Received Interrupt Enable + CSRCV : Boolean := False; + -- unspecified + Reserved_14_15 : HAL.UInt2 := 16#0#; + -- Write-only. Response Index Error Interrupt Enable + RINDE : Boolean := False; + -- Write-only. Response Direction Error Interrupt Enable + RDIRE : Boolean := False; + -- Write-only. Response CRC Error Interrupt Enable + RCRCE : Boolean := False; + -- Write-only. Response End Bit Error Interrupt Enable + RENDE : Boolean := False; + -- Write-only. Response Time-out Error Interrupt Enable + RTOE : Boolean := False; + -- Write-only. Data CRC Error Interrupt Enable + DCRCE : Boolean := False; + -- Write-only. Data Time-out Error Interrupt Enable + DTOE : Boolean := False; + -- Write-only. Completion Signal Timeout Error Interrupt Enable + CSTOE : Boolean := False; + -- Write-only. DMA Block Overrun Error Interrupt Enable + BLKOVRE : Boolean := False; + -- unspecified + Reserved_25_25 : HAL.Bit := 16#0#; + -- Write-only. FIFO empty Interrupt enable + FIFOEMPTY : Boolean := False; + -- Write-only. Transfer Done Interrupt enable + XFRDONE : Boolean := False; + -- Write-only. Boot Acknowledge Interrupt Enable + ACKRCV : Boolean := False; + -- Write-only. Boot Acknowledge Error Interrupt Enable + ACKRCVE : Boolean := False; + -- Write-only. Overrun Interrupt Enable + OVRE : Boolean := False; + -- Write-only. Underrun Interrupt Enable + UNRE : Boolean := False; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for HSMCI_HSMCI_IER_Register use record + CMDRDY at 0 range 0 .. 0; + RXRDY at 0 range 1 .. 1; + TXRDY at 0 range 2 .. 2; + BLKE at 0 range 3 .. 3; + DTIP at 0 range 4 .. 4; + NOTBUSY at 0 range 5 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + SDIOIRQA at 0 range 8 .. 8; + Reserved_9_11 at 0 range 9 .. 11; + SDIOWAIT at 0 range 12 .. 12; + CSRCV at 0 range 13 .. 13; + Reserved_14_15 at 0 range 14 .. 15; + RINDE at 0 range 16 .. 16; + RDIRE at 0 range 17 .. 17; + RCRCE at 0 range 18 .. 18; + RENDE at 0 range 19 .. 19; + RTOE at 0 range 20 .. 20; + DCRCE at 0 range 21 .. 21; + DTOE at 0 range 22 .. 22; + CSTOE at 0 range 23 .. 23; + BLKOVRE at 0 range 24 .. 24; + Reserved_25_25 at 0 range 25 .. 25; + FIFOEMPTY at 0 range 26 .. 26; + XFRDONE at 0 range 27 .. 27; + ACKRCV at 0 range 28 .. 28; + ACKRCVE at 0 range 29 .. 29; + OVRE at 0 range 30 .. 30; + UNRE at 0 range 31 .. 31; + end record; + + -- Interrupt Disable Register + type HSMCI_HSMCI_IDR_Register is record + -- Write-only. Command Ready Interrupt Disable + CMDRDY : Boolean := False; + -- Write-only. Receiver Ready Interrupt Disable + RXRDY : Boolean := False; + -- Write-only. Transmit Ready Interrupt Disable + TXRDY : Boolean := False; + -- Write-only. Data Block Ended Interrupt Disable + BLKE : Boolean := False; + -- Write-only. Data Transfer in Progress Interrupt Disable + DTIP : Boolean := False; + -- Write-only. Data Not Busy Interrupt Disable + NOTBUSY : Boolean := False; + -- unspecified + Reserved_6_7 : HAL.UInt2 := 16#0#; + -- Write-only. SDIO Interrupt for Slot A Interrupt Disable + SDIOIRQA : Boolean := False; + -- unspecified + Reserved_9_11 : HAL.UInt3 := 16#0#; + -- Write-only. SDIO Read Wait Operation Status Interrupt Disable + SDIOWAIT : Boolean := False; + -- Write-only. Completion Signal received interrupt Disable + CSRCV : Boolean := False; + -- unspecified + Reserved_14_15 : HAL.UInt2 := 16#0#; + -- Write-only. Response Index Error Interrupt Disable + RINDE : Boolean := False; + -- Write-only. Response Direction Error Interrupt Disable + RDIRE : Boolean := False; + -- Write-only. Response CRC Error Interrupt Disable + RCRCE : Boolean := False; + -- Write-only. Response End Bit Error Interrupt Disable + RENDE : Boolean := False; + -- Write-only. Response Time-out Error Interrupt Disable + RTOE : Boolean := False; + -- Write-only. Data CRC Error Interrupt Disable + DCRCE : Boolean := False; + -- Write-only. Data Time-out Error Interrupt Disable + DTOE : Boolean := False; + -- Write-only. Completion Signal Time out Error Interrupt Disable + CSTOE : Boolean := False; + -- Write-only. DMA Block Overrun Error Interrupt Disable + BLKOVRE : Boolean := False; + -- unspecified + Reserved_25_25 : HAL.Bit := 16#0#; + -- Write-only. FIFO empty Interrupt Disable + FIFOEMPTY : Boolean := False; + -- Write-only. Transfer Done Interrupt Disable + XFRDONE : Boolean := False; + -- Write-only. Boot Acknowledge Interrupt Disable + ACKRCV : Boolean := False; + -- Write-only. Boot Acknowledge Error Interrupt Disable + ACKRCVE : Boolean := False; + -- Write-only. Overrun Interrupt Disable + OVRE : Boolean := False; + -- Write-only. Underrun Interrupt Disable + UNRE : Boolean := False; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for HSMCI_HSMCI_IDR_Register use record + CMDRDY at 0 range 0 .. 0; + RXRDY at 0 range 1 .. 1; + TXRDY at 0 range 2 .. 2; + BLKE at 0 range 3 .. 3; + DTIP at 0 range 4 .. 4; + NOTBUSY at 0 range 5 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + SDIOIRQA at 0 range 8 .. 8; + Reserved_9_11 at 0 range 9 .. 11; + SDIOWAIT at 0 range 12 .. 12; + CSRCV at 0 range 13 .. 13; + Reserved_14_15 at 0 range 14 .. 15; + RINDE at 0 range 16 .. 16; + RDIRE at 0 range 17 .. 17; + RCRCE at 0 range 18 .. 18; + RENDE at 0 range 19 .. 19; + RTOE at 0 range 20 .. 20; + DCRCE at 0 range 21 .. 21; + DTOE at 0 range 22 .. 22; + CSTOE at 0 range 23 .. 23; + BLKOVRE at 0 range 24 .. 24; + Reserved_25_25 at 0 range 25 .. 25; + FIFOEMPTY at 0 range 26 .. 26; + XFRDONE at 0 range 27 .. 27; + ACKRCV at 0 range 28 .. 28; + ACKRCVE at 0 range 29 .. 29; + OVRE at 0 range 30 .. 30; + UNRE at 0 range 31 .. 31; + end record; + + -- Interrupt Mask Register + type HSMCI_HSMCI_IMR_Register is record + -- Read-only. Command Ready Interrupt Mask + CMDRDY : Boolean; + -- Read-only. Receiver Ready Interrupt Mask + RXRDY : Boolean; + -- Read-only. Transmit Ready Interrupt Mask + TXRDY : Boolean; + -- Read-only. Data Block Ended Interrupt Mask + BLKE : Boolean; + -- Read-only. Data Transfer in Progress Interrupt Mask + DTIP : Boolean; + -- Read-only. Data Not Busy Interrupt Mask + NOTBUSY : Boolean; + -- unspecified + Reserved_6_7 : HAL.UInt2; + -- Read-only. SDIO Interrupt for Slot A Interrupt Mask + SDIOIRQA : Boolean; + -- unspecified + Reserved_9_11 : HAL.UInt3; + -- Read-only. SDIO Read Wait Operation Status Interrupt Mask + SDIOWAIT : Boolean; + -- Read-only. Completion Signal Received Interrupt Mask + CSRCV : Boolean; + -- unspecified + Reserved_14_15 : HAL.UInt2; + -- Read-only. Response Index Error Interrupt Mask + RINDE : Boolean; + -- Read-only. Response Direction Error Interrupt Mask + RDIRE : Boolean; + -- Read-only. Response CRC Error Interrupt Mask + RCRCE : Boolean; + -- Read-only. Response End Bit Error Interrupt Mask + RENDE : Boolean; + -- Read-only. Response Time-out Error Interrupt Mask + RTOE : Boolean; + -- Read-only. Data CRC Error Interrupt Mask + DCRCE : Boolean; + -- Read-only. Data Time-out Error Interrupt Mask + DTOE : Boolean; + -- Read-only. Completion Signal Time-out Error Interrupt Mask + CSTOE : Boolean; + -- Read-only. DMA Block Overrun Error Interrupt Mask + BLKOVRE : Boolean; + -- unspecified + Reserved_25_25 : HAL.Bit; + -- Read-only. FIFO Empty Interrupt Mask + FIFOEMPTY : Boolean; + -- Read-only. Transfer Done Interrupt Mask + XFRDONE : Boolean; + -- Read-only. Boot Operation Acknowledge Received Interrupt Mask + ACKRCV : Boolean; + -- Read-only. Boot Operation Acknowledge Error Interrupt Mask + ACKRCVE : Boolean; + -- Read-only. Overrun Interrupt Mask + OVRE : Boolean; + -- Read-only. Underrun Interrupt Mask + UNRE : Boolean; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for HSMCI_HSMCI_IMR_Register use record + CMDRDY at 0 range 0 .. 0; + RXRDY at 0 range 1 .. 1; + TXRDY at 0 range 2 .. 2; + BLKE at 0 range 3 .. 3; + DTIP at 0 range 4 .. 4; + NOTBUSY at 0 range 5 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + SDIOIRQA at 0 range 8 .. 8; + Reserved_9_11 at 0 range 9 .. 11; + SDIOWAIT at 0 range 12 .. 12; + CSRCV at 0 range 13 .. 13; + Reserved_14_15 at 0 range 14 .. 15; + RINDE at 0 range 16 .. 16; + RDIRE at 0 range 17 .. 17; + RCRCE at 0 range 18 .. 18; + RENDE at 0 range 19 .. 19; + RTOE at 0 range 20 .. 20; + DCRCE at 0 range 21 .. 21; + DTOE at 0 range 22 .. 22; + CSTOE at 0 range 23 .. 23; + BLKOVRE at 0 range 24 .. 24; + Reserved_25_25 at 0 range 25 .. 25; + FIFOEMPTY at 0 range 26 .. 26; + XFRDONE at 0 range 27 .. 27; + ACKRCV at 0 range 28 .. 28; + ACKRCVE at 0 range 29 .. 29; + OVRE at 0 range 30 .. 30; + UNRE at 0 range 31 .. 31; + end record; + + -- DMA Channel Read and Write Chunk Size + type HSMCI_DMA_CHKSIZE_Field is + ( + -- 1 data available + Val_1, + -- 2 data available + Val_2, + -- 4 data available + Val_4, + -- 8 data available + Val_8, + -- 16 data available + Val_16) + with Size => 3; + for HSMCI_DMA_CHKSIZE_Field use + (Val_1 => 0, + Val_2 => 1, + Val_4 => 2, + Val_8 => 3, + Val_16 => 4); + + -- DMA Configuration Register + type HSMCI_HSMCI_DMA_Register is record + -- unspecified + Reserved_0_3 : HAL.UInt4 := 16#0#; + -- DMA Channel Read and Write Chunk Size + CHKSIZE : HSMCI_DMA_CHKSIZE_Field := SAM_SVD.HSMCI.Val_1; + -- unspecified + Reserved_7_7 : HAL.Bit := 16#0#; + -- DMA Hardware Handshaking Enable + DMAEN : Boolean := False; + -- unspecified + Reserved_9_31 : HAL.UInt23 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for HSMCI_HSMCI_DMA_Register use record + Reserved_0_3 at 0 range 0 .. 3; + CHKSIZE at 0 range 4 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + DMAEN at 0 range 8 .. 8; + Reserved_9_31 at 0 range 9 .. 31; + end record; + + -- Configuration Register + type HSMCI_HSMCI_CFG_Register is record + -- HSMCI Internal FIFO control mode + FIFOMODE : Boolean := False; + -- unspecified + Reserved_1_3 : HAL.UInt3 := 16#0#; + -- Flow Error flag reset control mode + FERRCTRL : Boolean := False; + -- unspecified + Reserved_5_7 : HAL.UInt3 := 16#0#; + -- High Speed Mode + HSMODE : Boolean := False; + -- unspecified + Reserved_9_11 : HAL.UInt3 := 16#0#; + -- Synchronize on the last block + LSYNC : Boolean := False; + -- unspecified + Reserved_13_31 : HAL.UInt19 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for HSMCI_HSMCI_CFG_Register use record + FIFOMODE at 0 range 0 .. 0; + Reserved_1_3 at 0 range 1 .. 3; + FERRCTRL at 0 range 4 .. 4; + Reserved_5_7 at 0 range 5 .. 7; + HSMODE at 0 range 8 .. 8; + Reserved_9_11 at 0 range 9 .. 11; + LSYNC at 0 range 12 .. 12; + Reserved_13_31 at 0 range 13 .. 31; + end record; + + -- Write Protect Key + type HSMCI_WPMR_WPKEY_Field is + ( + -- Reset value for the field + Hsmci_Wpmr_Wpkey_Field_Reset, + -- Writing any other value in this field aborts the write operation of + -- the WPEN bit.Always reads as 0. + Passwd) + with Size => 24; + for HSMCI_WPMR_WPKEY_Field use + (Hsmci_Wpmr_Wpkey_Field_Reset => 0, + Passwd => 5063497); + + -- Write Protection Mode Register + type HSMCI_HSMCI_WPMR_Register is record + -- Write Protect Enable + WPEN : Boolean := False; + -- unspecified + Reserved_1_7 : HAL.UInt7 := 16#0#; + -- Write Protect Key + WPKEY : HSMCI_WPMR_WPKEY_Field := Hsmci_Wpmr_Wpkey_Field_Reset; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for HSMCI_HSMCI_WPMR_Register use record + WPEN at 0 range 0 .. 0; + Reserved_1_7 at 0 range 1 .. 7; + WPKEY at 0 range 8 .. 31; + end record; + + subtype HSMCI_HSMCI_WPSR_WPVSRC_Field is HAL.UInt16; + + -- Write Protection Status Register + type HSMCI_HSMCI_WPSR_Register is record + -- Read-only. Write Protection Violation Status + WPVS : Boolean; + -- unspecified + Reserved_1_7 : HAL.UInt7; + -- Read-only. Write Protection Violation Source + WPVSRC : HSMCI_HSMCI_WPSR_WPVSRC_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for HSMCI_HSMCI_WPSR_Register use record + WPVS at 0 range 0 .. 0; + Reserved_1_7 at 0 range 1 .. 7; + WPVSRC at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype HSMCI_HSMCI_VERSION_VERSION_Field is HAL.UInt12; + subtype HSMCI_HSMCI_VERSION_MFN_Field is HAL.UInt3; + + -- Version Register + type HSMCI_HSMCI_VERSION_Register is record + -- Read-only. Hardware Module Version + VERSION : HSMCI_HSMCI_VERSION_VERSION_Field; + -- unspecified + Reserved_12_15 : HAL.UInt4; + -- Read-only. Metal Fix Number + MFN : HSMCI_HSMCI_VERSION_MFN_Field; + -- unspecified + Reserved_19_31 : HAL.UInt13; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for HSMCI_HSMCI_VERSION_Register use record + VERSION at 0 range 0 .. 11; + Reserved_12_15 at 0 range 12 .. 15; + MFN at 0 range 16 .. 18; + Reserved_19_31 at 0 range 19 .. 31; + end record; + + -- FIFO Memory Aperture0 0 + + -- FIFO Memory Aperture0 0 + type HSMCI_HSMCI_FIFO_Registers is array (0 .. 255) of HAL.UInt32 + with Volatile; + + ----------------- + -- Peripherals -- + ----------------- + + -- High Speed MultiMedia Card Interface + type HSMCI_Peripheral is record + -- Control Register + HSMCI_CR : aliased HSMCI_HSMCI_CR_Register; + -- Mode Register + HSMCI_MR : aliased HSMCI_HSMCI_MR_Register; + -- Data Timeout Register + HSMCI_DTOR : aliased HSMCI_HSMCI_DTOR_Register; + -- SD/SDIO Card Register + HSMCI_SDCR : aliased HSMCI_HSMCI_SDCR_Register; + -- Argument Register + HSMCI_ARGR : aliased HAL.UInt32; + -- Command Register + HSMCI_CMDR : aliased HSMCI_HSMCI_CMDR_Register; + -- Block Register + HSMCI_BLKR : aliased HSMCI_HSMCI_BLKR_Register; + -- Completion Signal Timeout Register + HSMCI_CSTOR : aliased HSMCI_HSMCI_CSTOR_Register; + -- Response Register 0 + HSMCI_RSPR : aliased HSMCI_HSMCI_RSPR_Registers; + -- Receive Data Register + HSMCI_RDR : aliased HAL.UInt32; + -- Transmit Data Register + HSMCI_TDR : aliased HAL.UInt32; + -- Status Register + HSMCI_SR : aliased HSMCI_HSMCI_SR_Register; + -- Interrupt Enable Register + HSMCI_IER : aliased HSMCI_HSMCI_IER_Register; + -- Interrupt Disable Register + HSMCI_IDR : aliased HSMCI_HSMCI_IDR_Register; + -- Interrupt Mask Register + HSMCI_IMR : aliased HSMCI_HSMCI_IMR_Register; + -- DMA Configuration Register + HSMCI_DMA : aliased HSMCI_HSMCI_DMA_Register; + -- Configuration Register + HSMCI_CFG : aliased HSMCI_HSMCI_CFG_Register; + -- Write Protection Mode Register + HSMCI_WPMR : aliased HSMCI_HSMCI_WPMR_Register; + -- Write Protection Status Register + HSMCI_WPSR : aliased HSMCI_HSMCI_WPSR_Register; + -- Version Register + HSMCI_VERSION : aliased HSMCI_HSMCI_VERSION_Register; + -- FIFO Memory Aperture0 0 + HSMCI_FIFO : aliased HSMCI_HSMCI_FIFO_Registers; + end record + with Volatile; + + for HSMCI_Peripheral use record + HSMCI_CR at 16#0# range 0 .. 31; + HSMCI_MR at 16#4# range 0 .. 31; + HSMCI_DTOR at 16#8# range 0 .. 31; + HSMCI_SDCR at 16#C# range 0 .. 31; + HSMCI_ARGR at 16#10# range 0 .. 31; + HSMCI_CMDR at 16#14# range 0 .. 31; + HSMCI_BLKR at 16#18# range 0 .. 31; + HSMCI_CSTOR at 16#1C# range 0 .. 31; + HSMCI_RSPR at 16#20# range 0 .. 127; + HSMCI_RDR at 16#30# range 0 .. 31; + HSMCI_TDR at 16#34# range 0 .. 31; + HSMCI_SR at 16#40# range 0 .. 31; + HSMCI_IER at 16#44# range 0 .. 31; + HSMCI_IDR at 16#48# range 0 .. 31; + HSMCI_IMR at 16#4C# range 0 .. 31; + HSMCI_DMA at 16#50# range 0 .. 31; + HSMCI_CFG at 16#54# range 0 .. 31; + HSMCI_WPMR at 16#E4# range 0 .. 31; + HSMCI_WPSR at 16#E8# range 0 .. 31; + HSMCI_VERSION at 16#FC# range 0 .. 31; + HSMCI_FIFO at 16#200# range 0 .. 8191; + end record; + + -- High Speed MultiMedia Card Interface + HSMCI_Periph : aliased HSMCI_Peripheral + with Import, Address => System'To_Address (16#40000000#); + +end SAM_SVD.HSMCI; diff --git a/arch/ARM/SAM/svd/atsamv71/sam_svd-icm.ads b/arch/ARM/SAM/svd/atsamv71/sam_svd-icm.ads new file mode 100644 index 000000000..249385b9b --- /dev/null +++ b/arch/ARM/SAM/svd/atsamv71/sam_svd-icm.ads @@ -0,0 +1,438 @@ +-- This spec has been automatically generated from ATSAMV71Q21.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package SAM_SVD.ICM is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + subtype ICM_ICM_CFG_BBC_Field is HAL.UInt4; + + -- User SHA Algorithm + type ICM_CFG_UALGO_Field is + ( + -- SHA1 algorithm processed + Sha1, + -- SHA256 algorithm processed + Sha256, + -- SHA224 algorithm processed + Sha224) + with Size => 3; + for ICM_CFG_UALGO_Field use + (Sha1 => 0, + Sha256 => 1, + Sha224 => 4); + + subtype ICM_ICM_CFG_HAPROT_Field is HAL.UInt6; + subtype ICM_ICM_CFG_DAPROT_Field is HAL.UInt6; + + -- Configuration Register + type ICM_ICM_CFG_Register is record + -- Write Back Disable + WBDIS : Boolean := False; + -- End of Monitoring Disable + EOMDIS : Boolean := False; + -- Secondary List Branching Disable + SLBDIS : Boolean := False; + -- unspecified + Reserved_3_3 : HAL.Bit := 16#0#; + -- Bus Burden Control + BBC : ICM_ICM_CFG_BBC_Field := 16#0#; + -- Automatic Switch To Compare Digest + ASCD : Boolean := False; + -- Dual Input Buffer + DUALBUFF : Boolean := False; + -- unspecified + Reserved_10_11 : HAL.UInt2 := 16#0#; + -- User Initial Hash Value + UIHASH : Boolean := False; + -- User SHA Algorithm + UALGO : ICM_CFG_UALGO_Field := SAM_SVD.ICM.Sha1; + -- Region Hash Area Protection + HAPROT : ICM_ICM_CFG_HAPROT_Field := 16#0#; + -- unspecified + Reserved_22_23 : HAL.UInt2 := 16#0#; + -- Region Descriptor Area Protection + DAPROT : ICM_ICM_CFG_DAPROT_Field := 16#0#; + -- unspecified + Reserved_30_31 : HAL.UInt2 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for ICM_ICM_CFG_Register use record + WBDIS at 0 range 0 .. 0; + EOMDIS at 0 range 1 .. 1; + SLBDIS at 0 range 2 .. 2; + Reserved_3_3 at 0 range 3 .. 3; + BBC at 0 range 4 .. 7; + ASCD at 0 range 8 .. 8; + DUALBUFF at 0 range 9 .. 9; + Reserved_10_11 at 0 range 10 .. 11; + UIHASH at 0 range 12 .. 12; + UALGO at 0 range 13 .. 15; + HAPROT at 0 range 16 .. 21; + Reserved_22_23 at 0 range 22 .. 23; + DAPROT at 0 range 24 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + subtype ICM_ICM_CTRL_REHASH_Field is HAL.UInt4; + subtype ICM_ICM_CTRL_RMDIS_Field is HAL.UInt4; + subtype ICM_ICM_CTRL_RMEN_Field is HAL.UInt4; + + -- Control Register + type ICM_ICM_CTRL_Register is record + -- Write-only. ICM Enable + ENABLE : Boolean := False; + -- Write-only. ICM Disable Register + DISABLE : Boolean := False; + -- Write-only. Software Reset + SWRST : Boolean := False; + -- unspecified + Reserved_3_3 : HAL.Bit := 16#0#; + -- Write-only. Recompute Internal Hash + REHASH : ICM_ICM_CTRL_REHASH_Field := 16#0#; + -- Write-only. Region Monitoring Disable + RMDIS : ICM_ICM_CTRL_RMDIS_Field := 16#0#; + -- Write-only. Region Monitoring Enable + RMEN : ICM_ICM_CTRL_RMEN_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for ICM_ICM_CTRL_Register use record + ENABLE at 0 range 0 .. 0; + DISABLE at 0 range 1 .. 1; + SWRST at 0 range 2 .. 2; + Reserved_3_3 at 0 range 3 .. 3; + REHASH at 0 range 4 .. 7; + RMDIS at 0 range 8 .. 11; + RMEN at 0 range 12 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype ICM_ICM_SR_RAWRMDIS_Field is HAL.UInt4; + subtype ICM_ICM_SR_RMDIS_Field is HAL.UInt4; + + -- Status Register + type ICM_ICM_SR_Register is record + -- Read-only. ICM Controller Enable Register + ENABLE : Boolean; + -- unspecified + Reserved_1_7 : HAL.UInt7; + -- Read-only. Region Monitoring Disabled Raw Status + RAWRMDIS : ICM_ICM_SR_RAWRMDIS_Field; + -- Read-only. Region Monitoring Disabled Status + RMDIS : ICM_ICM_SR_RMDIS_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for ICM_ICM_SR_Register use record + ENABLE at 0 range 0 .. 0; + Reserved_1_7 at 0 range 1 .. 7; + RAWRMDIS at 0 range 8 .. 11; + RMDIS at 0 range 12 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype ICM_ICM_IER_RHC_Field is HAL.UInt4; + subtype ICM_ICM_IER_RDM_Field is HAL.UInt4; + subtype ICM_ICM_IER_RBE_Field is HAL.UInt4; + subtype ICM_ICM_IER_RWC_Field is HAL.UInt4; + subtype ICM_ICM_IER_REC_Field is HAL.UInt4; + subtype ICM_ICM_IER_RSU_Field is HAL.UInt4; + + -- Interrupt Enable Register + type ICM_ICM_IER_Register is record + -- Write-only. Region Hash Completed Interrupt Enable + RHC : ICM_ICM_IER_RHC_Field := 16#0#; + -- Write-only. Region Digest Mismatch Interrupt Enable + RDM : ICM_ICM_IER_RDM_Field := 16#0#; + -- Write-only. Region Bus Error Interrupt Enable + RBE : ICM_ICM_IER_RBE_Field := 16#0#; + -- Write-only. Region Wrap Condition detected Interrupt Enable + RWC : ICM_ICM_IER_RWC_Field := 16#0#; + -- Write-only. Region End bit Condition Detected Interrupt Enable + REC : ICM_ICM_IER_REC_Field := 16#0#; + -- Write-only. Region Status Updated Interrupt Disable + RSU : ICM_ICM_IER_RSU_Field := 16#0#; + -- Write-only. Undefined Register Access Detection Interrupt Enable + URAD : Boolean := False; + -- unspecified + Reserved_25_31 : HAL.UInt7 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for ICM_ICM_IER_Register use record + RHC at 0 range 0 .. 3; + RDM at 0 range 4 .. 7; + RBE at 0 range 8 .. 11; + RWC at 0 range 12 .. 15; + REC at 0 range 16 .. 19; + RSU at 0 range 20 .. 23; + URAD at 0 range 24 .. 24; + Reserved_25_31 at 0 range 25 .. 31; + end record; + + subtype ICM_ICM_IDR_RHC_Field is HAL.UInt4; + subtype ICM_ICM_IDR_RDM_Field is HAL.UInt4; + subtype ICM_ICM_IDR_RBE_Field is HAL.UInt4; + subtype ICM_ICM_IDR_RWC_Field is HAL.UInt4; + subtype ICM_ICM_IDR_REC_Field is HAL.UInt4; + subtype ICM_ICM_IDR_RSU_Field is HAL.UInt4; + + -- Interrupt Disable Register + type ICM_ICM_IDR_Register is record + -- Write-only. Region Hash Completed Interrupt Disable + RHC : ICM_ICM_IDR_RHC_Field := 16#0#; + -- Write-only. Region Digest Mismatch Interrupt Disable + RDM : ICM_ICM_IDR_RDM_Field := 16#0#; + -- Write-only. Region Bus Error Interrupt Disable + RBE : ICM_ICM_IDR_RBE_Field := 16#0#; + -- Write-only. Region Wrap Condition Detected Interrupt Disable + RWC : ICM_ICM_IDR_RWC_Field := 16#0#; + -- Write-only. Region End bit Condition detected Interrupt Disable + REC : ICM_ICM_IDR_REC_Field := 16#0#; + -- Write-only. Region Status Updated Interrupt Disable + RSU : ICM_ICM_IDR_RSU_Field := 16#0#; + -- Write-only. Undefined Register Access Detection Interrupt Disable + URAD : Boolean := False; + -- unspecified + Reserved_25_31 : HAL.UInt7 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for ICM_ICM_IDR_Register use record + RHC at 0 range 0 .. 3; + RDM at 0 range 4 .. 7; + RBE at 0 range 8 .. 11; + RWC at 0 range 12 .. 15; + REC at 0 range 16 .. 19; + RSU at 0 range 20 .. 23; + URAD at 0 range 24 .. 24; + Reserved_25_31 at 0 range 25 .. 31; + end record; + + subtype ICM_ICM_IMR_RHC_Field is HAL.UInt4; + subtype ICM_ICM_IMR_RDM_Field is HAL.UInt4; + subtype ICM_ICM_IMR_RBE_Field is HAL.UInt4; + subtype ICM_ICM_IMR_RWC_Field is HAL.UInt4; + subtype ICM_ICM_IMR_REC_Field is HAL.UInt4; + subtype ICM_ICM_IMR_RSU_Field is HAL.UInt4; + + -- Interrupt Mask Register + type ICM_ICM_IMR_Register is record + -- Read-only. Region Hash Completed Interrupt Mask + RHC : ICM_ICM_IMR_RHC_Field; + -- Read-only. Region Digest Mismatch Interrupt Mask + RDM : ICM_ICM_IMR_RDM_Field; + -- Read-only. Region Bus Error Interrupt Mask + RBE : ICM_ICM_IMR_RBE_Field; + -- Read-only. Region Wrap Condition Detected Interrupt Mask + RWC : ICM_ICM_IMR_RWC_Field; + -- Read-only. Region End bit Condition Detected Interrupt Mask + REC : ICM_ICM_IMR_REC_Field; + -- Read-only. Region Status Updated Interrupt Mask + RSU : ICM_ICM_IMR_RSU_Field; + -- Read-only. Undefined Register Access Detection Interrupt Mask + URAD : Boolean; + -- unspecified + Reserved_25_31 : HAL.UInt7; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for ICM_ICM_IMR_Register use record + RHC at 0 range 0 .. 3; + RDM at 0 range 4 .. 7; + RBE at 0 range 8 .. 11; + RWC at 0 range 12 .. 15; + REC at 0 range 16 .. 19; + RSU at 0 range 20 .. 23; + URAD at 0 range 24 .. 24; + Reserved_25_31 at 0 range 25 .. 31; + end record; + + subtype ICM_ICM_ISR_RHC_Field is HAL.UInt4; + subtype ICM_ICM_ISR_RDM_Field is HAL.UInt4; + subtype ICM_ICM_ISR_RBE_Field is HAL.UInt4; + subtype ICM_ICM_ISR_RWC_Field is HAL.UInt4; + subtype ICM_ICM_ISR_REC_Field is HAL.UInt4; + subtype ICM_ICM_ISR_RSU_Field is HAL.UInt4; + + -- Interrupt Status Register + type ICM_ICM_ISR_Register is record + -- Read-only. Region Hash Completed + RHC : ICM_ICM_ISR_RHC_Field; + -- Read-only. Region Digest Mismatch + RDM : ICM_ICM_ISR_RDM_Field; + -- Read-only. Region Bus Error + RBE : ICM_ICM_ISR_RBE_Field; + -- Read-only. Region Wrap Condition Detected + RWC : ICM_ICM_ISR_RWC_Field; + -- Read-only. Region End bit Condition Detected + REC : ICM_ICM_ISR_REC_Field; + -- Read-only. Region Status Updated Detected + RSU : ICM_ICM_ISR_RSU_Field; + -- Read-only. Undefined Register Access Detection Status + URAD : Boolean; + -- unspecified + Reserved_25_31 : HAL.UInt7; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for ICM_ICM_ISR_Register use record + RHC at 0 range 0 .. 3; + RDM at 0 range 4 .. 7; + RBE at 0 range 8 .. 11; + RWC at 0 range 12 .. 15; + REC at 0 range 16 .. 19; + RSU at 0 range 20 .. 23; + URAD at 0 range 24 .. 24; + Reserved_25_31 at 0 range 25 .. 31; + end record; + + -- Undefined Register Access Trace + type ICM_UASR_URAT_Field is + ( + -- Unspecified structure member set to one detected when the descriptor + -- is loaded. + Unspec_Struct_Member, + -- ICM_CFG modified during active monitoring. + Icm_Cfg_Modified, + -- ICM_DSCR modified during active monitoring. + Icm_Dscr_Modified, + -- ICM_HASH modified during active monitoring + Icm_Hash_Modified, + -- Write-only register read access + Read_Access) + with Size => 3; + for ICM_UASR_URAT_Field use + (Unspec_Struct_Member => 0, + Icm_Cfg_Modified => 1, + Icm_Dscr_Modified => 2, + Icm_Hash_Modified => 3, + Read_Access => 4); + + -- Undefined Access Status Register + type ICM_ICM_UASR_Register is record + -- Read-only. Undefined Register Access Trace + URAT : ICM_UASR_URAT_Field; + -- unspecified + Reserved_3_31 : HAL.UInt29; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for ICM_ICM_UASR_Register use record + URAT at 0 range 0 .. 2; + Reserved_3_31 at 0 range 3 .. 31; + end record; + + subtype ICM_ICM_DSCR_DASA_Field is HAL.UInt26; + + -- Region Descriptor Area Start Address Register + type ICM_ICM_DSCR_Register is record + -- unspecified + Reserved_0_5 : HAL.UInt6 := 16#0#; + -- Descriptor Area Start Address + DASA : ICM_ICM_DSCR_DASA_Field := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for ICM_ICM_DSCR_Register use record + Reserved_0_5 at 0 range 0 .. 5; + DASA at 0 range 6 .. 31; + end record; + + subtype ICM_ICM_HASH_HASA_Field is HAL.UInt25; + + -- Region Hash Area Start Address Register + type ICM_ICM_HASH_Register is record + -- unspecified + Reserved_0_6 : HAL.UInt7 := 16#0#; + -- Hash Area Start Address + HASA : ICM_ICM_HASH_HASA_Field := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for ICM_ICM_HASH_Register use record + Reserved_0_6 at 0 range 0 .. 6; + HASA at 0 range 7 .. 31; + end record; + + -- User Initial Hash Value 0 Register 0 + + -- User Initial Hash Value 0 Register 0 + type ICM_ICM_UIHVAL_Registers is array (0 .. 7) of HAL.UInt32 + with Volatile; + + ----------------- + -- Peripherals -- + ----------------- + + -- Integrity Check Monitor + type ICM_Peripheral is record + -- Configuration Register + ICM_CFG : aliased ICM_ICM_CFG_Register; + -- Control Register + ICM_CTRL : aliased ICM_ICM_CTRL_Register; + -- Status Register + ICM_SR : aliased ICM_ICM_SR_Register; + -- Interrupt Enable Register + ICM_IER : aliased ICM_ICM_IER_Register; + -- Interrupt Disable Register + ICM_IDR : aliased ICM_ICM_IDR_Register; + -- Interrupt Mask Register + ICM_IMR : aliased ICM_ICM_IMR_Register; + -- Interrupt Status Register + ICM_ISR : aliased ICM_ICM_ISR_Register; + -- Undefined Access Status Register + ICM_UASR : aliased ICM_ICM_UASR_Register; + -- Region Descriptor Area Start Address Register + ICM_DSCR : aliased ICM_ICM_DSCR_Register; + -- Region Hash Area Start Address Register + ICM_HASH : aliased ICM_ICM_HASH_Register; + -- User Initial Hash Value 0 Register 0 + ICM_UIHVAL : aliased ICM_ICM_UIHVAL_Registers; + end record + with Volatile; + + for ICM_Peripheral use record + ICM_CFG at 16#0# range 0 .. 31; + ICM_CTRL at 16#4# range 0 .. 31; + ICM_SR at 16#8# range 0 .. 31; + ICM_IER at 16#10# range 0 .. 31; + ICM_IDR at 16#14# range 0 .. 31; + ICM_IMR at 16#18# range 0 .. 31; + ICM_ISR at 16#1C# range 0 .. 31; + ICM_UASR at 16#20# range 0 .. 31; + ICM_DSCR at 16#30# range 0 .. 31; + ICM_HASH at 16#34# range 0 .. 31; + ICM_UIHVAL at 16#38# range 0 .. 255; + end record; + + -- Integrity Check Monitor + ICM_Periph : aliased ICM_Peripheral + with Import, Address => System'To_Address (16#40048000#); + +end SAM_SVD.ICM; diff --git a/arch/ARM/SAM/svd/atsamv71/sam_svd-interrupts.ads b/arch/ARM/SAM/svd/atsamv71/sam_svd-interrupts.ads new file mode 100644 index 000000000..4ddedaf61 --- /dev/null +++ b/arch/ARM/SAM/svd/atsamv71/sam_svd-interrupts.ads @@ -0,0 +1,77 @@ +-- This spec has been automatically generated from ATSAMV71Q21.svd + +-- Definition of the device's interrupts +package SAM_SVD.Interrupts is + + ---------------- + -- Interrupts -- + ---------------- + + SUPC : constant := 0; + RSTC : constant := 1; + RTC : constant := 2; + RTT : constant := 3; + WDT : constant := 4; + PMC : constant := 5; + EFC : constant := 6; + UART0 : constant := 7; + UART1 : constant := 8; + PIOA : constant := 10; + PIOB : constant := 11; + PIOC : constant := 12; + USART0 : constant := 13; + USART1 : constant := 14; + USART2 : constant := 15; + PIOD : constant := 16; + PIOE : constant := 17; + HSMCI : constant := 18; + TWIHS0 : constant := 19; + TWIHS1 : constant := 20; + SPI0 : constant := 21; + SSC : constant := 22; + TC0 : constant := 23; + TC1 : constant := 24; + TC2 : constant := 25; + TC3 : constant := 26; + TC4 : constant := 27; + TC5 : constant := 28; + AFEC0 : constant := 29; + DACC : constant := 30; + PWM0 : constant := 31; + ICM : constant := 32; + ACC : constant := 33; + USBHS : constant := 34; + MCAN0_INT0 : constant := 35; + MCAN0_INT1 : constant := 36; + MCAN1_INT0 : constant := 37; + MCAN1_INT1 : constant := 38; + GMAC : constant := 39; + AFEC1 : constant := 40; + TWIHS2 : constant := 41; + SPI1 : constant := 42; + QSPI : constant := 43; + UART2 : constant := 44; + UART3 : constant := 45; + UART4 : constant := 46; + TC6 : constant := 47; + TC7 : constant := 48; + TC8 : constant := 49; + TC9 : constant := 50; + TC10 : constant := 51; + TC11 : constant := 52; + MLB : constant := 53; + AES : constant := 56; + TRNG : constant := 57; + XDMAC : constant := 58; + ISI : constant := 59; + PWM1 : constant := 60; + FPU : constant := 61; + SDRAMC : constant := 62; + RSWDT : constant := 63; + CCW : constant := 64; + CCF : constant := 65; + GMAC_Q1 : constant := 66; + GMAC_Q2 : constant := 67; + IXC : constant := 68; + +end SAM_SVD.Interrupts; diff --git a/arch/ARM/SAM/svd/atsamv71/sam_svd-isi.ads b/arch/ARM/SAM/svd/atsamv71/sam_svd-isi.ads new file mode 100644 index 000000000..27a8bbe65 --- /dev/null +++ b/arch/ARM/SAM/svd/atsamv71/sam_svd-isi.ads @@ -0,0 +1,962 @@ +-- This spec has been automatically generated from ATSAMV71Q21.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package SAM_SVD.ISI is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + subtype ISI_ISI_CFG1_FRATE_Field is HAL.UInt3; + + -- Threshold Mask + type ISI_CFG1_THMASK_Field is + ( + -- Only 4 beats AHB burst allowed + Beats_4, + -- Only 4 and 8 beats AHB burst allowed + Beats_8, + -- 4, 8 and 16 beats AHB burst allowed + Beats_16) + with Size => 2; + for ISI_CFG1_THMASK_Field use + (Beats_4 => 0, + Beats_8 => 1, + Beats_16 => 2); + + subtype ISI_ISI_CFG1_SLD_Field is HAL.UInt8; + subtype ISI_ISI_CFG1_SFD_Field is HAL.UInt8; + + -- ISI Configuration 1 Register + type ISI_ISI_CFG1_Register is record + -- unspecified + Reserved_0_1 : HAL.UInt2 := 16#0#; + -- Horizontal Synchronization Polarity + HSYNC_POL : Boolean := False; + -- Vertical Synchronization Polarity + VSYNC_POL : Boolean := False; + -- Pixel Clock Polarity + PIXCLK_POL : Boolean := False; + -- Grayscale Little Endian + GRAYLE : Boolean := False; + -- Embedded Synchronization + EMB_SYNC : Boolean := False; + -- Embedded Synchronization Correction + CRC_SYNC : Boolean := False; + -- Frame Rate [0..7] + FRATE : ISI_ISI_CFG1_FRATE_Field := 16#0#; + -- Disable Codec Request + DISCR : Boolean := False; + -- Full Mode is Allowed + FULL : Boolean := False; + -- Threshold Mask + THMASK : ISI_CFG1_THMASK_Field := SAM_SVD.ISI.Beats_4; + -- unspecified + Reserved_15_15 : HAL.Bit := 16#0#; + -- Start of Line Delay + SLD : ISI_ISI_CFG1_SLD_Field := 16#0#; + -- Start of Frame Delay + SFD : ISI_ISI_CFG1_SFD_Field := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for ISI_ISI_CFG1_Register use record + Reserved_0_1 at 0 range 0 .. 1; + HSYNC_POL at 0 range 2 .. 2; + VSYNC_POL at 0 range 3 .. 3; + PIXCLK_POL at 0 range 4 .. 4; + GRAYLE at 0 range 5 .. 5; + EMB_SYNC at 0 range 6 .. 6; + CRC_SYNC at 0 range 7 .. 7; + FRATE at 0 range 8 .. 10; + DISCR at 0 range 11 .. 11; + FULL at 0 range 12 .. 12; + THMASK at 0 range 13 .. 14; + Reserved_15_15 at 0 range 15 .. 15; + SLD at 0 range 16 .. 23; + SFD at 0 range 24 .. 31; + end record; + + subtype ISI_ISI_CFG2_IM_VSIZE_Field is HAL.UInt11; + subtype ISI_ISI_CFG2_IM_HSIZE_Field is HAL.UInt11; + + -- YCrCb Format Swap Mode + type ISI_CFG2_YCC_SWAP_Field is + ( + -- Byte 0 Cb(i)Byte 1 Y(i)Byte 2 Cr(i)Byte 3 Y(i+1) + Default, + -- Byte 0 Cr(i)Byte 1 Y(i)Byte 2 Cb(i)Byte 3 Y(i+1) + Mode1, + -- Byte 0 Y(i)Byte 1 Cb(i)Byte 2 Y(i+1)Byte 3 Cr(i) + Mode2, + -- Byte 0 Y(i)Byte 1 Cr(i)Byte 2 Y(i+1)Byte 3 Cb(i) + Mode3) + with Size => 2; + for ISI_CFG2_YCC_SWAP_Field use + (Default => 0, + Mode1 => 1, + Mode2 => 2, + Mode3 => 3); + + -- RGB Pixel Mapping Configuration + type ISI_CFG2_RGB_CFG_Field is + ( + -- Byte 0 R/G(MSB)Byte 1 G(LSB)/BByte 2 R/G(MSB)Byte 3 G(LSB)/B + Default, + -- Byte 0 B/G(MSB)Byte 1 G(LSB)/RByte 2 B/G(MSB)Byte 3 G(LSB)/R + Mode1, + -- Byte 0 G(LSB)/RByte 1 B/G(MSB)Byte 2 G(LSB)/RByte 3 B/G(MSB) + Mode2, + -- Byte 0 G(LSB)/BByte 1 R/G(MSB)Byte 2 G(LSB)/BByte 3 R/G(MSB) + Mode3) + with Size => 2; + for ISI_CFG2_RGB_CFG_Field use + (Default => 0, + Mode1 => 1, + Mode2 => 2, + Mode3 => 3); + + -- ISI Configuration 2 Register + type ISI_ISI_CFG2_Register is record + -- Vertical Size of the Image Sensor [0..2047] + IM_VSIZE : ISI_ISI_CFG2_IM_VSIZE_Field := 16#0#; + -- Grayscale Pixel Format Mode + GS_MODE : Boolean := False; + -- RGB Input Mode + RGB_MODE : Boolean := False; + -- Grayscale Mode Format Enable + GRAYSCALE : Boolean := False; + -- RGB Format Swap Mode + RGB_SWAP : Boolean := False; + -- Color Space for the Image Data + COL_SPACE : Boolean := False; + -- Horizontal Size of the Image Sensor [0..2047] + IM_HSIZE : ISI_ISI_CFG2_IM_HSIZE_Field := 16#0#; + -- unspecified + Reserved_27_27 : HAL.Bit := 16#0#; + -- YCrCb Format Swap Mode + YCC_SWAP : ISI_CFG2_YCC_SWAP_Field := SAM_SVD.ISI.Default; + -- RGB Pixel Mapping Configuration + RGB_CFG : ISI_CFG2_RGB_CFG_Field := SAM_SVD.ISI.Default; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for ISI_ISI_CFG2_Register use record + IM_VSIZE at 0 range 0 .. 10; + GS_MODE at 0 range 11 .. 11; + RGB_MODE at 0 range 12 .. 12; + GRAYSCALE at 0 range 13 .. 13; + RGB_SWAP at 0 range 14 .. 14; + COL_SPACE at 0 range 15 .. 15; + IM_HSIZE at 0 range 16 .. 26; + Reserved_27_27 at 0 range 27 .. 27; + YCC_SWAP at 0 range 28 .. 29; + RGB_CFG at 0 range 30 .. 31; + end record; + + subtype ISI_ISI_PSIZE_PREV_VSIZE_Field is HAL.UInt10; + subtype ISI_ISI_PSIZE_PREV_HSIZE_Field is HAL.UInt10; + + -- ISI Preview Size Register + type ISI_ISI_PSIZE_Register is record + -- Vertical Size for the Preview Path + PREV_VSIZE : ISI_ISI_PSIZE_PREV_VSIZE_Field := 16#0#; + -- unspecified + Reserved_10_15 : HAL.UInt6 := 16#0#; + -- Horizontal Size for the Preview Path + PREV_HSIZE : ISI_ISI_PSIZE_PREV_HSIZE_Field := 16#0#; + -- unspecified + Reserved_26_31 : HAL.UInt6 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for ISI_ISI_PSIZE_Register use record + PREV_VSIZE at 0 range 0 .. 9; + Reserved_10_15 at 0 range 10 .. 15; + PREV_HSIZE at 0 range 16 .. 25; + Reserved_26_31 at 0 range 26 .. 31; + end record; + + subtype ISI_ISI_PDECF_DEC_FACTOR_Field is HAL.UInt8; + + -- ISI Preview Decimation Factor Register + type ISI_ISI_PDECF_Register is record + -- Decimation Factor + DEC_FACTOR : ISI_ISI_PDECF_DEC_FACTOR_Field := 16#0#; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for ISI_ISI_PDECF_Register use record + DEC_FACTOR at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- ISI_ISI_Y2R_SET0_C array element + subtype ISI_ISI_Y2R_SET0_C_Element is HAL.UInt8; + + -- ISI_ISI_Y2R_SET0_C array + type ISI_ISI_Y2R_SET0_C_Field_Array is array (0 .. 3) + of ISI_ISI_Y2R_SET0_C_Element + with Component_Size => 8, Size => 32; + + -- ISI Color Space Conversion YCrCb To RGB Set 0 Register + type ISI_ISI_Y2R_SET0_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- C as a value + Val : HAL.UInt32; + when True => + -- C as an array + Arr : ISI_ISI_Y2R_SET0_C_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, + Bit_Order => System.Low_Order_First; + + for ISI_ISI_Y2R_SET0_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + subtype ISI_ISI_Y2R_SET1_C4_Field is HAL.UInt9; + + -- ISI Color Space Conversion YCrCb To RGB Set 1 Register + type ISI_ISI_Y2R_SET1_Register is record + -- Color Space Conversion Matrix Coefficient C4 + C4 : ISI_ISI_Y2R_SET1_C4_Field := 16#0#; + -- unspecified + Reserved_9_11 : HAL.UInt3 := 16#0#; + -- Color Space Conversion Luminance Default Offset + Yoff : Boolean := False; + -- Color Space Conversion Red Chrominance Default Offset + Croff : Boolean := False; + -- Color Space Conversion Blue Chrominance Default Offset + Cboff : Boolean := False; + -- unspecified + Reserved_15_31 : HAL.UInt17 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for ISI_ISI_Y2R_SET1_Register use record + C4 at 0 range 0 .. 8; + Reserved_9_11 at 0 range 9 .. 11; + Yoff at 0 range 12 .. 12; + Croff at 0 range 13 .. 13; + Cboff at 0 range 14 .. 14; + Reserved_15_31 at 0 range 15 .. 31; + end record; + + subtype ISI_ISI_R2Y_SET0_C0_Field is HAL.UInt7; + subtype ISI_ISI_R2Y_SET0_C1_Field is HAL.UInt7; + subtype ISI_ISI_R2Y_SET0_C2_Field is HAL.UInt7; + + -- ISI Color Space Conversion RGB To YCrCb Set 0 Register + type ISI_ISI_R2Y_SET0_Register is record + -- Color Space Conversion Matrix Coefficient C0 + C0 : ISI_ISI_R2Y_SET0_C0_Field := 16#0#; + -- unspecified + Reserved_7_7 : HAL.Bit := 16#0#; + -- Color Space Conversion Matrix Coefficient C1 + C1 : ISI_ISI_R2Y_SET0_C1_Field := 16#0#; + -- unspecified + Reserved_15_15 : HAL.Bit := 16#0#; + -- Color Space Conversion Matrix Coefficient C2 + C2 : ISI_ISI_R2Y_SET0_C2_Field := 16#0#; + -- unspecified + Reserved_23_23 : HAL.Bit := 16#0#; + -- Color Space Conversion Red Component Offset + Roff : Boolean := False; + -- unspecified + Reserved_25_31 : HAL.UInt7 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for ISI_ISI_R2Y_SET0_Register use record + C0 at 0 range 0 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + C1 at 0 range 8 .. 14; + Reserved_15_15 at 0 range 15 .. 15; + C2 at 0 range 16 .. 22; + Reserved_23_23 at 0 range 23 .. 23; + Roff at 0 range 24 .. 24; + Reserved_25_31 at 0 range 25 .. 31; + end record; + + subtype ISI_ISI_R2Y_SET1_C3_Field is HAL.UInt7; + subtype ISI_ISI_R2Y_SET1_C4_Field is HAL.UInt7; + subtype ISI_ISI_R2Y_SET1_C5_Field is HAL.UInt7; + + -- ISI Color Space Conversion RGB To YCrCb Set 1 Register + type ISI_ISI_R2Y_SET1_Register is record + -- Color Space Conversion Matrix Coefficient C3 + C3 : ISI_ISI_R2Y_SET1_C3_Field := 16#0#; + -- unspecified + Reserved_7_7 : HAL.Bit := 16#0#; + -- Color Space Conversion Matrix Coefficient C4 + C4 : ISI_ISI_R2Y_SET1_C4_Field := 16#0#; + -- unspecified + Reserved_15_15 : HAL.Bit := 16#0#; + -- Color Space Conversion Matrix Coefficient C5 + C5 : ISI_ISI_R2Y_SET1_C5_Field := 16#0#; + -- unspecified + Reserved_23_23 : HAL.Bit := 16#0#; + -- Color Space Conversion Green Component Offset + Goff : Boolean := False; + -- unspecified + Reserved_25_31 : HAL.UInt7 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for ISI_ISI_R2Y_SET1_Register use record + C3 at 0 range 0 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + C4 at 0 range 8 .. 14; + Reserved_15_15 at 0 range 15 .. 15; + C5 at 0 range 16 .. 22; + Reserved_23_23 at 0 range 23 .. 23; + Goff at 0 range 24 .. 24; + Reserved_25_31 at 0 range 25 .. 31; + end record; + + subtype ISI_ISI_R2Y_SET2_C6_Field is HAL.UInt7; + subtype ISI_ISI_R2Y_SET2_C7_Field is HAL.UInt7; + subtype ISI_ISI_R2Y_SET2_C8_Field is HAL.UInt7; + + -- ISI Color Space Conversion RGB To YCrCb Set 2 Register + type ISI_ISI_R2Y_SET2_Register is record + -- Color Space Conversion Matrix Coefficient C6 + C6 : ISI_ISI_R2Y_SET2_C6_Field := 16#0#; + -- unspecified + Reserved_7_7 : HAL.Bit := 16#0#; + -- Color Space Conversion Matrix Coefficient C7 + C7 : ISI_ISI_R2Y_SET2_C7_Field := 16#0#; + -- unspecified + Reserved_15_15 : HAL.Bit := 16#0#; + -- Color Space Conversion Matrix Coefficient C8 + C8 : ISI_ISI_R2Y_SET2_C8_Field := 16#0#; + -- unspecified + Reserved_23_23 : HAL.Bit := 16#0#; + -- Color Space Conversion Blue Component Offset + Boff : Boolean := False; + -- unspecified + Reserved_25_31 : HAL.UInt7 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for ISI_ISI_R2Y_SET2_Register use record + C6 at 0 range 0 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + C7 at 0 range 8 .. 14; + Reserved_15_15 at 0 range 15 .. 15; + C8 at 0 range 16 .. 22; + Reserved_23_23 at 0 range 23 .. 23; + Boff at 0 range 24 .. 24; + Reserved_25_31 at 0 range 25 .. 31; + end record; + + -- ISI Control Register + type ISI_ISI_CR_Register is record + -- Write-only. ISI Module Enable Request + ISI_EN : Boolean := False; + -- Write-only. ISI Module Disable Request + ISI_DIS : Boolean := False; + -- Write-only. ISI Software Reset Request + ISI_SRST : Boolean := False; + -- unspecified + Reserved_3_7 : HAL.UInt5 := 16#0#; + -- Write-only. ISI Codec Request + ISI_CDC : Boolean := False; + -- unspecified + Reserved_9_31 : HAL.UInt23 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for ISI_ISI_CR_Register use record + ISI_EN at 0 range 0 .. 0; + ISI_DIS at 0 range 1 .. 1; + ISI_SRST at 0 range 2 .. 2; + Reserved_3_7 at 0 range 3 .. 7; + ISI_CDC at 0 range 8 .. 8; + Reserved_9_31 at 0 range 9 .. 31; + end record; + + -- ISI Status Register + type ISI_ISI_SR_Register is record + -- Read-only. Module Enable + ENABLE : Boolean; + -- Read-only. Module Disable Request has Terminated (cleared on read) + DIS_DONE : Boolean; + -- Read-only. Module Software Reset Request has Terminated (cleared on + -- read) + SRST : Boolean; + -- unspecified + Reserved_3_7 : HAL.UInt5; + -- Read-only. Pending Codec Request + CDC_PND : Boolean; + -- unspecified + Reserved_9_9 : HAL.Bit; + -- Read-only. Vertical Synchronization (cleared on read) + VSYNC : Boolean; + -- unspecified + Reserved_11_15 : HAL.UInt5; + -- Read-only. Preview DMA Transfer has Terminated (cleared on read) + PXFR_DONE : Boolean; + -- Read-only. Codec DMA Transfer has Terminated (cleared on read) + CXFR_DONE : Boolean; + -- unspecified + Reserved_18_18 : HAL.Bit; + -- Read-only. Synchronization in Progress + SIP : Boolean; + -- unspecified + Reserved_20_23 : HAL.UInt4; + -- Read-only. Preview Datapath Overflow (cleared on read) + P_OVR : Boolean; + -- Read-only. Codec Datapath Overflow (cleared on read) + C_OVR : Boolean; + -- Read-only. CRC Synchronization Error (cleared on read) + CRC_ERR : Boolean; + -- Read-only. Frame Rate Overrun (cleared on read) + FR_OVR : Boolean; + -- unspecified + Reserved_28_31 : HAL.UInt4; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for ISI_ISI_SR_Register use record + ENABLE at 0 range 0 .. 0; + DIS_DONE at 0 range 1 .. 1; + SRST at 0 range 2 .. 2; + Reserved_3_7 at 0 range 3 .. 7; + CDC_PND at 0 range 8 .. 8; + Reserved_9_9 at 0 range 9 .. 9; + VSYNC at 0 range 10 .. 10; + Reserved_11_15 at 0 range 11 .. 15; + PXFR_DONE at 0 range 16 .. 16; + CXFR_DONE at 0 range 17 .. 17; + Reserved_18_18 at 0 range 18 .. 18; + SIP at 0 range 19 .. 19; + Reserved_20_23 at 0 range 20 .. 23; + P_OVR at 0 range 24 .. 24; + C_OVR at 0 range 25 .. 25; + CRC_ERR at 0 range 26 .. 26; + FR_OVR at 0 range 27 .. 27; + Reserved_28_31 at 0 range 28 .. 31; + end record; + + -- ISI Interrupt Enable Register + type ISI_ISI_IER_Register is record + -- unspecified + Reserved_0_0 : HAL.Bit := 16#0#; + -- Write-only. Disable Done Interrupt Enable + DIS_DONE : Boolean := False; + -- Write-only. Software Reset Interrupt Enable + SRST : Boolean := False; + -- unspecified + Reserved_3_9 : HAL.UInt7 := 16#0#; + -- Write-only. Vertical Synchronization Interrupt Enable + VSYNC : Boolean := False; + -- unspecified + Reserved_11_15 : HAL.UInt5 := 16#0#; + -- Write-only. Preview DMA Transfer Done Interrupt Enable + PXFR_DONE : Boolean := False; + -- Write-only. Codec DMA Transfer Done Interrupt Enable + CXFR_DONE : Boolean := False; + -- unspecified + Reserved_18_23 : HAL.UInt6 := 16#0#; + -- Write-only. Preview Datapath Overflow Interrupt Enable + P_OVR : Boolean := False; + -- Write-only. Codec Datapath Overflow Interrupt Enable + C_OVR : Boolean := False; + -- Write-only. Embedded Synchronization CRC Error Interrupt Enable + CRC_ERR : Boolean := False; + -- Write-only. Frame Rate Overflow Interrupt Enable + FR_OVR : Boolean := False; + -- unspecified + Reserved_28_31 : HAL.UInt4 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for ISI_ISI_IER_Register use record + Reserved_0_0 at 0 range 0 .. 0; + DIS_DONE at 0 range 1 .. 1; + SRST at 0 range 2 .. 2; + Reserved_3_9 at 0 range 3 .. 9; + VSYNC at 0 range 10 .. 10; + Reserved_11_15 at 0 range 11 .. 15; + PXFR_DONE at 0 range 16 .. 16; + CXFR_DONE at 0 range 17 .. 17; + Reserved_18_23 at 0 range 18 .. 23; + P_OVR at 0 range 24 .. 24; + C_OVR at 0 range 25 .. 25; + CRC_ERR at 0 range 26 .. 26; + FR_OVR at 0 range 27 .. 27; + Reserved_28_31 at 0 range 28 .. 31; + end record; + + -- ISI Interrupt Disable Register + type ISI_ISI_IDR_Register is record + -- unspecified + Reserved_0_0 : HAL.Bit := 16#0#; + -- Write-only. Disable Done Interrupt Disable + DIS_DONE : Boolean := False; + -- Write-only. Software Reset Interrupt Disable + SRST : Boolean := False; + -- unspecified + Reserved_3_9 : HAL.UInt7 := 16#0#; + -- Write-only. Vertical Synchronization Interrupt Disable + VSYNC : Boolean := False; + -- unspecified + Reserved_11_15 : HAL.UInt5 := 16#0#; + -- Write-only. Preview DMA Transfer Done Interrupt Disable + PXFR_DONE : Boolean := False; + -- Write-only. Codec DMA Transfer Done Interrupt Disable + CXFR_DONE : Boolean := False; + -- unspecified + Reserved_18_23 : HAL.UInt6 := 16#0#; + -- Write-only. Preview Datapath Overflow Interrupt Disable + P_OVR : Boolean := False; + -- Write-only. Codec Datapath Overflow Interrupt Disable + C_OVR : Boolean := False; + -- Write-only. Embedded Synchronization CRC Error Interrupt Disable + CRC_ERR : Boolean := False; + -- Write-only. Frame Rate Overflow Interrupt Disable + FR_OVR : Boolean := False; + -- unspecified + Reserved_28_31 : HAL.UInt4 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for ISI_ISI_IDR_Register use record + Reserved_0_0 at 0 range 0 .. 0; + DIS_DONE at 0 range 1 .. 1; + SRST at 0 range 2 .. 2; + Reserved_3_9 at 0 range 3 .. 9; + VSYNC at 0 range 10 .. 10; + Reserved_11_15 at 0 range 11 .. 15; + PXFR_DONE at 0 range 16 .. 16; + CXFR_DONE at 0 range 17 .. 17; + Reserved_18_23 at 0 range 18 .. 23; + P_OVR at 0 range 24 .. 24; + C_OVR at 0 range 25 .. 25; + CRC_ERR at 0 range 26 .. 26; + FR_OVR at 0 range 27 .. 27; + Reserved_28_31 at 0 range 28 .. 31; + end record; + + -- ISI Interrupt Mask Register + type ISI_ISI_IMR_Register is record + -- unspecified + Reserved_0_0 : HAL.Bit; + -- Read-only. Module Disable Operation Completed + DIS_DONE : Boolean; + -- Read-only. Software Reset Completed + SRST : Boolean; + -- unspecified + Reserved_3_9 : HAL.UInt7; + -- Read-only. Vertical Synchronization + VSYNC : Boolean; + -- unspecified + Reserved_11_15 : HAL.UInt5; + -- Read-only. Preview DMA Transfer Completed + PXFR_DONE : Boolean; + -- Read-only. Codec DMA Transfer Completed + CXFR_DONE : Boolean; + -- unspecified + Reserved_18_23 : HAL.UInt6; + -- Read-only. Preview FIFO Overflow + P_OVR : Boolean; + -- Read-only. Codec FIFO Overflow + C_OVR : Boolean; + -- Read-only. CRC Synchronization Error + CRC_ERR : Boolean; + -- Read-only. Frame Rate Overrun + FR_OVR : Boolean; + -- unspecified + Reserved_28_31 : HAL.UInt4; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for ISI_ISI_IMR_Register use record + Reserved_0_0 at 0 range 0 .. 0; + DIS_DONE at 0 range 1 .. 1; + SRST at 0 range 2 .. 2; + Reserved_3_9 at 0 range 3 .. 9; + VSYNC at 0 range 10 .. 10; + Reserved_11_15 at 0 range 11 .. 15; + PXFR_DONE at 0 range 16 .. 16; + CXFR_DONE at 0 range 17 .. 17; + Reserved_18_23 at 0 range 18 .. 23; + P_OVR at 0 range 24 .. 24; + C_OVR at 0 range 25 .. 25; + CRC_ERR at 0 range 26 .. 26; + FR_OVR at 0 range 27 .. 27; + Reserved_28_31 at 0 range 28 .. 31; + end record; + + -- DMA Channel Enable Register + type ISI_ISI_DMA_CHER_Register is record + -- Write-only. Preview Channel Enable + P_CH_EN : Boolean := False; + -- Write-only. Codec Channel Enable + C_CH_EN : Boolean := False; + -- unspecified + Reserved_2_31 : HAL.UInt30 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for ISI_ISI_DMA_CHER_Register use record + P_CH_EN at 0 range 0 .. 0; + C_CH_EN at 0 range 1 .. 1; + Reserved_2_31 at 0 range 2 .. 31; + end record; + + -- DMA Channel Disable Register + type ISI_ISI_DMA_CHDR_Register is record + -- Write-only. Preview Channel Disable Request + P_CH_DIS : Boolean := False; + -- Write-only. Codec Channel Disable Request + C_CH_DIS : Boolean := False; + -- unspecified + Reserved_2_31 : HAL.UInt30 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for ISI_ISI_DMA_CHDR_Register use record + P_CH_DIS at 0 range 0 .. 0; + C_CH_DIS at 0 range 1 .. 1; + Reserved_2_31 at 0 range 2 .. 31; + end record; + + -- DMA Channel Status Register + type ISI_ISI_DMA_CHSR_Register is record + -- Read-only. Preview DMA Channel Status + P_CH_S : Boolean; + -- Read-only. Code DMA Channel Status + C_CH_S : Boolean; + -- unspecified + Reserved_2_31 : HAL.UInt30; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for ISI_ISI_DMA_CHSR_Register use record + P_CH_S at 0 range 0 .. 0; + C_CH_S at 0 range 1 .. 1; + Reserved_2_31 at 0 range 2 .. 31; + end record; + + subtype ISI_ISI_DMA_P_ADDR_P_ADDR_Field is HAL.UInt30; + + -- DMA Preview Base Address Register + type ISI_ISI_DMA_P_ADDR_Register is record + -- unspecified + Reserved_0_1 : HAL.UInt2 := 16#0#; + -- Preview Image Base Address + P_ADDR : ISI_ISI_DMA_P_ADDR_P_ADDR_Field := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for ISI_ISI_DMA_P_ADDR_Register use record + Reserved_0_1 at 0 range 0 .. 1; + P_ADDR at 0 range 2 .. 31; + end record; + + -- DMA Preview Control Register + type ISI_ISI_DMA_P_CTRL_Register is record + -- Descriptor Fetch Control Bit + P_FETCH : Boolean := False; + -- Descriptor Writeback Control Bit + P_WB : Boolean := False; + -- Transfer Done Flag Control + P_IEN : Boolean := False; + -- Preview Transfer Done + P_DONE : Boolean := False; + -- unspecified + Reserved_4_31 : HAL.UInt28 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for ISI_ISI_DMA_P_CTRL_Register use record + P_FETCH at 0 range 0 .. 0; + P_WB at 0 range 1 .. 1; + P_IEN at 0 range 2 .. 2; + P_DONE at 0 range 3 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + subtype ISI_ISI_DMA_P_DSCR_P_DSCR_Field is HAL.UInt30; + + -- DMA Preview Descriptor Address Register + type ISI_ISI_DMA_P_DSCR_Register is record + -- unspecified + Reserved_0_1 : HAL.UInt2 := 16#0#; + -- Preview Descriptor Base Address + P_DSCR : ISI_ISI_DMA_P_DSCR_P_DSCR_Field := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for ISI_ISI_DMA_P_DSCR_Register use record + Reserved_0_1 at 0 range 0 .. 1; + P_DSCR at 0 range 2 .. 31; + end record; + + subtype ISI_ISI_DMA_C_ADDR_C_ADDR_Field is HAL.UInt30; + + -- DMA Codec Base Address Register + type ISI_ISI_DMA_C_ADDR_Register is record + -- unspecified + Reserved_0_1 : HAL.UInt2 := 16#0#; + -- Codec Image Base Address + C_ADDR : ISI_ISI_DMA_C_ADDR_C_ADDR_Field := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for ISI_ISI_DMA_C_ADDR_Register use record + Reserved_0_1 at 0 range 0 .. 1; + C_ADDR at 0 range 2 .. 31; + end record; + + -- DMA Codec Control Register + type ISI_ISI_DMA_C_CTRL_Register is record + -- Descriptor Fetch Control Bit + C_FETCH : Boolean := False; + -- Descriptor Writeback Control Bit + C_WB : Boolean := False; + -- Transfer Done Flag Control + C_IEN : Boolean := False; + -- Codec Transfer Done + C_DONE : Boolean := False; + -- unspecified + Reserved_4_31 : HAL.UInt28 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for ISI_ISI_DMA_C_CTRL_Register use record + C_FETCH at 0 range 0 .. 0; + C_WB at 0 range 1 .. 1; + C_IEN at 0 range 2 .. 2; + C_DONE at 0 range 3 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + subtype ISI_ISI_DMA_C_DSCR_C_DSCR_Field is HAL.UInt30; + + -- DMA Codec Descriptor Address Register + type ISI_ISI_DMA_C_DSCR_Register is record + -- unspecified + Reserved_0_1 : HAL.UInt2 := 16#0#; + -- Codec Descriptor Base Address + C_DSCR : ISI_ISI_DMA_C_DSCR_C_DSCR_Field := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for ISI_ISI_DMA_C_DSCR_Register use record + Reserved_0_1 at 0 range 0 .. 1; + C_DSCR at 0 range 2 .. 31; + end record; + + -- Write Protection Key Password + type ISI_WPMR_WPKEY_Field is + ( + -- Reset value for the field + Isi_Wpmr_Wpkey_Field_Reset, + -- Writing any other value in this field aborts the write operation of + -- the WPEN bit.Always reads as 0. + Passwd) + with Size => 24; + for ISI_WPMR_WPKEY_Field use + (Isi_Wpmr_Wpkey_Field_Reset => 0, + Passwd => 4805449); + + -- Write Protection Mode Register + type ISI_ISI_WPMR_Register is record + -- Write Protection Enable + WPEN : Boolean := False; + -- unspecified + Reserved_1_7 : HAL.UInt7 := 16#0#; + -- Write Protection Key Password + WPKEY : ISI_WPMR_WPKEY_Field := Isi_Wpmr_Wpkey_Field_Reset; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for ISI_ISI_WPMR_Register use record + WPEN at 0 range 0 .. 0; + Reserved_1_7 at 0 range 1 .. 7; + WPKEY at 0 range 8 .. 31; + end record; + + subtype ISI_ISI_WPSR_WPVSRC_Field is HAL.UInt16; + + -- Write Protection Status Register + type ISI_ISI_WPSR_Register is record + -- Read-only. Write Protection Violation Status + WPVS : Boolean; + -- unspecified + Reserved_1_7 : HAL.UInt7; + -- Read-only. Write Protection Violation Source + WPVSRC : ISI_ISI_WPSR_WPVSRC_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for ISI_ISI_WPSR_Register use record + WPVS at 0 range 0 .. 0; + Reserved_1_7 at 0 range 1 .. 7; + WPVSRC at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype ISI_ISI_VERSION_VERSION_Field is HAL.UInt12; + subtype ISI_ISI_VERSION_MFN_Field is HAL.UInt3; + + -- Version Register + type ISI_ISI_VERSION_Register is record + -- Read-only. Version of the Hardware Module + VERSION : ISI_ISI_VERSION_VERSION_Field; + -- unspecified + Reserved_12_15 : HAL.UInt4; + -- Read-only. Metal Fix Number + MFN : ISI_ISI_VERSION_MFN_Field; + -- unspecified + Reserved_19_31 : HAL.UInt13; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for ISI_ISI_VERSION_Register use record + VERSION at 0 range 0 .. 11; + Reserved_12_15 at 0 range 12 .. 15; + MFN at 0 range 16 .. 18; + Reserved_19_31 at 0 range 19 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- Image Sensor Interface + type ISI_Peripheral is record + -- ISI Configuration 1 Register + ISI_CFG1 : aliased ISI_ISI_CFG1_Register; + -- ISI Configuration 2 Register + ISI_CFG2 : aliased ISI_ISI_CFG2_Register; + -- ISI Preview Size Register + ISI_PSIZE : aliased ISI_ISI_PSIZE_Register; + -- ISI Preview Decimation Factor Register + ISI_PDECF : aliased ISI_ISI_PDECF_Register; + -- ISI Color Space Conversion YCrCb To RGB Set 0 Register + ISI_Y2R_SET0 : aliased ISI_ISI_Y2R_SET0_Register; + -- ISI Color Space Conversion YCrCb To RGB Set 1 Register + ISI_Y2R_SET1 : aliased ISI_ISI_Y2R_SET1_Register; + -- ISI Color Space Conversion RGB To YCrCb Set 0 Register + ISI_R2Y_SET0 : aliased ISI_ISI_R2Y_SET0_Register; + -- ISI Color Space Conversion RGB To YCrCb Set 1 Register + ISI_R2Y_SET1 : aliased ISI_ISI_R2Y_SET1_Register; + -- ISI Color Space Conversion RGB To YCrCb Set 2 Register + ISI_R2Y_SET2 : aliased ISI_ISI_R2Y_SET2_Register; + -- ISI Control Register + ISI_CR : aliased ISI_ISI_CR_Register; + -- ISI Status Register + ISI_SR : aliased ISI_ISI_SR_Register; + -- ISI Interrupt Enable Register + ISI_IER : aliased ISI_ISI_IER_Register; + -- ISI Interrupt Disable Register + ISI_IDR : aliased ISI_ISI_IDR_Register; + -- ISI Interrupt Mask Register + ISI_IMR : aliased ISI_ISI_IMR_Register; + -- DMA Channel Enable Register + ISI_DMA_CHER : aliased ISI_ISI_DMA_CHER_Register; + -- DMA Channel Disable Register + ISI_DMA_CHDR : aliased ISI_ISI_DMA_CHDR_Register; + -- DMA Channel Status Register + ISI_DMA_CHSR : aliased ISI_ISI_DMA_CHSR_Register; + -- DMA Preview Base Address Register + ISI_DMA_P_ADDR : aliased ISI_ISI_DMA_P_ADDR_Register; + -- DMA Preview Control Register + ISI_DMA_P_CTRL : aliased ISI_ISI_DMA_P_CTRL_Register; + -- DMA Preview Descriptor Address Register + ISI_DMA_P_DSCR : aliased ISI_ISI_DMA_P_DSCR_Register; + -- DMA Codec Base Address Register + ISI_DMA_C_ADDR : aliased ISI_ISI_DMA_C_ADDR_Register; + -- DMA Codec Control Register + ISI_DMA_C_CTRL : aliased ISI_ISI_DMA_C_CTRL_Register; + -- DMA Codec Descriptor Address Register + ISI_DMA_C_DSCR : aliased ISI_ISI_DMA_C_DSCR_Register; + -- Write Protection Mode Register + ISI_WPMR : aliased ISI_ISI_WPMR_Register; + -- Write Protection Status Register + ISI_WPSR : aliased ISI_ISI_WPSR_Register; + -- Version Register + ISI_VERSION : aliased ISI_ISI_VERSION_Register; + end record + with Volatile; + + for ISI_Peripheral use record + ISI_CFG1 at 16#0# range 0 .. 31; + ISI_CFG2 at 16#4# range 0 .. 31; + ISI_PSIZE at 16#8# range 0 .. 31; + ISI_PDECF at 16#C# range 0 .. 31; + ISI_Y2R_SET0 at 16#10# range 0 .. 31; + ISI_Y2R_SET1 at 16#14# range 0 .. 31; + ISI_R2Y_SET0 at 16#18# range 0 .. 31; + ISI_R2Y_SET1 at 16#1C# range 0 .. 31; + ISI_R2Y_SET2 at 16#20# range 0 .. 31; + ISI_CR at 16#24# range 0 .. 31; + ISI_SR at 16#28# range 0 .. 31; + ISI_IER at 16#2C# range 0 .. 31; + ISI_IDR at 16#30# range 0 .. 31; + ISI_IMR at 16#34# range 0 .. 31; + ISI_DMA_CHER at 16#38# range 0 .. 31; + ISI_DMA_CHDR at 16#3C# range 0 .. 31; + ISI_DMA_CHSR at 16#40# range 0 .. 31; + ISI_DMA_P_ADDR at 16#44# range 0 .. 31; + ISI_DMA_P_CTRL at 16#48# range 0 .. 31; + ISI_DMA_P_DSCR at 16#4C# range 0 .. 31; + ISI_DMA_C_ADDR at 16#50# range 0 .. 31; + ISI_DMA_C_CTRL at 16#54# range 0 .. 31; + ISI_DMA_C_DSCR at 16#58# range 0 .. 31; + ISI_WPMR at 16#E4# range 0 .. 31; + ISI_WPSR at 16#E8# range 0 .. 31; + ISI_VERSION at 16#FC# range 0 .. 31; + end record; + + -- Image Sensor Interface + ISI_Periph : aliased ISI_Peripheral + with Import, Address => System'To_Address (16#4004C000#); + +end SAM_SVD.ISI; diff --git a/arch/ARM/SAM/svd/atsamv71/sam_svd-lockbit.ads b/arch/ARM/SAM/svd/atsamv71/sam_svd-lockbit.ads new file mode 100644 index 000000000..419998102 --- /dev/null +++ b/arch/ARM/SAM/svd/atsamv71/sam_svd-lockbit.ads @@ -0,0 +1,463 @@ +-- This spec has been automatically generated from ATSAMV71Q21.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +-- with HAL; +with System; + +package SAM_SVD.LOCKBIT is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + -- Lock Bits Word 0 + type LOCKBIT_LOCKBIT_WORD0_Register is record + -- Lock Region 0 + LOCK_REGION_0 : Boolean := False; + -- Lock Region 1 + LOCK_REGION_1 : Boolean := False; + -- Lock Region 2 + LOCK_REGION_2 : Boolean := False; + -- Lock Region 3 + LOCK_REGION_3 : Boolean := False; + -- Lock Region 4 + LOCK_REGION_4 : Boolean := False; + -- Lock Region 5 + LOCK_REGION_5 : Boolean := False; + -- Lock Region 6 + LOCK_REGION_6 : Boolean := False; + -- Lock Region 7 + LOCK_REGION_7 : Boolean := False; + -- Lock Region 8 + LOCK_REGION_8 : Boolean := False; + -- Lock Region 9 + LOCK_REGION_9 : Boolean := False; + -- Lock Region 10 + LOCK_REGION_10 : Boolean := False; + -- Lock Region 11 + LOCK_REGION_11 : Boolean := False; + -- Lock Region 12 + LOCK_REGION_12 : Boolean := False; + -- Lock Region 13 + LOCK_REGION_13 : Boolean := False; + -- Lock Region 14 + LOCK_REGION_14 : Boolean := False; + -- Lock Region 15 + LOCK_REGION_15 : Boolean := False; + -- Lock Region 16 + LOCK_REGION_16 : Boolean := False; + -- Lock Region 17 + LOCK_REGION_17 : Boolean := False; + -- Lock Region 18 + LOCK_REGION_18 : Boolean := False; + -- Lock Region 19 + LOCK_REGION_19 : Boolean := False; + -- Lock Region 20 + LOCK_REGION_20 : Boolean := False; + -- Lock Region 21 + LOCK_REGION_21 : Boolean := False; + -- Lock Region 22 + LOCK_REGION_22 : Boolean := False; + -- Lock Region 23 + LOCK_REGION_23 : Boolean := False; + -- Lock Region 24 + LOCK_REGION_24 : Boolean := False; + -- Lock Region 25 + LOCK_REGION_25 : Boolean := False; + -- Lock Region 26 + LOCK_REGION_26 : Boolean := False; + -- Lock Region 27 + LOCK_REGION_27 : Boolean := False; + -- Lock Region 28 + LOCK_REGION_28 : Boolean := False; + -- Lock Region 29 + LOCK_REGION_29 : Boolean := False; + -- Lock Region 30 + LOCK_REGION_30 : Boolean := False; + -- Lock Region 31 + LOCK_REGION_31 : Boolean := False; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for LOCKBIT_LOCKBIT_WORD0_Register use record + LOCK_REGION_0 at 0 range 0 .. 0; + LOCK_REGION_1 at 0 range 1 .. 1; + LOCK_REGION_2 at 0 range 2 .. 2; + LOCK_REGION_3 at 0 range 3 .. 3; + LOCK_REGION_4 at 0 range 4 .. 4; + LOCK_REGION_5 at 0 range 5 .. 5; + LOCK_REGION_6 at 0 range 6 .. 6; + LOCK_REGION_7 at 0 range 7 .. 7; + LOCK_REGION_8 at 0 range 8 .. 8; + LOCK_REGION_9 at 0 range 9 .. 9; + LOCK_REGION_10 at 0 range 10 .. 10; + LOCK_REGION_11 at 0 range 11 .. 11; + LOCK_REGION_12 at 0 range 12 .. 12; + LOCK_REGION_13 at 0 range 13 .. 13; + LOCK_REGION_14 at 0 range 14 .. 14; + LOCK_REGION_15 at 0 range 15 .. 15; + LOCK_REGION_16 at 0 range 16 .. 16; + LOCK_REGION_17 at 0 range 17 .. 17; + LOCK_REGION_18 at 0 range 18 .. 18; + LOCK_REGION_19 at 0 range 19 .. 19; + LOCK_REGION_20 at 0 range 20 .. 20; + LOCK_REGION_21 at 0 range 21 .. 21; + LOCK_REGION_22 at 0 range 22 .. 22; + LOCK_REGION_23 at 0 range 23 .. 23; + LOCK_REGION_24 at 0 range 24 .. 24; + LOCK_REGION_25 at 0 range 25 .. 25; + LOCK_REGION_26 at 0 range 26 .. 26; + LOCK_REGION_27 at 0 range 27 .. 27; + LOCK_REGION_28 at 0 range 28 .. 28; + LOCK_REGION_29 at 0 range 29 .. 29; + LOCK_REGION_30 at 0 range 30 .. 30; + LOCK_REGION_31 at 0 range 31 .. 31; + end record; + + -- Lock Bits Word 1 + type LOCKBIT_LOCKBIT_WORD1_Register is record + -- Lock Region 32 + LOCK_REGION_32 : Boolean := False; + -- Lock Region 33 + LOCK_REGION_33 : Boolean := False; + -- Lock Region 34 + LOCK_REGION_34 : Boolean := False; + -- Lock Region 35 + LOCK_REGION_35 : Boolean := False; + -- Lock Region 36 + LOCK_REGION_36 : Boolean := False; + -- Lock Region 37 + LOCK_REGION_37 : Boolean := False; + -- Lock Region 38 + LOCK_REGION_38 : Boolean := False; + -- Lock Region 39 + LOCK_REGION_39 : Boolean := False; + -- Lock Region 40 + LOCK_REGION_40 : Boolean := False; + -- Lock Region 41 + LOCK_REGION_41 : Boolean := False; + -- Lock Region 42 + LOCK_REGION_42 : Boolean := False; + -- Lock Region 43 + LOCK_REGION_43 : Boolean := False; + -- Lock Region 44 + LOCK_REGION_44 : Boolean := False; + -- Lock Region 45 + LOCK_REGION_45 : Boolean := False; + -- Lock Region 46 + LOCK_REGION_46 : Boolean := False; + -- Lock Region 47 + LOCK_REGION_47 : Boolean := False; + -- Lock Region 48 + LOCK_REGION_48 : Boolean := False; + -- Lock Region 49 + LOCK_REGION_49 : Boolean := False; + -- Lock Region 50 + LOCK_REGION_50 : Boolean := False; + -- Lock Region 51 + LOCK_REGION_51 : Boolean := False; + -- Lock Region 52 + LOCK_REGION_52 : Boolean := False; + -- Lock Region 53 + LOCK_REGION_53 : Boolean := False; + -- Lock Region 54 + LOCK_REGION_54 : Boolean := False; + -- Lock Region 55 + LOCK_REGION_55 : Boolean := False; + -- Lock Region 56 + LOCK_REGION_56 : Boolean := False; + -- Lock Region 57 + LOCK_REGION_57 : Boolean := False; + -- Lock Region 58 + LOCK_REGION_58 : Boolean := False; + -- Lock Region 59 + LOCK_REGION_59 : Boolean := False; + -- Lock Region 60 + LOCK_REGION_60 : Boolean := False; + -- Lock Region 61 + LOCK_REGION_61 : Boolean := False; + -- Lock Region 62 + LOCK_REGION_62 : Boolean := False; + -- Lock Region 63 + LOCK_REGION_63 : Boolean := False; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for LOCKBIT_LOCKBIT_WORD1_Register use record + LOCK_REGION_32 at 0 range 0 .. 0; + LOCK_REGION_33 at 0 range 1 .. 1; + LOCK_REGION_34 at 0 range 2 .. 2; + LOCK_REGION_35 at 0 range 3 .. 3; + LOCK_REGION_36 at 0 range 4 .. 4; + LOCK_REGION_37 at 0 range 5 .. 5; + LOCK_REGION_38 at 0 range 6 .. 6; + LOCK_REGION_39 at 0 range 7 .. 7; + LOCK_REGION_40 at 0 range 8 .. 8; + LOCK_REGION_41 at 0 range 9 .. 9; + LOCK_REGION_42 at 0 range 10 .. 10; + LOCK_REGION_43 at 0 range 11 .. 11; + LOCK_REGION_44 at 0 range 12 .. 12; + LOCK_REGION_45 at 0 range 13 .. 13; + LOCK_REGION_46 at 0 range 14 .. 14; + LOCK_REGION_47 at 0 range 15 .. 15; + LOCK_REGION_48 at 0 range 16 .. 16; + LOCK_REGION_49 at 0 range 17 .. 17; + LOCK_REGION_50 at 0 range 18 .. 18; + LOCK_REGION_51 at 0 range 19 .. 19; + LOCK_REGION_52 at 0 range 20 .. 20; + LOCK_REGION_53 at 0 range 21 .. 21; + LOCK_REGION_54 at 0 range 22 .. 22; + LOCK_REGION_55 at 0 range 23 .. 23; + LOCK_REGION_56 at 0 range 24 .. 24; + LOCK_REGION_57 at 0 range 25 .. 25; + LOCK_REGION_58 at 0 range 26 .. 26; + LOCK_REGION_59 at 0 range 27 .. 27; + LOCK_REGION_60 at 0 range 28 .. 28; + LOCK_REGION_61 at 0 range 29 .. 29; + LOCK_REGION_62 at 0 range 30 .. 30; + LOCK_REGION_63 at 0 range 31 .. 31; + end record; + + -- Lock Bits Word 2 + type LOCKBIT_LOCKBIT_WORD2_Register is record + -- Lock Region 64 + LOCK_REGION_64 : Boolean := False; + -- Lock Region 65 + LOCK_REGION_65 : Boolean := False; + -- Lock Region 66 + LOCK_REGION_66 : Boolean := False; + -- Lock Region 67 + LOCK_REGION_67 : Boolean := False; + -- Lock Region 68 + LOCK_REGION_68 : Boolean := False; + -- Lock Region 69 + LOCK_REGION_69 : Boolean := False; + -- Lock Region 70 + LOCK_REGION_70 : Boolean := False; + -- Lock Region 71 + LOCK_REGION_71 : Boolean := False; + -- Lock Region 72 + LOCK_REGION_72 : Boolean := False; + -- Lock Region 73 + LOCK_REGION_73 : Boolean := False; + -- Lock Region 74 + LOCK_REGION_74 : Boolean := False; + -- Lock Region 75 + LOCK_REGION_75 : Boolean := False; + -- Lock Region 76 + LOCK_REGION_76 : Boolean := False; + -- Lock Region 77 + LOCK_REGION_77 : Boolean := False; + -- Lock Region 78 + LOCK_REGION_78 : Boolean := False; + -- Lock Region 79 + LOCK_REGION_79 : Boolean := False; + -- Lock Region 80 + LOCK_REGION_80 : Boolean := False; + -- Lock Region 81 + LOCK_REGION_81 : Boolean := False; + -- Lock Region 82 + LOCK_REGION_82 : Boolean := False; + -- Lock Region 83 + LOCK_REGION_83 : Boolean := False; + -- Lock Region 84 + LOCK_REGION_84 : Boolean := False; + -- Lock Region 85 + LOCK_REGION_85 : Boolean := False; + -- Lock Region 86 + LOCK_REGION_86 : Boolean := False; + -- Lock Region 87 + LOCK_REGION_87 : Boolean := False; + -- Lock Region 88 + LOCK_REGION_88 : Boolean := False; + -- Lock Region 89 + LOCK_REGION_89 : Boolean := False; + -- Lock Region 90 + LOCK_REGION_90 : Boolean := False; + -- Lock Region 91 + LOCK_REGION_91 : Boolean := False; + -- Lock Region 92 + LOCK_REGION_92 : Boolean := False; + -- Lock Region 93 + LOCK_REGION_93 : Boolean := False; + -- Lock Region 94 + LOCK_REGION_94 : Boolean := False; + -- Lock Region 95 + LOCK_REGION_95 : Boolean := False; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for LOCKBIT_LOCKBIT_WORD2_Register use record + LOCK_REGION_64 at 0 range 0 .. 0; + LOCK_REGION_65 at 0 range 1 .. 1; + LOCK_REGION_66 at 0 range 2 .. 2; + LOCK_REGION_67 at 0 range 3 .. 3; + LOCK_REGION_68 at 0 range 4 .. 4; + LOCK_REGION_69 at 0 range 5 .. 5; + LOCK_REGION_70 at 0 range 6 .. 6; + LOCK_REGION_71 at 0 range 7 .. 7; + LOCK_REGION_72 at 0 range 8 .. 8; + LOCK_REGION_73 at 0 range 9 .. 9; + LOCK_REGION_74 at 0 range 10 .. 10; + LOCK_REGION_75 at 0 range 11 .. 11; + LOCK_REGION_76 at 0 range 12 .. 12; + LOCK_REGION_77 at 0 range 13 .. 13; + LOCK_REGION_78 at 0 range 14 .. 14; + LOCK_REGION_79 at 0 range 15 .. 15; + LOCK_REGION_80 at 0 range 16 .. 16; + LOCK_REGION_81 at 0 range 17 .. 17; + LOCK_REGION_82 at 0 range 18 .. 18; + LOCK_REGION_83 at 0 range 19 .. 19; + LOCK_REGION_84 at 0 range 20 .. 20; + LOCK_REGION_85 at 0 range 21 .. 21; + LOCK_REGION_86 at 0 range 22 .. 22; + LOCK_REGION_87 at 0 range 23 .. 23; + LOCK_REGION_88 at 0 range 24 .. 24; + LOCK_REGION_89 at 0 range 25 .. 25; + LOCK_REGION_90 at 0 range 26 .. 26; + LOCK_REGION_91 at 0 range 27 .. 27; + LOCK_REGION_92 at 0 range 28 .. 28; + LOCK_REGION_93 at 0 range 29 .. 29; + LOCK_REGION_94 at 0 range 30 .. 30; + LOCK_REGION_95 at 0 range 31 .. 31; + end record; + + -- Lock Bits Word 3 + type LOCKBIT_LOCKBIT_WORD3_Register is record + -- Lock Region 96 + LOCK_REGION_96 : Boolean := False; + -- Lock Region 97 + LOCK_REGION_97 : Boolean := False; + -- Lock Region 98 + LOCK_REGION_98 : Boolean := False; + -- Lock Region 99 + LOCK_REGION_99 : Boolean := False; + -- Lock Region 100 + LOCK_REGION_100 : Boolean := False; + -- Lock Region 101 + LOCK_REGION_101 : Boolean := False; + -- Lock Region 102 + LOCK_REGION_102 : Boolean := False; + -- Lock Region 103 + LOCK_REGION_103 : Boolean := False; + -- Lock Region 104 + LOCK_REGION_104 : Boolean := False; + -- Lock Region 105 + LOCK_REGION_105 : Boolean := False; + -- Lock Region 106 + LOCK_REGION_106 : Boolean := False; + -- Lock Region 107 + LOCK_REGION_107 : Boolean := False; + -- Lock Region 108 + LOCK_REGION_108 : Boolean := False; + -- Lock Region 109 + LOCK_REGION_109 : Boolean := False; + -- Lock Region 110 + LOCK_REGION_110 : Boolean := False; + -- Lock Region 111 + LOCK_REGION_111 : Boolean := False; + -- Lock Region 112 + LOCK_REGION_112 : Boolean := False; + -- Lock Region 113 + LOCK_REGION_113 : Boolean := False; + -- Lock Region 114 + LOCK_REGION_114 : Boolean := False; + -- Lock Region 115 + LOCK_REGION_115 : Boolean := False; + -- Lock Region 116 + LOCK_REGION_116 : Boolean := False; + -- Lock Region 117 + LOCK_REGION_117 : Boolean := False; + -- Lock Region 118 + LOCK_REGION_118 : Boolean := False; + -- Lock Region 119 + LOCK_REGION_119 : Boolean := False; + -- Lock Region 120 + LOCK_REGION_120 : Boolean := False; + -- Lock Region 121 + LOCK_REGION_121 : Boolean := False; + -- Lock Region 122 + LOCK_REGION_122 : Boolean := False; + -- Lock Region 123 + LOCK_REGION_123 : Boolean := False; + -- Lock Region 124 + LOCK_REGION_124 : Boolean := False; + -- Lock Region 125 + LOCK_REGION_125 : Boolean := False; + -- Lock Region 126 + LOCK_REGION_126 : Boolean := False; + -- Lock Region 127 + LOCK_REGION_127 : Boolean := False; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for LOCKBIT_LOCKBIT_WORD3_Register use record + LOCK_REGION_96 at 0 range 0 .. 0; + LOCK_REGION_97 at 0 range 1 .. 1; + LOCK_REGION_98 at 0 range 2 .. 2; + LOCK_REGION_99 at 0 range 3 .. 3; + LOCK_REGION_100 at 0 range 4 .. 4; + LOCK_REGION_101 at 0 range 5 .. 5; + LOCK_REGION_102 at 0 range 6 .. 6; + LOCK_REGION_103 at 0 range 7 .. 7; + LOCK_REGION_104 at 0 range 8 .. 8; + LOCK_REGION_105 at 0 range 9 .. 9; + LOCK_REGION_106 at 0 range 10 .. 10; + LOCK_REGION_107 at 0 range 11 .. 11; + LOCK_REGION_108 at 0 range 12 .. 12; + LOCK_REGION_109 at 0 range 13 .. 13; + LOCK_REGION_110 at 0 range 14 .. 14; + LOCK_REGION_111 at 0 range 15 .. 15; + LOCK_REGION_112 at 0 range 16 .. 16; + LOCK_REGION_113 at 0 range 17 .. 17; + LOCK_REGION_114 at 0 range 18 .. 18; + LOCK_REGION_115 at 0 range 19 .. 19; + LOCK_REGION_116 at 0 range 20 .. 20; + LOCK_REGION_117 at 0 range 21 .. 21; + LOCK_REGION_118 at 0 range 22 .. 22; + LOCK_REGION_119 at 0 range 23 .. 23; + LOCK_REGION_120 at 0 range 24 .. 24; + LOCK_REGION_121 at 0 range 25 .. 25; + LOCK_REGION_122 at 0 range 26 .. 26; + LOCK_REGION_123 at 0 range 27 .. 27; + LOCK_REGION_124 at 0 range 28 .. 28; + LOCK_REGION_125 at 0 range 29 .. 29; + LOCK_REGION_126 at 0 range 30 .. 30; + LOCK_REGION_127 at 0 range 31 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + type LOCKBIT_Peripheral is record + -- Lock Bits Word 0 + LOCKBIT_WORD0 : aliased LOCKBIT_LOCKBIT_WORD0_Register; + -- Lock Bits Word 1 + LOCKBIT_WORD1 : aliased LOCKBIT_LOCKBIT_WORD1_Register; + -- Lock Bits Word 2 + LOCKBIT_WORD2 : aliased LOCKBIT_LOCKBIT_WORD2_Register; + -- Lock Bits Word 3 + LOCKBIT_WORD3 : aliased LOCKBIT_LOCKBIT_WORD3_Register; + end record + with Volatile; + + for LOCKBIT_Peripheral use record + LOCKBIT_WORD0 at 16#0# range 0 .. 31; + LOCKBIT_WORD1 at 16#4# range 0 .. 31; + LOCKBIT_WORD2 at 16#8# range 0 .. 31; + LOCKBIT_WORD3 at 16#C# range 0 .. 31; + end record; + + LOCKBIT_Periph : aliased LOCKBIT_Peripheral + with Import, Address => System'To_Address (16#0#); + +end SAM_SVD.LOCKBIT; diff --git a/arch/ARM/SAM/svd/atsamv71/sam_svd-matrix.ads b/arch/ARM/SAM/svd/atsamv71/sam_svd-matrix.ads new file mode 100644 index 000000000..84bddd6f2 --- /dev/null +++ b/arch/ARM/SAM/svd/atsamv71/sam_svd-matrix.ads @@ -0,0 +1,559 @@ +-- This spec has been automatically generated from ATSAMV71Q21.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package SAM_SVD.MATRIX is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + -- Undefined Length Burst Type + type MATRIX_MCFG_ULBT_Field is + ( + -- Unlimited Length Burst-No predicted end of burst is generated, + -- therefore INCR bursts coming from this master can only be broken if + -- the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not + -- reached, the burst is normally completed by the master, at the + -- latest, on the next AHB 1-Kbyte address boundary, allowing up to + -- 256-beat word bursts or 128-beat double-word bursts.This value should + -- not be used in the very particular case of a master capable of + -- performing back-to-back undefined length bursts on a single slave, + -- since this could indefinitely freeze the slave arbitration and thus + -- prevent another master from accessing this slave. + Unltd_Length, + -- Single Access-The undefined length burst is treated as a succession + -- of single accesses, allowing re-arbitration at each beat of the INCR + -- burst or bursts sequence. + Single_Access, + -- 4-beat Burst-The undefined length burst or bursts sequence is split + -- into 4-beat bursts or less, allowing re-arbitration every 4 beats. + Val_4Beat_Burst, + -- 8-beat Burst-The undefined length burst or bursts sequence is split + -- into 8-beat bursts or less, allowing re-arbitration every 8 beats. + Val_8Beat_Burst, + -- 16-beat Burst-The undefined length burst or bursts sequence is split + -- into 16-beat bursts or less, allowing re-arbitration every 16 beats. + Val_16Beat_Burst, + -- 32-beat Burst -The undefined length burst or bursts sequence is split + -- into 32-beat bursts or less, allowing re-arbitration every 32 beats. + Val_32Beat_Burst, + -- 64-beat Burst-The undefined length burst or bursts sequence is split + -- into 64-beat bursts or less, allowing re-arbitration every 64 beats. + Val_64Beat_Burst, + -- 128-beat Burst-The undefined length burst or bursts sequence is split + -- into 128-beat bursts or less, allowing re-arbitration every 128 + -- beats. + Val_128Beat_Burst) + with Size => 3; + for MATRIX_MCFG_ULBT_Field use + (Unltd_Length => 0, + Single_Access => 1, + Val_4Beat_Burst => 2, + Val_8Beat_Burst => 3, + Val_16Beat_Burst => 4, + Val_32Beat_Burst => 5, + Val_64Beat_Burst => 6, + Val_128Beat_Burst => 7); + + -- Master Configuration Register 0 + type MATRIX_MATRIX_MCFG_Register is record + -- Undefined Length Burst Type + ULBT : MATRIX_MCFG_ULBT_Field := SAM_SVD.MATRIX.Unltd_Length; + -- unspecified + Reserved_3_31 : HAL.UInt29 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for MATRIX_MATRIX_MCFG_Register use record + ULBT at 0 range 0 .. 2; + Reserved_3_31 at 0 range 3 .. 31; + end record; + + -- Master Configuration Register 0 + type MATRIX_MATRIX_MCFG_Registers is array (0 .. 11) + of MATRIX_MATRIX_MCFG_Register + with Volatile; + + subtype MATRIX_MATRIX_SCFG_SLOT_CYCLE_Field is HAL.UInt9; + + -- Default Master Type + type MATRIX_SCFG_DEFMSTR_TYPE_Field is + ( + -- No Default Master-At the end of the current slave access, if no other + -- master request is pending, the slave is disconnected from all + -- masters.This results in a one clock cycle latency for the first + -- access of a burst transfer or for a single access. + None, + -- Last Default Master-At the end of the current slave access, if no + -- other master request is pending, the slave stays connected to the + -- last master having accessed it.This results in not having one clock + -- cycle latency when the last master tries to access the slave again. + Last, + -- Fixed Default Master-At the end of the current slave access, if no + -- other master request is pending, the slave connects to the fixed + -- master the number that has been written in the FIXED_DEFMSTR + -- field.This results in not having one clock cycle latency when the + -- fixed master tries to access the slave again. + Fixed) + with Size => 2; + for MATRIX_SCFG_DEFMSTR_TYPE_Field use + (None => 0, + Last => 1, + Fixed => 2); + + subtype MATRIX_MATRIX_SCFG_FIXED_DEFMSTR_Field is HAL.UInt4; + + -- Slave Configuration Register 0 + type MATRIX_MATRIX_SCFG_Register is record + -- Maximum Bus Grant Duration for Masters + SLOT_CYCLE : MATRIX_MATRIX_SCFG_SLOT_CYCLE_Field := 16#0#; + -- unspecified + Reserved_9_15 : HAL.UInt7 := 16#0#; + -- Default Master Type + DEFMSTR_TYPE : MATRIX_SCFG_DEFMSTR_TYPE_Field := SAM_SVD.MATRIX.None; + -- Fixed Default Master + FIXED_DEFMSTR : MATRIX_MATRIX_SCFG_FIXED_DEFMSTR_Field := 16#0#; + -- unspecified + Reserved_22_31 : HAL.UInt10 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for MATRIX_MATRIX_SCFG_Register use record + SLOT_CYCLE at 0 range 0 .. 8; + Reserved_9_15 at 0 range 9 .. 15; + DEFMSTR_TYPE at 0 range 16 .. 17; + FIXED_DEFMSTR at 0 range 18 .. 21; + Reserved_22_31 at 0 range 22 .. 31; + end record; + + -- Slave Configuration Register 0 + type MATRIX_MATRIX_SCFG_Registers is array (0 .. 8) + of MATRIX_MATRIX_SCFG_Register + with Volatile; + + ------------------------------------------ + -- MATRIX_MATRIX_PR cluster's Registers -- + ------------------------------------------ + + subtype MATRIX_MATRIX_PRAS_MATRIX_MATRIX_PR_M0PR_Field is HAL.UInt2; + subtype MATRIX_MATRIX_PRAS_MATRIX_MATRIX_PR_M1PR_Field is HAL.UInt2; + subtype MATRIX_MATRIX_PRAS_MATRIX_MATRIX_PR_M2PR_Field is HAL.UInt2; + subtype MATRIX_MATRIX_PRAS_MATRIX_MATRIX_PR_M3PR_Field is HAL.UInt2; + subtype MATRIX_MATRIX_PRAS_MATRIX_MATRIX_PR_M4PR_Field is HAL.UInt2; + subtype MATRIX_MATRIX_PRAS_MATRIX_MATRIX_PR_M5PR_Field is HAL.UInt2; + subtype MATRIX_MATRIX_PRAS_MATRIX_MATRIX_PR_M6PR_Field is HAL.UInt2; + subtype MATRIX_MATRIX_PRAS_MATRIX_MATRIX_PR_M7PR_Field is HAL.UInt2; + + -- Priority Register A for Slave 0 + type MATRIX_MATRIX_PRAS_MATRIX_MATRIX_PR_Register is record + -- Master 0 Priority + M0PR : MATRIX_MATRIX_PRAS_MATRIX_MATRIX_PR_M0PR_Field := + 16#0#; + -- unspecified + Reserved_2_3 : HAL.UInt2 := 16#0#; + -- Master 1 Priority + M1PR : MATRIX_MATRIX_PRAS_MATRIX_MATRIX_PR_M1PR_Field := + 16#0#; + -- unspecified + Reserved_6_7 : HAL.UInt2 := 16#0#; + -- Master 2 Priority + M2PR : MATRIX_MATRIX_PRAS_MATRIX_MATRIX_PR_M2PR_Field := + 16#0#; + -- unspecified + Reserved_10_11 : HAL.UInt2 := 16#0#; + -- Master 3 Priority + M3PR : MATRIX_MATRIX_PRAS_MATRIX_MATRIX_PR_M3PR_Field := + 16#0#; + -- unspecified + Reserved_14_15 : HAL.UInt2 := 16#0#; + -- Master 4 Priority + M4PR : MATRIX_MATRIX_PRAS_MATRIX_MATRIX_PR_M4PR_Field := + 16#0#; + -- unspecified + Reserved_18_19 : HAL.UInt2 := 16#0#; + -- Master 5 Priority + M5PR : MATRIX_MATRIX_PRAS_MATRIX_MATRIX_PR_M5PR_Field := + 16#0#; + -- unspecified + Reserved_22_23 : HAL.UInt2 := 16#0#; + -- Master 6 Priority + M6PR : MATRIX_MATRIX_PRAS_MATRIX_MATRIX_PR_M6PR_Field := + 16#0#; + -- unspecified + Reserved_26_27 : HAL.UInt2 := 16#0#; + -- Master 7 Priority + M7PR : MATRIX_MATRIX_PRAS_MATRIX_MATRIX_PR_M7PR_Field := + 16#0#; + -- unspecified + Reserved_30_31 : HAL.UInt2 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for MATRIX_MATRIX_PRAS_MATRIX_MATRIX_PR_Register use record + M0PR at 0 range 0 .. 1; + Reserved_2_3 at 0 range 2 .. 3; + M1PR at 0 range 4 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + M2PR at 0 range 8 .. 9; + Reserved_10_11 at 0 range 10 .. 11; + M3PR at 0 range 12 .. 13; + Reserved_14_15 at 0 range 14 .. 15; + M4PR at 0 range 16 .. 17; + Reserved_18_19 at 0 range 18 .. 19; + M5PR at 0 range 20 .. 21; + Reserved_22_23 at 0 range 22 .. 23; + M6PR at 0 range 24 .. 25; + Reserved_26_27 at 0 range 26 .. 27; + M7PR at 0 range 28 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + subtype MATRIX_MATRIX_PRBS_MATRIX_MATRIX_PR_M8PR_Field is HAL.UInt2; + subtype MATRIX_MATRIX_PRBS_MATRIX_MATRIX_PR_M9PR_Field is HAL.UInt2; + subtype MATRIX_MATRIX_PRBS_MATRIX_MATRIX_PR_M10PR_Field is HAL.UInt2; + subtype MATRIX_MATRIX_PRBS_MATRIX_MATRIX_PR_M11PR_Field is HAL.UInt2; + + -- Priority Register B for Slave 0 + type MATRIX_MATRIX_PRBS_MATRIX_MATRIX_PR_Register is record + -- Master 8 Priority + M8PR : MATRIX_MATRIX_PRBS_MATRIX_MATRIX_PR_M8PR_Field := + 16#0#; + -- unspecified + Reserved_2_3 : HAL.UInt2 := 16#0#; + -- Master 9 Priority + M9PR : MATRIX_MATRIX_PRBS_MATRIX_MATRIX_PR_M9PR_Field := + 16#0#; + -- unspecified + Reserved_6_7 : HAL.UInt2 := 16#0#; + -- Master 10 Priority + M10PR : MATRIX_MATRIX_PRBS_MATRIX_MATRIX_PR_M10PR_Field := + 16#0#; + -- unspecified + Reserved_10_11 : HAL.UInt2 := 16#0#; + -- Master 11 Priority + M11PR : MATRIX_MATRIX_PRBS_MATRIX_MATRIX_PR_M11PR_Field := + 16#0#; + -- unspecified + Reserved_14_31 : HAL.UInt18 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for MATRIX_MATRIX_PRBS_MATRIX_MATRIX_PR_Register use record + M8PR at 0 range 0 .. 1; + Reserved_2_3 at 0 range 2 .. 3; + M9PR at 0 range 4 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + M10PR at 0 range 8 .. 9; + Reserved_10_11 at 0 range 10 .. 11; + M11PR at 0 range 12 .. 13; + Reserved_14_31 at 0 range 14 .. 31; + end record; + + -- Priority Register A for Slave 0 + type MATRIX_MATRIX_PR_Cluster is record + -- Priority Register A for Slave 0 + MATRIX_PRAS : aliased MATRIX_MATRIX_PRAS_MATRIX_MATRIX_PR_Register; + -- Priority Register B for Slave 0 + MATRIX_PRBS : aliased MATRIX_MATRIX_PRBS_MATRIX_MATRIX_PR_Register; + end record + with Volatile, Size => 64; + + for MATRIX_MATRIX_PR_Cluster use record + MATRIX_PRAS at 16#0# range 0 .. 31; + MATRIX_PRBS at 16#4# range 0 .. 31; + end record; + + -- Priority Register A for Slave 0 + type MATRIX_MATRIX_PR_Clusters is array (0 .. 8) + of MATRIX_MATRIX_PR_Cluster; + + -- MATRIX_MATRIX_MRCR_RCB array + type MATRIX_MATRIX_MRCR_RCB_Field_Array is array (0 .. 11) of Boolean + with Component_Size => 1, Size => 12; + + -- Type definition for MATRIX_MATRIX_MRCR_RCB + type MATRIX_MATRIX_MRCR_RCB_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- RCB as a value + Val : HAL.UInt12; + when True => + -- RCB as an array + Arr : MATRIX_MATRIX_MRCR_RCB_Field_Array; + end case; + end record + with Unchecked_Union, Size => 12; + + for MATRIX_MATRIX_MRCR_RCB_Field use record + Val at 0 range 0 .. 11; + Arr at 0 range 0 .. 11; + end record; + + -- Master Remap Control Register + type MATRIX_MATRIX_MRCR_Register is record + -- Remap Command Bit for Master 0 + RCB : MATRIX_MATRIX_MRCR_RCB_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_12_31 : HAL.UInt20 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for MATRIX_MATRIX_MRCR_Register use record + RCB at 0 range 0 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + subtype MATRIX_CCFG_CAN0_CAN0DMABA_Field is HAL.UInt16; + + -- CAN0 Configuration Register + type MATRIX_CCFG_CAN0_Register is record + -- unspecified + Reserved_0_15 : HAL.UInt16 := 16#0#; + -- CAN0 DMA Base Address + CAN0DMABA : MATRIX_CCFG_CAN0_CAN0DMABA_Field := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for MATRIX_CCFG_CAN0_Register use record + Reserved_0_15 at 0 range 0 .. 15; + CAN0DMABA at 0 range 16 .. 31; + end record; + + -- MATRIX_CCFG_SYSIO_SYSIO array + type MATRIX_CCFG_SYSIO_SYSIO_Field_Array is array (4 .. 7) of Boolean + with Component_Size => 1, Size => 4; + + -- Type definition for MATRIX_CCFG_SYSIO_SYSIO + type MATRIX_CCFG_SYSIO_SYSIO_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- SYSIO as a value + Val : HAL.UInt4; + when True => + -- SYSIO as an array + Arr : MATRIX_CCFG_SYSIO_SYSIO_Field_Array; + end case; + end record + with Unchecked_Union, Size => 4; + + for MATRIX_CCFG_SYSIO_SYSIO_Field use record + Val at 0 range 0 .. 3; + Arr at 0 range 0 .. 3; + end record; + + subtype MATRIX_CCFG_SYSIO_CAN1DMABA_Field is HAL.UInt16; + + -- System I/O and CAN1 Configuration Register + type MATRIX_CCFG_SYSIO_Register is record + -- unspecified + Reserved_0_3 : HAL.UInt4 := 16#0#; + -- PB4 or TDI Assignment + SYSIO : MATRIX_CCFG_SYSIO_SYSIO_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_8_11 : HAL.UInt4 := 16#0#; + -- PB12 or ERASE Assignment + SYSIO12 : Boolean := False; + -- unspecified + Reserved_13_15 : HAL.UInt3 := 16#0#; + -- CAN1 DMA Base Address + CAN1DMABA : MATRIX_CCFG_SYSIO_CAN1DMABA_Field := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for MATRIX_CCFG_SYSIO_Register use record + Reserved_0_3 at 0 range 0 .. 3; + SYSIO at 0 range 4 .. 7; + Reserved_8_11 at 0 range 8 .. 11; + SYSIO12 at 0 range 12 .. 12; + Reserved_13_15 at 0 range 13 .. 15; + CAN1DMABA at 0 range 16 .. 31; + end record; + + -- MATRIX_CCFG_SMCNFCS_SMC_NFCS array + type MATRIX_CCFG_SMCNFCS_SMC_NFCS_Field_Array is array (0 .. 3) of Boolean + with Component_Size => 1, Size => 4; + + -- Type definition for MATRIX_CCFG_SMCNFCS_SMC_NFCS + type MATRIX_CCFG_SMCNFCS_SMC_NFCS_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- SMC_NFCS as a value + Val : HAL.UInt4; + when True => + -- SMC_NFCS as an array + Arr : MATRIX_CCFG_SMCNFCS_SMC_NFCS_Field_Array; + end case; + end record + with Unchecked_Union, Size => 4; + + for MATRIX_CCFG_SMCNFCS_SMC_NFCS_Field use record + Val at 0 range 0 .. 3; + Arr at 0 range 0 .. 3; + end record; + + -- SMC NAND Flash Chip Select Configuration Register + type MATRIX_CCFG_SMCNFCS_Register is record + -- SMC NAND Flash Chip Select 0 Assignment + SMC_NFCS : MATRIX_CCFG_SMCNFCS_SMC_NFCS_Field := + (As_Array => False, Val => 16#0#); + -- SDRAM Enable + SDRAMEN : Boolean := False; + -- unspecified + Reserved_5_31 : HAL.UInt27 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for MATRIX_CCFG_SMCNFCS_Register use record + SMC_NFCS at 0 range 0 .. 3; + SDRAMEN at 0 range 4 .. 4; + Reserved_5_31 at 0 range 5 .. 31; + end record; + + -- Write Protection Key + type MATRIX_WPMR_WPKEY_Field is + ( + -- Reset value for the field + Matrix_Wpmr_Wpkey_Field_Reset, + -- Writing any other value in this field aborts the write operation of + -- the WPEN bit.Always reads as 0. + Passwd) + with Size => 24; + for MATRIX_WPMR_WPKEY_Field use + (Matrix_Wpmr_Wpkey_Field_Reset => 0, + Passwd => 5062996); + + -- Write Protection Mode Register + type MATRIX_MATRIX_WPMR_Register is record + -- Write Protection Enable + WPEN : Boolean := False; + -- unspecified + Reserved_1_7 : HAL.UInt7 := 16#0#; + -- Write Protection Key + WPKEY : MATRIX_WPMR_WPKEY_Field := Matrix_Wpmr_Wpkey_Field_Reset; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for MATRIX_MATRIX_WPMR_Register use record + WPEN at 0 range 0 .. 0; + Reserved_1_7 at 0 range 1 .. 7; + WPKEY at 0 range 8 .. 31; + end record; + + subtype MATRIX_MATRIX_WPSR_WPVSRC_Field is HAL.UInt16; + + -- Write Protection Status Register + type MATRIX_MATRIX_WPSR_Register is record + -- Read-only. Write Protection Violation Status + WPVS : Boolean; + -- unspecified + Reserved_1_7 : HAL.UInt7; + -- Read-only. Write Protection Violation Source + WPVSRC : MATRIX_MATRIX_WPSR_WPVSRC_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for MATRIX_MATRIX_WPSR_Register use record + WPVS at 0 range 0 .. 0; + Reserved_1_7 at 0 range 1 .. 7; + WPVSRC at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype MATRIX_MATRIX_VERSION_VERSION_Field is HAL.UInt12; + subtype MATRIX_MATRIX_VERSION_MFN_Field is HAL.UInt3; + + -- Version Register + type MATRIX_MATRIX_VERSION_Register is record + -- Read-only. Version of the Hardware Module + VERSION : MATRIX_MATRIX_VERSION_VERSION_Field; + -- unspecified + Reserved_12_15 : HAL.UInt4; + -- Read-only. Metal Fix Number + MFN : MATRIX_MATRIX_VERSION_MFN_Field; + -- unspecified + Reserved_19_31 : HAL.UInt13; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for MATRIX_MATRIX_VERSION_Register use record + VERSION at 0 range 0 .. 11; + Reserved_12_15 at 0 range 12 .. 15; + MFN at 0 range 16 .. 18; + Reserved_19_31 at 0 range 19 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- AHB Bus Matrix + type MATRIX_Peripheral is record + -- Master Configuration Register 0 + MATRIX_MCFG : aliased MATRIX_MATRIX_MCFG_Registers; + -- Slave Configuration Register 0 + MATRIX_SCFG : aliased MATRIX_MATRIX_SCFG_Registers; + -- Priority Register A for Slave 0 + MATRIX_MATRIX_PR : aliased MATRIX_MATRIX_PR_Clusters; + -- Master Remap Control Register + MATRIX_MRCR : aliased MATRIX_MATRIX_MRCR_Register; + -- CAN0 Configuration Register + CCFG_CAN0 : aliased MATRIX_CCFG_CAN0_Register; + -- System I/O and CAN1 Configuration Register + CCFG_SYSIO : aliased MATRIX_CCFG_SYSIO_Register; + -- SMC NAND Flash Chip Select Configuration Register + CCFG_SMCNFCS : aliased MATRIX_CCFG_SMCNFCS_Register; + -- Write Protection Mode Register + MATRIX_WPMR : aliased MATRIX_MATRIX_WPMR_Register; + -- Write Protection Status Register + MATRIX_WPSR : aliased MATRIX_MATRIX_WPSR_Register; + -- Version Register + MATRIX_VERSION : aliased MATRIX_MATRIX_VERSION_Register; + end record + with Volatile; + + for MATRIX_Peripheral use record + MATRIX_MCFG at 16#0# range 0 .. 383; + MATRIX_SCFG at 16#40# range 0 .. 287; + MATRIX_MATRIX_PR at 16#80# range 0 .. 575; + MATRIX_MRCR at 16#100# range 0 .. 31; + CCFG_CAN0 at 16#110# range 0 .. 31; + CCFG_SYSIO at 16#114# range 0 .. 31; + CCFG_SMCNFCS at 16#124# range 0 .. 31; + MATRIX_WPMR at 16#1E4# range 0 .. 31; + MATRIX_WPSR at 16#1E8# range 0 .. 31; + MATRIX_VERSION at 16#1FC# range 0 .. 31; + end record; + + -- AHB Bus Matrix + MATRIX_Periph : aliased MATRIX_Peripheral + with Import, Address => System'To_Address (16#40088000#); + +end SAM_SVD.MATRIX; diff --git a/arch/ARM/SAM/svd/atsamv71/sam_svd-mcan.ads b/arch/ARM/SAM/svd/atsamv71/sam_svd-mcan.ads new file mode 100644 index 000000000..75942c03a --- /dev/null +++ b/arch/ARM/SAM/svd/atsamv71/sam_svd-mcan.ads @@ -0,0 +1,2111 @@ +-- This spec has been automatically generated from ATSAMV71Q21.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package SAM_SVD.MCAN is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + subtype MCAN_MCAN_CREL_DAY_Field is HAL.UInt8; + subtype MCAN_MCAN_CREL_MON_Field is HAL.UInt8; + subtype MCAN_MCAN_CREL_YEAR_Field is HAL.UInt4; + subtype MCAN_MCAN_CREL_SUBSTEP_Field is HAL.UInt4; + subtype MCAN_MCAN_CREL_STEP_Field is HAL.UInt4; + subtype MCAN_MCAN_CREL_REL_Field is HAL.UInt4; + + -- Core Release Register + type MCAN_MCAN_CREL_Register is record + -- Read-only. Timestamp Day + DAY : MCAN_MCAN_CREL_DAY_Field; + -- Read-only. Timestamp Month + MON : MCAN_MCAN_CREL_MON_Field; + -- Read-only. Timestamp Year + YEAR : MCAN_MCAN_CREL_YEAR_Field; + -- Read-only. Sub-step of Core Release + SUBSTEP : MCAN_MCAN_CREL_SUBSTEP_Field; + -- Read-only. Step of Core Release + STEP : MCAN_MCAN_CREL_STEP_Field; + -- Read-only. Core Release + REL : MCAN_MCAN_CREL_REL_Field; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for MCAN_MCAN_CREL_Register use record + DAY at 0 range 0 .. 7; + MON at 0 range 8 .. 15; + YEAR at 0 range 16 .. 19; + SUBSTEP at 0 range 20 .. 23; + STEP at 0 range 24 .. 27; + REL at 0 range 28 .. 31; + end record; + + subtype MCAN_MCAN_FBTP_FSJW_Field is HAL.UInt2; + subtype MCAN_MCAN_FBTP_FTSEG2_Field is HAL.UInt3; + subtype MCAN_MCAN_FBTP_FTSEG1_Field is HAL.UInt4; + subtype MCAN_MCAN_FBTP_FBRP_Field is HAL.UInt5; + + -- Transceiver Delay Compensation + type MCAN_FBTP_TDC_Field is + ( + -- Transceiver Delay Compensation disabled. + Disabled, + -- Transceiver Delay Compensation enabled. + Enabled) + with Size => 1; + for MCAN_FBTP_TDC_Field use + (Disabled => 0, + Enabled => 1); + + subtype MCAN_MCAN_FBTP_TDCO_Field is HAL.UInt5; + + -- Fast Bit Timing and Prescaler Register + type MCAN_MCAN_FBTP_Register is record + -- Fast (Re) Synchronization Jump Width + FSJW : MCAN_MCAN_FBTP_FSJW_Field := 16#0#; + -- unspecified + Reserved_2_3 : HAL.UInt2 := 16#0#; + -- Fast Time Segment After Sample Point + FTSEG2 : MCAN_MCAN_FBTP_FTSEG2_Field := 16#0#; + -- unspecified + Reserved_7_7 : HAL.Bit := 16#0#; + -- Fast Time Segment Before Sample Point + FTSEG1 : MCAN_MCAN_FBTP_FTSEG1_Field := 16#0#; + -- unspecified + Reserved_12_15 : HAL.UInt4 := 16#0#; + -- Fast Baud Rate Prescaler + FBRP : MCAN_MCAN_FBTP_FBRP_Field := 16#0#; + -- unspecified + Reserved_21_22 : HAL.UInt2 := 16#0#; + -- Transceiver Delay Compensation + TDC : MCAN_FBTP_TDC_Field := SAM_SVD.MCAN.Disabled; + -- Transceiver Delay Compensation Offset + TDCO : MCAN_MCAN_FBTP_TDCO_Field := 16#0#; + -- unspecified + Reserved_29_31 : HAL.UInt3 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for MCAN_MCAN_FBTP_Register use record + FSJW at 0 range 0 .. 1; + Reserved_2_3 at 0 range 2 .. 3; + FTSEG2 at 0 range 4 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + FTSEG1 at 0 range 8 .. 11; + Reserved_12_15 at 0 range 12 .. 15; + FBRP at 0 range 16 .. 20; + Reserved_21_22 at 0 range 21 .. 22; + TDC at 0 range 23 .. 23; + TDCO at 0 range 24 .. 28; + Reserved_29_31 at 0 range 29 .. 31; + end record; + + -- Loop Back Mode (read/write) + type MCAN_TEST_LBCK_Field is + ( + -- Reset value. Loop Back mode is disabled. + Disabled, + -- Loop Back mode is enabled (see Section 6.1.9). + Enabled) + with Size => 1; + for MCAN_TEST_LBCK_Field use + (Disabled => 0, + Enabled => 1); + + -- Control of Transmit Pin (read/write) + type MCAN_TEST_TX_Field is + ( + -- Reset value, CANTX controlled by the CAN Core, updated at the end of + -- the CAN bit time. + Reset, + -- Sample Point can be monitored at pin CANTX. + Sample_Point_Monitoring, + -- Dominant ('0') level at pin CANTX. + Dominant, + -- Recessive ('1') at pin CANTX. + Recessive) + with Size => 2; + for MCAN_TEST_TX_Field use + (Reset => 0, + Sample_Point_Monitoring => 1, + Dominant => 2, + Recessive => 3); + + subtype MCAN_MCAN_TEST_TDCV_Field is HAL.UInt6; + + -- Test Register + type MCAN_MCAN_TEST_Register is record + -- unspecified + Reserved_0_3 : HAL.UInt4 := 16#0#; + -- Loop Back Mode (read/write) + LBCK : MCAN_TEST_LBCK_Field := SAM_SVD.MCAN.Disabled; + -- Control of Transmit Pin (read/write) + TX : MCAN_TEST_TX_Field := SAM_SVD.MCAN.Reset; + -- Receive Pin (read-only) + RX : Boolean := False; + -- Transceiver Delay Compensation Value (read-only) + TDCV : MCAN_MCAN_TEST_TDCV_Field := 16#0#; + -- unspecified + Reserved_14_31 : HAL.UInt18 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for MCAN_MCAN_TEST_Register use record + Reserved_0_3 at 0 range 0 .. 3; + LBCK at 0 range 4 .. 4; + TX at 0 range 5 .. 6; + RX at 0 range 7 .. 7; + TDCV at 0 range 8 .. 13; + Reserved_14_31 at 0 range 14 .. 31; + end record; + + subtype MCAN_MCAN_RWD_WDC_Field is HAL.UInt8; + subtype MCAN_MCAN_RWD_WDV_Field is HAL.UInt8; + + -- RAM Watchdog Register + type MCAN_MCAN_RWD_Register is record + -- Watchdog Configuration (read/write) + WDC : MCAN_MCAN_RWD_WDC_Field := 16#0#; + -- Watchdog Value (read-only) + WDV : MCAN_MCAN_RWD_WDV_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for MCAN_MCAN_RWD_Register use record + WDC at 0 range 0 .. 7; + WDV at 0 range 8 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + -- Initialization (read/write) + type MCAN_CCCR_INIT_Field is + ( + -- Normal operation. + Disabled, + -- Initialization is started. + Enabled) + with Size => 1; + for MCAN_CCCR_INIT_Field use + (Disabled => 0, + Enabled => 1); + + -- Configuration Change Enable (read/write, write protection) + type MCAN_CCCR_CCE_Field is + ( + -- The processor has no write access to the protected configuration + -- registers. + Protected_k, + -- The processor has write access to the protected configuration + -- registers (while MCAN_CCCR.INIT = '1'). + Configurable) + with Size => 1; + for MCAN_CCCR_CCE_Field use + (Protected_k => 0, + Configurable => 1); + + -- Restricted Operation Mode (read/write, write protection against '1') + type MCAN_CCCR_ASM_Field is + ( + -- Normal CAN operation. + Normal, + -- Restricted operation mode active. + Restricted) + with Size => 1; + for MCAN_CCCR_ASM_Field use + (Normal => 0, + Restricted => 1); + + -- Clock Stop Request (read/write) + type MCAN_CCCR_CSR_Field is + ( + -- No clock stop is requested. + No_Clock_Stop, + -- Clock stop requested. When clock stop is requested, first INIT and + -- then CSA will be set after all pend-ing transfer requests have been + -- completed and the CAN bus reached idle. + Clock_Stop) + with Size => 1; + for MCAN_CCCR_CSR_Field use + (No_Clock_Stop => 0, + Clock_Stop => 1); + + -- Bus Monitoring Mode (read/write, write protection against '1') + type MCAN_CCCR_MON_Field is + ( + -- Bus Monitoring mode is disabled. + Disabled, + -- Bus Monitoring mode is enabled. + Enabled) + with Size => 1; + for MCAN_CCCR_MON_Field use + (Disabled => 0, + Enabled => 1); + + -- Disable Automatic Retransmission (read/write, write protection) + type MCAN_CCCR_DAR_Field is + ( + -- Automatic retransmission of messages not transmitted successfully + -- enabled. + Auto_Retx, + -- Automatic retransmission disabled. + No_Auto_Retx) + with Size => 1; + for MCAN_CCCR_DAR_Field use + (Auto_Retx => 0, + No_Auto_Retx => 1); + + -- Test Mode Enable (read/write, write protection against '1') + type MCAN_CCCR_TEST_Field is + ( + -- Normal operation, MCAN_TEST register holds reset values. + Disabled, + -- Test mode, write access to MCAN_TEST register enabled. + Enabled) + with Size => 1; + for MCAN_CCCR_TEST_Field use + (Disabled => 0, + Enabled => 1); + + -- CAN Mode Enable (read/write, write protection) + type MCAN_CCCR_CME_Field is + ( + -- CAN operation according to ISO11898-1 enabled + Iso11898_1, + -- CAN FD operation enabled + Fd) + with Size => 2; + for MCAN_CCCR_CME_Field use + (Iso11898_1 => 0, + Fd => 1); + + -- CAN Mode Request (read/write) + type MCAN_CCCR_CMR_Field is + ( + -- No mode change + No_Change, + -- Request CAN FD operation + Fd, + -- Request CAN FD operation with bit rate switching + Fd_Bitrate_Switch, + -- Request CAN operation according ISO11898-1 + Iso11898_1) + with Size => 2; + for MCAN_CCCR_CMR_Field use + (No_Change => 0, + Fd => 1, + Fd_Bitrate_Switch => 2, + Iso11898_1 => 3); + + -- CC Control Register + type MCAN_MCAN_CCCR_Register is record + -- Initialization (read/write) + INIT : MCAN_CCCR_INIT_Field := SAM_SVD.MCAN.Disabled; + -- Configuration Change Enable (read/write, write protection) + CCE : MCAN_CCCR_CCE_Field := SAM_SVD.MCAN.Protected_k; + -- Restricted Operation Mode (read/write, write protection against '1') + ASM : MCAN_CCCR_ASM_Field := SAM_SVD.MCAN.Normal; + -- Clock Stop Acknowledge (read-only) + CSA : Boolean := False; + -- Clock Stop Request (read/write) + CSR : MCAN_CCCR_CSR_Field := SAM_SVD.MCAN.No_Clock_Stop; + -- Bus Monitoring Mode (read/write, write protection against '1') + MON : MCAN_CCCR_MON_Field := SAM_SVD.MCAN.Disabled; + -- Disable Automatic Retransmission (read/write, write protection) + DAR : MCAN_CCCR_DAR_Field := SAM_SVD.MCAN.Auto_Retx; + -- Test Mode Enable (read/write, write protection against '1') + TEST : MCAN_CCCR_TEST_Field := SAM_SVD.MCAN.Disabled; + -- CAN Mode Enable (read/write, write protection) + CME : MCAN_CCCR_CME_Field := SAM_SVD.MCAN.Iso11898_1; + -- CAN Mode Request (read/write) + CMR : MCAN_CCCR_CMR_Field := SAM_SVD.MCAN.No_Change; + -- CAN FD Operation (read-only) + FDO : Boolean := False; + -- CAN FD Bit Rate Switching (read-only) + FDBS : Boolean := False; + -- Transmit Pause (read/write, write protection) + TXP : Boolean := False; + -- unspecified + Reserved_15_31 : HAL.UInt17 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for MCAN_MCAN_CCCR_Register use record + INIT at 0 range 0 .. 0; + CCE at 0 range 1 .. 1; + ASM at 0 range 2 .. 2; + CSA at 0 range 3 .. 3; + CSR at 0 range 4 .. 4; + MON at 0 range 5 .. 5; + DAR at 0 range 6 .. 6; + TEST at 0 range 7 .. 7; + CME at 0 range 8 .. 9; + CMR at 0 range 10 .. 11; + FDO at 0 range 12 .. 12; + FDBS at 0 range 13 .. 13; + TXP at 0 range 14 .. 14; + Reserved_15_31 at 0 range 15 .. 31; + end record; + + subtype MCAN_MCAN_BTP_SJW_Field is HAL.UInt4; + subtype MCAN_MCAN_BTP_TSEG2_Field is HAL.UInt4; + subtype MCAN_MCAN_BTP_TSEG1_Field is HAL.UInt6; + subtype MCAN_MCAN_BTP_BRP_Field is HAL.UInt10; + + -- Bit Timing and Prescaler Register + type MCAN_MCAN_BTP_Register is record + -- (Re) Synchronization Jump Width + SJW : MCAN_MCAN_BTP_SJW_Field := 16#0#; + -- Time Segment After Sample Point + TSEG2 : MCAN_MCAN_BTP_TSEG2_Field := 16#0#; + -- Time Segment Before Sample Point + TSEG1 : MCAN_MCAN_BTP_TSEG1_Field := 16#0#; + -- unspecified + Reserved_14_15 : HAL.UInt2 := 16#0#; + -- Baud Rate Prescaler + BRP : MCAN_MCAN_BTP_BRP_Field := 16#0#; + -- unspecified + Reserved_26_31 : HAL.UInt6 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for MCAN_MCAN_BTP_Register use record + SJW at 0 range 0 .. 3; + TSEG2 at 0 range 4 .. 7; + TSEG1 at 0 range 8 .. 13; + Reserved_14_15 at 0 range 14 .. 15; + BRP at 0 range 16 .. 25; + Reserved_26_31 at 0 range 26 .. 31; + end record; + + -- Timestamp Select + type MCAN_TSCC_TSS_Field is + ( + -- Timestamp counter value always 0x0000 + Always_0, + -- Timestamp counter value incremented according to TCP + Tcp_Inc, + -- External timestamp counter value used + Ext_Timestamp) + with Size => 2; + for MCAN_TSCC_TSS_Field use + (Always_0 => 0, + Tcp_Inc => 1, + Ext_Timestamp => 2); + + subtype MCAN_MCAN_TSCC_TCP_Field is HAL.UInt4; + + -- Timestamp Counter Configuration Register + type MCAN_MCAN_TSCC_Register is record + -- Timestamp Select + TSS : MCAN_TSCC_TSS_Field := SAM_SVD.MCAN.Always_0; + -- unspecified + Reserved_2_15 : HAL.UInt14 := 16#0#; + -- Timestamp Counter Prescaler + TCP : MCAN_MCAN_TSCC_TCP_Field := 16#0#; + -- unspecified + Reserved_20_31 : HAL.UInt12 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for MCAN_MCAN_TSCC_Register use record + TSS at 0 range 0 .. 1; + Reserved_2_15 at 0 range 2 .. 15; + TCP at 0 range 16 .. 19; + Reserved_20_31 at 0 range 20 .. 31; + end record; + + subtype MCAN_MCAN_TSCV_TSC_Field is HAL.UInt16; + + -- Timestamp Counter Value Register + type MCAN_MCAN_TSCV_Register is record + -- Timestamp Counter (cleared on write) + TSC : MCAN_MCAN_TSCV_TSC_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for MCAN_MCAN_TSCV_Register use record + TSC at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + -- Enable Timeout Counter + type MCAN_TOCC_ETOC_Field is + ( + -- Timeout Counter disabled. + No_Timeout, + -- Timeout Counter enabled. + Tos_Controlled) + with Size => 1; + for MCAN_TOCC_ETOC_Field use + (No_Timeout => 0, + Tos_Controlled => 1); + + -- Timeout Select + type MCAN_TOCC_TOS_Field is + ( + -- Continuous operation + Continuous, + -- Timeout controlled by Tx Event FIFO + Tx_Ev_Timeout, + -- Timeout controlled by Receive FIFO 0 + Rx0_Ev_Timeout, + -- Timeout controlled by Receive FIFO 1 + Rx1_Ev_Timeout) + with Size => 2; + for MCAN_TOCC_TOS_Field use + (Continuous => 0, + Tx_Ev_Timeout => 1, + Rx0_Ev_Timeout => 2, + Rx1_Ev_Timeout => 3); + + subtype MCAN_MCAN_TOCC_TOP_Field is HAL.UInt16; + + -- Timeout Counter Configuration Register + type MCAN_MCAN_TOCC_Register is record + -- Enable Timeout Counter + ETOC : MCAN_TOCC_ETOC_Field := SAM_SVD.MCAN.No_Timeout; + -- Timeout Select + TOS : MCAN_TOCC_TOS_Field := SAM_SVD.MCAN.Continuous; + -- unspecified + Reserved_3_15 : HAL.UInt13 := 16#0#; + -- Timeout Period + TOP : MCAN_MCAN_TOCC_TOP_Field := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for MCAN_MCAN_TOCC_Register use record + ETOC at 0 range 0 .. 0; + TOS at 0 range 1 .. 2; + Reserved_3_15 at 0 range 3 .. 15; + TOP at 0 range 16 .. 31; + end record; + + subtype MCAN_MCAN_TOCV_TOC_Field is HAL.UInt16; + + -- Timeout Counter Value Register + type MCAN_MCAN_TOCV_Register is record + -- Timeout Counter (cleared on write) + TOC : MCAN_MCAN_TOCV_TOC_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for MCAN_MCAN_TOCV_Register use record + TOC at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype MCAN_MCAN_ECR_TEC_Field is HAL.UInt8; + subtype MCAN_MCAN_ECR_REC_Field is HAL.UInt7; + subtype MCAN_MCAN_ECR_CEL_Field is HAL.UInt8; + + -- Error Counter Register + type MCAN_MCAN_ECR_Register is record + -- Read-only. Transmit Error Counter + TEC : MCAN_MCAN_ECR_TEC_Field; + -- Read-only. Receive Error Counter + REC : MCAN_MCAN_ECR_REC_Field; + -- Read-only. Receive Error Passive + RP : Boolean; + -- Read-only. CAN Error Logging (cleared on read) + CEL : MCAN_MCAN_ECR_CEL_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for MCAN_MCAN_ECR_Register use record + TEC at 0 range 0 .. 7; + REC at 0 range 8 .. 14; + RP at 0 range 15 .. 15; + CEL at 0 range 16 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- Last Error Code (set to 111 on read) + type MCAN_PSR_LEC_Field is + ( + -- No error occurred since LEC has been reset by successful reception or + -- transmission. + No_Error, + -- More than 5 equal bits in a sequence have occurred in a part of a + -- received message where this is not allowed. + Stuff_Error, + -- A fixed format part of a received frame has the wrong format. + Form_Error, + -- The message transmitted by the MCAN was not acknowledged by another + -- node. + Ack_Error, + -- During the transmission of a message (with the exception of the + -- arbitration field), the device wanted to send a recessive level (bit + -- of logical value '1'), but the monitored bus value was dominant. + Bit1_Error, + -- During the transmission of a message (or acknowledge bit, or active + -- error flag, or overload flag), the device wanted to send a dominant + -- level (data or identifier bit logical value '0'), but the monitored + -- bus value was recessive. During Bus_Off recovery this status is set + -- each time a sequence of 11 recessive bits has been monitored. This + -- enables the processor to monitor the proceeding of the Bus_Off + -- recovery sequence (indicating the bus is not stuck at dominant or + -- continuously disturbed). + Bit0_Error, + -- The CRC check sum of a received message was incorrect. The CRC of an + -- incoming message does not match with the CRC calculated from the + -- received data. + Crc_Error, + -- Any read access to the Protocol Status Register re-initializes the + -- LEC to '7'. When the LEC shows the value '7', no CAN bus event was + -- detected since the last processor read access to the Protocol Status + -- Register. + No_Change) + with Size => 3; + for MCAN_PSR_LEC_Field use + (No_Error => 0, + Stuff_Error => 1, + Form_Error => 2, + Ack_Error => 3, + Bit1_Error => 4, + Bit0_Error => 5, + Crc_Error => 6, + No_Change => 7); + + -- Activity + type MCAN_PSR_ACT_Field is + ( + -- Node is synchronizing on CAN communication + Synchronizing, + -- Node is neither receiver nor transmitter + Idle, + -- Node is operating as receiver + Receiver, + -- Node is operating as transmitter + Transmitter) + with Size => 2; + for MCAN_PSR_ACT_Field use + (Synchronizing => 0, + Idle => 1, + Receiver => 2, + Transmitter => 3); + + subtype MCAN_MCAN_PSR_FLEC_Field is HAL.UInt3; + + -- Protocol Status Register + type MCAN_MCAN_PSR_Register is record + -- Read-only. Last Error Code (set to 111 on read) + LEC : MCAN_PSR_LEC_Field; + -- Read-only. Activity + ACT : MCAN_PSR_ACT_Field; + -- Read-only. Error Passive + EP : Boolean; + -- Read-only. Warning Status + EW : Boolean; + -- Read-only. Bus_Off Status + BO : Boolean; + -- Read-only. Fast Last Error Code (set to 111 on read) + FLEC : MCAN_MCAN_PSR_FLEC_Field; + -- Read-only. ESI Flag of Last Received CAN FD Message (cleared on read) + RESI : Boolean; + -- Read-only. BRS Flag of Last Received CAN FD Message (cleared on read) + RBRS : Boolean; + -- Read-only. Received a CAN FD Message (cleared on read) + REDL : Boolean; + -- unspecified + Reserved_14_31 : HAL.UInt18; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for MCAN_MCAN_PSR_Register use record + LEC at 0 range 0 .. 2; + ACT at 0 range 3 .. 4; + EP at 0 range 5 .. 5; + EW at 0 range 6 .. 6; + BO at 0 range 7 .. 7; + FLEC at 0 range 8 .. 10; + RESI at 0 range 11 .. 11; + RBRS at 0 range 12 .. 12; + REDL at 0 range 13 .. 13; + Reserved_14_31 at 0 range 14 .. 31; + end record; + + -- Interrupt Register + type MCAN_MCAN_IR_Register is record + -- Receive FIFO 0 New Message + RF0N : Boolean := False; + -- Receive FIFO 0 Watermark Reached + RF0W : Boolean := False; + -- Receive FIFO 0 Full + RF0F : Boolean := False; + -- Receive FIFO 0 Message Lost + RF0L : Boolean := False; + -- Receive FIFO 1 New Message + RF1N : Boolean := False; + -- Receive FIFO 1 Watermark Reached + RF1W : Boolean := False; + -- Receive FIFO 1 Full + RF1F : Boolean := False; + -- Receive FIFO 1 Message Lost + RF1L : Boolean := False; + -- High Priority Message + HPM : Boolean := False; + -- Transmission Completed + TC : Boolean := False; + -- Transmission Cancellation Finished + TCF : Boolean := False; + -- Tx FIFO Empty + TFE : Boolean := False; + -- Tx Event FIFO New Entry + TEFN : Boolean := False; + -- Tx Event FIFO Watermark Reached + TEFW : Boolean := False; + -- Tx Event FIFO Full + TEFF : Boolean := False; + -- Tx Event FIFO Element Lost + TEFL : Boolean := False; + -- Timestamp Wraparound + TSW : Boolean := False; + -- Message RAM Access Failure + MRAF : Boolean := False; + -- Timeout Occurred + TOO : Boolean := False; + -- Message stored to Dedicated Receive Buffer + DRX : Boolean := False; + -- Bit Error Corrected + BEC : Boolean := False; + -- Bit Error Uncorrected + BEU : Boolean := False; + -- Error Logging Overflow + ELO : Boolean := False; + -- Error Passive + EP : Boolean := False; + -- Warning Status + EW : Boolean := False; + -- Bus_Off Status + BO : Boolean := False; + -- Watchdog Interrupt + WDI : Boolean := False; + -- CRC Error + CRCE : Boolean := False; + -- Bit Error + BE : Boolean := False; + -- Acknowledge Error + ACKE : Boolean := False; + -- Format Error + FOE : Boolean := False; + -- Stuff Error + STE : Boolean := False; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for MCAN_MCAN_IR_Register use record + RF0N at 0 range 0 .. 0; + RF0W at 0 range 1 .. 1; + RF0F at 0 range 2 .. 2; + RF0L at 0 range 3 .. 3; + RF1N at 0 range 4 .. 4; + RF1W at 0 range 5 .. 5; + RF1F at 0 range 6 .. 6; + RF1L at 0 range 7 .. 7; + HPM at 0 range 8 .. 8; + TC at 0 range 9 .. 9; + TCF at 0 range 10 .. 10; + TFE at 0 range 11 .. 11; + TEFN at 0 range 12 .. 12; + TEFW at 0 range 13 .. 13; + TEFF at 0 range 14 .. 14; + TEFL at 0 range 15 .. 15; + TSW at 0 range 16 .. 16; + MRAF at 0 range 17 .. 17; + TOO at 0 range 18 .. 18; + DRX at 0 range 19 .. 19; + BEC at 0 range 20 .. 20; + BEU at 0 range 21 .. 21; + ELO at 0 range 22 .. 22; + EP at 0 range 23 .. 23; + EW at 0 range 24 .. 24; + BO at 0 range 25 .. 25; + WDI at 0 range 26 .. 26; + CRCE at 0 range 27 .. 27; + BE at 0 range 28 .. 28; + ACKE at 0 range 29 .. 29; + FOE at 0 range 30 .. 30; + STE at 0 range 31 .. 31; + end record; + + -- Interrupt Enable Register + type MCAN_MCAN_IE_Register is record + -- Receive FIFO 0 New Message Interrupt Enable + RF0NE : Boolean := False; + -- Receive FIFO 0 Watermark Reached Interrupt Enable + RF0WE : Boolean := False; + -- Receive FIFO 0 Full Interrupt Enable + RF0FE : Boolean := False; + -- Receive FIFO 0 Message Lost Interrupt Enable + RF0LE : Boolean := False; + -- Receive FIFO 1 New Message Interrupt Enable + RF1NE : Boolean := False; + -- Receive FIFO 1 Watermark Reached Interrupt Enable + RF1WE : Boolean := False; + -- Receive FIFO 1 Full Interrupt Enable + RF1FE : Boolean := False; + -- Receive FIFO 1 Message Lost Interrupt Enable + RF1LE : Boolean := False; + -- High Priority Message Interrupt Enable + HPME : Boolean := False; + -- Transmission Completed Interrupt Enable + TCE : Boolean := False; + -- Transmission Cancellation Finished Interrupt Enable + TCFE : Boolean := False; + -- Tx FIFO Empty Interrupt Enable + TFEE : Boolean := False; + -- Tx Event FIFO New Entry Interrupt Enable + TEFNE : Boolean := False; + -- Tx Event FIFO Watermark Reached Interrupt Enable + TEFWE : Boolean := False; + -- Tx Event FIFO Full Interrupt Enable + TEFFE : Boolean := False; + -- Tx Event FIFO Event Lost Interrupt Enable + TEFLE : Boolean := False; + -- Timestamp Wraparound Interrupt Enable + TSWE : Boolean := False; + -- Message RAM Access Failure Interrupt Enable + MRAFE : Boolean := False; + -- Timeout Occurred Interrupt Enable + TOOE : Boolean := False; + -- Message stored to Dedicated Receive Buffer Interrupt Enable + DRXE : Boolean := False; + -- Bit Error Corrected Interrupt Enable + BECE : Boolean := False; + -- Bit Error Uncorrected Interrupt Enable + BEUE : Boolean := False; + -- Error Logging Overflow Interrupt Enable + ELOE : Boolean := False; + -- Error Passive Interrupt Enable + EPE : Boolean := False; + -- Warning Status Interrupt Enable + EWE : Boolean := False; + -- Bus_Off Status Interrupt Enable + BOE : Boolean := False; + -- Watchdog Interrupt Enable + WDIE : Boolean := False; + -- CRC Error Interrupt Enable + CRCEE : Boolean := False; + -- Bit Error Interrupt Enable + BEE : Boolean := False; + -- Acknowledge Error Interrupt Enable + ACKEE : Boolean := False; + -- Format Error Interrupt Enable + FOEE : Boolean := False; + -- Stuff Error Interrupt Enable + STEE : Boolean := False; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for MCAN_MCAN_IE_Register use record + RF0NE at 0 range 0 .. 0; + RF0WE at 0 range 1 .. 1; + RF0FE at 0 range 2 .. 2; + RF0LE at 0 range 3 .. 3; + RF1NE at 0 range 4 .. 4; + RF1WE at 0 range 5 .. 5; + RF1FE at 0 range 6 .. 6; + RF1LE at 0 range 7 .. 7; + HPME at 0 range 8 .. 8; + TCE at 0 range 9 .. 9; + TCFE at 0 range 10 .. 10; + TFEE at 0 range 11 .. 11; + TEFNE at 0 range 12 .. 12; + TEFWE at 0 range 13 .. 13; + TEFFE at 0 range 14 .. 14; + TEFLE at 0 range 15 .. 15; + TSWE at 0 range 16 .. 16; + MRAFE at 0 range 17 .. 17; + TOOE at 0 range 18 .. 18; + DRXE at 0 range 19 .. 19; + BECE at 0 range 20 .. 20; + BEUE at 0 range 21 .. 21; + ELOE at 0 range 22 .. 22; + EPE at 0 range 23 .. 23; + EWE at 0 range 24 .. 24; + BOE at 0 range 25 .. 25; + WDIE at 0 range 26 .. 26; + CRCEE at 0 range 27 .. 27; + BEE at 0 range 28 .. 28; + ACKEE at 0 range 29 .. 29; + FOEE at 0 range 30 .. 30; + STEE at 0 range 31 .. 31; + end record; + + -- Interrupt Line Select Register + type MCAN_MCAN_ILS_Register is record + -- Receive FIFO 0 New Message Interrupt Line + RF0NL : Boolean := False; + -- Receive FIFO 0 Watermark Reached Interrupt Line + RF0WL : Boolean := False; + -- Receive FIFO 0 Full Interrupt Line + RF0FL : Boolean := False; + -- Receive FIFO 0 Message Lost Interrupt Line + RF0LL : Boolean := False; + -- Receive FIFO 1 New Message Interrupt Line + RF1NL : Boolean := False; + -- Receive FIFO 1 Watermark Reached Interrupt Line + RF1WL : Boolean := False; + -- Receive FIFO 1 Full Interrupt Line + RF1FL : Boolean := False; + -- Receive FIFO 1 Message Lost Interrupt Line + RF1LL : Boolean := False; + -- High Priority Message Interrupt Line + HPML : Boolean := False; + -- Transmission Completed Interrupt Line + TCL : Boolean := False; + -- Transmission Cancellation Finished Interrupt Line + TCFL : Boolean := False; + -- Tx FIFO Empty Interrupt Line + TFEL : Boolean := False; + -- Tx Event FIFO New Entry Interrupt Line + TEFNL : Boolean := False; + -- Tx Event FIFO Watermark Reached Interrupt Line + TEFWL : Boolean := False; + -- Tx Event FIFO Full Interrupt Line + TEFFL : Boolean := False; + -- Tx Event FIFO Event Lost Interrupt Line + TEFLL : Boolean := False; + -- Timestamp Wraparound Interrupt Line + TSWL : Boolean := False; + -- Message RAM Access Failure Interrupt Line + MRAFL : Boolean := False; + -- Timeout Occurred Interrupt Line + TOOL : Boolean := False; + -- Message stored to Dedicated Receive Buffer Interrupt Line + DRXL : Boolean := False; + -- Bit Error Corrected Interrupt Line + BECL : Boolean := False; + -- Bit Error Uncorrected Interrupt Line + BEUL : Boolean := False; + -- Error Logging Overflow Interrupt Line + ELOL : Boolean := False; + -- Error Passive Interrupt Line + EPL : Boolean := False; + -- Warning Status Interrupt Line + EWL : Boolean := False; + -- Bus_Off Status Interrupt Line + BOL : Boolean := False; + -- Watchdog Interrupt Line + WDIL : Boolean := False; + -- CRC Error Interrupt Line + CRCEL : Boolean := False; + -- Bit Error Interrupt Line + BEL : Boolean := False; + -- Acknowledge Error Interrupt Line + ACKEL : Boolean := False; + -- Format Error Interrupt Line + FOEL : Boolean := False; + -- Stuff Error Interrupt Line + STEL : Boolean := False; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for MCAN_MCAN_ILS_Register use record + RF0NL at 0 range 0 .. 0; + RF0WL at 0 range 1 .. 1; + RF0FL at 0 range 2 .. 2; + RF0LL at 0 range 3 .. 3; + RF1NL at 0 range 4 .. 4; + RF1WL at 0 range 5 .. 5; + RF1FL at 0 range 6 .. 6; + RF1LL at 0 range 7 .. 7; + HPML at 0 range 8 .. 8; + TCL at 0 range 9 .. 9; + TCFL at 0 range 10 .. 10; + TFEL at 0 range 11 .. 11; + TEFNL at 0 range 12 .. 12; + TEFWL at 0 range 13 .. 13; + TEFFL at 0 range 14 .. 14; + TEFLL at 0 range 15 .. 15; + TSWL at 0 range 16 .. 16; + MRAFL at 0 range 17 .. 17; + TOOL at 0 range 18 .. 18; + DRXL at 0 range 19 .. 19; + BECL at 0 range 20 .. 20; + BEUL at 0 range 21 .. 21; + ELOL at 0 range 22 .. 22; + EPL at 0 range 23 .. 23; + EWL at 0 range 24 .. 24; + BOL at 0 range 25 .. 25; + WDIL at 0 range 26 .. 26; + CRCEL at 0 range 27 .. 27; + BEL at 0 range 28 .. 28; + ACKEL at 0 range 29 .. 29; + FOEL at 0 range 30 .. 30; + STEL at 0 range 31 .. 31; + end record; + + -- MCAN_MCAN_ILE_EINT array + type MCAN_MCAN_ILE_EINT_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for MCAN_MCAN_ILE_EINT + type MCAN_MCAN_ILE_EINT_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- EINT as a value + Val : HAL.UInt2; + when True => + -- EINT as an array + Arr : MCAN_MCAN_ILE_EINT_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for MCAN_MCAN_ILE_EINT_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- Interrupt Line Enable Register + type MCAN_MCAN_ILE_Register is record + -- Enable Interrupt Line 0 + EINT : MCAN_MCAN_ILE_EINT_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_2_31 : HAL.UInt30 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for MCAN_MCAN_ILE_Register use record + EINT at 0 range 0 .. 1; + Reserved_2_31 at 0 range 2 .. 31; + end record; + + -- Reject Remote Frames Extended + type MCAN_GFC_RRFE_Field is + ( + -- Filter remote frames with 29-bit extended IDs. + Filter, + -- Reject all remote frames with 29-bit extended IDs. + Reject) + with Size => 1; + for MCAN_GFC_RRFE_Field use + (Filter => 0, + Reject => 1); + + -- Reject Remote Frames Standard + type MCAN_GFC_RRFS_Field is + ( + -- Filter remote frames with 11-bit standard IDs. + Filter, + -- Reject all remote frames with 11-bit standard IDs. + Reject) + with Size => 1; + for MCAN_GFC_RRFS_Field use + (Filter => 0, + Reject => 1); + + -- Accept Non-matching Frames Extended + type MCAN_GFC_ANFE_Field is + ( + -- Message stored in Receive FIFO 0 + Rx_Fifo_0, + -- Message stored in Receive FIFO 1 + Rx_Fifo_1) + with Size => 2; + for MCAN_GFC_ANFE_Field use + (Rx_Fifo_0 => 0, + Rx_Fifo_1 => 1); + + -- Accept Non-matching Frames Standard + type MCAN_GFC_ANFS_Field is + ( + -- Message stored in Receive FIFO 0 + Rx_Fifo_0, + -- Message stored in Receive FIFO 1 + Rx_Fifo_1) + with Size => 2; + for MCAN_GFC_ANFS_Field use + (Rx_Fifo_0 => 0, + Rx_Fifo_1 => 1); + + -- Global Filter Configuration Register + type MCAN_MCAN_GFC_Register is record + -- Reject Remote Frames Extended + RRFE : MCAN_GFC_RRFE_Field := SAM_SVD.MCAN.Filter; + -- Reject Remote Frames Standard + RRFS : MCAN_GFC_RRFS_Field := SAM_SVD.MCAN.Filter; + -- Accept Non-matching Frames Extended + ANFE : MCAN_GFC_ANFE_Field := SAM_SVD.MCAN.Rx_Fifo_0; + -- Accept Non-matching Frames Standard + ANFS : MCAN_GFC_ANFS_Field := SAM_SVD.MCAN.Rx_Fifo_0; + -- unspecified + Reserved_6_31 : HAL.UInt26 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for MCAN_MCAN_GFC_Register use record + RRFE at 0 range 0 .. 0; + RRFS at 0 range 1 .. 1; + ANFE at 0 range 2 .. 3; + ANFS at 0 range 4 .. 5; + Reserved_6_31 at 0 range 6 .. 31; + end record; + + subtype MCAN_MCAN_SIDFC_FLSSA_Field is HAL.UInt14; + subtype MCAN_MCAN_SIDFC_LSS_Field is HAL.UInt8; + + -- Standard ID Filter Configuration Register + type MCAN_MCAN_SIDFC_Register is record + -- unspecified + Reserved_0_1 : HAL.UInt2 := 16#0#; + -- Filter List Standard Start Address + FLSSA : MCAN_MCAN_SIDFC_FLSSA_Field := 16#0#; + -- List Size Standard + LSS : MCAN_MCAN_SIDFC_LSS_Field := 16#0#; + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for MCAN_MCAN_SIDFC_Register use record + Reserved_0_1 at 0 range 0 .. 1; + FLSSA at 0 range 2 .. 15; + LSS at 0 range 16 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype MCAN_MCAN_XIDFC_FLESA_Field is HAL.UInt14; + subtype MCAN_MCAN_XIDFC_LSE_Field is HAL.UInt7; + + -- Extended ID Filter Configuration Register + type MCAN_MCAN_XIDFC_Register is record + -- unspecified + Reserved_0_1 : HAL.UInt2 := 16#0#; + -- Filter List Extended Start Address + FLESA : MCAN_MCAN_XIDFC_FLESA_Field := 16#0#; + -- List Size Extended + LSE : MCAN_MCAN_XIDFC_LSE_Field := 16#0#; + -- unspecified + Reserved_23_31 : HAL.UInt9 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for MCAN_MCAN_XIDFC_Register use record + Reserved_0_1 at 0 range 0 .. 1; + FLESA at 0 range 2 .. 15; + LSE at 0 range 16 .. 22; + Reserved_23_31 at 0 range 23 .. 31; + end record; + + subtype MCAN_MCAN_XIDAM_EIDM_Field is HAL.UInt29; + + -- Extended ID AND Mask Register + type MCAN_MCAN_XIDAM_Register is record + -- Extended ID Mask + EIDM : MCAN_MCAN_XIDAM_EIDM_Field := 16#0#; + -- unspecified + Reserved_29_31 : HAL.UInt3 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for MCAN_MCAN_XIDAM_Register use record + EIDM at 0 range 0 .. 28; + Reserved_29_31 at 0 range 29 .. 31; + end record; + + subtype MCAN_MCAN_HPMS_BIDX_Field is HAL.UInt6; + + -- Message Storage Indicator + type MCAN_HPMS_MSI_Field is + ( + -- No FIFO selected. + No_Fifo_Sel, + -- FIFO message. + Lost, + -- Message stored in FIFO 0. + Fifo_0, + -- Message stored in FIFO 1. + Fifo_1) + with Size => 2; + for MCAN_HPMS_MSI_Field use + (No_Fifo_Sel => 0, + Lost => 1, + Fifo_0 => 2, + Fifo_1 => 3); + + subtype MCAN_MCAN_HPMS_FIDX_Field is HAL.UInt7; + + -- High Priority Message Status Register + type MCAN_MCAN_HPMS_Register is record + -- Read-only. Buffer Index + BIDX : MCAN_MCAN_HPMS_BIDX_Field; + -- Read-only. Message Storage Indicator + MSI : MCAN_HPMS_MSI_Field; + -- Read-only. Filter Index + FIDX : MCAN_MCAN_HPMS_FIDX_Field; + -- Read-only. Filter List + FLST : Boolean; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for MCAN_MCAN_HPMS_Register use record + BIDX at 0 range 0 .. 5; + MSI at 0 range 6 .. 7; + FIDX at 0 range 8 .. 14; + FLST at 0 range 15 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + -- MCAN_MCAN_NDAT1_ND array + type MCAN_MCAN_NDAT1_ND_Field_Array is array (0 .. 31) of Boolean + with Component_Size => 1, Size => 32; + + -- New Data 1 Register + type MCAN_MCAN_NDAT1_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- ND as a value + Val : HAL.UInt32; + when True => + -- ND as an array + Arr : MCAN_MCAN_NDAT1_ND_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, + Bit_Order => System.Low_Order_First; + + for MCAN_MCAN_NDAT1_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- MCAN_MCAN_NDAT2_ND array + type MCAN_MCAN_NDAT2_ND_Field_Array is array (32 .. 63) of Boolean + with Component_Size => 1, Size => 32; + + -- New Data 2 Register + type MCAN_MCAN_NDAT2_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- ND as a value + Val : HAL.UInt32; + when True => + -- ND as an array + Arr : MCAN_MCAN_NDAT2_ND_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, + Bit_Order => System.Low_Order_First; + + for MCAN_MCAN_NDAT2_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + subtype MCAN_MCAN_RXF0C_F0SA_Field is HAL.UInt14; + subtype MCAN_MCAN_RXF0C_F0S_Field is HAL.UInt7; + subtype MCAN_MCAN_RXF0C_F0WM_Field is HAL.UInt7; + + -- Receive FIFO 0 Configuration Register + type MCAN_MCAN_RXF0C_Register is record + -- unspecified + Reserved_0_1 : HAL.UInt2 := 16#0#; + -- Receive FIFO 0 Start Address + F0SA : MCAN_MCAN_RXF0C_F0SA_Field := 16#0#; + -- Receive FIFO 0 Start Address + F0S : MCAN_MCAN_RXF0C_F0S_Field := 16#0#; + -- unspecified + Reserved_23_23 : HAL.Bit := 16#0#; + -- Receive FIFO 0 Watermark + F0WM : MCAN_MCAN_RXF0C_F0WM_Field := 16#0#; + -- FIFO 0 Operation Mode + F0OM : Boolean := False; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for MCAN_MCAN_RXF0C_Register use record + Reserved_0_1 at 0 range 0 .. 1; + F0SA at 0 range 2 .. 15; + F0S at 0 range 16 .. 22; + Reserved_23_23 at 0 range 23 .. 23; + F0WM at 0 range 24 .. 30; + F0OM at 0 range 31 .. 31; + end record; + + subtype MCAN_MCAN_RXF0S_F0FL_Field is HAL.UInt7; + subtype MCAN_MCAN_RXF0S_F0GI_Field is HAL.UInt6; + subtype MCAN_MCAN_RXF0S_F0PI_Field is HAL.UInt6; + + -- Receive FIFO 0 Status Register + type MCAN_MCAN_RXF0S_Register is record + -- Read-only. Receive FIFO 0 Fill Level + F0FL : MCAN_MCAN_RXF0S_F0FL_Field; + -- unspecified + Reserved_7_7 : HAL.Bit; + -- Read-only. Receive FIFO 0 Get Index + F0GI : MCAN_MCAN_RXF0S_F0GI_Field; + -- unspecified + Reserved_14_15 : HAL.UInt2; + -- Read-only. Receive FIFO 0 Put Index + F0PI : MCAN_MCAN_RXF0S_F0PI_Field; + -- unspecified + Reserved_22_23 : HAL.UInt2; + -- Read-only. Receive FIFO 0 Fill Level + F0F : Boolean; + -- Read-only. Receive FIFO 0 Message Lost + RF0L : Boolean; + -- unspecified + Reserved_26_31 : HAL.UInt6; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for MCAN_MCAN_RXF0S_Register use record + F0FL at 0 range 0 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + F0GI at 0 range 8 .. 13; + Reserved_14_15 at 0 range 14 .. 15; + F0PI at 0 range 16 .. 21; + Reserved_22_23 at 0 range 22 .. 23; + F0F at 0 range 24 .. 24; + RF0L at 0 range 25 .. 25; + Reserved_26_31 at 0 range 26 .. 31; + end record; + + subtype MCAN_MCAN_RXF0A_F0AI_Field is HAL.UInt6; + + -- Receive FIFO 0 Acknowledge Register + type MCAN_MCAN_RXF0A_Register is record + -- Receive FIFO 0 Acknowledge Index + F0AI : MCAN_MCAN_RXF0A_F0AI_Field := 16#0#; + -- unspecified + Reserved_6_31 : HAL.UInt26 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for MCAN_MCAN_RXF0A_Register use record + F0AI at 0 range 0 .. 5; + Reserved_6_31 at 0 range 6 .. 31; + end record; + + subtype MCAN_MCAN_RXBC_RBSA_Field is HAL.UInt14; + + -- Receive Rx Buffer Configuration Register + type MCAN_MCAN_RXBC_Register is record + -- unspecified + Reserved_0_1 : HAL.UInt2 := 16#0#; + -- Receive Buffer Start Address + RBSA : MCAN_MCAN_RXBC_RBSA_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for MCAN_MCAN_RXBC_Register use record + Reserved_0_1 at 0 range 0 .. 1; + RBSA at 0 range 2 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype MCAN_MCAN_RXF1C_F1SA_Field is HAL.UInt14; + subtype MCAN_MCAN_RXF1C_F1S_Field is HAL.UInt7; + subtype MCAN_MCAN_RXF1C_F1WM_Field is HAL.UInt7; + + -- Receive FIFO 1 Configuration Register + type MCAN_MCAN_RXF1C_Register is record + -- unspecified + Reserved_0_1 : HAL.UInt2 := 16#0#; + -- Receive FIFO 1 Start Address + F1SA : MCAN_MCAN_RXF1C_F1SA_Field := 16#0#; + -- Receive FIFO 1 Start Address + F1S : MCAN_MCAN_RXF1C_F1S_Field := 16#0#; + -- unspecified + Reserved_23_23 : HAL.Bit := 16#0#; + -- Receive FIFO 1 Watermark + F1WM : MCAN_MCAN_RXF1C_F1WM_Field := 16#0#; + -- FIFO 1 Operation Mode + F1OM : Boolean := False; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for MCAN_MCAN_RXF1C_Register use record + Reserved_0_1 at 0 range 0 .. 1; + F1SA at 0 range 2 .. 15; + F1S at 0 range 16 .. 22; + Reserved_23_23 at 0 range 23 .. 23; + F1WM at 0 range 24 .. 30; + F1OM at 0 range 31 .. 31; + end record; + + subtype MCAN_MCAN_RXF1S_F1FL_Field is HAL.UInt7; + subtype MCAN_MCAN_RXF1S_F1GI_Field is HAL.UInt6; + subtype MCAN_MCAN_RXF1S_F1PI_Field is HAL.UInt6; + + -- Debug Message Status + type MCAN_RXF1S_DMS_Field is + ( + -- Idle state, wait for reception of debug messages, DMA request is + -- cleared. + Idle, + -- Debug message A received. + Msg_A, + -- Debug messages A, B received. + Msg_Ab, + -- Debug messages A, B, C received, DMA request is set. + Msg_Abc) + with Size => 2; + for MCAN_RXF1S_DMS_Field use + (Idle => 0, + Msg_A => 1, + Msg_Ab => 2, + Msg_Abc => 3); + + -- Receive FIFO 1 Status Register + type MCAN_MCAN_RXF1S_Register is record + -- Read-only. Receive FIFO 1 Fill Level + F1FL : MCAN_MCAN_RXF1S_F1FL_Field; + -- unspecified + Reserved_7_7 : HAL.Bit; + -- Read-only. Receive FIFO 1 Get Index + F1GI : MCAN_MCAN_RXF1S_F1GI_Field; + -- unspecified + Reserved_14_15 : HAL.UInt2; + -- Read-only. Receive FIFO 1 Put Index + F1PI : MCAN_MCAN_RXF1S_F1PI_Field; + -- unspecified + Reserved_22_23 : HAL.UInt2; + -- Read-only. Receive FIFO 1 Fill Level + F1F : Boolean; + -- Read-only. Receive FIFO 1 Message Lost + RF1L : Boolean; + -- unspecified + Reserved_26_29 : HAL.UInt4; + -- Read-only. Debug Message Status + DMS : MCAN_RXF1S_DMS_Field; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for MCAN_MCAN_RXF1S_Register use record + F1FL at 0 range 0 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + F1GI at 0 range 8 .. 13; + Reserved_14_15 at 0 range 14 .. 15; + F1PI at 0 range 16 .. 21; + Reserved_22_23 at 0 range 22 .. 23; + F1F at 0 range 24 .. 24; + RF1L at 0 range 25 .. 25; + Reserved_26_29 at 0 range 26 .. 29; + DMS at 0 range 30 .. 31; + end record; + + subtype MCAN_MCAN_RXF1A_F1AI_Field is HAL.UInt6; + + -- Receive FIFO 1 Acknowledge Register + type MCAN_MCAN_RXF1A_Register is record + -- Receive FIFO 1 Acknowledge Index + F1AI : MCAN_MCAN_RXF1A_F1AI_Field := 16#0#; + -- unspecified + Reserved_6_31 : HAL.UInt26 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for MCAN_MCAN_RXF1A_Register use record + F1AI at 0 range 0 .. 5; + Reserved_6_31 at 0 range 6 .. 31; + end record; + + -- Receive FIFO 0 Data Field Size + type MCAN_RXESC_F0DS_Field is + ( + -- 8-byte data field + Val_8_Byte, + -- 12-byte data field + Val_12_Byte, + -- 16-byte data field + Val_16_Byte, + -- 20-byte data field + Val_20_Byte, + -- 24-byte data field + Val_24_Byte, + -- 32-byte data field + Val_32_Byte, + -- 48-byte data field + Val_48_Byte, + -- 64-byte data field + Val_64_Byte) + with Size => 3; + for MCAN_RXESC_F0DS_Field use + (Val_8_Byte => 0, + Val_12_Byte => 1, + Val_16_Byte => 2, + Val_20_Byte => 3, + Val_24_Byte => 4, + Val_32_Byte => 5, + Val_48_Byte => 6, + Val_64_Byte => 7); + + -- Receive FIFO 1 Data Field Size + type MCAN_RXESC_F1DS_Field is + ( + -- 8-byte data field + Val_8_Byte, + -- 12-byte data field + Val_12_Byte, + -- 16-byte data field + Val_16_Byte, + -- 20-byte data field + Val_20_Byte, + -- 24-byte data field + Val_24_Byte, + -- 32-byte data field + Val_32_Byte, + -- 48-byte data field + Val_48_Byte, + -- 64-byte data field + Val_64_Byte) + with Size => 3; + for MCAN_RXESC_F1DS_Field use + (Val_8_Byte => 0, + Val_12_Byte => 1, + Val_16_Byte => 2, + Val_20_Byte => 3, + Val_24_Byte => 4, + Val_32_Byte => 5, + Val_48_Byte => 6, + Val_64_Byte => 7); + + -- Receive Buffer Data Field Size + type MCAN_RXESC_RBDS_Field is + ( + -- 8-byte data field + Val_8_Byte, + -- 12-byte data field + Val_12_Byte, + -- 16-byte data field + Val_16_Byte, + -- 20-byte data field + Val_20_Byte, + -- 24-byte data field + Val_24_Byte, + -- 32-byte data field + Val_32_Byte, + -- 48-byte data field + Val_48_Byte, + -- 64-byte data field + Val_64_Byte) + with Size => 3; + for MCAN_RXESC_RBDS_Field use + (Val_8_Byte => 0, + Val_12_Byte => 1, + Val_16_Byte => 2, + Val_20_Byte => 3, + Val_24_Byte => 4, + Val_32_Byte => 5, + Val_48_Byte => 6, + Val_64_Byte => 7); + + -- Receive Buffer / FIFO Element Size Configuration Register + type MCAN_MCAN_RXESC_Register is record + -- Receive FIFO 0 Data Field Size + F0DS : MCAN_RXESC_F0DS_Field := SAM_SVD.MCAN.Val_8_Byte; + -- unspecified + Reserved_3_3 : HAL.Bit := 16#0#; + -- Receive FIFO 1 Data Field Size + F1DS : MCAN_RXESC_F1DS_Field := SAM_SVD.MCAN.Val_8_Byte; + -- unspecified + Reserved_7_7 : HAL.Bit := 16#0#; + -- Receive Buffer Data Field Size + RBDS : MCAN_RXESC_RBDS_Field := SAM_SVD.MCAN.Val_8_Byte; + -- unspecified + Reserved_11_31 : HAL.UInt21 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for MCAN_MCAN_RXESC_Register use record + F0DS at 0 range 0 .. 2; + Reserved_3_3 at 0 range 3 .. 3; + F1DS at 0 range 4 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + RBDS at 0 range 8 .. 10; + Reserved_11_31 at 0 range 11 .. 31; + end record; + + subtype MCAN_MCAN_TXBC_TBSA_Field is HAL.UInt14; + subtype MCAN_MCAN_TXBC_NDTB_Field is HAL.UInt6; + subtype MCAN_MCAN_TXBC_TFQS_Field is HAL.UInt6; + + -- Transmit Buffer Configuration Register + type MCAN_MCAN_TXBC_Register is record + -- unspecified + Reserved_0_1 : HAL.UInt2 := 16#0#; + -- Tx Buffers Start Address + TBSA : MCAN_MCAN_TXBC_TBSA_Field := 16#0#; + -- Number of Dedicated Transmit Buffers + NDTB : MCAN_MCAN_TXBC_NDTB_Field := 16#0#; + -- unspecified + Reserved_22_23 : HAL.UInt2 := 16#0#; + -- Transmit FIFO/Queue Size + TFQS : MCAN_MCAN_TXBC_TFQS_Field := 16#0#; + -- Tx FIFO/Queue Mode + TFQM : Boolean := False; + -- unspecified + Reserved_31_31 : HAL.Bit := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for MCAN_MCAN_TXBC_Register use record + Reserved_0_1 at 0 range 0 .. 1; + TBSA at 0 range 2 .. 15; + NDTB at 0 range 16 .. 21; + Reserved_22_23 at 0 range 22 .. 23; + TFQS at 0 range 24 .. 29; + TFQM at 0 range 30 .. 30; + Reserved_31_31 at 0 range 31 .. 31; + end record; + + subtype MCAN_MCAN_TXFQS_TFFL_Field is HAL.UInt6; + subtype MCAN_MCAN_TXFQS_TFGI_Field is HAL.UInt5; + subtype MCAN_MCAN_TXFQS_TFQPI_Field is HAL.UInt5; + + -- Transmit FIFO/Queue Status Register + type MCAN_MCAN_TXFQS_Register is record + -- Read-only. Tx FIFO Free Level + TFFL : MCAN_MCAN_TXFQS_TFFL_Field; + -- unspecified + Reserved_6_7 : HAL.UInt2; + -- Read-only. Tx FIFO Get Index + TFGI : MCAN_MCAN_TXFQS_TFGI_Field; + -- unspecified + Reserved_13_15 : HAL.UInt3; + -- Read-only. Tx FIFO/Queue Put Index + TFQPI : MCAN_MCAN_TXFQS_TFQPI_Field; + -- Read-only. Tx FIFO/Queue Full + TFQF : Boolean; + -- unspecified + Reserved_22_31 : HAL.UInt10; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for MCAN_MCAN_TXFQS_Register use record + TFFL at 0 range 0 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + TFGI at 0 range 8 .. 12; + Reserved_13_15 at 0 range 13 .. 15; + TFQPI at 0 range 16 .. 20; + TFQF at 0 range 21 .. 21; + Reserved_22_31 at 0 range 22 .. 31; + end record; + + -- Tx Buffer Data Field Size + type MCAN_TXESC_TBDS_Field is + ( + -- 8-byte data field + Val_8_Byte, + -- 12-byte data field + Val_12_Byte, + -- 16-byte data field + Val_16_Byte, + -- 20-byte data field + Val_20_Byte, + -- 24-byte data field + Val_24_Byte, + -- 32-byte data field + Val_32_Byte, + -- 48- byte data field + Val_48_Byte, + -- 64-byte data field + Val_64_Byte) + with Size => 3; + for MCAN_TXESC_TBDS_Field use + (Val_8_Byte => 0, + Val_12_Byte => 1, + Val_16_Byte => 2, + Val_20_Byte => 3, + Val_24_Byte => 4, + Val_32_Byte => 5, + Val_48_Byte => 6, + Val_64_Byte => 7); + + -- Transmit Buffer Element Size Configuration Register + type MCAN_MCAN_TXESC_Register is record + -- Tx Buffer Data Field Size + TBDS : MCAN_TXESC_TBDS_Field := SAM_SVD.MCAN.Val_8_Byte; + -- unspecified + Reserved_3_31 : HAL.UInt29 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for MCAN_MCAN_TXESC_Register use record + TBDS at 0 range 0 .. 2; + Reserved_3_31 at 0 range 3 .. 31; + end record; + + -- MCAN_MCAN_TXBRP_TRP array + type MCAN_MCAN_TXBRP_TRP_Field_Array is array (0 .. 31) of Boolean + with Component_Size => 1, Size => 32; + + -- Transmit Buffer Request Pending Register + type MCAN_MCAN_TXBRP_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- TRP as a value + Val : HAL.UInt32; + when True => + -- TRP as an array + Arr : MCAN_MCAN_TXBRP_TRP_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, + Bit_Order => System.Low_Order_First; + + for MCAN_MCAN_TXBRP_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- MCAN_MCAN_TXBAR_AR array + type MCAN_MCAN_TXBAR_AR_Field_Array is array (0 .. 31) of Boolean + with Component_Size => 1, Size => 32; + + -- Transmit Buffer Add Request Register + type MCAN_MCAN_TXBAR_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- AR as a value + Val : HAL.UInt32; + when True => + -- AR as an array + Arr : MCAN_MCAN_TXBAR_AR_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, + Bit_Order => System.Low_Order_First; + + for MCAN_MCAN_TXBAR_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- MCAN_MCAN_TXBCR_CR array + type MCAN_MCAN_TXBCR_CR_Field_Array is array (0 .. 31) of Boolean + with Component_Size => 1, Size => 32; + + -- Transmit Buffer Cancellation Request Register + type MCAN_MCAN_TXBCR_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CR as a value + Val : HAL.UInt32; + when True => + -- CR as an array + Arr : MCAN_MCAN_TXBCR_CR_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, + Bit_Order => System.Low_Order_First; + + for MCAN_MCAN_TXBCR_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- MCAN_MCAN_TXBTO_TO array + type MCAN_MCAN_TXBTO_TO_Field_Array is array (0 .. 31) of Boolean + with Component_Size => 1, Size => 32; + + -- Transmit Buffer Transmission Occurred Register + type MCAN_MCAN_TXBTO_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- TO as a value + Val : HAL.UInt32; + when True => + -- TO as an array + Arr : MCAN_MCAN_TXBTO_TO_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, + Bit_Order => System.Low_Order_First; + + for MCAN_MCAN_TXBTO_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- MCAN_MCAN_TXBCF_CF array + type MCAN_MCAN_TXBCF_CF_Field_Array is array (0 .. 31) of Boolean + with Component_Size => 1, Size => 32; + + -- Transmit Buffer Cancellation Finished Register + type MCAN_MCAN_TXBCF_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CF as a value + Val : HAL.UInt32; + when True => + -- CF as an array + Arr : MCAN_MCAN_TXBCF_CF_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, + Bit_Order => System.Low_Order_First; + + for MCAN_MCAN_TXBCF_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- MCAN_MCAN_TXBTIE_TIE array + type MCAN_MCAN_TXBTIE_TIE_Field_Array is array (0 .. 31) of Boolean + with Component_Size => 1, Size => 32; + + -- Transmit Buffer Transmission Interrupt Enable Register + type MCAN_MCAN_TXBTIE_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- TIE as a value + Val : HAL.UInt32; + when True => + -- TIE as an array + Arr : MCAN_MCAN_TXBTIE_TIE_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, + Bit_Order => System.Low_Order_First; + + for MCAN_MCAN_TXBTIE_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- MCAN_MCAN_TXBCIE_CFIE array + type MCAN_MCAN_TXBCIE_CFIE_Field_Array is array (0 .. 31) of Boolean + with Component_Size => 1, Size => 32; + + -- Transmit Buffer Cancellation Finished Interrupt Enable Register + type MCAN_MCAN_TXBCIE_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CFIE as a value + Val : HAL.UInt32; + when True => + -- CFIE as an array + Arr : MCAN_MCAN_TXBCIE_CFIE_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, + Bit_Order => System.Low_Order_First; + + for MCAN_MCAN_TXBCIE_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + subtype MCAN_MCAN_TXEFC_EFSA_Field is HAL.UInt14; + subtype MCAN_MCAN_TXEFC_EFS_Field is HAL.UInt6; + subtype MCAN_MCAN_TXEFC_EFWM_Field is HAL.UInt6; + + -- Transmit Event FIFO Configuration Register + type MCAN_MCAN_TXEFC_Register is record + -- unspecified + Reserved_0_1 : HAL.UInt2 := 16#0#; + -- Event FIFO Start Address + EFSA : MCAN_MCAN_TXEFC_EFSA_Field := 16#0#; + -- Event FIFO Size + EFS : MCAN_MCAN_TXEFC_EFS_Field := 16#0#; + -- unspecified + Reserved_22_23 : HAL.UInt2 := 16#0#; + -- Event FIFO Watermark + EFWM : MCAN_MCAN_TXEFC_EFWM_Field := 16#0#; + -- unspecified + Reserved_30_31 : HAL.UInt2 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for MCAN_MCAN_TXEFC_Register use record + Reserved_0_1 at 0 range 0 .. 1; + EFSA at 0 range 2 .. 15; + EFS at 0 range 16 .. 21; + Reserved_22_23 at 0 range 22 .. 23; + EFWM at 0 range 24 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + subtype MCAN_MCAN_TXEFS_EFFL_Field is HAL.UInt6; + subtype MCAN_MCAN_TXEFS_EFGI_Field is HAL.UInt5; + subtype MCAN_MCAN_TXEFS_EFPI_Field is HAL.UInt5; + + -- Transmit Event FIFO Status Register + type MCAN_MCAN_TXEFS_Register is record + -- Read-only. Event FIFO Fill Level + EFFL : MCAN_MCAN_TXEFS_EFFL_Field; + -- unspecified + Reserved_6_7 : HAL.UInt2; + -- Read-only. Event FIFO Get Index + EFGI : MCAN_MCAN_TXEFS_EFGI_Field; + -- unspecified + Reserved_13_15 : HAL.UInt3; + -- Read-only. Event FIFO Put Index + EFPI : MCAN_MCAN_TXEFS_EFPI_Field; + -- unspecified + Reserved_21_23 : HAL.UInt3; + -- Read-only. Event FIFO Full + EFF : Boolean; + -- Read-only. Tx Event FIFO Element Lost + TEFL : Boolean; + -- unspecified + Reserved_26_31 : HAL.UInt6; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for MCAN_MCAN_TXEFS_Register use record + EFFL at 0 range 0 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + EFGI at 0 range 8 .. 12; + Reserved_13_15 at 0 range 13 .. 15; + EFPI at 0 range 16 .. 20; + Reserved_21_23 at 0 range 21 .. 23; + EFF at 0 range 24 .. 24; + TEFL at 0 range 25 .. 25; + Reserved_26_31 at 0 range 26 .. 31; + end record; + + subtype MCAN_MCAN_TXEFA_EFAI_Field is HAL.UInt5; + + -- Transmit Event FIFO Acknowledge Register + type MCAN_MCAN_TXEFA_Register is record + -- Event FIFO Acknowledge Index + EFAI : MCAN_MCAN_TXEFA_EFAI_Field := 16#0#; + -- unspecified + Reserved_5_31 : HAL.UInt27 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for MCAN_MCAN_TXEFA_Register use record + EFAI at 0 range 0 .. 4; + Reserved_5_31 at 0 range 5 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- Controller Area Network + type MCAN_Peripheral is record + -- Core Release Register + MCAN_CREL : aliased MCAN_MCAN_CREL_Register; + -- Endian Register + MCAN_ENDN : aliased HAL.UInt32; + -- Customer Register + MCAN_CUST : aliased HAL.UInt32; + -- Fast Bit Timing and Prescaler Register + MCAN_FBTP : aliased MCAN_MCAN_FBTP_Register; + -- Test Register + MCAN_TEST : aliased MCAN_MCAN_TEST_Register; + -- RAM Watchdog Register + MCAN_RWD : aliased MCAN_MCAN_RWD_Register; + -- CC Control Register + MCAN_CCCR : aliased MCAN_MCAN_CCCR_Register; + -- Bit Timing and Prescaler Register + MCAN_BTP : aliased MCAN_MCAN_BTP_Register; + -- Timestamp Counter Configuration Register + MCAN_TSCC : aliased MCAN_MCAN_TSCC_Register; + -- Timestamp Counter Value Register + MCAN_TSCV : aliased MCAN_MCAN_TSCV_Register; + -- Timeout Counter Configuration Register + MCAN_TOCC : aliased MCAN_MCAN_TOCC_Register; + -- Timeout Counter Value Register + MCAN_TOCV : aliased MCAN_MCAN_TOCV_Register; + -- Error Counter Register + MCAN_ECR : aliased MCAN_MCAN_ECR_Register; + -- Protocol Status Register + MCAN_PSR : aliased MCAN_MCAN_PSR_Register; + -- Interrupt Register + MCAN_IR : aliased MCAN_MCAN_IR_Register; + -- Interrupt Enable Register + MCAN_IE : aliased MCAN_MCAN_IE_Register; + -- Interrupt Line Select Register + MCAN_ILS : aliased MCAN_MCAN_ILS_Register; + -- Interrupt Line Enable Register + MCAN_ILE : aliased MCAN_MCAN_ILE_Register; + -- Global Filter Configuration Register + MCAN_GFC : aliased MCAN_MCAN_GFC_Register; + -- Standard ID Filter Configuration Register + MCAN_SIDFC : aliased MCAN_MCAN_SIDFC_Register; + -- Extended ID Filter Configuration Register + MCAN_XIDFC : aliased MCAN_MCAN_XIDFC_Register; + -- Extended ID AND Mask Register + MCAN_XIDAM : aliased MCAN_MCAN_XIDAM_Register; + -- High Priority Message Status Register + MCAN_HPMS : aliased MCAN_MCAN_HPMS_Register; + -- New Data 1 Register + MCAN_NDAT1 : aliased MCAN_MCAN_NDAT1_Register; + -- New Data 2 Register + MCAN_NDAT2 : aliased MCAN_MCAN_NDAT2_Register; + -- Receive FIFO 0 Configuration Register + MCAN_RXF0C : aliased MCAN_MCAN_RXF0C_Register; + -- Receive FIFO 0 Status Register + MCAN_RXF0S : aliased MCAN_MCAN_RXF0S_Register; + -- Receive FIFO 0 Acknowledge Register + MCAN_RXF0A : aliased MCAN_MCAN_RXF0A_Register; + -- Receive Rx Buffer Configuration Register + MCAN_RXBC : aliased MCAN_MCAN_RXBC_Register; + -- Receive FIFO 1 Configuration Register + MCAN_RXF1C : aliased MCAN_MCAN_RXF1C_Register; + -- Receive FIFO 1 Status Register + MCAN_RXF1S : aliased MCAN_MCAN_RXF1S_Register; + -- Receive FIFO 1 Acknowledge Register + MCAN_RXF1A : aliased MCAN_MCAN_RXF1A_Register; + -- Receive Buffer / FIFO Element Size Configuration Register + MCAN_RXESC : aliased MCAN_MCAN_RXESC_Register; + -- Transmit Buffer Configuration Register + MCAN_TXBC : aliased MCAN_MCAN_TXBC_Register; + -- Transmit FIFO/Queue Status Register + MCAN_TXFQS : aliased MCAN_MCAN_TXFQS_Register; + -- Transmit Buffer Element Size Configuration Register + MCAN_TXESC : aliased MCAN_MCAN_TXESC_Register; + -- Transmit Buffer Request Pending Register + MCAN_TXBRP : aliased MCAN_MCAN_TXBRP_Register; + -- Transmit Buffer Add Request Register + MCAN_TXBAR : aliased MCAN_MCAN_TXBAR_Register; + -- Transmit Buffer Cancellation Request Register + MCAN_TXBCR : aliased MCAN_MCAN_TXBCR_Register; + -- Transmit Buffer Transmission Occurred Register + MCAN_TXBTO : aliased MCAN_MCAN_TXBTO_Register; + -- Transmit Buffer Cancellation Finished Register + MCAN_TXBCF : aliased MCAN_MCAN_TXBCF_Register; + -- Transmit Buffer Transmission Interrupt Enable Register + MCAN_TXBTIE : aliased MCAN_MCAN_TXBTIE_Register; + -- Transmit Buffer Cancellation Finished Interrupt Enable Register + MCAN_TXBCIE : aliased MCAN_MCAN_TXBCIE_Register; + -- Transmit Event FIFO Configuration Register + MCAN_TXEFC : aliased MCAN_MCAN_TXEFC_Register; + -- Transmit Event FIFO Status Register + MCAN_TXEFS : aliased MCAN_MCAN_TXEFS_Register; + -- Transmit Event FIFO Acknowledge Register + MCAN_TXEFA : aliased MCAN_MCAN_TXEFA_Register; + end record + with Volatile; + + for MCAN_Peripheral use record + MCAN_CREL at 16#0# range 0 .. 31; + MCAN_ENDN at 16#4# range 0 .. 31; + MCAN_CUST at 16#8# range 0 .. 31; + MCAN_FBTP at 16#C# range 0 .. 31; + MCAN_TEST at 16#10# range 0 .. 31; + MCAN_RWD at 16#14# range 0 .. 31; + MCAN_CCCR at 16#18# range 0 .. 31; + MCAN_BTP at 16#1C# range 0 .. 31; + MCAN_TSCC at 16#20# range 0 .. 31; + MCAN_TSCV at 16#24# range 0 .. 31; + MCAN_TOCC at 16#28# range 0 .. 31; + MCAN_TOCV at 16#2C# range 0 .. 31; + MCAN_ECR at 16#40# range 0 .. 31; + MCAN_PSR at 16#44# range 0 .. 31; + MCAN_IR at 16#50# range 0 .. 31; + MCAN_IE at 16#54# range 0 .. 31; + MCAN_ILS at 16#58# range 0 .. 31; + MCAN_ILE at 16#5C# range 0 .. 31; + MCAN_GFC at 16#80# range 0 .. 31; + MCAN_SIDFC at 16#84# range 0 .. 31; + MCAN_XIDFC at 16#88# range 0 .. 31; + MCAN_XIDAM at 16#90# range 0 .. 31; + MCAN_HPMS at 16#94# range 0 .. 31; + MCAN_NDAT1 at 16#98# range 0 .. 31; + MCAN_NDAT2 at 16#9C# range 0 .. 31; + MCAN_RXF0C at 16#A0# range 0 .. 31; + MCAN_RXF0S at 16#A4# range 0 .. 31; + MCAN_RXF0A at 16#A8# range 0 .. 31; + MCAN_RXBC at 16#AC# range 0 .. 31; + MCAN_RXF1C at 16#B0# range 0 .. 31; + MCAN_RXF1S at 16#B4# range 0 .. 31; + MCAN_RXF1A at 16#B8# range 0 .. 31; + MCAN_RXESC at 16#BC# range 0 .. 31; + MCAN_TXBC at 16#C0# range 0 .. 31; + MCAN_TXFQS at 16#C4# range 0 .. 31; + MCAN_TXESC at 16#C8# range 0 .. 31; + MCAN_TXBRP at 16#CC# range 0 .. 31; + MCAN_TXBAR at 16#D0# range 0 .. 31; + MCAN_TXBCR at 16#D4# range 0 .. 31; + MCAN_TXBTO at 16#D8# range 0 .. 31; + MCAN_TXBCF at 16#DC# range 0 .. 31; + MCAN_TXBTIE at 16#E0# range 0 .. 31; + MCAN_TXBCIE at 16#E4# range 0 .. 31; + MCAN_TXEFC at 16#F0# range 0 .. 31; + MCAN_TXEFS at 16#F4# range 0 .. 31; + MCAN_TXEFA at 16#F8# range 0 .. 31; + end record; + + -- Controller Area Network + MCAN0_Periph : aliased MCAN_Peripheral + with Import, Address => System'To_Address (16#40030000#); + + -- Controller Area Network + MCAN1_Periph : aliased MCAN_Peripheral + with Import, Address => System'To_Address (16#40034000#); + +end SAM_SVD.MCAN; diff --git a/arch/ARM/SAM/svd/atsamv71/sam_svd-mlb.ads b/arch/ARM/SAM/svd/atsamv71/sam_svd-mlb.ads new file mode 100644 index 000000000..ec595372b --- /dev/null +++ b/arch/ARM/SAM/svd/atsamv71/sam_svd-mlb.ads @@ -0,0 +1,504 @@ +-- This spec has been automatically generated from ATSAMV71Q21.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package SAM_SVD.MLB is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + -- MLBCLK (MediaLB clock) speed select + type MLB_MLBC0_MLBCLK_Field is + ( + -- 256xFs (for MLBPEN = 0) + Val_256_Fs, + -- 512xFs (for MLBPEN = 0) + Val_512_Fs, + -- 1024xFs (for MLBPEN = 0) + Val_1024_Fs) + with Size => 3; + for MLB_MLBC0_MLBCLK_Field use + (Val_256_Fs => 0, + Val_512_Fs => 1, + Val_1024_Fs => 2); + + -- The number of frames per sub-buffer for synchronous channels + type MLB_MLBC0_FCNT_Field is + ( + -- 1 frame per sub-buffer (Operation is the same as Standard mode.) + Val_1_Frame, + -- 2 frames per sub-buffer + Val_2_Frames, + -- 4 frames per sub-buffer + Val_4_Frames, + -- 8 frames per sub-buffer + Val_8_Frames, + -- 16 frames per sub-buffer + Val_16_Frames, + -- 32 frames per sub-buffer + Val_32_Frames, + -- 64 frames per sub-buffer + Val_64_Frames) + with Size => 3; + for MLB_MLBC0_FCNT_Field use + (Val_1_Frame => 0, + Val_2_Frames => 1, + Val_4_Frames => 2, + Val_8_Frames => 3, + Val_16_Frames => 4, + Val_32_Frames => 5, + Val_64_Frames => 6); + + -- MediaLB Control 0 Register + type MLB_MLB_MLBC0_Register is record + -- MediaLB Enable + MLBEN : Boolean := False; + -- unspecified + Reserved_1_1 : HAL.Bit := 16#0#; + -- MLBCLK (MediaLB clock) speed select + MLBCLK : MLB_MLBC0_MLBCLK_Field := SAM_SVD.MLB.Val_256_Fs; + -- Must be Written to 0 + ZERO : Boolean := False; + -- unspecified + Reserved_6_6 : HAL.Bit := 16#0#; + -- MediaLB Lock Status (read-only) + MLBLK : Boolean := False; + -- unspecified + Reserved_8_11 : HAL.UInt4 := 16#0#; + -- Asynchronous Tx Packet Retry + ASYRETRY : Boolean := False; + -- unspecified + Reserved_13_13 : HAL.Bit := 16#0#; + -- Control Tx Packet Retry + CTLRETRY : Boolean := False; + -- The number of frames per sub-buffer for synchronous channels + FCNT : MLB_MLBC0_FCNT_Field := SAM_SVD.MLB.Val_1_Frame; + -- unspecified + Reserved_18_31 : HAL.UInt14 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for MLB_MLB_MLBC0_Register use record + MLBEN at 0 range 0 .. 0; + Reserved_1_1 at 0 range 1 .. 1; + MLBCLK at 0 range 2 .. 4; + ZERO at 0 range 5 .. 5; + Reserved_6_6 at 0 range 6 .. 6; + MLBLK at 0 range 7 .. 7; + Reserved_8_11 at 0 range 8 .. 11; + ASYRETRY at 0 range 12 .. 12; + Reserved_13_13 at 0 range 13 .. 13; + CTLRETRY at 0 range 14 .. 14; + FCNT at 0 range 15 .. 17; + Reserved_18_31 at 0 range 18 .. 31; + end record; + + -- MediaLB System Status Register + type MLB_MLB_MSS_Register is record + -- Reset System Command Detected in the System Quadlet (cleared by + -- writing a 0) + RSTSYSCMD : Boolean := False; + -- Network Lock System Command Detected in the System Quadlet (cleared + -- by writing a 0) + LKSYSCMD : Boolean := False; + -- Network Unlock System Command Detected in the System Quadlet (cleared + -- by writing a 0) + ULKSYSCMD : Boolean := False; + -- Channel Scan System Command Detected in the System Quadlet (cleared + -- by writing a 0) + CSSYSCMD : Boolean := False; + -- Software System Command Detected in the System Quadlet (cleared by + -- writing a 0) + SWSYSCMD : Boolean := False; + -- Service Request Enabled + SERVREQ : Boolean := False; + -- unspecified + Reserved_6_31 : HAL.UInt26 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for MLB_MLB_MSS_Register use record + RSTSYSCMD at 0 range 0 .. 0; + LKSYSCMD at 0 range 1 .. 1; + ULKSYSCMD at 0 range 2 .. 2; + CSSYSCMD at 0 range 3 .. 3; + SWSYSCMD at 0 range 4 .. 4; + SERVREQ at 0 range 5 .. 5; + Reserved_6_31 at 0 range 6 .. 31; + end record; + + -- MLB_MLB_MSD_SD array element + subtype MLB_MLB_MSD_SD_Element is HAL.UInt8; + + -- MLB_MLB_MSD_SD array + type MLB_MLB_MSD_SD_Field_Array is array (0 .. 3) + of MLB_MLB_MSD_SD_Element + with Component_Size => 8, Size => 32; + + -- MediaLB System Data Register + type MLB_MLB_MSD_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- SD as a value + Val : HAL.UInt32; + when True => + -- SD as an array + Arr : MLB_MLB_MSD_SD_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, + Bit_Order => System.Low_Order_First; + + for MLB_MLB_MSD_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- MediaLB Interrupt Enable Register + type MLB_MLB_MIEN_Register is record + -- Isochronous Rx Protocol Error Enable + ISOC_PE : Boolean := False; + -- Isochronous Rx Buffer Overflow Enable + ISOC_BUFO : Boolean := False; + -- unspecified + Reserved_2_15 : HAL.UInt14 := 16#0#; + -- Synchronous Protocol Error Enable + SYNC_PE : Boolean := False; + -- Asynchronous Rx Done Enable + ARX_DONE : Boolean := False; + -- Asynchronous Rx Protocol Error Enable + ARX_PE : Boolean := False; + -- Asynchronous Rx Break Enable + ARX_BREAK : Boolean := False; + -- Asynchronous Tx Packet Done Enable + ATX_DONE : Boolean := False; + -- Asynchronous Tx Protocol Error Enable + ATX_PE : Boolean := False; + -- Asynchronous Tx Break Enable + ATX_BREAK : Boolean := False; + -- unspecified + Reserved_23_23 : HAL.Bit := 16#0#; + -- Control Rx Packet Done Enable + CRX_DONE : Boolean := False; + -- Control Rx Protocol Error Enable + CRX_PE : Boolean := False; + -- Control Rx Break Enable + CRX_BREAK : Boolean := False; + -- Control Tx Packet Done Enable + CTX_DONE : Boolean := False; + -- Control Tx Protocol Error Enable + CTX_PE : Boolean := False; + -- Control Tx Break Enable + CTX_BREAK : Boolean := False; + -- unspecified + Reserved_30_31 : HAL.UInt2 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for MLB_MLB_MIEN_Register use record + ISOC_PE at 0 range 0 .. 0; + ISOC_BUFO at 0 range 1 .. 1; + Reserved_2_15 at 0 range 2 .. 15; + SYNC_PE at 0 range 16 .. 16; + ARX_DONE at 0 range 17 .. 17; + ARX_PE at 0 range 18 .. 18; + ARX_BREAK at 0 range 19 .. 19; + ATX_DONE at 0 range 20 .. 20; + ATX_PE at 0 range 21 .. 21; + ATX_BREAK at 0 range 22 .. 22; + Reserved_23_23 at 0 range 23 .. 23; + CRX_DONE at 0 range 24 .. 24; + CRX_PE at 0 range 25 .. 25; + CRX_BREAK at 0 range 26 .. 26; + CTX_DONE at 0 range 27 .. 27; + CTX_PE at 0 range 28 .. 28; + CTX_BREAK at 0 range 29 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + subtype MLB_MLB_MLBC1_NDA_Field is HAL.UInt8; + + -- MediaLB Control 1 Register + type MLB_MLB_MLBC1_Register is record + -- unspecified + Reserved_0_5 : HAL.UInt6 := 16#0#; + -- MediaLB Lock Error Status (cleared by writing a 0) + LOCK : Boolean := False; + -- MediaLB Clock Missing Status (cleared by writing a 0) + CLKM : Boolean := False; + -- Node Device Address + NDA : MLB_MLB_MLBC1_NDA_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for MLB_MLB_MLBC1_Register use record + Reserved_0_5 at 0 range 0 .. 5; + LOCK at 0 range 6 .. 6; + CLKM at 0 range 7 .. 7; + NDA at 0 range 8 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + -- MLB_MLB_HCTL_RST array + type MLB_MLB_HCTL_RST_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for MLB_MLB_HCTL_RST + type MLB_MLB_HCTL_RST_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- RST as a value + Val : HAL.UInt2; + when True => + -- RST as an array + Arr : MLB_MLB_HCTL_RST_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for MLB_MLB_HCTL_RST_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- HBI Control Register + type MLB_MLB_HCTL_Register is record + -- Address Generation Unit 0 Software Reset + RST : MLB_MLB_HCTL_RST_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_2_14 : HAL.UInt13 := 16#0#; + -- HBI Enable + EN : Boolean := False; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for MLB_MLB_HCTL_Register use record + RST at 0 range 0 .. 1; + Reserved_2_14 at 0 range 2 .. 14; + EN at 0 range 15 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + -- HBI Channel Mask 0 Register 0 + + -- HBI Channel Mask 0 Register 0 + type MLB_MLB_HCMR_Registers is array (0 .. 1) of HAL.UInt32 + with Volatile; + + -- HBI Channel Error 0 Register 0 + + -- HBI Channel Error 0 Register 0 + type MLB_MLB_HCER_Registers is array (0 .. 1) of HAL.UInt32 + with Volatile; + + -- HBI Channel Busy 0 Register 0 + + -- HBI Channel Busy 0 Register 0 + type MLB_MLB_HCBR_Registers is array (0 .. 1) of HAL.UInt32 + with Volatile; + + -- MIF Data 0 Register 0 + + -- MIF Data 0 Register 0 + type MLB_MLB_MDAT_Registers is array (0 .. 3) of HAL.UInt32 + with Volatile; + + -- MIF Data Write Enable 0 Register 0 + + -- MIF Data Write Enable 0 Register 0 + type MLB_MLB_MDWE_Registers is array (0 .. 3) of HAL.UInt32 + with Volatile; + + -- MIF Control Register + type MLB_MLB_MCTL_Register is record + -- Transfer Complete (Write 0 to Clear) + XCMP : Boolean := False; + -- unspecified + Reserved_1_31 : HAL.UInt31 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for MLB_MLB_MCTL_Register use record + XCMP at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + subtype MLB_MLB_MADR_ADDR_Field is HAL.UInt14; + + -- Target Location Bit + type MLB_MADR_TB_Field is + ( + -- Selects CTR + Ctr, + -- Selects DBR + Dbr) + with Size => 1; + for MLB_MADR_TB_Field use + (Ctr => 0, + Dbr => 1); + + -- MIF Address Register + type MLB_MLB_MADR_Register is record + -- CTR or DBR Address + ADDR : MLB_MLB_MADR_ADDR_Field := 16#0#; + -- unspecified + Reserved_14_29 : HAL.UInt16 := 16#0#; + -- Target Location Bit + TB : MLB_MADR_TB_Field := SAM_SVD.MLB.Ctr; + -- Write-Not-Read Selection + WNR : Boolean := False; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for MLB_MLB_MADR_Register use record + ADDR at 0 range 0 .. 13; + Reserved_14_29 at 0 range 14 .. 29; + TB at 0 range 30 .. 30; + WNR at 0 range 31 .. 31; + end record; + + -- DMA Packet Buffering Mode + type MLB_ACTL_MPB_Field is + ( + -- Single-packet mode + Single_Packet, + -- Multiple-packet mode + Multiple_Packet) + with Size => 1; + for MLB_ACTL_MPB_Field use + (Single_Packet => 0, + Multiple_Packet => 1); + + -- AHB Control Register + type MLB_MLB_ACTL_Register is record + -- Software Clear Enable + SCE : Boolean := False; + -- AHB Interrupt Mux Enable + SMX : Boolean := False; + -- DMA Mode + DMA_MODE : Boolean := False; + -- unspecified + Reserved_3_3 : HAL.Bit := 16#0#; + -- DMA Packet Buffering Mode + MPB : MLB_ACTL_MPB_Field := SAM_SVD.MLB.Single_Packet; + -- unspecified + Reserved_5_31 : HAL.UInt27 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for MLB_MLB_ACTL_Register use record + SCE at 0 range 0 .. 0; + SMX at 0 range 1 .. 1; + DMA_MODE at 0 range 2 .. 2; + Reserved_3_3 at 0 range 3 .. 3; + MPB at 0 range 4 .. 4; + Reserved_5_31 at 0 range 5 .. 31; + end record; + + -- AHB Channel Status 0 Register 0 + + -- AHB Channel Status 0 Register 0 + type MLB_MLB_ACSR_Registers is array (0 .. 1) of HAL.UInt32 + with Volatile; + + -- AHB Channel Mask 0 Register 0 + + -- AHB Channel Mask 0 Register 0 + type MLB_MLB_ACMR_Registers is array (0 .. 1) of HAL.UInt32 + with Volatile; + + ----------------- + -- Peripherals -- + ----------------- + + -- MediaLB + type MLB_Peripheral is record + -- MediaLB Control 0 Register + MLB_MLBC0 : aliased MLB_MLB_MLBC0_Register; + -- MediaLB Channel Status 0 Register + MLB_MS0 : aliased HAL.UInt32; + -- MediaLB Channel Status1 Register + MLB_MS1 : aliased HAL.UInt32; + -- MediaLB System Status Register + MLB_MSS : aliased MLB_MLB_MSS_Register; + -- MediaLB System Data Register + MLB_MSD : aliased MLB_MLB_MSD_Register; + -- MediaLB Interrupt Enable Register + MLB_MIEN : aliased MLB_MLB_MIEN_Register; + -- MediaLB Control 1 Register + MLB_MLBC1 : aliased MLB_MLB_MLBC1_Register; + -- HBI Control Register + MLB_HCTL : aliased MLB_MLB_HCTL_Register; + -- HBI Channel Mask 0 Register 0 + MLB_HCMR : aliased MLB_MLB_HCMR_Registers; + -- HBI Channel Error 0 Register 0 + MLB_HCER : aliased MLB_MLB_HCER_Registers; + -- HBI Channel Busy 0 Register 0 + MLB_HCBR : aliased MLB_MLB_HCBR_Registers; + -- MIF Data 0 Register 0 + MLB_MDAT : aliased MLB_MLB_MDAT_Registers; + -- MIF Data Write Enable 0 Register 0 + MLB_MDWE : aliased MLB_MLB_MDWE_Registers; + -- MIF Control Register + MLB_MCTL : aliased MLB_MLB_MCTL_Register; + -- MIF Address Register + MLB_MADR : aliased MLB_MLB_MADR_Register; + -- AHB Control Register + MLB_ACTL : aliased MLB_MLB_ACTL_Register; + -- AHB Channel Status 0 Register 0 + MLB_ACSR : aliased MLB_MLB_ACSR_Registers; + -- AHB Channel Mask 0 Register 0 + MLB_ACMR : aliased MLB_MLB_ACMR_Registers; + end record + with Volatile; + + for MLB_Peripheral use record + MLB_MLBC0 at 16#0# range 0 .. 31; + MLB_MS0 at 16#C# range 0 .. 31; + MLB_MS1 at 16#14# range 0 .. 31; + MLB_MSS at 16#20# range 0 .. 31; + MLB_MSD at 16#24# range 0 .. 31; + MLB_MIEN at 16#2C# range 0 .. 31; + MLB_MLBC1 at 16#3C# range 0 .. 31; + MLB_HCTL at 16#80# range 0 .. 31; + MLB_HCMR at 16#88# range 0 .. 63; + MLB_HCER at 16#90# range 0 .. 63; + MLB_HCBR at 16#98# range 0 .. 63; + MLB_MDAT at 16#C0# range 0 .. 127; + MLB_MDWE at 16#D0# range 0 .. 127; + MLB_MCTL at 16#E0# range 0 .. 31; + MLB_MADR at 16#E4# range 0 .. 31; + MLB_ACTL at 16#3C0# range 0 .. 31; + MLB_ACSR at 16#3D0# range 0 .. 63; + MLB_ACMR at 16#3D8# range 0 .. 63; + end record; + + -- MediaLB + MLB_Periph : aliased MLB_Peripheral + with Import, Address => System'To_Address (16#40068000#); + +end SAM_SVD.MLB; diff --git a/arch/ARM/SAM/svd/atsamv71/sam_svd-mpu.ads b/arch/ARM/SAM/svd/atsamv71/sam_svd-mpu.ads new file mode 100644 index 000000000..0d2cb797f --- /dev/null +++ b/arch/ARM/SAM/svd/atsamv71/sam_svd-mpu.ads @@ -0,0 +1,190 @@ +-- This spec has been automatically generated from ATSAMV71Q21.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package SAM_SVD.MPU is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + subtype MPU_MPU_TYPE_DREGION_Field is HAL.UInt8; + subtype MPU_MPU_TYPE_IREGION_Field is HAL.UInt8; + + -- MPU Type Register + type MPU_MPU_TYPE_Register is record + -- Indicates support for unified or separate instruction and date memory + -- maps. + SEPARATE_k : Boolean := False; + -- unspecified + Reserved_1_7 : HAL.UInt7 := 16#0#; + -- Indicates the number of supported MPU instruction regions. + DREGION : MPU_MPU_TYPE_DREGION_Field := 16#0#; + -- Indicates the number of supported MPU data regions. + IREGION : MPU_MPU_TYPE_IREGION_Field := 16#0#; + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for MPU_MPU_TYPE_Register use record + SEPARATE_k at 0 range 0 .. 0; + Reserved_1_7 at 0 range 1 .. 7; + DREGION at 0 range 8 .. 15; + IREGION at 0 range 16 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- MPU Control Register + type MPU_MPU_CTRL_Register is record + -- Enables the MPU + ENABLE : Boolean := False; + -- Enables the operation of MPU during hard fault, NMI, and FAULTMASK + -- handlers. + HFNMIENA : Boolean := False; + -- Enables privileged software access to the default memory map. + PRIVDEFENA : Boolean := False; + -- unspecified + Reserved_3_31 : HAL.UInt29 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for MPU_MPU_CTRL_Register use record + ENABLE at 0 range 0 .. 0; + HFNMIENA at 0 range 1 .. 1; + PRIVDEFENA at 0 range 2 .. 2; + Reserved_3_31 at 0 range 3 .. 31; + end record; + + subtype MPU_MPU_RNR_REGION_Field is HAL.UInt8; + + -- MPU Region Number Register + type MPU_MPU_RNR_Register is record + -- Indicates the MPU region referenced by the MPU_RBAR and MPU_RASR + -- registers. + REGION : MPU_MPU_RNR_REGION_Field := 16#0#; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for MPU_MPU_RNR_Register use record + REGION at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype MPU_MPU_RBAR_REGION_Field is HAL.UInt4; + subtype MPU_MPU_RBAR_ADDR_Field is HAL.UInt27; + + -- MPU Region Base Address Register + type MPU_MPU_RBAR_Register is record + -- MPU region field. + REGION : MPU_MPU_RBAR_REGION_Field := 16#0#; + -- MPU Region Number valid bit. + VALID : Boolean := False; + -- Region base address field. + ADDR : MPU_MPU_RBAR_ADDR_Field := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for MPU_MPU_RBAR_Register use record + REGION at 0 range 0 .. 3; + VALID at 0 range 4 .. 4; + ADDR at 0 range 5 .. 31; + end record; + + subtype MPU_MPU_RASR_SIZE_Field is HAL.UInt5; + subtype MPU_MPU_RASR_SRD_Field is HAL.UInt8; + subtype MPU_MPU_RASR_TEX_Field is HAL.UInt3; + subtype MPU_MPU_RASR_AP_Field is HAL.UInt3; + + -- MPU Region Attribute and Size Register + type MPU_MPU_RASR_Register is record + -- Region enable bit. + ENABLE : Boolean := False; + -- Specifies the size of the MPU protection region. + SIZE : MPU_MPU_RASR_SIZE_Field := 16#0#; + -- unspecified + Reserved_6_7 : HAL.UInt2 := 16#0#; + -- Subregion disable bits. + SRD : MPU_MPU_RASR_SRD_Field := 16#0#; + -- MPU access permission attributes. + B : Boolean := False; + -- MPU access permission attributes. + C : Boolean := False; + -- Shareable bit. + S : Boolean := False; + -- MPU access permission attributes. + TEX : MPU_MPU_RASR_TEX_Field := 16#0#; + -- unspecified + Reserved_22_23 : HAL.UInt2 := 16#0#; + -- Access permission field. + AP : MPU_MPU_RASR_AP_Field := 16#0#; + -- unspecified + Reserved_27_27 : HAL.Bit := 16#0#; + -- Instruction access disable bit. + XN : Boolean := False; + -- unspecified + Reserved_29_31 : HAL.UInt3 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for MPU_MPU_RASR_Register use record + ENABLE at 0 range 0 .. 0; + SIZE at 0 range 1 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + SRD at 0 range 8 .. 15; + B at 0 range 16 .. 16; + C at 0 range 17 .. 17; + S at 0 range 18 .. 18; + TEX at 0 range 19 .. 21; + Reserved_22_23 at 0 range 22 .. 23; + AP at 0 range 24 .. 26; + Reserved_27_27 at 0 range 27 .. 27; + XN at 0 range 28 .. 28; + Reserved_29_31 at 0 range 29 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- Memory Protection Unit Registers + type MPU_Peripheral is record + -- MPU Type Register + MPU_TYPE : aliased MPU_MPU_TYPE_Register; + -- MPU Control Register + MPU_CTRL : aliased MPU_MPU_CTRL_Register; + -- MPU Region Number Register + MPU_RNR : aliased MPU_MPU_RNR_Register; + -- MPU Region Base Address Register + MPU_RBAR : aliased MPU_MPU_RBAR_Register; + -- MPU Region Attribute and Size Register + MPU_RASR : aliased MPU_MPU_RASR_Register; + end record + with Volatile; + + for MPU_Peripheral use record + MPU_TYPE at 16#0# range 0 .. 31; + MPU_CTRL at 16#4# range 0 .. 31; + MPU_RNR at 16#8# range 0 .. 31; + MPU_RBAR at 16#C# range 0 .. 31; + MPU_RASR at 16#10# range 0 .. 31; + end record; + + -- Memory Protection Unit Registers + MPU_Periph : aliased MPU_Peripheral + with Import, Address => System'To_Address (16#E000ED90#); + +end SAM_SVD.MPU; diff --git a/arch/ARM/SAM/svd/atsamv71/sam_svd-nvic.ads b/arch/ARM/SAM/svd/atsamv71/sam_svd-nvic.ads new file mode 100644 index 000000000..9d73e8050 --- /dev/null +++ b/arch/ARM/SAM/svd/atsamv71/sam_svd-nvic.ads @@ -0,0 +1,432 @@ +-- This spec has been automatically generated from ATSAMV71Q21.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package SAM_SVD.NVIC is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + subtype NVIC_NVICSTIR_INTID_Field is HAL.UInt9; + + -- Software Trigger Interrupt Register + type NVIC_NVICSTIR_Register is record + -- Interrupt ID of the interrupt to trigger, in the range 0-239. For + -- example, a value of 0x03 specifies interrupt IRQ3. + INTID : NVIC_NVICSTIR_INTID_Field := 16#0#; + -- unspecified + Reserved_9_31 : HAL.UInt23 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for NVIC_NVICSTIR_Register use record + INTID at 0 range 0 .. 8; + Reserved_9_31 at 0 range 9 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- Nested Vectored Interrupt Controller + type NVIC_Peripheral is record + -- Interrupt Set Enable Register n + NVICISER0 : aliased HAL.UInt32; + -- Interrupt Set Enable Register n + NVICISER1 : aliased HAL.UInt32; + -- Interrupt Set Enable Register n + NVICISER2 : aliased HAL.UInt32; + -- Interrupt Set Enable Register n + NVICISER3 : aliased HAL.UInt32; + -- Interrupt Clear Enable Register n + NVICICER0 : aliased HAL.UInt32; + -- Interrupt Clear Enable Register n + NVICICER1 : aliased HAL.UInt32; + -- Interrupt Clear Enable Register n + NVICICER2 : aliased HAL.UInt32; + -- Interrupt Clear Enable Register n + NVICICER3 : aliased HAL.UInt32; + -- Interrupt Set Pending Register n + NVICISPR0 : aliased HAL.UInt32; + -- Interrupt Set Pending Register n + NVICISPR1 : aliased HAL.UInt32; + -- Interrupt Set Pending Register n + NVICISPR2 : aliased HAL.UInt32; + -- Interrupt Set Pending Register n + NVICISPR3 : aliased HAL.UInt32; + -- Interrupt Clear Pending Register n + NVICICPR0 : aliased HAL.UInt32; + -- Interrupt Clear Pending Register n + NVICICPR1 : aliased HAL.UInt32; + -- Interrupt Clear Pending Register n + NVICICPR2 : aliased HAL.UInt32; + -- Interrupt Clear Pending Register n + NVICICPR3 : aliased HAL.UInt32; + -- Interrupt Active bit Register n + NVICIABR0 : aliased HAL.UInt32; + -- Interrupt Active bit Register n + NVICIABR1 : aliased HAL.UInt32; + -- Interrupt Active bit Register n + NVICIABR2 : aliased HAL.UInt32; + -- Interrupt Active bit Register n + NVICIABR3 : aliased HAL.UInt32; + -- Interrupt Priority Register n + NVICIP0 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP1 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP2 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP3 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP4 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP5 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP6 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP7 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP8 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP9 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP10 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP11 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP12 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP13 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP14 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP15 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP16 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP17 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP18 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP19 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP20 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP21 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP22 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP23 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP24 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP25 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP26 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP27 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP28 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP29 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP30 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP31 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP32 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP33 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP34 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP35 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP36 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP37 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP38 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP39 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP40 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP41 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP42 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP43 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP44 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP45 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP46 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP47 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP48 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP49 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP50 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP51 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP52 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP53 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP54 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP55 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP56 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP57 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP58 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP59 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP60 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP61 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP62 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP63 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP64 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP65 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP66 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP67 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP68 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP69 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP70 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP71 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP72 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP73 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP74 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP75 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP76 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP77 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP78 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP79 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP80 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP81 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP82 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP83 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP84 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP85 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP86 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP87 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP88 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP89 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP90 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP91 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP92 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP93 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP94 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP95 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP96 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP97 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP98 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP99 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP100 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP101 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP102 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP103 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP104 : aliased HAL.UInt8; + -- Interrupt Priority Register n + NVICIP105 : aliased HAL.UInt8; + -- Software Trigger Interrupt Register + NVICSTIR : aliased NVIC_NVICSTIR_Register; + end record + with Volatile; + + for NVIC_Peripheral use record + NVICISER0 at 16#0# range 0 .. 31; + NVICISER1 at 16#4# range 0 .. 31; + NVICISER2 at 16#8# range 0 .. 31; + NVICISER3 at 16#C# range 0 .. 31; + NVICICER0 at 16#80# range 0 .. 31; + NVICICER1 at 16#84# range 0 .. 31; + NVICICER2 at 16#88# range 0 .. 31; + NVICICER3 at 16#8C# range 0 .. 31; + NVICISPR0 at 16#100# range 0 .. 31; + NVICISPR1 at 16#104# range 0 .. 31; + NVICISPR2 at 16#108# range 0 .. 31; + NVICISPR3 at 16#10C# range 0 .. 31; + NVICICPR0 at 16#180# range 0 .. 31; + NVICICPR1 at 16#184# range 0 .. 31; + NVICICPR2 at 16#188# range 0 .. 31; + NVICICPR3 at 16#18C# range 0 .. 31; + NVICIABR0 at 16#200# range 0 .. 31; + NVICIABR1 at 16#204# range 0 .. 31; + NVICIABR2 at 16#208# range 0 .. 31; + NVICIABR3 at 16#20C# range 0 .. 31; + NVICIP0 at 16#300# range 0 .. 7; + NVICIP1 at 16#301# range 0 .. 7; + NVICIP2 at 16#302# range 0 .. 7; + NVICIP3 at 16#303# range 0 .. 7; + NVICIP4 at 16#304# range 0 .. 7; + NVICIP5 at 16#305# range 0 .. 7; + NVICIP6 at 16#306# range 0 .. 7; + NVICIP7 at 16#307# range 0 .. 7; + NVICIP8 at 16#308# range 0 .. 7; + NVICIP9 at 16#309# range 0 .. 7; + NVICIP10 at 16#30A# range 0 .. 7; + NVICIP11 at 16#30B# range 0 .. 7; + NVICIP12 at 16#30C# range 0 .. 7; + NVICIP13 at 16#30D# range 0 .. 7; + NVICIP14 at 16#30E# range 0 .. 7; + NVICIP15 at 16#30F# range 0 .. 7; + NVICIP16 at 16#310# range 0 .. 7; + NVICIP17 at 16#311# range 0 .. 7; + NVICIP18 at 16#312# range 0 .. 7; + NVICIP19 at 16#313# range 0 .. 7; + NVICIP20 at 16#314# range 0 .. 7; + NVICIP21 at 16#315# range 0 .. 7; + NVICIP22 at 16#316# range 0 .. 7; + NVICIP23 at 16#317# range 0 .. 7; + NVICIP24 at 16#318# range 0 .. 7; + NVICIP25 at 16#319# range 0 .. 7; + NVICIP26 at 16#31A# range 0 .. 7; + NVICIP27 at 16#31B# range 0 .. 7; + NVICIP28 at 16#31C# range 0 .. 7; + NVICIP29 at 16#31D# range 0 .. 7; + NVICIP30 at 16#31E# range 0 .. 7; + NVICIP31 at 16#31F# range 0 .. 7; + NVICIP32 at 16#320# range 0 .. 7; + NVICIP33 at 16#321# range 0 .. 7; + NVICIP34 at 16#322# range 0 .. 7; + NVICIP35 at 16#323# range 0 .. 7; + NVICIP36 at 16#324# range 0 .. 7; + NVICIP37 at 16#325# range 0 .. 7; + NVICIP38 at 16#326# range 0 .. 7; + NVICIP39 at 16#327# range 0 .. 7; + NVICIP40 at 16#328# range 0 .. 7; + NVICIP41 at 16#329# range 0 .. 7; + NVICIP42 at 16#32A# range 0 .. 7; + NVICIP43 at 16#32B# range 0 .. 7; + NVICIP44 at 16#32C# range 0 .. 7; + NVICIP45 at 16#32D# range 0 .. 7; + NVICIP46 at 16#32E# range 0 .. 7; + NVICIP47 at 16#32F# range 0 .. 7; + NVICIP48 at 16#330# range 0 .. 7; + NVICIP49 at 16#331# range 0 .. 7; + NVICIP50 at 16#332# range 0 .. 7; + NVICIP51 at 16#333# range 0 .. 7; + NVICIP52 at 16#334# range 0 .. 7; + NVICIP53 at 16#335# range 0 .. 7; + NVICIP54 at 16#336# range 0 .. 7; + NVICIP55 at 16#337# range 0 .. 7; + NVICIP56 at 16#338# range 0 .. 7; + NVICIP57 at 16#339# range 0 .. 7; + NVICIP58 at 16#33A# range 0 .. 7; + NVICIP59 at 16#33B# range 0 .. 7; + NVICIP60 at 16#33C# range 0 .. 7; + NVICIP61 at 16#33D# range 0 .. 7; + NVICIP62 at 16#33E# range 0 .. 7; + NVICIP63 at 16#33F# range 0 .. 7; + NVICIP64 at 16#340# range 0 .. 7; + NVICIP65 at 16#341# range 0 .. 7; + NVICIP66 at 16#342# range 0 .. 7; + NVICIP67 at 16#343# range 0 .. 7; + NVICIP68 at 16#344# range 0 .. 7; + NVICIP69 at 16#345# range 0 .. 7; + NVICIP70 at 16#346# range 0 .. 7; + NVICIP71 at 16#347# range 0 .. 7; + NVICIP72 at 16#348# range 0 .. 7; + NVICIP73 at 16#349# range 0 .. 7; + NVICIP74 at 16#34A# range 0 .. 7; + NVICIP75 at 16#34B# range 0 .. 7; + NVICIP76 at 16#34C# range 0 .. 7; + NVICIP77 at 16#34D# range 0 .. 7; + NVICIP78 at 16#34E# range 0 .. 7; + NVICIP79 at 16#34F# range 0 .. 7; + NVICIP80 at 16#350# range 0 .. 7; + NVICIP81 at 16#351# range 0 .. 7; + NVICIP82 at 16#352# range 0 .. 7; + NVICIP83 at 16#353# range 0 .. 7; + NVICIP84 at 16#354# range 0 .. 7; + NVICIP85 at 16#355# range 0 .. 7; + NVICIP86 at 16#356# range 0 .. 7; + NVICIP87 at 16#357# range 0 .. 7; + NVICIP88 at 16#358# range 0 .. 7; + NVICIP89 at 16#359# range 0 .. 7; + NVICIP90 at 16#35A# range 0 .. 7; + NVICIP91 at 16#35B# range 0 .. 7; + NVICIP92 at 16#35C# range 0 .. 7; + NVICIP93 at 16#35D# range 0 .. 7; + NVICIP94 at 16#35E# range 0 .. 7; + NVICIP95 at 16#35F# range 0 .. 7; + NVICIP96 at 16#360# range 0 .. 7; + NVICIP97 at 16#361# range 0 .. 7; + NVICIP98 at 16#362# range 0 .. 7; + NVICIP99 at 16#363# range 0 .. 7; + NVICIP100 at 16#364# range 0 .. 7; + NVICIP101 at 16#365# range 0 .. 7; + NVICIP102 at 16#366# range 0 .. 7; + NVICIP103 at 16#367# range 0 .. 7; + NVICIP104 at 16#368# range 0 .. 7; + NVICIP105 at 16#369# range 0 .. 7; + NVICSTIR at 16#E00# range 0 .. 31; + end record; + + -- Nested Vectored Interrupt Controller + NVIC_Periph : aliased NVIC_Peripheral + with Import, Address => System'To_Address (16#E000E100#); + +end SAM_SVD.NVIC; diff --git a/arch/ARM/SAM/svd/atsamv71/sam_svd-pio.ads b/arch/ARM/SAM/svd/atsamv71/sam_svd-pio.ads new file mode 100644 index 000000000..c906cb765 --- /dev/null +++ b/arch/ARM/SAM/svd/atsamv71/sam_svd-pio.ads @@ -0,0 +1,1589 @@ +-- This spec has been automatically generated from ATSAMV71Q21.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package SAM_SVD.PIO is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + -- PIO_PIO_PER_P array + type PIO_PIO_PER_P_Field_Array is array (0 .. 31) of Boolean + with Component_Size => 1, Size => 32; + + -- PIO Enable Register + type PIO_PIO_PER_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- P as a value + Val : HAL.UInt32; + when True => + -- P as an array + Arr : PIO_PIO_PER_P_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, + Bit_Order => System.Low_Order_First; + + for PIO_PIO_PER_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- PIO_PIO_PDR_P array + type PIO_PIO_PDR_P_Field_Array is array (0 .. 31) of Boolean + with Component_Size => 1, Size => 32; + + -- PIO Disable Register + type PIO_PIO_PDR_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- P as a value + Val : HAL.UInt32; + when True => + -- P as an array + Arr : PIO_PIO_PDR_P_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, + Bit_Order => System.Low_Order_First; + + for PIO_PIO_PDR_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- PIO_PIO_PSR_P array + type PIO_PIO_PSR_P_Field_Array is array (0 .. 31) of Boolean + with Component_Size => 1, Size => 32; + + -- PIO Status Register + type PIO_PIO_PSR_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- P as a value + Val : HAL.UInt32; + when True => + -- P as an array + Arr : PIO_PIO_PSR_P_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, + Bit_Order => System.Low_Order_First; + + for PIO_PIO_PSR_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- PIO_PIO_OER_P array + type PIO_PIO_OER_P_Field_Array is array (0 .. 31) of Boolean + with Component_Size => 1, Size => 32; + + -- Output Enable Register + type PIO_PIO_OER_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- P as a value + Val : HAL.UInt32; + when True => + -- P as an array + Arr : PIO_PIO_OER_P_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, + Bit_Order => System.Low_Order_First; + + for PIO_PIO_OER_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- PIO_PIO_ODR_P array + type PIO_PIO_ODR_P_Field_Array is array (0 .. 31) of Boolean + with Component_Size => 1, Size => 32; + + -- Output Disable Register + type PIO_PIO_ODR_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- P as a value + Val : HAL.UInt32; + when True => + -- P as an array + Arr : PIO_PIO_ODR_P_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, + Bit_Order => System.Low_Order_First; + + for PIO_PIO_ODR_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- PIO_PIO_OSR_P array + type PIO_PIO_OSR_P_Field_Array is array (0 .. 31) of Boolean + with Component_Size => 1, Size => 32; + + -- Output Status Register + type PIO_PIO_OSR_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- P as a value + Val : HAL.UInt32; + when True => + -- P as an array + Arr : PIO_PIO_OSR_P_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, + Bit_Order => System.Low_Order_First; + + for PIO_PIO_OSR_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- PIO_PIO_IFER_P array + type PIO_PIO_IFER_P_Field_Array is array (0 .. 31) of Boolean + with Component_Size => 1, Size => 32; + + -- Glitch Input Filter Enable Register + type PIO_PIO_IFER_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- P as a value + Val : HAL.UInt32; + when True => + -- P as an array + Arr : PIO_PIO_IFER_P_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, + Bit_Order => System.Low_Order_First; + + for PIO_PIO_IFER_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- PIO_PIO_IFDR_P array + type PIO_PIO_IFDR_P_Field_Array is array (0 .. 31) of Boolean + with Component_Size => 1, Size => 32; + + -- Glitch Input Filter Disable Register + type PIO_PIO_IFDR_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- P as a value + Val : HAL.UInt32; + when True => + -- P as an array + Arr : PIO_PIO_IFDR_P_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, + Bit_Order => System.Low_Order_First; + + for PIO_PIO_IFDR_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- PIO_PIO_IFSR_P array + type PIO_PIO_IFSR_P_Field_Array is array (0 .. 31) of Boolean + with Component_Size => 1, Size => 32; + + -- Glitch Input Filter Status Register + type PIO_PIO_IFSR_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- P as a value + Val : HAL.UInt32; + when True => + -- P as an array + Arr : PIO_PIO_IFSR_P_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, + Bit_Order => System.Low_Order_First; + + for PIO_PIO_IFSR_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- PIO_PIO_SODR_P array + type PIO_PIO_SODR_P_Field_Array is array (0 .. 31) of Boolean + with Component_Size => 1, Size => 32; + + -- Set Output Data Register + type PIO_PIO_SODR_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- P as a value + Val : HAL.UInt32; + when True => + -- P as an array + Arr : PIO_PIO_SODR_P_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, + Bit_Order => System.Low_Order_First; + + for PIO_PIO_SODR_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- PIO_PIO_CODR_P array + type PIO_PIO_CODR_P_Field_Array is array (0 .. 31) of Boolean + with Component_Size => 1, Size => 32; + + -- Clear Output Data Register + type PIO_PIO_CODR_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- P as a value + Val : HAL.UInt32; + when True => + -- P as an array + Arr : PIO_PIO_CODR_P_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, + Bit_Order => System.Low_Order_First; + + for PIO_PIO_CODR_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- PIO_PIO_ODSR_P array + type PIO_PIO_ODSR_P_Field_Array is array (0 .. 31) of Boolean + with Component_Size => 1, Size => 32; + + -- Output Data Status Register + type PIO_PIO_ODSR_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- P as a value + Val : HAL.UInt32; + when True => + -- P as an array + Arr : PIO_PIO_ODSR_P_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, + Bit_Order => System.Low_Order_First; + + for PIO_PIO_ODSR_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- PIO_PIO_PDSR_P array + type PIO_PIO_PDSR_P_Field_Array is array (0 .. 31) of Boolean + with Component_Size => 1, Size => 32; + + -- Pin Data Status Register + type PIO_PIO_PDSR_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- P as a value + Val : HAL.UInt32; + when True => + -- P as an array + Arr : PIO_PIO_PDSR_P_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, + Bit_Order => System.Low_Order_First; + + for PIO_PIO_PDSR_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- PIO_PIO_IER_P array + type PIO_PIO_IER_P_Field_Array is array (0 .. 31) of Boolean + with Component_Size => 1, Size => 32; + + -- Interrupt Enable Register + type PIO_PIO_IER_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- P as a value + Val : HAL.UInt32; + when True => + -- P as an array + Arr : PIO_PIO_IER_P_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, + Bit_Order => System.Low_Order_First; + + for PIO_PIO_IER_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- PIO_PIO_IDR_P array + type PIO_PIO_IDR_P_Field_Array is array (0 .. 31) of Boolean + with Component_Size => 1, Size => 32; + + -- Interrupt Disable Register + type PIO_PIO_IDR_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- P as a value + Val : HAL.UInt32; + when True => + -- P as an array + Arr : PIO_PIO_IDR_P_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, + Bit_Order => System.Low_Order_First; + + for PIO_PIO_IDR_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- PIO_PIO_IMR_P array + type PIO_PIO_IMR_P_Field_Array is array (0 .. 31) of Boolean + with Component_Size => 1, Size => 32; + + -- Interrupt Mask Register + type PIO_PIO_IMR_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- P as a value + Val : HAL.UInt32; + when True => + -- P as an array + Arr : PIO_PIO_IMR_P_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, + Bit_Order => System.Low_Order_First; + + for PIO_PIO_IMR_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- PIO_PIO_ISR_P array + type PIO_PIO_ISR_P_Field_Array is array (0 .. 31) of Boolean + with Component_Size => 1, Size => 32; + + -- Interrupt Status Register + type PIO_PIO_ISR_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- P as a value + Val : HAL.UInt32; + when True => + -- P as an array + Arr : PIO_PIO_ISR_P_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, + Bit_Order => System.Low_Order_First; + + for PIO_PIO_ISR_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- PIO_PIO_MDER_P array + type PIO_PIO_MDER_P_Field_Array is array (0 .. 31) of Boolean + with Component_Size => 1, Size => 32; + + -- Multi-driver Enable Register + type PIO_PIO_MDER_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- P as a value + Val : HAL.UInt32; + when True => + -- P as an array + Arr : PIO_PIO_MDER_P_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, + Bit_Order => System.Low_Order_First; + + for PIO_PIO_MDER_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- PIO_PIO_MDDR_P array + type PIO_PIO_MDDR_P_Field_Array is array (0 .. 31) of Boolean + with Component_Size => 1, Size => 32; + + -- Multi-driver Disable Register + type PIO_PIO_MDDR_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- P as a value + Val : HAL.UInt32; + when True => + -- P as an array + Arr : PIO_PIO_MDDR_P_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, + Bit_Order => System.Low_Order_First; + + for PIO_PIO_MDDR_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- PIO_PIO_MDSR_P array + type PIO_PIO_MDSR_P_Field_Array is array (0 .. 31) of Boolean + with Component_Size => 1, Size => 32; + + -- Multi-driver Status Register + type PIO_PIO_MDSR_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- P as a value + Val : HAL.UInt32; + when True => + -- P as an array + Arr : PIO_PIO_MDSR_P_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, + Bit_Order => System.Low_Order_First; + + for PIO_PIO_MDSR_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- PIO_PIO_PUDR_P array + type PIO_PIO_PUDR_P_Field_Array is array (0 .. 31) of Boolean + with Component_Size => 1, Size => 32; + + -- Pull-up Disable Register + type PIO_PIO_PUDR_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- P as a value + Val : HAL.UInt32; + when True => + -- P as an array + Arr : PIO_PIO_PUDR_P_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, + Bit_Order => System.Low_Order_First; + + for PIO_PIO_PUDR_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- PIO_PIO_PUER_P array + type PIO_PIO_PUER_P_Field_Array is array (0 .. 31) of Boolean + with Component_Size => 1, Size => 32; + + -- Pull-up Enable Register + type PIO_PIO_PUER_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- P as a value + Val : HAL.UInt32; + when True => + -- P as an array + Arr : PIO_PIO_PUER_P_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, + Bit_Order => System.Low_Order_First; + + for PIO_PIO_PUER_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- PIO_PIO_PUSR_P array + type PIO_PIO_PUSR_P_Field_Array is array (0 .. 31) of Boolean + with Component_Size => 1, Size => 32; + + -- Pad Pull-up Status Register + type PIO_PIO_PUSR_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- P as a value + Val : HAL.UInt32; + when True => + -- P as an array + Arr : PIO_PIO_PUSR_P_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, + Bit_Order => System.Low_Order_First; + + for PIO_PIO_PUSR_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- PIO_PIO_ABCDSR_P array + type PIO_PIO_ABCDSR_P_Field_Array is array (0 .. 31) of Boolean + with Component_Size => 1, Size => 32; + + -- Peripheral ABCD Select Register 0 + type PIO_PIO_ABCDSR_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- P as a value + Val : HAL.UInt32; + when True => + -- P as an array + Arr : PIO_PIO_ABCDSR_P_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, + Bit_Order => System.Low_Order_First; + + for PIO_PIO_ABCDSR_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- Peripheral ABCD Select Register 0 + type PIO_PIO_ABCDSR_Registers is array (0 .. 1) of PIO_PIO_ABCDSR_Register + with Volatile; + + -- PIO_PIO_IFSCDR_P array + type PIO_PIO_IFSCDR_P_Field_Array is array (0 .. 31) of Boolean + with Component_Size => 1, Size => 32; + + -- Input Filter Slow Clock Disable Register + type PIO_PIO_IFSCDR_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- P as a value + Val : HAL.UInt32; + when True => + -- P as an array + Arr : PIO_PIO_IFSCDR_P_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, + Bit_Order => System.Low_Order_First; + + for PIO_PIO_IFSCDR_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- PIO_PIO_IFSCER_P array + type PIO_PIO_IFSCER_P_Field_Array is array (0 .. 31) of Boolean + with Component_Size => 1, Size => 32; + + -- Input Filter Slow Clock Enable Register + type PIO_PIO_IFSCER_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- P as a value + Val : HAL.UInt32; + when True => + -- P as an array + Arr : PIO_PIO_IFSCER_P_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, + Bit_Order => System.Low_Order_First; + + for PIO_PIO_IFSCER_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- PIO_PIO_IFSCSR_P array + type PIO_PIO_IFSCSR_P_Field_Array is array (0 .. 31) of Boolean + with Component_Size => 1, Size => 32; + + -- Input Filter Slow Clock Status Register + type PIO_PIO_IFSCSR_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- P as a value + Val : HAL.UInt32; + when True => + -- P as an array + Arr : PIO_PIO_IFSCSR_P_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, + Bit_Order => System.Low_Order_First; + + for PIO_PIO_IFSCSR_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + subtype PIO_PIO_SCDR_DIV_Field is HAL.UInt14; + + -- Slow Clock Divider Debouncing Register + type PIO_PIO_SCDR_Register is record + -- Slow Clock Divider Selection for Debouncing + DIV : PIO_PIO_SCDR_DIV_Field := 16#0#; + -- unspecified + Reserved_14_31 : HAL.UInt18 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PIO_PIO_SCDR_Register use record + DIV at 0 range 0 .. 13; + Reserved_14_31 at 0 range 14 .. 31; + end record; + + -- PIO_PIO_PPDDR_P array + type PIO_PIO_PPDDR_P_Field_Array is array (0 .. 31) of Boolean + with Component_Size => 1, Size => 32; + + -- Pad Pull-down Disable Register + type PIO_PIO_PPDDR_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- P as a value + Val : HAL.UInt32; + when True => + -- P as an array + Arr : PIO_PIO_PPDDR_P_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, + Bit_Order => System.Low_Order_First; + + for PIO_PIO_PPDDR_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- PIO_PIO_PPDER_P array + type PIO_PIO_PPDER_P_Field_Array is array (0 .. 31) of Boolean + with Component_Size => 1, Size => 32; + + -- Pad Pull-down Enable Register + type PIO_PIO_PPDER_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- P as a value + Val : HAL.UInt32; + when True => + -- P as an array + Arr : PIO_PIO_PPDER_P_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, + Bit_Order => System.Low_Order_First; + + for PIO_PIO_PPDER_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- PIO_PIO_PPDSR_P array + type PIO_PIO_PPDSR_P_Field_Array is array (0 .. 31) of Boolean + with Component_Size => 1, Size => 32; + + -- Pad Pull-down Status Register + type PIO_PIO_PPDSR_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- P as a value + Val : HAL.UInt32; + when True => + -- P as an array + Arr : PIO_PIO_PPDSR_P_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, + Bit_Order => System.Low_Order_First; + + for PIO_PIO_PPDSR_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- PIO_PIO_OWER_P array + type PIO_PIO_OWER_P_Field_Array is array (0 .. 31) of Boolean + with Component_Size => 1, Size => 32; + + -- Output Write Enable + type PIO_PIO_OWER_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- P as a value + Val : HAL.UInt32; + when True => + -- P as an array + Arr : PIO_PIO_OWER_P_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, + Bit_Order => System.Low_Order_First; + + for PIO_PIO_OWER_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- PIO_PIO_OWDR_P array + type PIO_PIO_OWDR_P_Field_Array is array (0 .. 31) of Boolean + with Component_Size => 1, Size => 32; + + -- Output Write Disable + type PIO_PIO_OWDR_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- P as a value + Val : HAL.UInt32; + when True => + -- P as an array + Arr : PIO_PIO_OWDR_P_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, + Bit_Order => System.Low_Order_First; + + for PIO_PIO_OWDR_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- PIO_PIO_OWSR_P array + type PIO_PIO_OWSR_P_Field_Array is array (0 .. 31) of Boolean + with Component_Size => 1, Size => 32; + + -- Output Write Status Register + type PIO_PIO_OWSR_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- P as a value + Val : HAL.UInt32; + when True => + -- P as an array + Arr : PIO_PIO_OWSR_P_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, + Bit_Order => System.Low_Order_First; + + for PIO_PIO_OWSR_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- PIO_PIO_AIMER_P array + type PIO_PIO_AIMER_P_Field_Array is array (0 .. 31) of Boolean + with Component_Size => 1, Size => 32; + + -- Additional Interrupt Modes Enable Register + type PIO_PIO_AIMER_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- P as a value + Val : HAL.UInt32; + when True => + -- P as an array + Arr : PIO_PIO_AIMER_P_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, + Bit_Order => System.Low_Order_First; + + for PIO_PIO_AIMER_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- PIO_PIO_AIMDR_P array + type PIO_PIO_AIMDR_P_Field_Array is array (0 .. 31) of Boolean + with Component_Size => 1, Size => 32; + + -- Additional Interrupt Modes Disable Register + type PIO_PIO_AIMDR_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- P as a value + Val : HAL.UInt32; + when True => + -- P as an array + Arr : PIO_PIO_AIMDR_P_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, + Bit_Order => System.Low_Order_First; + + for PIO_PIO_AIMDR_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- PIO_PIO_AIMMR_P array + type PIO_PIO_AIMMR_P_Field_Array is array (0 .. 31) of Boolean + with Component_Size => 1, Size => 32; + + -- Additional Interrupt Modes Mask Register + type PIO_PIO_AIMMR_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- P as a value + Val : HAL.UInt32; + when True => + -- P as an array + Arr : PIO_PIO_AIMMR_P_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, + Bit_Order => System.Low_Order_First; + + for PIO_PIO_AIMMR_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- PIO_PIO_ESR_P array + type PIO_PIO_ESR_P_Field_Array is array (0 .. 31) of Boolean + with Component_Size => 1, Size => 32; + + -- Edge Select Register + type PIO_PIO_ESR_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- P as a value + Val : HAL.UInt32; + when True => + -- P as an array + Arr : PIO_PIO_ESR_P_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, + Bit_Order => System.Low_Order_First; + + for PIO_PIO_ESR_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- PIO_PIO_LSR_P array + type PIO_PIO_LSR_P_Field_Array is array (0 .. 31) of Boolean + with Component_Size => 1, Size => 32; + + -- Level Select Register + type PIO_PIO_LSR_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- P as a value + Val : HAL.UInt32; + when True => + -- P as an array + Arr : PIO_PIO_LSR_P_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, + Bit_Order => System.Low_Order_First; + + for PIO_PIO_LSR_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- PIO_PIO_ELSR_P array + type PIO_PIO_ELSR_P_Field_Array is array (0 .. 31) of Boolean + with Component_Size => 1, Size => 32; + + -- Edge/Level Status Register + type PIO_PIO_ELSR_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- P as a value + Val : HAL.UInt32; + when True => + -- P as an array + Arr : PIO_PIO_ELSR_P_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, + Bit_Order => System.Low_Order_First; + + for PIO_PIO_ELSR_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- PIO_PIO_FELLSR_P array + type PIO_PIO_FELLSR_P_Field_Array is array (0 .. 31) of Boolean + with Component_Size => 1, Size => 32; + + -- Falling Edge/Low-Level Select Register + type PIO_PIO_FELLSR_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- P as a value + Val : HAL.UInt32; + when True => + -- P as an array + Arr : PIO_PIO_FELLSR_P_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, + Bit_Order => System.Low_Order_First; + + for PIO_PIO_FELLSR_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- PIO_PIO_REHLSR_P array + type PIO_PIO_REHLSR_P_Field_Array is array (0 .. 31) of Boolean + with Component_Size => 1, Size => 32; + + -- Rising Edge/High-Level Select Register + type PIO_PIO_REHLSR_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- P as a value + Val : HAL.UInt32; + when True => + -- P as an array + Arr : PIO_PIO_REHLSR_P_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, + Bit_Order => System.Low_Order_First; + + for PIO_PIO_REHLSR_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- PIO_PIO_FRLHSR_P array + type PIO_PIO_FRLHSR_P_Field_Array is array (0 .. 31) of Boolean + with Component_Size => 1, Size => 32; + + -- Fall/Rise - Low/High Status Register + type PIO_PIO_FRLHSR_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- P as a value + Val : HAL.UInt32; + when True => + -- P as an array + Arr : PIO_PIO_FRLHSR_P_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, + Bit_Order => System.Low_Order_First; + + for PIO_PIO_FRLHSR_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- PIO_PIO_LOCKSR_P array + type PIO_PIO_LOCKSR_P_Field_Array is array (0 .. 31) of Boolean + with Component_Size => 1, Size => 32; + + -- Lock Status + type PIO_PIO_LOCKSR_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- P as a value + Val : HAL.UInt32; + when True => + -- P as an array + Arr : PIO_PIO_LOCKSR_P_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, + Bit_Order => System.Low_Order_First; + + for PIO_PIO_LOCKSR_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- Write Protection Key + type PIO_WPMR_WPKEY_Field is + ( + -- Reset value for the field + Pio_Wpmr_Wpkey_Field_Reset, + -- Writing any other value in this field aborts the write operation of + -- the WPEN bit.Always reads as 0. + Passwd) + with Size => 24; + for PIO_WPMR_WPKEY_Field use + (Pio_Wpmr_Wpkey_Field_Reset => 0, + Passwd => 5261647); + + -- Write Protection Mode Register + type PIO_PIO_WPMR_Register is record + -- Write Protection Enable + WPEN : Boolean := False; + -- unspecified + Reserved_1_7 : HAL.UInt7 := 16#0#; + -- Write Protection Key + WPKEY : PIO_WPMR_WPKEY_Field := Pio_Wpmr_Wpkey_Field_Reset; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PIO_PIO_WPMR_Register use record + WPEN at 0 range 0 .. 0; + Reserved_1_7 at 0 range 1 .. 7; + WPKEY at 0 range 8 .. 31; + end record; + + subtype PIO_PIO_WPSR_WPVSRC_Field is HAL.UInt16; + + -- Write Protection Status Register + type PIO_PIO_WPSR_Register is record + -- Read-only. Write Protection Violation Status + WPVS : Boolean; + -- unspecified + Reserved_1_7 : HAL.UInt7; + -- Read-only. Write Protection Violation Source + WPVSRC : PIO_PIO_WPSR_WPVSRC_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PIO_PIO_WPSR_Register use record + WPVS at 0 range 0 .. 0; + Reserved_1_7 at 0 range 1 .. 7; + WPVSRC at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype PIO_PIO_VERSION_VERSION_Field is HAL.UInt12; + subtype PIO_PIO_VERSION_MFN_Field is HAL.UInt3; + + -- Version Register + type PIO_PIO_VERSION_Register is record + -- Read-only. Hardware Module Version + VERSION : PIO_PIO_VERSION_VERSION_Field; + -- unspecified + Reserved_12_15 : HAL.UInt4; + -- Read-only. Metal Fix Number + MFN : PIO_PIO_VERSION_MFN_Field; + -- unspecified + Reserved_19_31 : HAL.UInt13; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PIO_PIO_VERSION_Register use record + VERSION at 0 range 0 .. 11; + Reserved_12_15 at 0 range 12 .. 15; + MFN at 0 range 16 .. 18; + Reserved_19_31 at 0 range 19 .. 31; + end record; + + -- PIO_PIO_SCHMITT_SCHMITT array + type PIO_PIO_SCHMITT_SCHMITT_Field_Array is array (0 .. 31) of Boolean + with Component_Size => 1, Size => 32; + + -- Schmitt Trigger Register + type PIO_PIO_SCHMITT_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- SCHMITT as a value + Val : HAL.UInt32; + when True => + -- SCHMITT as an array + Arr : PIO_PIO_SCHMITT_SCHMITT_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, + Bit_Order => System.Low_Order_First; + + for PIO_PIO_SCHMITT_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- Drive of PIO Line 0 + type PIO_DRIVER_LINE0_Field is + ( + -- Lowest drive + Low_Drive, + -- Highest drive + High_Drive) + with Size => 1; + for PIO_DRIVER_LINE0_Field use + (Low_Drive => 0, + High_Drive => 1); + + -- PIO_PIO_DRIVER_LINE array + type PIO_PIO_DRIVER_LINE_Field_Array is array (0 .. 31) + of PIO_DRIVER_LINE0_Field + with Component_Size => 1, Size => 32; + + -- I/O Drive Register + type PIO_PIO_DRIVER_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- LINE as a value + Val : HAL.UInt32; + when True => + -- LINE as an array + Arr : PIO_PIO_DRIVER_LINE_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, + Bit_Order => System.Low_Order_First; + + for PIO_PIO_DRIVER_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- Parallel Capture Mode Data Size + type PIO_PCMR_DSIZE_Field is + ( + -- The reception data in the PIO_PCRHR is a byte (8-bit) + Byte, + -- The reception data in the PIO_PCRHR is a half-word (16-bit) + Halfword, + -- The reception data in the PIO_PCRHR is a word (32-bit) + Word) + with Size => 2; + for PIO_PCMR_DSIZE_Field use + (Byte => 0, + Halfword => 1, + Word => 2); + + -- Parallel Capture Mode Register + type PIO_PIO_PCMR_Register is record + -- Parallel Capture Mode Enable + PCEN : Boolean := False; + -- unspecified + Reserved_1_3 : HAL.UInt3 := 16#0#; + -- Parallel Capture Mode Data Size + DSIZE : PIO_PCMR_DSIZE_Field := SAM_SVD.PIO.Byte; + -- unspecified + Reserved_6_8 : HAL.UInt3 := 16#0#; + -- Parallel Capture Mode Always Sampling + ALWYS : Boolean := False; + -- Parallel Capture Mode Half Sampling + HALFS : Boolean := False; + -- Parallel Capture Mode First Sample + FRSTS : Boolean := False; + -- unspecified + Reserved_12_31 : HAL.UInt20 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PIO_PIO_PCMR_Register use record + PCEN at 0 range 0 .. 0; + Reserved_1_3 at 0 range 1 .. 3; + DSIZE at 0 range 4 .. 5; + Reserved_6_8 at 0 range 6 .. 8; + ALWYS at 0 range 9 .. 9; + HALFS at 0 range 10 .. 10; + FRSTS at 0 range 11 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + -- Parallel Capture Interrupt Enable Register + type PIO_PIO_PCIER_Register is record + -- Write-only. Parallel Capture Mode Data Ready Interrupt Enable + DRDY : Boolean := False; + -- Write-only. Parallel Capture Mode Overrun Error Interrupt Enable + OVRE : Boolean := False; + -- Write-only. End of Reception Transfer Interrupt Enable + ENDRX : Boolean := False; + -- Write-only. Reception Buffer Full Interrupt Enable + RXBUFF : Boolean := False; + -- unspecified + Reserved_4_31 : HAL.UInt28 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PIO_PIO_PCIER_Register use record + DRDY at 0 range 0 .. 0; + OVRE at 0 range 1 .. 1; + ENDRX at 0 range 2 .. 2; + RXBUFF at 0 range 3 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + -- Parallel Capture Interrupt Disable Register + type PIO_PIO_PCIDR_Register is record + -- Write-only. Parallel Capture Mode Data Ready Interrupt Disable + DRDY : Boolean := False; + -- Write-only. Parallel Capture Mode Overrun Error Interrupt Disable + OVRE : Boolean := False; + -- Write-only. End of Reception Transfer Interrupt Disable + ENDRX : Boolean := False; + -- Write-only. Reception Buffer Full Interrupt Disable + RXBUFF : Boolean := False; + -- unspecified + Reserved_4_31 : HAL.UInt28 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PIO_PIO_PCIDR_Register use record + DRDY at 0 range 0 .. 0; + OVRE at 0 range 1 .. 1; + ENDRX at 0 range 2 .. 2; + RXBUFF at 0 range 3 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + -- Parallel Capture Interrupt Mask Register + type PIO_PIO_PCIMR_Register is record + -- Read-only. Parallel Capture Mode Data Ready Interrupt Mask + DRDY : Boolean; + -- Read-only. Parallel Capture Mode Overrun Error Interrupt Mask + OVRE : Boolean; + -- Read-only. End of Reception Transfer Interrupt Mask + ENDRX : Boolean; + -- Read-only. Reception Buffer Full Interrupt Mask + RXBUFF : Boolean; + -- unspecified + Reserved_4_31 : HAL.UInt28; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PIO_PIO_PCIMR_Register use record + DRDY at 0 range 0 .. 0; + OVRE at 0 range 1 .. 1; + ENDRX at 0 range 2 .. 2; + RXBUFF at 0 range 3 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + -- Parallel Capture Interrupt Status Register + type PIO_PIO_PCISR_Register is record + -- Read-only. Parallel Capture Mode Data Ready + DRDY : Boolean; + -- Read-only. Parallel Capture Mode Overrun Error + OVRE : Boolean; + -- unspecified + Reserved_2_31 : HAL.UInt30; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PIO_PIO_PCISR_Register use record + DRDY at 0 range 0 .. 0; + OVRE at 0 range 1 .. 1; + Reserved_2_31 at 0 range 2 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- Parallel Input/Output Controller + type PIO_Peripheral is record + -- PIO Enable Register + PIO_PER : aliased PIO_PIO_PER_Register; + -- PIO Disable Register + PIO_PDR : aliased PIO_PIO_PDR_Register; + -- PIO Status Register + PIO_PSR : aliased PIO_PIO_PSR_Register; + -- Output Enable Register + PIO_OER : aliased PIO_PIO_OER_Register; + -- Output Disable Register + PIO_ODR : aliased PIO_PIO_ODR_Register; + -- Output Status Register + PIO_OSR : aliased PIO_PIO_OSR_Register; + -- Glitch Input Filter Enable Register + PIO_IFER : aliased PIO_PIO_IFER_Register; + -- Glitch Input Filter Disable Register + PIO_IFDR : aliased PIO_PIO_IFDR_Register; + -- Glitch Input Filter Status Register + PIO_IFSR : aliased PIO_PIO_IFSR_Register; + -- Set Output Data Register + PIO_SODR : aliased PIO_PIO_SODR_Register; + -- Clear Output Data Register + PIO_CODR : aliased PIO_PIO_CODR_Register; + -- Output Data Status Register + PIO_ODSR : aliased PIO_PIO_ODSR_Register; + -- Pin Data Status Register + PIO_PDSR : aliased PIO_PIO_PDSR_Register; + -- Interrupt Enable Register + PIO_IER : aliased PIO_PIO_IER_Register; + -- Interrupt Disable Register + PIO_IDR : aliased PIO_PIO_IDR_Register; + -- Interrupt Mask Register + PIO_IMR : aliased PIO_PIO_IMR_Register; + -- Interrupt Status Register + PIO_ISR : aliased PIO_PIO_ISR_Register; + -- Multi-driver Enable Register + PIO_MDER : aliased PIO_PIO_MDER_Register; + -- Multi-driver Disable Register + PIO_MDDR : aliased PIO_PIO_MDDR_Register; + -- Multi-driver Status Register + PIO_MDSR : aliased PIO_PIO_MDSR_Register; + -- Pull-up Disable Register + PIO_PUDR : aliased PIO_PIO_PUDR_Register; + -- Pull-up Enable Register + PIO_PUER : aliased PIO_PIO_PUER_Register; + -- Pad Pull-up Status Register + PIO_PUSR : aliased PIO_PIO_PUSR_Register; + -- Peripheral ABCD Select Register 0 + PIO_ABCDSR : aliased PIO_PIO_ABCDSR_Registers; + -- Input Filter Slow Clock Disable Register + PIO_IFSCDR : aliased PIO_PIO_IFSCDR_Register; + -- Input Filter Slow Clock Enable Register + PIO_IFSCER : aliased PIO_PIO_IFSCER_Register; + -- Input Filter Slow Clock Status Register + PIO_IFSCSR : aliased PIO_PIO_IFSCSR_Register; + -- Slow Clock Divider Debouncing Register + PIO_SCDR : aliased PIO_PIO_SCDR_Register; + -- Pad Pull-down Disable Register + PIO_PPDDR : aliased PIO_PIO_PPDDR_Register; + -- Pad Pull-down Enable Register + PIO_PPDER : aliased PIO_PIO_PPDER_Register; + -- Pad Pull-down Status Register + PIO_PPDSR : aliased PIO_PIO_PPDSR_Register; + -- Output Write Enable + PIO_OWER : aliased PIO_PIO_OWER_Register; + -- Output Write Disable + PIO_OWDR : aliased PIO_PIO_OWDR_Register; + -- Output Write Status Register + PIO_OWSR : aliased PIO_PIO_OWSR_Register; + -- Additional Interrupt Modes Enable Register + PIO_AIMER : aliased PIO_PIO_AIMER_Register; + -- Additional Interrupt Modes Disable Register + PIO_AIMDR : aliased PIO_PIO_AIMDR_Register; + -- Additional Interrupt Modes Mask Register + PIO_AIMMR : aliased PIO_PIO_AIMMR_Register; + -- Edge Select Register + PIO_ESR : aliased PIO_PIO_ESR_Register; + -- Level Select Register + PIO_LSR : aliased PIO_PIO_LSR_Register; + -- Edge/Level Status Register + PIO_ELSR : aliased PIO_PIO_ELSR_Register; + -- Falling Edge/Low-Level Select Register + PIO_FELLSR : aliased PIO_PIO_FELLSR_Register; + -- Rising Edge/High-Level Select Register + PIO_REHLSR : aliased PIO_PIO_REHLSR_Register; + -- Fall/Rise - Low/High Status Register + PIO_FRLHSR : aliased PIO_PIO_FRLHSR_Register; + -- Lock Status + PIO_LOCKSR : aliased PIO_PIO_LOCKSR_Register; + -- Write Protection Mode Register + PIO_WPMR : aliased PIO_PIO_WPMR_Register; + -- Write Protection Status Register + PIO_WPSR : aliased PIO_PIO_WPSR_Register; + -- Version Register + PIO_VERSION : aliased PIO_PIO_VERSION_Register; + -- Schmitt Trigger Register + PIO_SCHMITT : aliased PIO_PIO_SCHMITT_Register; + -- I/O Drive Register + PIO_DRIVER : aliased PIO_PIO_DRIVER_Register; + -- Parallel Capture Mode Register + PIO_PCMR : aliased PIO_PIO_PCMR_Register; + -- Parallel Capture Interrupt Enable Register + PIO_PCIER : aliased PIO_PIO_PCIER_Register; + -- Parallel Capture Interrupt Disable Register + PIO_PCIDR : aliased PIO_PIO_PCIDR_Register; + -- Parallel Capture Interrupt Mask Register + PIO_PCIMR : aliased PIO_PIO_PCIMR_Register; + -- Parallel Capture Interrupt Status Register + PIO_PCISR : aliased PIO_PIO_PCISR_Register; + -- Parallel Capture Reception Holding Register + PIO_PCRHR : aliased HAL.UInt32; + end record + with Volatile; + + for PIO_Peripheral use record + PIO_PER at 16#0# range 0 .. 31; + PIO_PDR at 16#4# range 0 .. 31; + PIO_PSR at 16#8# range 0 .. 31; + PIO_OER at 16#10# range 0 .. 31; + PIO_ODR at 16#14# range 0 .. 31; + PIO_OSR at 16#18# range 0 .. 31; + PIO_IFER at 16#20# range 0 .. 31; + PIO_IFDR at 16#24# range 0 .. 31; + PIO_IFSR at 16#28# range 0 .. 31; + PIO_SODR at 16#30# range 0 .. 31; + PIO_CODR at 16#34# range 0 .. 31; + PIO_ODSR at 16#38# range 0 .. 31; + PIO_PDSR at 16#3C# range 0 .. 31; + PIO_IER at 16#40# range 0 .. 31; + PIO_IDR at 16#44# range 0 .. 31; + PIO_IMR at 16#48# range 0 .. 31; + PIO_ISR at 16#4C# range 0 .. 31; + PIO_MDER at 16#50# range 0 .. 31; + PIO_MDDR at 16#54# range 0 .. 31; + PIO_MDSR at 16#58# range 0 .. 31; + PIO_PUDR at 16#60# range 0 .. 31; + PIO_PUER at 16#64# range 0 .. 31; + PIO_PUSR at 16#68# range 0 .. 31; + PIO_ABCDSR at 16#70# range 0 .. 63; + PIO_IFSCDR at 16#80# range 0 .. 31; + PIO_IFSCER at 16#84# range 0 .. 31; + PIO_IFSCSR at 16#88# range 0 .. 31; + PIO_SCDR at 16#8C# range 0 .. 31; + PIO_PPDDR at 16#90# range 0 .. 31; + PIO_PPDER at 16#94# range 0 .. 31; + PIO_PPDSR at 16#98# range 0 .. 31; + PIO_OWER at 16#A0# range 0 .. 31; + PIO_OWDR at 16#A4# range 0 .. 31; + PIO_OWSR at 16#A8# range 0 .. 31; + PIO_AIMER at 16#B0# range 0 .. 31; + PIO_AIMDR at 16#B4# range 0 .. 31; + PIO_AIMMR at 16#B8# range 0 .. 31; + PIO_ESR at 16#C0# range 0 .. 31; + PIO_LSR at 16#C4# range 0 .. 31; + PIO_ELSR at 16#C8# range 0 .. 31; + PIO_FELLSR at 16#D0# range 0 .. 31; + PIO_REHLSR at 16#D4# range 0 .. 31; + PIO_FRLHSR at 16#D8# range 0 .. 31; + PIO_LOCKSR at 16#E0# range 0 .. 31; + PIO_WPMR at 16#E4# range 0 .. 31; + PIO_WPSR at 16#E8# range 0 .. 31; + PIO_VERSION at 16#FC# range 0 .. 31; + PIO_SCHMITT at 16#100# range 0 .. 31; + PIO_DRIVER at 16#118# range 0 .. 31; + PIO_PCMR at 16#150# range 0 .. 31; + PIO_PCIER at 16#154# range 0 .. 31; + PIO_PCIDR at 16#158# range 0 .. 31; + PIO_PCIMR at 16#15C# range 0 .. 31; + PIO_PCISR at 16#160# range 0 .. 31; + PIO_PCRHR at 16#164# range 0 .. 31; + end record; + + -- Parallel Input/Output Controller + PIOA_Periph : aliased PIO_Peripheral + with Import, Address => System'To_Address (16#400E0E00#); + + -- Parallel Input/Output Controller + PIOB_Periph : aliased PIO_Peripheral + with Import, Address => System'To_Address (16#400E1000#); + + -- Parallel Input/Output Controller + PIOC_Periph : aliased PIO_Peripheral + with Import, Address => System'To_Address (16#400E1200#); + + -- Parallel Input/Output Controller + PIOD_Periph : aliased PIO_Peripheral + with Import, Address => System'To_Address (16#400E1400#); + + -- Parallel Input/Output Controller + PIOE_Periph : aliased PIO_Peripheral + with Import, Address => System'To_Address (16#400E1600#); + +end SAM_SVD.PIO; diff --git a/arch/ARM/SAM/svd/atsamv71/sam_svd-pmc.ads b/arch/ARM/SAM/svd/atsamv71/sam_svd-pmc.ads new file mode 100644 index 000000000..b7cbeeb5d --- /dev/null +++ b/arch/ARM/SAM/svd/atsamv71/sam_svd-pmc.ads @@ -0,0 +1,2380 @@ +-- This spec has been automatically generated from ATSAMV71Q21.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package SAM_SVD.PMC is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + -- PMC_PMC_SCER_PCK array + type PMC_PMC_SCER_PCK_Field_Array is array (0 .. 6) of Boolean + with Component_Size => 1, Size => 7; + + -- Type definition for PMC_PMC_SCER_PCK + type PMC_PMC_SCER_PCK_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- PCK as a value + Val : HAL.UInt7; + when True => + -- PCK as an array + Arr : PMC_PMC_SCER_PCK_Field_Array; + end case; + end record + with Unchecked_Union, Size => 7; + + for PMC_PMC_SCER_PCK_Field use record + Val at 0 range 0 .. 6; + Arr at 0 range 0 .. 6; + end record; + + -- System Clock Enable Register + type PMC_PMC_SCER_Register is record + -- unspecified + Reserved_0_4 : HAL.UInt5 := 16#0#; + -- Write-only. Enable USB FS Clock + USBCLK : Boolean := False; + -- unspecified + Reserved_6_7 : HAL.UInt2 := 16#0#; + -- Write-only. Programmable Clock 0 Output Enable + PCK : PMC_PMC_SCER_PCK_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_15_31 : HAL.UInt17 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PMC_PMC_SCER_Register use record + Reserved_0_4 at 0 range 0 .. 4; + USBCLK at 0 range 5 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + PCK at 0 range 8 .. 14; + Reserved_15_31 at 0 range 15 .. 31; + end record; + + -- PMC_PMC_SCDR_PCK array + type PMC_PMC_SCDR_PCK_Field_Array is array (0 .. 6) of Boolean + with Component_Size => 1, Size => 7; + + -- Type definition for PMC_PMC_SCDR_PCK + type PMC_PMC_SCDR_PCK_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- PCK as a value + Val : HAL.UInt7; + when True => + -- PCK as an array + Arr : PMC_PMC_SCDR_PCK_Field_Array; + end case; + end record + with Unchecked_Union, Size => 7; + + for PMC_PMC_SCDR_PCK_Field use record + Val at 0 range 0 .. 6; + Arr at 0 range 0 .. 6; + end record; + + -- System Clock Disable Register + type PMC_PMC_SCDR_Register is record + -- unspecified + Reserved_0_4 : HAL.UInt5 := 16#0#; + -- Write-only. Disable USB FS Clock + USBCLK : Boolean := False; + -- unspecified + Reserved_6_7 : HAL.UInt2 := 16#0#; + -- Write-only. Programmable Clock 0 Output Disable + PCK : PMC_PMC_SCDR_PCK_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_15_31 : HAL.UInt17 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PMC_PMC_SCDR_Register use record + Reserved_0_4 at 0 range 0 .. 4; + USBCLK at 0 range 5 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + PCK at 0 range 8 .. 14; + Reserved_15_31 at 0 range 15 .. 31; + end record; + + -- PMC_PMC_SCSR_PCK array + type PMC_PMC_SCSR_PCK_Field_Array is array (0 .. 6) of Boolean + with Component_Size => 1, Size => 7; + + -- Type definition for PMC_PMC_SCSR_PCK + type PMC_PMC_SCSR_PCK_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- PCK as a value + Val : HAL.UInt7; + when True => + -- PCK as an array + Arr : PMC_PMC_SCSR_PCK_Field_Array; + end case; + end record + with Unchecked_Union, Size => 7; + + for PMC_PMC_SCSR_PCK_Field use record + Val at 0 range 0 .. 6; + Arr at 0 range 0 .. 6; + end record; + + -- System Clock Status Register + type PMC_PMC_SCSR_Register is record + -- Read-only. HCLK Status + HCLKS : Boolean; + -- unspecified + Reserved_1_4 : HAL.UInt4; + -- Read-only. USB FS Clock Status + USBCLK : Boolean; + -- unspecified + Reserved_6_7 : HAL.UInt2; + -- Read-only. Programmable Clock 0 Output Status + PCK : PMC_PMC_SCSR_PCK_Field; + -- unspecified + Reserved_15_31 : HAL.UInt17; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PMC_PMC_SCSR_Register use record + HCLKS at 0 range 0 .. 0; + Reserved_1_4 at 0 range 1 .. 4; + USBCLK at 0 range 5 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + PCK at 0 range 8 .. 14; + Reserved_15_31 at 0 range 15 .. 31; + end record; + + -- PMC_PMC_PCER0_PID array + type PMC_PMC_PCER0_PID_Field_Array is array (7 .. 31) of Boolean + with Component_Size => 1, Size => 25; + + -- Type definition for PMC_PMC_PCER0_PID + type PMC_PMC_PCER0_PID_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- PID as a value + Val : HAL.UInt25; + when True => + -- PID as an array + Arr : PMC_PMC_PCER0_PID_Field_Array; + end case; + end record + with Unchecked_Union, Size => 25; + + for PMC_PMC_PCER0_PID_Field use record + Val at 0 range 0 .. 24; + Arr at 0 range 0 .. 24; + end record; + + -- Peripheral Clock Enable Register 0 + type PMC_PMC_PCER0_Register is record + -- unspecified + Reserved_0_6 : HAL.UInt7 := 16#0#; + -- Write-only. Peripheral Clock 7 Enable + PID : PMC_PMC_PCER0_PID_Field := + (As_Array => False, Val => 16#0#); + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PMC_PMC_PCER0_Register use record + Reserved_0_6 at 0 range 0 .. 6; + PID at 0 range 7 .. 31; + end record; + + -- PMC_PMC_PCDR0_PID array + type PMC_PMC_PCDR0_PID_Field_Array is array (7 .. 31) of Boolean + with Component_Size => 1, Size => 25; + + -- Type definition for PMC_PMC_PCDR0_PID + type PMC_PMC_PCDR0_PID_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- PID as a value + Val : HAL.UInt25; + when True => + -- PID as an array + Arr : PMC_PMC_PCDR0_PID_Field_Array; + end case; + end record + with Unchecked_Union, Size => 25; + + for PMC_PMC_PCDR0_PID_Field use record + Val at 0 range 0 .. 24; + Arr at 0 range 0 .. 24; + end record; + + -- Peripheral Clock Disable Register 0 + type PMC_PMC_PCDR0_Register is record + -- unspecified + Reserved_0_6 : HAL.UInt7 := 16#0#; + -- Write-only. Peripheral Clock 7 Disable + PID : PMC_PMC_PCDR0_PID_Field := + (As_Array => False, Val => 16#0#); + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PMC_PMC_PCDR0_Register use record + Reserved_0_6 at 0 range 0 .. 6; + PID at 0 range 7 .. 31; + end record; + + -- PMC_PMC_PCSR0_PID array + type PMC_PMC_PCSR0_PID_Field_Array is array (7 .. 31) of Boolean + with Component_Size => 1, Size => 25; + + -- Type definition for PMC_PMC_PCSR0_PID + type PMC_PMC_PCSR0_PID_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- PID as a value + Val : HAL.UInt25; + when True => + -- PID as an array + Arr : PMC_PMC_PCSR0_PID_Field_Array; + end case; + end record + with Unchecked_Union, Size => 25; + + for PMC_PMC_PCSR0_PID_Field use record + Val at 0 range 0 .. 24; + Arr at 0 range 0 .. 24; + end record; + + -- Peripheral Clock Status Register 0 + type PMC_PMC_PCSR0_Register is record + -- unspecified + Reserved_0_6 : HAL.UInt7; + -- Read-only. Peripheral Clock 7 Status + PID : PMC_PMC_PCSR0_PID_Field; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PMC_PMC_PCSR0_Register use record + Reserved_0_6 at 0 range 0 .. 6; + PID at 0 range 7 .. 31; + end record; + + subtype PMC_CKGR_UCKR_UPLLCOUNT_Field is HAL.UInt4; + + -- UTMI Clock Register + type PMC_CKGR_UCKR_Register is record + -- unspecified + Reserved_0_15 : HAL.UInt16 := 16#0#; + -- UTMI PLL Enable + UPLLEN : Boolean := False; + -- unspecified + Reserved_17_19 : HAL.UInt3 := 16#0#; + -- UTMI PLL Startup Time + UPLLCOUNT : PMC_CKGR_UCKR_UPLLCOUNT_Field := 16#0#; + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PMC_CKGR_UCKR_Register use record + Reserved_0_15 at 0 range 0 .. 15; + UPLLEN at 0 range 16 .. 16; + Reserved_17_19 at 0 range 17 .. 19; + UPLLCOUNT at 0 range 20 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- Main RC Oscillator Frequency Selection + type CKGR_MOR_MOSCRCF_Field is + ( + -- The RC oscillator frequency is at 4 MHz + Val_4_Mhz, + -- The RC oscillator frequency is at 8 MHz + Val_8_Mhz, + -- The RC oscillator frequency is at 12 MHz + Val_12_Mhz) + with Size => 3; + for CKGR_MOR_MOSCRCF_Field use + (Val_4_Mhz => 0, + Val_8_Mhz => 1, + Val_12_Mhz => 2); + + subtype PMC_CKGR_MOR_MOSCXTST_Field is HAL.UInt8; + + -- Write Access Password + type CKGR_MOR_KEY_Field is + ( + -- Reset value for the field + Ckgr_Mor_Key_Field_Reset, + -- Writing any other value in this field aborts the write + -- operation.Always reads as 0. + Passwd) + with Size => 8; + for CKGR_MOR_KEY_Field use + (Ckgr_Mor_Key_Field_Reset => 0, + Passwd => 55); + + -- Main Oscillator Register + type PMC_CKGR_MOR_Register is record + -- Main Crystal Oscillator Enable + MOSCXTEN : Boolean := False; + -- Main Crystal Oscillator Bypass + MOSCXTBY : Boolean := False; + -- Wait Mode Command (Write-only) + WAITMODE : Boolean := False; + -- Main RC Oscillator Enable + MOSCRCEN : Boolean := False; + -- Main RC Oscillator Frequency Selection + MOSCRCF : CKGR_MOR_MOSCRCF_Field := SAM_SVD.PMC.Val_4_Mhz; + -- unspecified + Reserved_7_7 : HAL.Bit := 16#0#; + -- Main Crystal Oscillator Startup Time + MOSCXTST : PMC_CKGR_MOR_MOSCXTST_Field := 16#0#; + -- Write Access Password + KEY : CKGR_MOR_KEY_Field := Ckgr_Mor_Key_Field_Reset; + -- Main Clock Oscillator Selection + MOSCSEL : Boolean := False; + -- Clock Failure Detector Enable + CFDEN : Boolean := False; + -- 32.768 kHz Crystal Oscillator Frequency Monitoring Enable + XT32KFME : Boolean := False; + -- unspecified + Reserved_27_31 : HAL.UInt5 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PMC_CKGR_MOR_Register use record + MOSCXTEN at 0 range 0 .. 0; + MOSCXTBY at 0 range 1 .. 1; + WAITMODE at 0 range 2 .. 2; + MOSCRCEN at 0 range 3 .. 3; + MOSCRCF at 0 range 4 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + MOSCXTST at 0 range 8 .. 15; + KEY at 0 range 16 .. 23; + MOSCSEL at 0 range 24 .. 24; + CFDEN at 0 range 25 .. 25; + XT32KFME at 0 range 26 .. 26; + Reserved_27_31 at 0 range 27 .. 31; + end record; + + subtype PMC_CKGR_MCFR_MAINF_Field is HAL.UInt16; + + -- Main Clock Frequency Register + type PMC_CKGR_MCFR_Register is record + -- Main Clock Frequency + MAINF : PMC_CKGR_MCFR_MAINF_Field := 16#0#; + -- Main Clock Frequency Measure Ready + MAINFRDY : Boolean := False; + -- unspecified + Reserved_17_19 : HAL.UInt3 := 16#0#; + -- RC Oscillator Frequency Measure (write-only) + RCMEAS : Boolean := False; + -- unspecified + Reserved_21_23 : HAL.UInt3 := 16#0#; + -- Counter Clock Source Selection + CCSS : Boolean := False; + -- unspecified + Reserved_25_31 : HAL.UInt7 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PMC_CKGR_MCFR_Register use record + MAINF at 0 range 0 .. 15; + MAINFRDY at 0 range 16 .. 16; + Reserved_17_19 at 0 range 17 .. 19; + RCMEAS at 0 range 20 .. 20; + Reserved_21_23 at 0 range 21 .. 23; + CCSS at 0 range 24 .. 24; + Reserved_25_31 at 0 range 25 .. 31; + end record; + + subtype PMC_CKGR_PLLAR_DIVA_Field is HAL.UInt8; + subtype PMC_CKGR_PLLAR_PLLACOUNT_Field is HAL.UInt6; + subtype PMC_CKGR_PLLAR_MULA_Field is HAL.UInt11; + + -- PLLA Register + type PMC_CKGR_PLLAR_Register is record + -- PLLA Front End Divider + DIVA : PMC_CKGR_PLLAR_DIVA_Field := 16#0#; + -- PLLA Counter + PLLACOUNT : PMC_CKGR_PLLAR_PLLACOUNT_Field := 16#0#; + -- unspecified + Reserved_14_15 : HAL.UInt2 := 16#0#; + -- PLLA Multiplier + MULA : PMC_CKGR_PLLAR_MULA_Field := 16#0#; + -- unspecified + Reserved_27_28 : HAL.UInt2 := 16#0#; + -- Must Be Set to 1 + ONE : Boolean := False; + -- unspecified + Reserved_30_31 : HAL.UInt2 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PMC_CKGR_PLLAR_Register use record + DIVA at 0 range 0 .. 7; + PLLACOUNT at 0 range 8 .. 13; + Reserved_14_15 at 0 range 14 .. 15; + MULA at 0 range 16 .. 26; + Reserved_27_28 at 0 range 27 .. 28; + ONE at 0 range 29 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + -- Master Clock Source Selection + type PMC_MCKR_CSS_Field is + ( + -- SLCK is selected + Slow_Clk, + -- MAINCK is selected + Main_Clk, + -- PLLACK is selected + Plla_Clk, + -- UPPLLCKDIV is selected + Upll_Clk) + with Size => 2; + for PMC_MCKR_CSS_Field use + (Slow_Clk => 0, + Main_Clk => 1, + Plla_Clk => 2, + Upll_Clk => 3); + + -- Processor Clock Prescaler + type PMC_MCKR_PRES_Field is + ( + -- Selected clock + Clk_1, + -- Selected clock divided by 2 + Clk_2, + -- Selected clock divided by 4 + Clk_4, + -- Selected clock divided by 8 + Clk_8, + -- Selected clock divided by 16 + Clk_16, + -- Selected clock divided by 32 + Clk_32, + -- Selected clock divided by 64 + Clk_64, + -- Selected clock divided by 3 + Clk_3) + with Size => 3; + for PMC_MCKR_PRES_Field use + (Clk_1 => 0, + Clk_2 => 1, + Clk_4 => 2, + Clk_8 => 3, + Clk_16 => 4, + Clk_32 => 5, + Clk_64 => 6, + Clk_3 => 7); + + -- Master Clock Division + type PMC_MCKR_MDIV_Field is + ( + -- MCK is FCLK divided by 1. + Eq_Pck, + -- MCK is FCLK divided by 2. + Pck_Div2, + -- MCK is FCLK divided by 4. + Pck_Div4, + -- MCK is FCLK divided by 3. + Pck_Div3) + with Size => 2; + for PMC_MCKR_MDIV_Field use + (Eq_Pck => 0, + Pck_Div2 => 1, + Pck_Div4 => 2, + Pck_Div3 => 3); + + -- Master Clock Register + type PMC_PMC_MCKR_Register is record + -- Master Clock Source Selection + CSS : PMC_MCKR_CSS_Field := SAM_SVD.PMC.Slow_Clk; + -- unspecified + Reserved_2_3 : HAL.UInt2 := 16#0#; + -- Processor Clock Prescaler + PRES : PMC_MCKR_PRES_Field := SAM_SVD.PMC.Clk_1; + -- unspecified + Reserved_7_7 : HAL.Bit := 16#0#; + -- Master Clock Division + MDIV : PMC_MCKR_MDIV_Field := SAM_SVD.PMC.Eq_Pck; + -- unspecified + Reserved_10_12 : HAL.UInt3 := 16#0#; + -- UPLL Divider by 2 + UPLLDIV2 : Boolean := False; + -- unspecified + Reserved_14_31 : HAL.UInt18 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PMC_PMC_MCKR_Register use record + CSS at 0 range 0 .. 1; + Reserved_2_3 at 0 range 2 .. 3; + PRES at 0 range 4 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + MDIV at 0 range 8 .. 9; + Reserved_10_12 at 0 range 10 .. 12; + UPLLDIV2 at 0 range 13 .. 13; + Reserved_14_31 at 0 range 14 .. 31; + end record; + + subtype PMC_PMC_USB_USBDIV_Field is HAL.UInt4; + + -- USB Clock Register + type PMC_PMC_USB_Register is record + -- USB Input Clock Selection + USBS : Boolean := False; + -- unspecified + Reserved_1_7 : HAL.UInt7 := 16#0#; + -- Divider for USB_48M + USBDIV : PMC_PMC_USB_USBDIV_Field := 16#0#; + -- unspecified + Reserved_12_31 : HAL.UInt20 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PMC_PMC_USB_Register use record + USBS at 0 range 0 .. 0; + Reserved_1_7 at 0 range 1 .. 7; + USBDIV at 0 range 8 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + -- Programmable Clock Source Selection + type PMC_PCK_CSS_Field is + ( + -- SLCK is selected + Slow_Clk, + -- MAINCK is selected + Main_Clk, + -- PLLACK is selected + Plla_Clk, + -- UPLLCKDIV is selected + Upll_Clk, + -- MCK is selected + Mck) + with Size => 3; + for PMC_PCK_CSS_Field use + (Slow_Clk => 0, + Main_Clk => 1, + Plla_Clk => 2, + Upll_Clk => 3, + Mck => 4); + + subtype PMC_PMC_PCK_PRES_Field is HAL.UInt8; + + -- Programmable Clock Register (chid = 0) 0 + type PMC_PMC_PCK_Register is record + -- Programmable Clock Source Selection + CSS : PMC_PCK_CSS_Field := SAM_SVD.PMC.Slow_Clk; + -- unspecified + Reserved_3_3 : HAL.Bit := 16#0#; + -- Programmable Clock Prescaler + PRES : PMC_PMC_PCK_PRES_Field := 16#0#; + -- unspecified + Reserved_12_31 : HAL.UInt20 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PMC_PMC_PCK_Register use record + CSS at 0 range 0 .. 2; + Reserved_3_3 at 0 range 3 .. 3; + PRES at 0 range 4 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + -- Programmable Clock Register (chid = 0) 0 + type PMC_PMC_PCK_Registers is array (0 .. 7) of PMC_PMC_PCK_Register + with Volatile; + + -- PMC_PMC_IER_PCKRDY array + type PMC_PMC_IER_PCKRDY_Field_Array is array (0 .. 6) of Boolean + with Component_Size => 1, Size => 7; + + -- Type definition for PMC_PMC_IER_PCKRDY + type PMC_PMC_IER_PCKRDY_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- PCKRDY as a value + Val : HAL.UInt7; + when True => + -- PCKRDY as an array + Arr : PMC_PMC_IER_PCKRDY_Field_Array; + end case; + end record + with Unchecked_Union, Size => 7; + + for PMC_PMC_IER_PCKRDY_Field use record + Val at 0 range 0 .. 6; + Arr at 0 range 0 .. 6; + end record; + + -- Interrupt Enable Register + type PMC_PMC_IER_Register is record + -- Write-only. Main Crystal Oscillator Status Interrupt Enable + MOSCXTS : Boolean := False; + -- Write-only. PLLA Lock Interrupt Enable + LOCKA : Boolean := False; + -- unspecified + Reserved_2_2 : HAL.Bit := 16#0#; + -- Write-only. Master Clock Ready Interrupt Enable + MCKRDY : Boolean := False; + -- unspecified + Reserved_4_5 : HAL.UInt2 := 16#0#; + -- Write-only. UTMI PLL Lock Interrupt Enable + LOCKU : Boolean := False; + -- unspecified + Reserved_7_7 : HAL.Bit := 16#0#; + -- Write-only. Programmable Clock Ready 0 Interrupt Enable + PCKRDY : PMC_PMC_IER_PCKRDY_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_15_15 : HAL.Bit := 16#0#; + -- Write-only. Main Clock Source Oscillator Selection Status Interrupt + -- Enable + MOSCSELS : Boolean := False; + -- Write-only. Main RC Oscillator Status Interrupt Enable + MOSCRCS : Boolean := False; + -- Write-only. Clock Failure Detector Event Interrupt Enable + CFDEV : Boolean := False; + -- unspecified + Reserved_19_20 : HAL.UInt2 := 16#0#; + -- Write-only. 32.768 kHz Crystal Oscillator Error Interrupt Enable + XT32KERR : Boolean := False; + -- unspecified + Reserved_22_31 : HAL.UInt10 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PMC_PMC_IER_Register use record + MOSCXTS at 0 range 0 .. 0; + LOCKA at 0 range 1 .. 1; + Reserved_2_2 at 0 range 2 .. 2; + MCKRDY at 0 range 3 .. 3; + Reserved_4_5 at 0 range 4 .. 5; + LOCKU at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + PCKRDY at 0 range 8 .. 14; + Reserved_15_15 at 0 range 15 .. 15; + MOSCSELS at 0 range 16 .. 16; + MOSCRCS at 0 range 17 .. 17; + CFDEV at 0 range 18 .. 18; + Reserved_19_20 at 0 range 19 .. 20; + XT32KERR at 0 range 21 .. 21; + Reserved_22_31 at 0 range 22 .. 31; + end record; + + -- PMC_PMC_IDR_PCKRDY array + type PMC_PMC_IDR_PCKRDY_Field_Array is array (0 .. 6) of Boolean + with Component_Size => 1, Size => 7; + + -- Type definition for PMC_PMC_IDR_PCKRDY + type PMC_PMC_IDR_PCKRDY_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- PCKRDY as a value + Val : HAL.UInt7; + when True => + -- PCKRDY as an array + Arr : PMC_PMC_IDR_PCKRDY_Field_Array; + end case; + end record + with Unchecked_Union, Size => 7; + + for PMC_PMC_IDR_PCKRDY_Field use record + Val at 0 range 0 .. 6; + Arr at 0 range 0 .. 6; + end record; + + -- Interrupt Disable Register + type PMC_PMC_IDR_Register is record + -- Write-only. Main Crystal Oscillator Status Interrupt Disable + MOSCXTS : Boolean := False; + -- Write-only. PLLA Lock Interrupt Disable + LOCKA : Boolean := False; + -- unspecified + Reserved_2_2 : HAL.Bit := 16#0#; + -- Write-only. Master Clock Ready Interrupt Disable + MCKRDY : Boolean := False; + -- unspecified + Reserved_4_5 : HAL.UInt2 := 16#0#; + -- Write-only. UTMI PLL Lock Interrupt Disable + LOCKU : Boolean := False; + -- unspecified + Reserved_7_7 : HAL.Bit := 16#0#; + -- Write-only. Programmable Clock Ready 0 Interrupt Disable + PCKRDY : PMC_PMC_IDR_PCKRDY_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_15_15 : HAL.Bit := 16#0#; + -- Write-only. Main Clock Source Oscillator Selection Status Interrupt + -- Disable + MOSCSELS : Boolean := False; + -- Write-only. Main RC Status Interrupt Disable + MOSCRCS : Boolean := False; + -- Write-only. Clock Failure Detector Event Interrupt Disable + CFDEV : Boolean := False; + -- unspecified + Reserved_19_20 : HAL.UInt2 := 16#0#; + -- Write-only. 32.768 kHz Crystal Oscillator Error Interrupt Disable + XT32KERR : Boolean := False; + -- unspecified + Reserved_22_31 : HAL.UInt10 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PMC_PMC_IDR_Register use record + MOSCXTS at 0 range 0 .. 0; + LOCKA at 0 range 1 .. 1; + Reserved_2_2 at 0 range 2 .. 2; + MCKRDY at 0 range 3 .. 3; + Reserved_4_5 at 0 range 4 .. 5; + LOCKU at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + PCKRDY at 0 range 8 .. 14; + Reserved_15_15 at 0 range 15 .. 15; + MOSCSELS at 0 range 16 .. 16; + MOSCRCS at 0 range 17 .. 17; + CFDEV at 0 range 18 .. 18; + Reserved_19_20 at 0 range 19 .. 20; + XT32KERR at 0 range 21 .. 21; + Reserved_22_31 at 0 range 22 .. 31; + end record; + + -- PMC_PMC_SR_PCKRDY array + type PMC_PMC_SR_PCKRDY_Field_Array is array (0 .. 6) of Boolean + with Component_Size => 1, Size => 7; + + -- Type definition for PMC_PMC_SR_PCKRDY + type PMC_PMC_SR_PCKRDY_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- PCKRDY as a value + Val : HAL.UInt7; + when True => + -- PCKRDY as an array + Arr : PMC_PMC_SR_PCKRDY_Field_Array; + end case; + end record + with Unchecked_Union, Size => 7; + + for PMC_PMC_SR_PCKRDY_Field use record + Val at 0 range 0 .. 6; + Arr at 0 range 0 .. 6; + end record; + + -- Status Register + type PMC_PMC_SR_Register is record + -- Read-only. Main Crystal Oscillator Status + MOSCXTS : Boolean; + -- Read-only. PLLA Lock Status + LOCKA : Boolean; + -- unspecified + Reserved_2_2 : HAL.Bit; + -- Read-only. Master Clock Status + MCKRDY : Boolean; + -- unspecified + Reserved_4_5 : HAL.UInt2; + -- Read-only. UTMI PLL Lock Status + LOCKU : Boolean; + -- Read-only. Slow Clock Source Oscillator Selection + OSCSELS : Boolean; + -- Read-only. Programmable Clock Ready Status + PCKRDY : PMC_PMC_SR_PCKRDY_Field; + -- unspecified + Reserved_15_15 : HAL.Bit; + -- Read-only. Main Clock Source Oscillator Selection Status + MOSCSELS : Boolean; + -- Read-only. Main RC Oscillator Status + MOSCRCS : Boolean; + -- Read-only. Clock Failure Detector Event + CFDEV : Boolean; + -- Read-only. Clock Failure Detector Status + CFDS : Boolean; + -- Read-only. Clock Failure Detector Fault Output Status + FOS : Boolean; + -- Read-only. Slow Crystal Oscillator Error + XT32KERR : Boolean; + -- unspecified + Reserved_22_31 : HAL.UInt10; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PMC_PMC_SR_Register use record + MOSCXTS at 0 range 0 .. 0; + LOCKA at 0 range 1 .. 1; + Reserved_2_2 at 0 range 2 .. 2; + MCKRDY at 0 range 3 .. 3; + Reserved_4_5 at 0 range 4 .. 5; + LOCKU at 0 range 6 .. 6; + OSCSELS at 0 range 7 .. 7; + PCKRDY at 0 range 8 .. 14; + Reserved_15_15 at 0 range 15 .. 15; + MOSCSELS at 0 range 16 .. 16; + MOSCRCS at 0 range 17 .. 17; + CFDEV at 0 range 18 .. 18; + CFDS at 0 range 19 .. 19; + FOS at 0 range 20 .. 20; + XT32KERR at 0 range 21 .. 21; + Reserved_22_31 at 0 range 22 .. 31; + end record; + + -- PMC_PMC_IMR_PCKRDY array + type PMC_PMC_IMR_PCKRDY_Field_Array is array (0 .. 6) of Boolean + with Component_Size => 1, Size => 7; + + -- Type definition for PMC_PMC_IMR_PCKRDY + type PMC_PMC_IMR_PCKRDY_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- PCKRDY as a value + Val : HAL.UInt7; + when True => + -- PCKRDY as an array + Arr : PMC_PMC_IMR_PCKRDY_Field_Array; + end case; + end record + with Unchecked_Union, Size => 7; + + for PMC_PMC_IMR_PCKRDY_Field use record + Val at 0 range 0 .. 6; + Arr at 0 range 0 .. 6; + end record; + + -- Interrupt Mask Register + type PMC_PMC_IMR_Register is record + -- Read-only. Main Crystal Oscillator Status Interrupt Mask + MOSCXTS : Boolean; + -- Read-only. PLLA Lock Interrupt Mask + LOCKA : Boolean; + -- unspecified + Reserved_2_2 : HAL.Bit; + -- Read-only. Master Clock Ready Interrupt Mask + MCKRDY : Boolean; + -- unspecified + Reserved_4_5 : HAL.UInt2; + -- Read-only. UTMI PLL Lock Interrupt Mask + LOCKU : Boolean; + -- unspecified + Reserved_7_7 : HAL.Bit; + -- Read-only. Programmable Clock Ready 0 Interrupt Mask + PCKRDY : PMC_PMC_IMR_PCKRDY_Field; + -- unspecified + Reserved_15_15 : HAL.Bit; + -- Read-only. Main Clock Source Oscillator Selection Status Interrupt + -- Mask + MOSCSELS : Boolean; + -- Read-only. Main RC Status Interrupt Mask + MOSCRCS : Boolean; + -- Read-only. Clock Failure Detector Event Interrupt Mask + CFDEV : Boolean; + -- unspecified + Reserved_19_20 : HAL.UInt2; + -- Read-only. 32.768 kHz Crystal Oscillator Error Interrupt Mask + XT32KERR : Boolean; + -- unspecified + Reserved_22_31 : HAL.UInt10; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PMC_PMC_IMR_Register use record + MOSCXTS at 0 range 0 .. 0; + LOCKA at 0 range 1 .. 1; + Reserved_2_2 at 0 range 2 .. 2; + MCKRDY at 0 range 3 .. 3; + Reserved_4_5 at 0 range 4 .. 5; + LOCKU at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + PCKRDY at 0 range 8 .. 14; + Reserved_15_15 at 0 range 15 .. 15; + MOSCSELS at 0 range 16 .. 16; + MOSCRCS at 0 range 17 .. 17; + CFDEV at 0 range 18 .. 18; + Reserved_19_20 at 0 range 19 .. 20; + XT32KERR at 0 range 21 .. 21; + Reserved_22_31 at 0 range 22 .. 31; + end record; + + -- PMC_PMC_FSMR_FSTT array + type PMC_PMC_FSMR_FSTT_Field_Array is array (0 .. 15) of Boolean + with Component_Size => 1, Size => 16; + + -- Type definition for PMC_PMC_FSMR_FSTT + type PMC_PMC_FSMR_FSTT_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- FSTT as a value + Val : HAL.UInt16; + when True => + -- FSTT as an array + Arr : PMC_PMC_FSMR_FSTT_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PMC_PMC_FSMR_FSTT_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Flash Low-power Mode + type PMC_FSMR_FLPM_Field is + ( + -- Flash is in Standby Mode when system enters Wait Mode + Flash_Standby, + -- Flash is in Deep-power-down mode when system enters Wait Mode + Flash_Deep_Powerdown, + -- Idle mode + Flash_Idle) + with Size => 2; + for PMC_FSMR_FLPM_Field use + (Flash_Standby => 0, + Flash_Deep_Powerdown => 1, + Flash_Idle => 2); + + -- Fast Startup Mode Register + type PMC_PMC_FSMR_Register is record + -- Fast Startup Input Enable 0 + FSTT : PMC_PMC_FSMR_FSTT_Field := + (As_Array => False, Val => 16#0#); + -- RTT Alarm Enable + RTTAL : Boolean := False; + -- RTC Alarm Enable + RTCAL : Boolean := False; + -- USB Alarm Enable + USBAL : Boolean := False; + -- unspecified + Reserved_19_19 : HAL.Bit := 16#0#; + -- Low-power Mode + LPM : Boolean := False; + -- Flash Low-power Mode + FLPM : PMC_FSMR_FLPM_Field := SAM_SVD.PMC.Flash_Standby; + -- Force Flash Low-power Mode + FFLPM : Boolean := False; + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PMC_PMC_FSMR_Register use record + FSTT at 0 range 0 .. 15; + RTTAL at 0 range 16 .. 16; + RTCAL at 0 range 17 .. 17; + USBAL at 0 range 18 .. 18; + Reserved_19_19 at 0 range 19 .. 19; + LPM at 0 range 20 .. 20; + FLPM at 0 range 21 .. 22; + FFLPM at 0 range 23 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- PMC_PMC_FSPR_FSTP array + type PMC_PMC_FSPR_FSTP_Field_Array is array (0 .. 15) of Boolean + with Component_Size => 1, Size => 16; + + -- Type definition for PMC_PMC_FSPR_FSTP + type PMC_PMC_FSPR_FSTP_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- FSTP as a value + Val : HAL.UInt16; + when True => + -- FSTP as an array + Arr : PMC_PMC_FSPR_FSTP_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for PMC_PMC_FSPR_FSTP_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Fast Startup Polarity Register + type PMC_PMC_FSPR_Register is record + -- Fast Startup Input Polarity 0 + FSTP : PMC_PMC_FSPR_FSTP_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PMC_PMC_FSPR_Register use record + FSTP at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + -- Fault Output Clear Register + type PMC_PMC_FOCR_Register is record + -- Write-only. Fault Output Clear + FOCLR : Boolean := False; + -- unspecified + Reserved_1_31 : HAL.UInt31 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PMC_PMC_FOCR_Register use record + FOCLR at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + -- Write Protection Key + type PMC_WPMR_WPKEY_Field is + ( + -- Reset value for the field + Pmc_Wpmr_Wpkey_Field_Reset, + -- Writing any other value in this field aborts the write operation of + -- the WPEN bit. Always reads as 0. + Passwd) + with Size => 24; + for PMC_WPMR_WPKEY_Field use + (Pmc_Wpmr_Wpkey_Field_Reset => 0, + Passwd => 5262659); + + -- Write Protection Mode Register + type PMC_PMC_WPMR_Register is record + -- Write Protection Enable + WPEN : Boolean := False; + -- unspecified + Reserved_1_7 : HAL.UInt7 := 16#0#; + -- Write Protection Key + WPKEY : PMC_WPMR_WPKEY_Field := Pmc_Wpmr_Wpkey_Field_Reset; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PMC_PMC_WPMR_Register use record + WPEN at 0 range 0 .. 0; + Reserved_1_7 at 0 range 1 .. 7; + WPKEY at 0 range 8 .. 31; + end record; + + subtype PMC_PMC_WPSR_WPVSRC_Field is HAL.UInt16; + + -- Write Protection Status Register + type PMC_PMC_WPSR_Register is record + -- Read-only. Write Protection Violation Status + WPVS : Boolean; + -- unspecified + Reserved_1_7 : HAL.UInt7; + -- Read-only. Write Protection Violation Source + WPVSRC : PMC_PMC_WPSR_WPVSRC_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PMC_PMC_WPSR_Register use record + WPVS at 0 range 0 .. 0; + Reserved_1_7 at 0 range 1 .. 7; + WPVSRC at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype PMC_PMC_VERSION_VERSION_Field is HAL.UInt12; + subtype PMC_PMC_VERSION_MFN_Field is HAL.UInt3; + + -- Version Register + type PMC_PMC_VERSION_Register is record + -- Read-only. Version of the Hardware Module + VERSION : PMC_PMC_VERSION_VERSION_Field; + -- unspecified + Reserved_12_15 : HAL.UInt4; + -- Read-only. Metal Fix Number + MFN : PMC_PMC_VERSION_MFN_Field; + -- unspecified + Reserved_19_31 : HAL.UInt13; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PMC_PMC_VERSION_Register use record + VERSION at 0 range 0 .. 11; + Reserved_12_15 at 0 range 12 .. 15; + MFN at 0 range 16 .. 18; + Reserved_19_31 at 0 range 19 .. 31; + end record; + + -- PMC_PMC_PCER1_PID array + type PMC_PMC_PCER1_PID_Field_Array is array (32 .. 35) of Boolean + with Component_Size => 1, Size => 4; + + -- Type definition for PMC_PMC_PCER1_PID + type PMC_PMC_PCER1_PID_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- PID as a value + Val : HAL.UInt4; + when True => + -- PID as an array + Arr : PMC_PMC_PCER1_PID_Field_Array; + end case; + end record + with Unchecked_Union, Size => 4; + + for PMC_PMC_PCER1_PID_Field use record + Val at 0 range 0 .. 3; + Arr at 0 range 0 .. 3; + end record; + + -- PMC_PMC_PCER1_PID array + type PMC_PMC_PCER1_PID_Field_Array_1 is array (39 .. 53) of Boolean + with Component_Size => 1, Size => 15; + + -- Type definition for PMC_PMC_PCER1_PID + type PMC_PMC_PCER1_PID_Field_1 + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- PID as a value + Val : HAL.UInt15; + when True => + -- PID as an array + Arr : PMC_PMC_PCER1_PID_Field_Array_1; + end case; + end record + with Unchecked_Union, Size => 15; + + for PMC_PMC_PCER1_PID_Field_1 use record + Val at 0 range 0 .. 14; + Arr at 0 range 0 .. 14; + end record; + + -- PMC_PMC_PCER1_PID array + type PMC_PMC_PCER1_PID_Field_Array_2 is array (56 .. 60) of Boolean + with Component_Size => 1, Size => 5; + + -- Type definition for PMC_PMC_PCER1_PID + type PMC_PMC_PCER1_PID_Field_2 + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- PID as a value + Val : HAL.UInt5; + when True => + -- PID as an array + Arr : PMC_PMC_PCER1_PID_Field_Array_2; + end case; + end record + with Unchecked_Union, Size => 5; + + for PMC_PMC_PCER1_PID_Field_2 use record + Val at 0 range 0 .. 4; + Arr at 0 range 0 .. 4; + end record; + + -- Peripheral Clock Enable Register 1 + type PMC_PMC_PCER1_Register is record + -- Write-only. Peripheral Clock 32 Enable + PID : PMC_PMC_PCER1_PID_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_4_4 : HAL.Bit := 16#0#; + -- Write-only. Peripheral Clock 37 Enable + PID37 : Boolean := False; + -- unspecified + Reserved_6_6 : HAL.Bit := 16#0#; + -- Write-only. Peripheral Clock 39 Enable + PID_1 : PMC_PMC_PCER1_PID_Field_1 := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_22_23 : HAL.UInt2 := 16#0#; + -- Write-only. Peripheral Clock 56 Enable + PID_2 : PMC_PMC_PCER1_PID_Field_2 := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_29_31 : HAL.UInt3 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PMC_PMC_PCER1_Register use record + PID at 0 range 0 .. 3; + Reserved_4_4 at 0 range 4 .. 4; + PID37 at 0 range 5 .. 5; + Reserved_6_6 at 0 range 6 .. 6; + PID_1 at 0 range 7 .. 21; + Reserved_22_23 at 0 range 22 .. 23; + PID_2 at 0 range 24 .. 28; + Reserved_29_31 at 0 range 29 .. 31; + end record; + + -- PMC_PMC_PCDR1_PID array + type PMC_PMC_PCDR1_PID_Field_Array is array (32 .. 35) of Boolean + with Component_Size => 1, Size => 4; + + -- Type definition for PMC_PMC_PCDR1_PID + type PMC_PMC_PCDR1_PID_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- PID as a value + Val : HAL.UInt4; + when True => + -- PID as an array + Arr : PMC_PMC_PCDR1_PID_Field_Array; + end case; + end record + with Unchecked_Union, Size => 4; + + for PMC_PMC_PCDR1_PID_Field use record + Val at 0 range 0 .. 3; + Arr at 0 range 0 .. 3; + end record; + + -- PMC_PMC_PCDR1_PID array + type PMC_PMC_PCDR1_PID_Field_Array_1 is array (39 .. 53) of Boolean + with Component_Size => 1, Size => 15; + + -- Type definition for PMC_PMC_PCDR1_PID + type PMC_PMC_PCDR1_PID_Field_1 + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- PID as a value + Val : HAL.UInt15; + when True => + -- PID as an array + Arr : PMC_PMC_PCDR1_PID_Field_Array_1; + end case; + end record + with Unchecked_Union, Size => 15; + + for PMC_PMC_PCDR1_PID_Field_1 use record + Val at 0 range 0 .. 14; + Arr at 0 range 0 .. 14; + end record; + + -- PMC_PMC_PCDR1_PID array + type PMC_PMC_PCDR1_PID_Field_Array_2 is array (56 .. 60) of Boolean + with Component_Size => 1, Size => 5; + + -- Type definition for PMC_PMC_PCDR1_PID + type PMC_PMC_PCDR1_PID_Field_2 + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- PID as a value + Val : HAL.UInt5; + when True => + -- PID as an array + Arr : PMC_PMC_PCDR1_PID_Field_Array_2; + end case; + end record + with Unchecked_Union, Size => 5; + + for PMC_PMC_PCDR1_PID_Field_2 use record + Val at 0 range 0 .. 4; + Arr at 0 range 0 .. 4; + end record; + + -- Peripheral Clock Disable Register 1 + type PMC_PMC_PCDR1_Register is record + -- Write-only. Peripheral Clock 32 Disable + PID : PMC_PMC_PCDR1_PID_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_4_4 : HAL.Bit := 16#0#; + -- Write-only. Peripheral Clock 37 Disable + PID37 : Boolean := False; + -- unspecified + Reserved_6_6 : HAL.Bit := 16#0#; + -- Write-only. Peripheral Clock 39 Disable + PID_1 : PMC_PMC_PCDR1_PID_Field_1 := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_22_23 : HAL.UInt2 := 16#0#; + -- Write-only. Peripheral Clock 56 Disable + PID_2 : PMC_PMC_PCDR1_PID_Field_2 := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_29_31 : HAL.UInt3 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PMC_PMC_PCDR1_Register use record + PID at 0 range 0 .. 3; + Reserved_4_4 at 0 range 4 .. 4; + PID37 at 0 range 5 .. 5; + Reserved_6_6 at 0 range 6 .. 6; + PID_1 at 0 range 7 .. 21; + Reserved_22_23 at 0 range 22 .. 23; + PID_2 at 0 range 24 .. 28; + Reserved_29_31 at 0 range 29 .. 31; + end record; + + -- PMC_PMC_PCSR1_PID array + type PMC_PMC_PCSR1_PID_Field_Array is array (32 .. 35) of Boolean + with Component_Size => 1, Size => 4; + + -- Type definition for PMC_PMC_PCSR1_PID + type PMC_PMC_PCSR1_PID_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- PID as a value + Val : HAL.UInt4; + when True => + -- PID as an array + Arr : PMC_PMC_PCSR1_PID_Field_Array; + end case; + end record + with Unchecked_Union, Size => 4; + + for PMC_PMC_PCSR1_PID_Field use record + Val at 0 range 0 .. 3; + Arr at 0 range 0 .. 3; + end record; + + -- PMC_PMC_PCSR1_PID array + type PMC_PMC_PCSR1_PID_Field_Array_1 is array (39 .. 53) of Boolean + with Component_Size => 1, Size => 15; + + -- Type definition for PMC_PMC_PCSR1_PID + type PMC_PMC_PCSR1_PID_Field_1 + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- PID as a value + Val : HAL.UInt15; + when True => + -- PID as an array + Arr : PMC_PMC_PCSR1_PID_Field_Array_1; + end case; + end record + with Unchecked_Union, Size => 15; + + for PMC_PMC_PCSR1_PID_Field_1 use record + Val at 0 range 0 .. 14; + Arr at 0 range 0 .. 14; + end record; + + -- PMC_PMC_PCSR1_PID array + type PMC_PMC_PCSR1_PID_Field_Array_2 is array (56 .. 60) of Boolean + with Component_Size => 1, Size => 5; + + -- Type definition for PMC_PMC_PCSR1_PID + type PMC_PMC_PCSR1_PID_Field_2 + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- PID as a value + Val : HAL.UInt5; + when True => + -- PID as an array + Arr : PMC_PMC_PCSR1_PID_Field_Array_2; + end case; + end record + with Unchecked_Union, Size => 5; + + for PMC_PMC_PCSR1_PID_Field_2 use record + Val at 0 range 0 .. 4; + Arr at 0 range 0 .. 4; + end record; + + -- Peripheral Clock Status Register 1 + type PMC_PMC_PCSR1_Register is record + -- Read-only. Peripheral Clock 32 Status + PID : PMC_PMC_PCSR1_PID_Field; + -- unspecified + Reserved_4_4 : HAL.Bit; + -- Read-only. Peripheral Clock 37 Status + PID37 : Boolean; + -- unspecified + Reserved_6_6 : HAL.Bit; + -- Read-only. Peripheral Clock 39 Status + PID_1 : PMC_PMC_PCSR1_PID_Field_1; + -- unspecified + Reserved_22_23 : HAL.UInt2; + -- Read-only. Peripheral Clock 56 Status + PID_2 : PMC_PMC_PCSR1_PID_Field_2; + -- unspecified + Reserved_29_31 : HAL.UInt3; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PMC_PMC_PCSR1_Register use record + PID at 0 range 0 .. 3; + Reserved_4_4 at 0 range 4 .. 4; + PID37 at 0 range 5 .. 5; + Reserved_6_6 at 0 range 6 .. 6; + PID_1 at 0 range 7 .. 21; + Reserved_22_23 at 0 range 22 .. 23; + PID_2 at 0 range 24 .. 28; + Reserved_29_31 at 0 range 29 .. 31; + end record; + + subtype PMC_PMC_PCR_PID_Field is HAL.UInt7; + + -- Generic Clock Source Selection + type PMC_PCR_GCLKCSS_Field is + ( + -- SLCK is selected + Slow_Clk, + -- MAINCK is selected + Main_Clk, + -- PLLACK is selected + Plla_Clk, + -- UPLLCK is selected + Upll_Clk, + -- MCK is selected + Mck_Clk) + with Size => 3; + for PMC_PCR_GCLKCSS_Field use + (Slow_Clk => 0, + Main_Clk => 1, + Plla_Clk => 2, + Upll_Clk => 3, + Mck_Clk => 4); + + subtype PMC_PMC_PCR_GCLKDIV_Field is HAL.UInt8; + + -- Peripheral Control Register + type PMC_PMC_PCR_Register is record + -- Peripheral ID + PID : PMC_PMC_PCR_PID_Field := 16#0#; + -- unspecified + Reserved_7_7 : HAL.Bit := 16#0#; + -- Generic Clock Source Selection + GCLKCSS : PMC_PCR_GCLKCSS_Field := SAM_SVD.PMC.Slow_Clk; + -- unspecified + Reserved_11_11 : HAL.Bit := 16#0#; + -- Command + CMD : Boolean := False; + -- unspecified + Reserved_13_19 : HAL.UInt7 := 16#0#; + -- Generic Clock Division Ratio + GCLKDIV : PMC_PMC_PCR_GCLKDIV_Field := 16#0#; + -- Enable + EN : Boolean := False; + -- Generic Clock Enable + GCLKEN : Boolean := False; + -- unspecified + Reserved_30_31 : HAL.UInt2 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PMC_PMC_PCR_Register use record + PID at 0 range 0 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + GCLKCSS at 0 range 8 .. 10; + Reserved_11_11 at 0 range 11 .. 11; + CMD at 0 range 12 .. 12; + Reserved_13_19 at 0 range 13 .. 19; + GCLKDIV at 0 range 20 .. 27; + EN at 0 range 28 .. 28; + GCLKEN at 0 range 29 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + subtype PMC_PMC_OCR_CAL4_Field is HAL.UInt7; + subtype PMC_PMC_OCR_CAL8_Field is HAL.UInt7; + subtype PMC_PMC_OCR_CAL12_Field is HAL.UInt7; + + -- Oscillator Calibration Register + type PMC_PMC_OCR_Register is record + -- Main RC Oscillator Calibration Bits for 4 MHz + CAL4 : PMC_PMC_OCR_CAL4_Field := 16#0#; + -- Selection of Main RC Oscillator Calibration Bits for 4 MHz + SEL4 : Boolean := False; + -- Main RC Oscillator Calibration Bits for 8 MHz + CAL8 : PMC_PMC_OCR_CAL8_Field := 16#0#; + -- Selection of Main RC Oscillator Calibration Bits for 8 MHz + SEL8 : Boolean := False; + -- Main RC Oscillator Calibration Bits for 12 MHz + CAL12 : PMC_PMC_OCR_CAL12_Field := 16#0#; + -- Selection of Main RC Oscillator Calibration Bits for 12 MHz + SEL12 : Boolean := False; + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PMC_PMC_OCR_Register use record + CAL4 at 0 range 0 .. 6; + SEL4 at 0 range 7 .. 7; + CAL8 at 0 range 8 .. 14; + SEL8 at 0 range 15 .. 15; + CAL12 at 0 range 16 .. 22; + SEL12 at 0 range 23 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- PMC_PMC_SLPWK_ER0_PID array + type PMC_PMC_SLPWK_ER0_PID_Field_Array is array (7 .. 31) of Boolean + with Component_Size => 1, Size => 25; + + -- Type definition for PMC_PMC_SLPWK_ER0_PID + type PMC_PMC_SLPWK_ER0_PID_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- PID as a value + Val : HAL.UInt25; + when True => + -- PID as an array + Arr : PMC_PMC_SLPWK_ER0_PID_Field_Array; + end case; + end record + with Unchecked_Union, Size => 25; + + for PMC_PMC_SLPWK_ER0_PID_Field use record + Val at 0 range 0 .. 24; + Arr at 0 range 0 .. 24; + end record; + + -- SleepWalking Enable Register 0 + type PMC_PMC_SLPWK_ER0_Register is record + -- unspecified + Reserved_0_6 : HAL.UInt7 := 16#0#; + -- Write-only. Peripheral 7 SleepWalking Enable + PID : PMC_PMC_SLPWK_ER0_PID_Field := + (As_Array => False, Val => 16#0#); + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PMC_PMC_SLPWK_ER0_Register use record + Reserved_0_6 at 0 range 0 .. 6; + PID at 0 range 7 .. 31; + end record; + + -- PMC_PMC_SLPWK_DR0_PID array + type PMC_PMC_SLPWK_DR0_PID_Field_Array is array (7 .. 31) of Boolean + with Component_Size => 1, Size => 25; + + -- Type definition for PMC_PMC_SLPWK_DR0_PID + type PMC_PMC_SLPWK_DR0_PID_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- PID as a value + Val : HAL.UInt25; + when True => + -- PID as an array + Arr : PMC_PMC_SLPWK_DR0_PID_Field_Array; + end case; + end record + with Unchecked_Union, Size => 25; + + for PMC_PMC_SLPWK_DR0_PID_Field use record + Val at 0 range 0 .. 24; + Arr at 0 range 0 .. 24; + end record; + + -- SleepWalking Disable Register 0 + type PMC_PMC_SLPWK_DR0_Register is record + -- unspecified + Reserved_0_6 : HAL.UInt7 := 16#0#; + -- Write-only. Peripheral 7 SleepWalking Disable + PID : PMC_PMC_SLPWK_DR0_PID_Field := + (As_Array => False, Val => 16#0#); + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PMC_PMC_SLPWK_DR0_Register use record + Reserved_0_6 at 0 range 0 .. 6; + PID at 0 range 7 .. 31; + end record; + + -- PMC_PMC_SLPWK_SR0_PID array + type PMC_PMC_SLPWK_SR0_PID_Field_Array is array (7 .. 31) of Boolean + with Component_Size => 1, Size => 25; + + -- Type definition for PMC_PMC_SLPWK_SR0_PID + type PMC_PMC_SLPWK_SR0_PID_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- PID as a value + Val : HAL.UInt25; + when True => + -- PID as an array + Arr : PMC_PMC_SLPWK_SR0_PID_Field_Array; + end case; + end record + with Unchecked_Union, Size => 25; + + for PMC_PMC_SLPWK_SR0_PID_Field use record + Val at 0 range 0 .. 24; + Arr at 0 range 0 .. 24; + end record; + + -- SleepWalking Status Register 0 + type PMC_PMC_SLPWK_SR0_Register is record + -- unspecified + Reserved_0_6 : HAL.UInt7; + -- Read-only. Peripheral 7 SleepWalking Status + PID : PMC_PMC_SLPWK_SR0_PID_Field; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PMC_PMC_SLPWK_SR0_Register use record + Reserved_0_6 at 0 range 0 .. 6; + PID at 0 range 7 .. 31; + end record; + + -- PMC_PMC_SLPWK_ASR0_PID array + type PMC_PMC_SLPWK_ASR0_PID_Field_Array is array (7 .. 31) of Boolean + with Component_Size => 1, Size => 25; + + -- Type definition for PMC_PMC_SLPWK_ASR0_PID + type PMC_PMC_SLPWK_ASR0_PID_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- PID as a value + Val : HAL.UInt25; + when True => + -- PID as an array + Arr : PMC_PMC_SLPWK_ASR0_PID_Field_Array; + end case; + end record + with Unchecked_Union, Size => 25; + + for PMC_PMC_SLPWK_ASR0_PID_Field use record + Val at 0 range 0 .. 24; + Arr at 0 range 0 .. 24; + end record; + + -- SleepWalking Activity Status Register 0 + type PMC_PMC_SLPWK_ASR0_Register is record + -- unspecified + Reserved_0_6 : HAL.UInt7; + -- Read-only. Peripheral 7 Activity Status + PID : PMC_PMC_SLPWK_ASR0_PID_Field; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PMC_PMC_SLPWK_ASR0_Register use record + Reserved_0_6 at 0 range 0 .. 6; + PID at 0 range 7 .. 31; + end record; + + subtype PMC_PMC_PMMR_PLLA_MMAX_Field is HAL.UInt11; + + -- PLL Maximum Multiplier Value Register + type PMC_PMC_PMMR_Register is record + -- PLLA Maximum Allowed Multiplier Value + PLLA_MMAX : PMC_PMC_PMMR_PLLA_MMAX_Field := 16#0#; + -- unspecified + Reserved_11_31 : HAL.UInt21 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PMC_PMC_PMMR_Register use record + PLLA_MMAX at 0 range 0 .. 10; + Reserved_11_31 at 0 range 11 .. 31; + end record; + + -- PMC_PMC_SLPWK_ER1_PID array + type PMC_PMC_SLPWK_ER1_PID_Field_Array is array (32 .. 35) of Boolean + with Component_Size => 1, Size => 4; + + -- Type definition for PMC_PMC_SLPWK_ER1_PID + type PMC_PMC_SLPWK_ER1_PID_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- PID as a value + Val : HAL.UInt4; + when True => + -- PID as an array + Arr : PMC_PMC_SLPWK_ER1_PID_Field_Array; + end case; + end record + with Unchecked_Union, Size => 4; + + for PMC_PMC_SLPWK_ER1_PID_Field use record + Val at 0 range 0 .. 3; + Arr at 0 range 0 .. 3; + end record; + + -- PMC_PMC_SLPWK_ER1_PID array + type PMC_PMC_SLPWK_ER1_PID_Field_Array_1 is array (39 .. 53) of Boolean + with Component_Size => 1, Size => 15; + + -- Type definition for PMC_PMC_SLPWK_ER1_PID + type PMC_PMC_SLPWK_ER1_PID_Field_1 + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- PID as a value + Val : HAL.UInt15; + when True => + -- PID as an array + Arr : PMC_PMC_SLPWK_ER1_PID_Field_Array_1; + end case; + end record + with Unchecked_Union, Size => 15; + + for PMC_PMC_SLPWK_ER1_PID_Field_1 use record + Val at 0 range 0 .. 14; + Arr at 0 range 0 .. 14; + end record; + + -- PMC_PMC_SLPWK_ER1_PID array + type PMC_PMC_SLPWK_ER1_PID_Field_Array_2 is array (56 .. 60) of Boolean + with Component_Size => 1, Size => 5; + + -- Type definition for PMC_PMC_SLPWK_ER1_PID + type PMC_PMC_SLPWK_ER1_PID_Field_2 + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- PID as a value + Val : HAL.UInt5; + when True => + -- PID as an array + Arr : PMC_PMC_SLPWK_ER1_PID_Field_Array_2; + end case; + end record + with Unchecked_Union, Size => 5; + + for PMC_PMC_SLPWK_ER1_PID_Field_2 use record + Val at 0 range 0 .. 4; + Arr at 0 range 0 .. 4; + end record; + + -- SleepWalking Enable Register 1 + type PMC_PMC_SLPWK_ER1_Register is record + -- Write-only. Peripheral 32 SleepWalking Enable + PID : PMC_PMC_SLPWK_ER1_PID_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_4_4 : HAL.Bit := 16#0#; + -- Write-only. Peripheral 37 SleepWalking Enable + PID37 : Boolean := False; + -- unspecified + Reserved_6_6 : HAL.Bit := 16#0#; + -- Write-only. Peripheral 39 SleepWalking Enable + PID_1 : PMC_PMC_SLPWK_ER1_PID_Field_1 := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_22_23 : HAL.UInt2 := 16#0#; + -- Write-only. Peripheral 56 SleepWalking Enable + PID_2 : PMC_PMC_SLPWK_ER1_PID_Field_2 := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_29_31 : HAL.UInt3 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PMC_PMC_SLPWK_ER1_Register use record + PID at 0 range 0 .. 3; + Reserved_4_4 at 0 range 4 .. 4; + PID37 at 0 range 5 .. 5; + Reserved_6_6 at 0 range 6 .. 6; + PID_1 at 0 range 7 .. 21; + Reserved_22_23 at 0 range 22 .. 23; + PID_2 at 0 range 24 .. 28; + Reserved_29_31 at 0 range 29 .. 31; + end record; + + -- PMC_PMC_SLPWK_DR1_PID array + type PMC_PMC_SLPWK_DR1_PID_Field_Array is array (32 .. 35) of Boolean + with Component_Size => 1, Size => 4; + + -- Type definition for PMC_PMC_SLPWK_DR1_PID + type PMC_PMC_SLPWK_DR1_PID_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- PID as a value + Val : HAL.UInt4; + when True => + -- PID as an array + Arr : PMC_PMC_SLPWK_DR1_PID_Field_Array; + end case; + end record + with Unchecked_Union, Size => 4; + + for PMC_PMC_SLPWK_DR1_PID_Field use record + Val at 0 range 0 .. 3; + Arr at 0 range 0 .. 3; + end record; + + -- PMC_PMC_SLPWK_DR1_PID array + type PMC_PMC_SLPWK_DR1_PID_Field_Array_1 is array (39 .. 53) of Boolean + with Component_Size => 1, Size => 15; + + -- Type definition for PMC_PMC_SLPWK_DR1_PID + type PMC_PMC_SLPWK_DR1_PID_Field_1 + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- PID as a value + Val : HAL.UInt15; + when True => + -- PID as an array + Arr : PMC_PMC_SLPWK_DR1_PID_Field_Array_1; + end case; + end record + with Unchecked_Union, Size => 15; + + for PMC_PMC_SLPWK_DR1_PID_Field_1 use record + Val at 0 range 0 .. 14; + Arr at 0 range 0 .. 14; + end record; + + -- PMC_PMC_SLPWK_DR1_PID array + type PMC_PMC_SLPWK_DR1_PID_Field_Array_2 is array (56 .. 60) of Boolean + with Component_Size => 1, Size => 5; + + -- Type definition for PMC_PMC_SLPWK_DR1_PID + type PMC_PMC_SLPWK_DR1_PID_Field_2 + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- PID as a value + Val : HAL.UInt5; + when True => + -- PID as an array + Arr : PMC_PMC_SLPWK_DR1_PID_Field_Array_2; + end case; + end record + with Unchecked_Union, Size => 5; + + for PMC_PMC_SLPWK_DR1_PID_Field_2 use record + Val at 0 range 0 .. 4; + Arr at 0 range 0 .. 4; + end record; + + -- SleepWalking Disable Register 1 + type PMC_PMC_SLPWK_DR1_Register is record + -- Write-only. Peripheral 32 SleepWalking Disable + PID : PMC_PMC_SLPWK_DR1_PID_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_4_4 : HAL.Bit := 16#0#; + -- Write-only. Peripheral 37 SleepWalking Disable + PID37 : Boolean := False; + -- unspecified + Reserved_6_6 : HAL.Bit := 16#0#; + -- Write-only. Peripheral 39 SleepWalking Disable + PID_1 : PMC_PMC_SLPWK_DR1_PID_Field_1 := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_22_23 : HAL.UInt2 := 16#0#; + -- Write-only. Peripheral 56 SleepWalking Disable + PID_2 : PMC_PMC_SLPWK_DR1_PID_Field_2 := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_29_31 : HAL.UInt3 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PMC_PMC_SLPWK_DR1_Register use record + PID at 0 range 0 .. 3; + Reserved_4_4 at 0 range 4 .. 4; + PID37 at 0 range 5 .. 5; + Reserved_6_6 at 0 range 6 .. 6; + PID_1 at 0 range 7 .. 21; + Reserved_22_23 at 0 range 22 .. 23; + PID_2 at 0 range 24 .. 28; + Reserved_29_31 at 0 range 29 .. 31; + end record; + + -- PMC_PMC_SLPWK_SR1_PID array + type PMC_PMC_SLPWK_SR1_PID_Field_Array is array (32 .. 35) of Boolean + with Component_Size => 1, Size => 4; + + -- Type definition for PMC_PMC_SLPWK_SR1_PID + type PMC_PMC_SLPWK_SR1_PID_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- PID as a value + Val : HAL.UInt4; + when True => + -- PID as an array + Arr : PMC_PMC_SLPWK_SR1_PID_Field_Array; + end case; + end record + with Unchecked_Union, Size => 4; + + for PMC_PMC_SLPWK_SR1_PID_Field use record + Val at 0 range 0 .. 3; + Arr at 0 range 0 .. 3; + end record; + + -- PMC_PMC_SLPWK_SR1_PID array + type PMC_PMC_SLPWK_SR1_PID_Field_Array_1 is array (39 .. 53) of Boolean + with Component_Size => 1, Size => 15; + + -- Type definition for PMC_PMC_SLPWK_SR1_PID + type PMC_PMC_SLPWK_SR1_PID_Field_1 + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- PID as a value + Val : HAL.UInt15; + when True => + -- PID as an array + Arr : PMC_PMC_SLPWK_SR1_PID_Field_Array_1; + end case; + end record + with Unchecked_Union, Size => 15; + + for PMC_PMC_SLPWK_SR1_PID_Field_1 use record + Val at 0 range 0 .. 14; + Arr at 0 range 0 .. 14; + end record; + + -- PMC_PMC_SLPWK_SR1_PID array + type PMC_PMC_SLPWK_SR1_PID_Field_Array_2 is array (56 .. 60) of Boolean + with Component_Size => 1, Size => 5; + + -- Type definition for PMC_PMC_SLPWK_SR1_PID + type PMC_PMC_SLPWK_SR1_PID_Field_2 + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- PID as a value + Val : HAL.UInt5; + when True => + -- PID as an array + Arr : PMC_PMC_SLPWK_SR1_PID_Field_Array_2; + end case; + end record + with Unchecked_Union, Size => 5; + + for PMC_PMC_SLPWK_SR1_PID_Field_2 use record + Val at 0 range 0 .. 4; + Arr at 0 range 0 .. 4; + end record; + + -- SleepWalking Status Register 1 + type PMC_PMC_SLPWK_SR1_Register is record + -- Read-only. Peripheral 32 SleepWalking Status + PID : PMC_PMC_SLPWK_SR1_PID_Field; + -- unspecified + Reserved_4_4 : HAL.Bit; + -- Read-only. Peripheral 37 SleepWalking Status + PID37 : Boolean; + -- unspecified + Reserved_6_6 : HAL.Bit; + -- Read-only. Peripheral 39 SleepWalking Status + PID_1 : PMC_PMC_SLPWK_SR1_PID_Field_1; + -- unspecified + Reserved_22_23 : HAL.UInt2; + -- Read-only. Peripheral 56 SleepWalking Status + PID_2 : PMC_PMC_SLPWK_SR1_PID_Field_2; + -- unspecified + Reserved_29_31 : HAL.UInt3; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PMC_PMC_SLPWK_SR1_Register use record + PID at 0 range 0 .. 3; + Reserved_4_4 at 0 range 4 .. 4; + PID37 at 0 range 5 .. 5; + Reserved_6_6 at 0 range 6 .. 6; + PID_1 at 0 range 7 .. 21; + Reserved_22_23 at 0 range 22 .. 23; + PID_2 at 0 range 24 .. 28; + Reserved_29_31 at 0 range 29 .. 31; + end record; + + -- PMC_PMC_SLPWK_ASR1_PID array + type PMC_PMC_SLPWK_ASR1_PID_Field_Array is array (32 .. 35) of Boolean + with Component_Size => 1, Size => 4; + + -- Type definition for PMC_PMC_SLPWK_ASR1_PID + type PMC_PMC_SLPWK_ASR1_PID_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- PID as a value + Val : HAL.UInt4; + when True => + -- PID as an array + Arr : PMC_PMC_SLPWK_ASR1_PID_Field_Array; + end case; + end record + with Unchecked_Union, Size => 4; + + for PMC_PMC_SLPWK_ASR1_PID_Field use record + Val at 0 range 0 .. 3; + Arr at 0 range 0 .. 3; + end record; + + -- PMC_PMC_SLPWK_ASR1_PID array + type PMC_PMC_SLPWK_ASR1_PID_Field_Array_1 is array (39 .. 53) of Boolean + with Component_Size => 1, Size => 15; + + -- Type definition for PMC_PMC_SLPWK_ASR1_PID + type PMC_PMC_SLPWK_ASR1_PID_Field_1 + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- PID as a value + Val : HAL.UInt15; + when True => + -- PID as an array + Arr : PMC_PMC_SLPWK_ASR1_PID_Field_Array_1; + end case; + end record + with Unchecked_Union, Size => 15; + + for PMC_PMC_SLPWK_ASR1_PID_Field_1 use record + Val at 0 range 0 .. 14; + Arr at 0 range 0 .. 14; + end record; + + -- PMC_PMC_SLPWK_ASR1_PID array + type PMC_PMC_SLPWK_ASR1_PID_Field_Array_2 is array (56 .. 60) of Boolean + with Component_Size => 1, Size => 5; + + -- Type definition for PMC_PMC_SLPWK_ASR1_PID + type PMC_PMC_SLPWK_ASR1_PID_Field_2 + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- PID as a value + Val : HAL.UInt5; + when True => + -- PID as an array + Arr : PMC_PMC_SLPWK_ASR1_PID_Field_Array_2; + end case; + end record + with Unchecked_Union, Size => 5; + + for PMC_PMC_SLPWK_ASR1_PID_Field_2 use record + Val at 0 range 0 .. 4; + Arr at 0 range 0 .. 4; + end record; + + -- SleepWalking Activity Status Register 1 + type PMC_PMC_SLPWK_ASR1_Register is record + -- Read-only. Peripheral 32 Activity Status + PID : PMC_PMC_SLPWK_ASR1_PID_Field; + -- unspecified + Reserved_4_4 : HAL.Bit; + -- Read-only. Peripheral 37 Activity Status + PID37 : Boolean; + -- unspecified + Reserved_6_6 : HAL.Bit; + -- Read-only. Peripheral 39 Activity Status + PID_1 : PMC_PMC_SLPWK_ASR1_PID_Field_1; + -- unspecified + Reserved_22_23 : HAL.UInt2; + -- Read-only. Peripheral 56 Activity Status + PID_2 : PMC_PMC_SLPWK_ASR1_PID_Field_2; + -- unspecified + Reserved_29_31 : HAL.UInt3; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PMC_PMC_SLPWK_ASR1_Register use record + PID at 0 range 0 .. 3; + Reserved_4_4 at 0 range 4 .. 4; + PID37 at 0 range 5 .. 5; + Reserved_6_6 at 0 range 6 .. 6; + PID_1 at 0 range 7 .. 21; + Reserved_22_23 at 0 range 22 .. 23; + PID_2 at 0 range 24 .. 28; + Reserved_29_31 at 0 range 29 .. 31; + end record; + + -- SleepWalking Activity In Progress Register + type PMC_PMC_SLPWK_AIPR_Register is record + -- Read-only. Activity In Progress + AIP : Boolean; + -- unspecified + Reserved_1_31 : HAL.UInt31; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PMC_PMC_SLPWK_AIPR_Register use record + AIP at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + subtype PMC_PMC_APLLACR_DCOFLTSEL_Field is HAL.UInt4; + subtype PMC_PMC_APLLACR_FLTSEL_Field is HAL.UInt4; + subtype PMC_PMC_APLLACR_BIAS_Field is HAL.UInt2; + + -- Audio PLL Analog Configuration Register + type PMC_PMC_APLLACR_Register is record + -- DCO Filter Selection + DCOFLTSEL : PMC_PMC_APLLACR_DCOFLTSEL_Field := 16#0#; + -- PLL Filter Selection + FLTSEL : PMC_PMC_APLLACR_FLTSEL_Field := 16#0#; + -- Bias Voltage Selection + BIAS : PMC_PMC_APLLACR_BIAS_Field := 16#0#; + -- unspecified + Reserved_10_31 : HAL.UInt22 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PMC_PMC_APLLACR_Register use record + DCOFLTSEL at 0 range 0 .. 3; + FLTSEL at 0 range 4 .. 7; + BIAS at 0 range 8 .. 9; + Reserved_10_31 at 0 range 10 .. 31; + end record; + + subtype PMC_PMC_WMST_WMST_Field is HAL.UInt8; + + -- Write Access Password + type PMC_WMST_KEY_Field is + ( + -- Reset value for the field + Pmc_Wmst_Key_Field_Reset, + -- Writing any other value in this field aborts the write + -- operation.Always reads as 0. + Passwd) + with Size => 8; + for PMC_WMST_KEY_Field use + (Pmc_Wmst_Key_Field_Reset => 0, + Passwd => 90); + + -- Wait Mode Startup Time Register + type PMC_PMC_WMST_Register is record + -- Wait Mode Startup Time + WMST : PMC_PMC_WMST_WMST_Field := 16#0#; + -- unspecified + Reserved_8_23 : HAL.UInt16 := 16#0#; + -- Write Access Password + KEY : PMC_WMST_KEY_Field := Pmc_Wmst_Key_Field_Reset; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PMC_PMC_WMST_Register use record + WMST at 0 range 0 .. 7; + Reserved_8_23 at 0 range 8 .. 23; + KEY at 0 range 24 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- Power Management Controller + type PMC_Peripheral is record + -- System Clock Enable Register + PMC_SCER : aliased PMC_PMC_SCER_Register; + -- System Clock Disable Register + PMC_SCDR : aliased PMC_PMC_SCDR_Register; + -- System Clock Status Register + PMC_SCSR : aliased PMC_PMC_SCSR_Register; + -- Peripheral Clock Enable Register 0 + PMC_PCER0 : aliased PMC_PMC_PCER0_Register; + -- Peripheral Clock Disable Register 0 + PMC_PCDR0 : aliased PMC_PMC_PCDR0_Register; + -- Peripheral Clock Status Register 0 + PMC_PCSR0 : aliased PMC_PMC_PCSR0_Register; + -- UTMI Clock Register + CKGR_UCKR : aliased PMC_CKGR_UCKR_Register; + -- Main Oscillator Register + CKGR_MOR : aliased PMC_CKGR_MOR_Register; + -- Main Clock Frequency Register + CKGR_MCFR : aliased PMC_CKGR_MCFR_Register; + -- PLLA Register + CKGR_PLLAR : aliased PMC_CKGR_PLLAR_Register; + -- Master Clock Register + PMC_MCKR : aliased PMC_PMC_MCKR_Register; + -- USB Clock Register + PMC_USB : aliased PMC_PMC_USB_Register; + -- Programmable Clock Register (chid = 0) 0 + PMC_PCK : aliased PMC_PMC_PCK_Registers; + -- Interrupt Enable Register + PMC_IER : aliased PMC_PMC_IER_Register; + -- Interrupt Disable Register + PMC_IDR : aliased PMC_PMC_IDR_Register; + -- Status Register + PMC_SR : aliased PMC_PMC_SR_Register; + -- Interrupt Mask Register + PMC_IMR : aliased PMC_PMC_IMR_Register; + -- Fast Startup Mode Register + PMC_FSMR : aliased PMC_PMC_FSMR_Register; + -- Fast Startup Polarity Register + PMC_FSPR : aliased PMC_PMC_FSPR_Register; + -- Fault Output Clear Register + PMC_FOCR : aliased PMC_PMC_FOCR_Register; + -- Write Protection Mode Register + PMC_WPMR : aliased PMC_PMC_WPMR_Register; + -- Write Protection Status Register + PMC_WPSR : aliased PMC_PMC_WPSR_Register; + -- Version Register + PMC_VERSION : aliased PMC_PMC_VERSION_Register; + -- Peripheral Clock Enable Register 1 + PMC_PCER1 : aliased PMC_PMC_PCER1_Register; + -- Peripheral Clock Disable Register 1 + PMC_PCDR1 : aliased PMC_PMC_PCDR1_Register; + -- Peripheral Clock Status Register 1 + PMC_PCSR1 : aliased PMC_PMC_PCSR1_Register; + -- Peripheral Control Register + PMC_PCR : aliased PMC_PMC_PCR_Register; + -- Oscillator Calibration Register + PMC_OCR : aliased PMC_PMC_OCR_Register; + -- SleepWalking Enable Register 0 + PMC_SLPWK_ER0 : aliased PMC_PMC_SLPWK_ER0_Register; + -- SleepWalking Disable Register 0 + PMC_SLPWK_DR0 : aliased PMC_PMC_SLPWK_DR0_Register; + -- SleepWalking Status Register 0 + PMC_SLPWK_SR0 : aliased PMC_PMC_SLPWK_SR0_Register; + -- SleepWalking Activity Status Register 0 + PMC_SLPWK_ASR0 : aliased PMC_PMC_SLPWK_ASR0_Register; + -- PLL Maximum Multiplier Value Register + PMC_PMMR : aliased PMC_PMC_PMMR_Register; + -- SleepWalking Enable Register 1 + PMC_SLPWK_ER1 : aliased PMC_PMC_SLPWK_ER1_Register; + -- SleepWalking Disable Register 1 + PMC_SLPWK_DR1 : aliased PMC_PMC_SLPWK_DR1_Register; + -- SleepWalking Status Register 1 + PMC_SLPWK_SR1 : aliased PMC_PMC_SLPWK_SR1_Register; + -- SleepWalking Activity Status Register 1 + PMC_SLPWK_ASR1 : aliased PMC_PMC_SLPWK_ASR1_Register; + -- SleepWalking Activity In Progress Register + PMC_SLPWK_AIPR : aliased PMC_PMC_SLPWK_AIPR_Register; + -- Audio PLL Analog Configuration Register + PMC_APLLACR : aliased PMC_PMC_APLLACR_Register; + -- Wait Mode Startup Time Register + PMC_WMST : aliased PMC_PMC_WMST_Register; + end record + with Volatile; + + for PMC_Peripheral use record + PMC_SCER at 16#0# range 0 .. 31; + PMC_SCDR at 16#4# range 0 .. 31; + PMC_SCSR at 16#8# range 0 .. 31; + PMC_PCER0 at 16#10# range 0 .. 31; + PMC_PCDR0 at 16#14# range 0 .. 31; + PMC_PCSR0 at 16#18# range 0 .. 31; + CKGR_UCKR at 16#1C# range 0 .. 31; + CKGR_MOR at 16#20# range 0 .. 31; + CKGR_MCFR at 16#24# range 0 .. 31; + CKGR_PLLAR at 16#28# range 0 .. 31; + PMC_MCKR at 16#30# range 0 .. 31; + PMC_USB at 16#38# range 0 .. 31; + PMC_PCK at 16#40# range 0 .. 255; + PMC_IER at 16#60# range 0 .. 31; + PMC_IDR at 16#64# range 0 .. 31; + PMC_SR at 16#68# range 0 .. 31; + PMC_IMR at 16#6C# range 0 .. 31; + PMC_FSMR at 16#70# range 0 .. 31; + PMC_FSPR at 16#74# range 0 .. 31; + PMC_FOCR at 16#78# range 0 .. 31; + PMC_WPMR at 16#E4# range 0 .. 31; + PMC_WPSR at 16#E8# range 0 .. 31; + PMC_VERSION at 16#FC# range 0 .. 31; + PMC_PCER1 at 16#100# range 0 .. 31; + PMC_PCDR1 at 16#104# range 0 .. 31; + PMC_PCSR1 at 16#108# range 0 .. 31; + PMC_PCR at 16#10C# range 0 .. 31; + PMC_OCR at 16#110# range 0 .. 31; + PMC_SLPWK_ER0 at 16#114# range 0 .. 31; + PMC_SLPWK_DR0 at 16#118# range 0 .. 31; + PMC_SLPWK_SR0 at 16#11C# range 0 .. 31; + PMC_SLPWK_ASR0 at 16#120# range 0 .. 31; + PMC_PMMR at 16#130# range 0 .. 31; + PMC_SLPWK_ER1 at 16#134# range 0 .. 31; + PMC_SLPWK_DR1 at 16#138# range 0 .. 31; + PMC_SLPWK_SR1 at 16#13C# range 0 .. 31; + PMC_SLPWK_ASR1 at 16#140# range 0 .. 31; + PMC_SLPWK_AIPR at 16#144# range 0 .. 31; + PMC_APLLACR at 16#158# range 0 .. 31; + PMC_WMST at 16#15C# range 0 .. 31; + end record; + + -- Power Management Controller + PMC_Periph : aliased PMC_Peripheral + with Import, Address => System'To_Address (16#400E0600#); + +end SAM_SVD.PMC; diff --git a/arch/ARM/SAM/svd/atsamv71/sam_svd-pwm.ads b/arch/ARM/SAM/svd/atsamv71/sam_svd-pwm.ads new file mode 100644 index 000000000..3b5f156c8 --- /dev/null +++ b/arch/ARM/SAM/svd/atsamv71/sam_svd-pwm.ads @@ -0,0 +1,2681 @@ +-- This spec has been automatically generated from ATSAMV71Q21.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package SAM_SVD.PWM is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + -- CLKA Divide Factor + type PWM_CLK_DIVA_Field is + ( + -- CLKA clock is turned off + Clka_Poff, + -- CLKA clock is clock selected by PREA + Prea) + with Size => 8; + for PWM_CLK_DIVA_Field use + (Clka_Poff => 0, + Prea => 1); + + -- CLKA Source Clock Selection + type PWM_CLK_PREA_Field is + ( + -- Peripheral clock + Clk, + -- Peripheral clock/2 + Clk_Div2, + -- Peripheral clock/4 + Clk_Div4, + -- Peripheral clock/8 + Clk_Div8, + -- Peripheral clock/16 + Clk_Div16, + -- Peripheral clock/32 + Clk_Div32, + -- Peripheral clock/64 + Clk_Div64, + -- Peripheral clock/128 + Clk_Div128, + -- Peripheral clock/256 + Clk_Div256, + -- Peripheral clock/512 + Clk_Div512, + -- Peripheral clock/1024 + Clk_Div1024) + with Size => 4; + for PWM_CLK_PREA_Field use + (Clk => 0, + Clk_Div2 => 1, + Clk_Div4 => 2, + Clk_Div8 => 3, + Clk_Div16 => 4, + Clk_Div32 => 5, + Clk_Div64 => 6, + Clk_Div128 => 7, + Clk_Div256 => 8, + Clk_Div512 => 9, + Clk_Div1024 => 10); + + -- CLKB Divide Factor + type PWM_CLK_DIVB_Field is + ( + -- CLKB clock is turned off + Clkb_Poff, + -- CLKB clock is clock selected by PREB + Preb) + with Size => 8; + for PWM_CLK_DIVB_Field use + (Clkb_Poff => 0, + Preb => 1); + + -- CLKB Source Clock Selection + type PWM_CLK_PREB_Field is + ( + -- Peripheral clock + Clk, + -- Peripheral clock/2 + Clk_Div2, + -- Peripheral clock/4 + Clk_Div4, + -- Peripheral clock/8 + Clk_Div8, + -- Peripheral clock/16 + Clk_Div16, + -- Peripheral clock/32 + Clk_Div32, + -- Peripheral clock/64 + Clk_Div64, + -- Peripheral clock/128 + Clk_Div128, + -- Peripheral clock/256 + Clk_Div256, + -- Peripheral clock/512 + Clk_Div512, + -- Peripheral clock/1024 + Clk_Div1024) + with Size => 4; + for PWM_CLK_PREB_Field use + (Clk => 0, + Clk_Div2 => 1, + Clk_Div4 => 2, + Clk_Div8 => 3, + Clk_Div16 => 4, + Clk_Div32 => 5, + Clk_Div64 => 6, + Clk_Div128 => 7, + Clk_Div256 => 8, + Clk_Div512 => 9, + Clk_Div1024 => 10); + + -- PWM Clock Register + type PWM_PWM_CLK_Register is record + -- CLKA Divide Factor + DIVA : PWM_CLK_DIVA_Field := SAM_SVD.PWM.Clka_Poff; + -- CLKA Source Clock Selection + PREA : PWM_CLK_PREA_Field := SAM_SVD.PWM.Clk; + -- unspecified + Reserved_12_15 : HAL.UInt4 := 16#0#; + -- CLKB Divide Factor + DIVB : PWM_CLK_DIVB_Field := SAM_SVD.PWM.Clkb_Poff; + -- CLKB Source Clock Selection + PREB : PWM_CLK_PREB_Field := SAM_SVD.PWM.Clk; + -- unspecified + Reserved_28_31 : HAL.UInt4 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PWM_PWM_CLK_Register use record + DIVA at 0 range 0 .. 7; + PREA at 0 range 8 .. 11; + Reserved_12_15 at 0 range 12 .. 15; + DIVB at 0 range 16 .. 23; + PREB at 0 range 24 .. 27; + Reserved_28_31 at 0 range 28 .. 31; + end record; + + -- PWM_PWM_ENA_CHID array + type PWM_PWM_ENA_CHID_Field_Array is array (0 .. 3) of Boolean + with Component_Size => 1, Size => 4; + + -- Type definition for PWM_PWM_ENA_CHID + type PWM_PWM_ENA_CHID_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CHID as a value + Val : HAL.UInt4; + when True => + -- CHID as an array + Arr : PWM_PWM_ENA_CHID_Field_Array; + end case; + end record + with Unchecked_Union, Size => 4; + + for PWM_PWM_ENA_CHID_Field use record + Val at 0 range 0 .. 3; + Arr at 0 range 0 .. 3; + end record; + + -- PWM Enable Register + type PWM_PWM_ENA_Register is record + -- Write-only. Channel ID + CHID : PWM_PWM_ENA_CHID_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_4_31 : HAL.UInt28 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PWM_PWM_ENA_Register use record + CHID at 0 range 0 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + -- PWM_PWM_DIS_CHID array + type PWM_PWM_DIS_CHID_Field_Array is array (0 .. 3) of Boolean + with Component_Size => 1, Size => 4; + + -- Type definition for PWM_PWM_DIS_CHID + type PWM_PWM_DIS_CHID_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CHID as a value + Val : HAL.UInt4; + when True => + -- CHID as an array + Arr : PWM_PWM_DIS_CHID_Field_Array; + end case; + end record + with Unchecked_Union, Size => 4; + + for PWM_PWM_DIS_CHID_Field use record + Val at 0 range 0 .. 3; + Arr at 0 range 0 .. 3; + end record; + + -- PWM Disable Register + type PWM_PWM_DIS_Register is record + -- Write-only. Channel ID + CHID : PWM_PWM_DIS_CHID_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_4_31 : HAL.UInt28 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PWM_PWM_DIS_Register use record + CHID at 0 range 0 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + -- PWM_PWM_SR_CHID array + type PWM_PWM_SR_CHID_Field_Array is array (0 .. 3) of Boolean + with Component_Size => 1, Size => 4; + + -- Type definition for PWM_PWM_SR_CHID + type PWM_PWM_SR_CHID_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CHID as a value + Val : HAL.UInt4; + when True => + -- CHID as an array + Arr : PWM_PWM_SR_CHID_Field_Array; + end case; + end record + with Unchecked_Union, Size => 4; + + for PWM_PWM_SR_CHID_Field use record + Val at 0 range 0 .. 3; + Arr at 0 range 0 .. 3; + end record; + + -- PWM Status Register + type PWM_PWM_SR_Register is record + -- Read-only. Channel ID + CHID : PWM_PWM_SR_CHID_Field; + -- unspecified + Reserved_4_31 : HAL.UInt28; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PWM_PWM_SR_Register use record + CHID at 0 range 0 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + -- PWM_PWM_IER1_CHID array + type PWM_PWM_IER1_CHID_Field_Array is array (0 .. 3) of Boolean + with Component_Size => 1, Size => 4; + + -- Type definition for PWM_PWM_IER1_CHID + type PWM_PWM_IER1_CHID_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CHID as a value + Val : HAL.UInt4; + when True => + -- CHID as an array + Arr : PWM_PWM_IER1_CHID_Field_Array; + end case; + end record + with Unchecked_Union, Size => 4; + + for PWM_PWM_IER1_CHID_Field use record + Val at 0 range 0 .. 3; + Arr at 0 range 0 .. 3; + end record; + + -- PWM_PWM_IER1_FCHID array + type PWM_PWM_IER1_FCHID_Field_Array is array (0 .. 3) of Boolean + with Component_Size => 1, Size => 4; + + -- Type definition for PWM_PWM_IER1_FCHID + type PWM_PWM_IER1_FCHID_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- FCHID as a value + Val : HAL.UInt4; + when True => + -- FCHID as an array + Arr : PWM_PWM_IER1_FCHID_Field_Array; + end case; + end record + with Unchecked_Union, Size => 4; + + for PWM_PWM_IER1_FCHID_Field use record + Val at 0 range 0 .. 3; + Arr at 0 range 0 .. 3; + end record; + + -- PWM Interrupt Enable Register 1 + type PWM_PWM_IER1_Register is record + -- Write-only. Counter Event on Channel 0 Interrupt Enable + CHID : PWM_PWM_IER1_CHID_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_4_15 : HAL.UInt12 := 16#0#; + -- Write-only. Fault Protection Trigger on Channel 0 Interrupt Enable + FCHID : PWM_PWM_IER1_FCHID_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_20_31 : HAL.UInt12 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PWM_PWM_IER1_Register use record + CHID at 0 range 0 .. 3; + Reserved_4_15 at 0 range 4 .. 15; + FCHID at 0 range 16 .. 19; + Reserved_20_31 at 0 range 20 .. 31; + end record; + + -- PWM_PWM_IDR1_CHID array + type PWM_PWM_IDR1_CHID_Field_Array is array (0 .. 3) of Boolean + with Component_Size => 1, Size => 4; + + -- Type definition for PWM_PWM_IDR1_CHID + type PWM_PWM_IDR1_CHID_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CHID as a value + Val : HAL.UInt4; + when True => + -- CHID as an array + Arr : PWM_PWM_IDR1_CHID_Field_Array; + end case; + end record + with Unchecked_Union, Size => 4; + + for PWM_PWM_IDR1_CHID_Field use record + Val at 0 range 0 .. 3; + Arr at 0 range 0 .. 3; + end record; + + -- PWM_PWM_IDR1_FCHID array + type PWM_PWM_IDR1_FCHID_Field_Array is array (0 .. 3) of Boolean + with Component_Size => 1, Size => 4; + + -- Type definition for PWM_PWM_IDR1_FCHID + type PWM_PWM_IDR1_FCHID_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- FCHID as a value + Val : HAL.UInt4; + when True => + -- FCHID as an array + Arr : PWM_PWM_IDR1_FCHID_Field_Array; + end case; + end record + with Unchecked_Union, Size => 4; + + for PWM_PWM_IDR1_FCHID_Field use record + Val at 0 range 0 .. 3; + Arr at 0 range 0 .. 3; + end record; + + -- PWM Interrupt Disable Register 1 + type PWM_PWM_IDR1_Register is record + -- Write-only. Counter Event on Channel 0 Interrupt Disable + CHID : PWM_PWM_IDR1_CHID_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_4_15 : HAL.UInt12 := 16#0#; + -- Write-only. Fault Protection Trigger on Channel 0 Interrupt Disable + FCHID : PWM_PWM_IDR1_FCHID_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_20_31 : HAL.UInt12 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PWM_PWM_IDR1_Register use record + CHID at 0 range 0 .. 3; + Reserved_4_15 at 0 range 4 .. 15; + FCHID at 0 range 16 .. 19; + Reserved_20_31 at 0 range 20 .. 31; + end record; + + -- PWM_PWM_IMR1_CHID array + type PWM_PWM_IMR1_CHID_Field_Array is array (0 .. 3) of Boolean + with Component_Size => 1, Size => 4; + + -- Type definition for PWM_PWM_IMR1_CHID + type PWM_PWM_IMR1_CHID_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CHID as a value + Val : HAL.UInt4; + when True => + -- CHID as an array + Arr : PWM_PWM_IMR1_CHID_Field_Array; + end case; + end record + with Unchecked_Union, Size => 4; + + for PWM_PWM_IMR1_CHID_Field use record + Val at 0 range 0 .. 3; + Arr at 0 range 0 .. 3; + end record; + + -- PWM_PWM_IMR1_FCHID array + type PWM_PWM_IMR1_FCHID_Field_Array is array (0 .. 3) of Boolean + with Component_Size => 1, Size => 4; + + -- Type definition for PWM_PWM_IMR1_FCHID + type PWM_PWM_IMR1_FCHID_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- FCHID as a value + Val : HAL.UInt4; + when True => + -- FCHID as an array + Arr : PWM_PWM_IMR1_FCHID_Field_Array; + end case; + end record + with Unchecked_Union, Size => 4; + + for PWM_PWM_IMR1_FCHID_Field use record + Val at 0 range 0 .. 3; + Arr at 0 range 0 .. 3; + end record; + + -- PWM Interrupt Mask Register 1 + type PWM_PWM_IMR1_Register is record + -- Read-only. Counter Event on Channel 0 Interrupt Mask + CHID : PWM_PWM_IMR1_CHID_Field; + -- unspecified + Reserved_4_15 : HAL.UInt12; + -- Read-only. Fault Protection Trigger on Channel 0 Interrupt Mask + FCHID : PWM_PWM_IMR1_FCHID_Field; + -- unspecified + Reserved_20_31 : HAL.UInt12; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PWM_PWM_IMR1_Register use record + CHID at 0 range 0 .. 3; + Reserved_4_15 at 0 range 4 .. 15; + FCHID at 0 range 16 .. 19; + Reserved_20_31 at 0 range 20 .. 31; + end record; + + -- PWM_PWM_ISR1_CHID array + type PWM_PWM_ISR1_CHID_Field_Array is array (0 .. 3) of Boolean + with Component_Size => 1, Size => 4; + + -- Type definition for PWM_PWM_ISR1_CHID + type PWM_PWM_ISR1_CHID_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CHID as a value + Val : HAL.UInt4; + when True => + -- CHID as an array + Arr : PWM_PWM_ISR1_CHID_Field_Array; + end case; + end record + with Unchecked_Union, Size => 4; + + for PWM_PWM_ISR1_CHID_Field use record + Val at 0 range 0 .. 3; + Arr at 0 range 0 .. 3; + end record; + + -- PWM_PWM_ISR1_FCHID array + type PWM_PWM_ISR1_FCHID_Field_Array is array (0 .. 3) of Boolean + with Component_Size => 1, Size => 4; + + -- Type definition for PWM_PWM_ISR1_FCHID + type PWM_PWM_ISR1_FCHID_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- FCHID as a value + Val : HAL.UInt4; + when True => + -- FCHID as an array + Arr : PWM_PWM_ISR1_FCHID_Field_Array; + end case; + end record + with Unchecked_Union, Size => 4; + + for PWM_PWM_ISR1_FCHID_Field use record + Val at 0 range 0 .. 3; + Arr at 0 range 0 .. 3; + end record; + + -- PWM Interrupt Status Register 1 + type PWM_PWM_ISR1_Register is record + -- Read-only. Counter Event on Channel 0 + CHID : PWM_PWM_ISR1_CHID_Field; + -- unspecified + Reserved_4_15 : HAL.UInt12; + -- Read-only. Fault Protection Trigger on Channel 0 + FCHID : PWM_PWM_ISR1_FCHID_Field; + -- unspecified + Reserved_20_31 : HAL.UInt12; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PWM_PWM_ISR1_Register use record + CHID at 0 range 0 .. 3; + Reserved_4_15 at 0 range 4 .. 15; + FCHID at 0 range 16 .. 19; + Reserved_20_31 at 0 range 20 .. 31; + end record; + + -- PWM_PWM_SCM_SYNC array + type PWM_PWM_SCM_SYNC_Field_Array is array (0 .. 3) of Boolean + with Component_Size => 1, Size => 4; + + -- Type definition for PWM_PWM_SCM_SYNC + type PWM_PWM_SCM_SYNC_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- SYNC as a value + Val : HAL.UInt4; + when True => + -- SYNC as an array + Arr : PWM_PWM_SCM_SYNC_Field_Array; + end case; + end record + with Unchecked_Union, Size => 4; + + for PWM_PWM_SCM_SYNC_Field use record + Val at 0 range 0 .. 3; + Arr at 0 range 0 .. 3; + end record; + + -- Synchronous Channels Update Mode + type PWM_SCM_UPDM_Field is + ( + -- Manual write of double buffer registers and manual update of + -- synchronous channels + Mode0, + -- Manual write of double buffer registers and automatic update of + -- synchronous channels + Mode1, + -- Automatic write of duty-cycle update registers by the DMA Controller + -- and automatic update of synchronous channels + Mode2) + with Size => 2; + for PWM_SCM_UPDM_Field use + (Mode0 => 0, + Mode1 => 1, + Mode2 => 2); + + subtype PWM_PWM_SCM_PTRCS_Field is HAL.UInt3; + + -- PWM Sync Channels Mode Register + type PWM_PWM_SCM_Register is record + -- Synchronous Channel 0 + SYNC : PWM_PWM_SCM_SYNC_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_4_15 : HAL.UInt12 := 16#0#; + -- Synchronous Channels Update Mode + UPDM : PWM_SCM_UPDM_Field := SAM_SVD.PWM.Mode0; + -- unspecified + Reserved_18_19 : HAL.UInt2 := 16#0#; + -- DMA Controller Transfer Request Mode + PTRM : Boolean := False; + -- DMA Controller Transfer Request Comparison Selection + PTRCS : PWM_PWM_SCM_PTRCS_Field := 16#0#; + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PWM_PWM_SCM_Register use record + SYNC at 0 range 0 .. 3; + Reserved_4_15 at 0 range 4 .. 15; + UPDM at 0 range 16 .. 17; + Reserved_18_19 at 0 range 18 .. 19; + PTRM at 0 range 20 .. 20; + PTRCS at 0 range 21 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype PWM_PWM_DMAR_DMADUTY_Field is HAL.UInt24; + + -- PWM DMA Register + type PWM_PWM_DMAR_Register is record + -- Write-only. Duty-Cycle Holding Register for DMA Access + DMADUTY : PWM_PWM_DMAR_DMADUTY_Field := 16#0#; + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PWM_PWM_DMAR_Register use record + DMADUTY at 0 range 0 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- PWM Sync Channels Update Control Register + type PWM_PWM_SCUC_Register is record + -- Synchronous Channels Update Unlock + UPDULOCK : Boolean := False; + -- unspecified + Reserved_1_31 : HAL.UInt31 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PWM_PWM_SCUC_Register use record + UPDULOCK at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + subtype PWM_PWM_SCUP_UPR_Field is HAL.UInt4; + subtype PWM_PWM_SCUP_UPRCNT_Field is HAL.UInt4; + + -- PWM Sync Channels Update Period Register + type PWM_PWM_SCUP_Register is record + -- Update Period + UPR : PWM_PWM_SCUP_UPR_Field := 16#0#; + -- Update Period Counter + UPRCNT : PWM_PWM_SCUP_UPRCNT_Field := 16#0#; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PWM_PWM_SCUP_Register use record + UPR at 0 range 0 .. 3; + UPRCNT at 0 range 4 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype PWM_PWM_SCUPUPD_UPRUPD_Field is HAL.UInt4; + + -- PWM Sync Channels Update Period Update Register + type PWM_PWM_SCUPUPD_Register is record + -- Write-only. Update Period Update + UPRUPD : PWM_PWM_SCUPUPD_UPRUPD_Field := 16#0#; + -- unspecified + Reserved_4_31 : HAL.UInt28 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PWM_PWM_SCUPUPD_Register use record + UPRUPD at 0 range 0 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + -- PWM_PWM_IER2_CMPM array + type PWM_PWM_IER2_CMPM_Field_Array is array (0 .. 7) of Boolean + with Component_Size => 1, Size => 8; + + -- Type definition for PWM_PWM_IER2_CMPM + type PWM_PWM_IER2_CMPM_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CMPM as a value + Val : HAL.UInt8; + when True => + -- CMPM as an array + Arr : PWM_PWM_IER2_CMPM_Field_Array; + end case; + end record + with Unchecked_Union, Size => 8; + + for PWM_PWM_IER2_CMPM_Field use record + Val at 0 range 0 .. 7; + Arr at 0 range 0 .. 7; + end record; + + -- PWM_PWM_IER2_CMPU array + type PWM_PWM_IER2_CMPU_Field_Array is array (0 .. 7) of Boolean + with Component_Size => 1, Size => 8; + + -- Type definition for PWM_PWM_IER2_CMPU + type PWM_PWM_IER2_CMPU_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CMPU as a value + Val : HAL.UInt8; + when True => + -- CMPU as an array + Arr : PWM_PWM_IER2_CMPU_Field_Array; + end case; + end record + with Unchecked_Union, Size => 8; + + for PWM_PWM_IER2_CMPU_Field use record + Val at 0 range 0 .. 7; + Arr at 0 range 0 .. 7; + end record; + + -- PWM Interrupt Enable Register 2 + type PWM_PWM_IER2_Register is record + -- Write-only. Write Ready for Synchronous Channels Update Interrupt + -- Enable + WRDY : Boolean := False; + -- unspecified + Reserved_1_2 : HAL.UInt2 := 16#0#; + -- Write-only. Synchronous Channels Update Underrun Error Interrupt + -- Enable + UNRE : Boolean := False; + -- unspecified + Reserved_4_7 : HAL.UInt4 := 16#0#; + -- Write-only. Comparison 0 Match Interrupt Enable + CMPM : PWM_PWM_IER2_CMPM_Field := + (As_Array => False, Val => 16#0#); + -- Write-only. Comparison 0 Update Interrupt Enable + CMPU : PWM_PWM_IER2_CMPU_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PWM_PWM_IER2_Register use record + WRDY at 0 range 0 .. 0; + Reserved_1_2 at 0 range 1 .. 2; + UNRE at 0 range 3 .. 3; + Reserved_4_7 at 0 range 4 .. 7; + CMPM at 0 range 8 .. 15; + CMPU at 0 range 16 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- PWM_PWM_IDR2_CMPM array + type PWM_PWM_IDR2_CMPM_Field_Array is array (0 .. 7) of Boolean + with Component_Size => 1, Size => 8; + + -- Type definition for PWM_PWM_IDR2_CMPM + type PWM_PWM_IDR2_CMPM_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CMPM as a value + Val : HAL.UInt8; + when True => + -- CMPM as an array + Arr : PWM_PWM_IDR2_CMPM_Field_Array; + end case; + end record + with Unchecked_Union, Size => 8; + + for PWM_PWM_IDR2_CMPM_Field use record + Val at 0 range 0 .. 7; + Arr at 0 range 0 .. 7; + end record; + + -- PWM_PWM_IDR2_CMPU array + type PWM_PWM_IDR2_CMPU_Field_Array is array (0 .. 7) of Boolean + with Component_Size => 1, Size => 8; + + -- Type definition for PWM_PWM_IDR2_CMPU + type PWM_PWM_IDR2_CMPU_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CMPU as a value + Val : HAL.UInt8; + when True => + -- CMPU as an array + Arr : PWM_PWM_IDR2_CMPU_Field_Array; + end case; + end record + with Unchecked_Union, Size => 8; + + for PWM_PWM_IDR2_CMPU_Field use record + Val at 0 range 0 .. 7; + Arr at 0 range 0 .. 7; + end record; + + -- PWM Interrupt Disable Register 2 + type PWM_PWM_IDR2_Register is record + -- Write-only. Write Ready for Synchronous Channels Update Interrupt + -- Disable + WRDY : Boolean := False; + -- unspecified + Reserved_1_2 : HAL.UInt2 := 16#0#; + -- Write-only. Synchronous Channels Update Underrun Error Interrupt + -- Disable + UNRE : Boolean := False; + -- unspecified + Reserved_4_7 : HAL.UInt4 := 16#0#; + -- Write-only. Comparison 0 Match Interrupt Disable + CMPM : PWM_PWM_IDR2_CMPM_Field := + (As_Array => False, Val => 16#0#); + -- Write-only. Comparison 0 Update Interrupt Disable + CMPU : PWM_PWM_IDR2_CMPU_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PWM_PWM_IDR2_Register use record + WRDY at 0 range 0 .. 0; + Reserved_1_2 at 0 range 1 .. 2; + UNRE at 0 range 3 .. 3; + Reserved_4_7 at 0 range 4 .. 7; + CMPM at 0 range 8 .. 15; + CMPU at 0 range 16 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- PWM_PWM_IMR2_CMPM array + type PWM_PWM_IMR2_CMPM_Field_Array is array (0 .. 7) of Boolean + with Component_Size => 1, Size => 8; + + -- Type definition for PWM_PWM_IMR2_CMPM + type PWM_PWM_IMR2_CMPM_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CMPM as a value + Val : HAL.UInt8; + when True => + -- CMPM as an array + Arr : PWM_PWM_IMR2_CMPM_Field_Array; + end case; + end record + with Unchecked_Union, Size => 8; + + for PWM_PWM_IMR2_CMPM_Field use record + Val at 0 range 0 .. 7; + Arr at 0 range 0 .. 7; + end record; + + -- PWM_PWM_IMR2_CMPU array + type PWM_PWM_IMR2_CMPU_Field_Array is array (0 .. 7) of Boolean + with Component_Size => 1, Size => 8; + + -- Type definition for PWM_PWM_IMR2_CMPU + type PWM_PWM_IMR2_CMPU_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CMPU as a value + Val : HAL.UInt8; + when True => + -- CMPU as an array + Arr : PWM_PWM_IMR2_CMPU_Field_Array; + end case; + end record + with Unchecked_Union, Size => 8; + + for PWM_PWM_IMR2_CMPU_Field use record + Val at 0 range 0 .. 7; + Arr at 0 range 0 .. 7; + end record; + + -- PWM Interrupt Mask Register 2 + type PWM_PWM_IMR2_Register is record + -- Read-only. Write Ready for Synchronous Channels Update Interrupt Mask + WRDY : Boolean; + -- unspecified + Reserved_1_2 : HAL.UInt2; + -- Read-only. Synchronous Channels Update Underrun Error Interrupt Mask + UNRE : Boolean; + -- unspecified + Reserved_4_7 : HAL.UInt4; + -- Read-only. Comparison 0 Match Interrupt Mask + CMPM : PWM_PWM_IMR2_CMPM_Field; + -- Read-only. Comparison 0 Update Interrupt Mask + CMPU : PWM_PWM_IMR2_CMPU_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PWM_PWM_IMR2_Register use record + WRDY at 0 range 0 .. 0; + Reserved_1_2 at 0 range 1 .. 2; + UNRE at 0 range 3 .. 3; + Reserved_4_7 at 0 range 4 .. 7; + CMPM at 0 range 8 .. 15; + CMPU at 0 range 16 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- PWM_PWM_ISR2_CMPM array + type PWM_PWM_ISR2_CMPM_Field_Array is array (0 .. 7) of Boolean + with Component_Size => 1, Size => 8; + + -- Type definition for PWM_PWM_ISR2_CMPM + type PWM_PWM_ISR2_CMPM_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CMPM as a value + Val : HAL.UInt8; + when True => + -- CMPM as an array + Arr : PWM_PWM_ISR2_CMPM_Field_Array; + end case; + end record + with Unchecked_Union, Size => 8; + + for PWM_PWM_ISR2_CMPM_Field use record + Val at 0 range 0 .. 7; + Arr at 0 range 0 .. 7; + end record; + + -- PWM_PWM_ISR2_CMPU array + type PWM_PWM_ISR2_CMPU_Field_Array is array (0 .. 7) of Boolean + with Component_Size => 1, Size => 8; + + -- Type definition for PWM_PWM_ISR2_CMPU + type PWM_PWM_ISR2_CMPU_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CMPU as a value + Val : HAL.UInt8; + when True => + -- CMPU as an array + Arr : PWM_PWM_ISR2_CMPU_Field_Array; + end case; + end record + with Unchecked_Union, Size => 8; + + for PWM_PWM_ISR2_CMPU_Field use record + Val at 0 range 0 .. 7; + Arr at 0 range 0 .. 7; + end record; + + -- PWM Interrupt Status Register 2 + type PWM_PWM_ISR2_Register is record + -- Read-only. Write Ready for Synchronous Channels Update + WRDY : Boolean; + -- unspecified + Reserved_1_2 : HAL.UInt2; + -- Read-only. Synchronous Channels Update Underrun Error + UNRE : Boolean; + -- unspecified + Reserved_4_7 : HAL.UInt4; + -- Read-only. Comparison 0 Match + CMPM : PWM_PWM_ISR2_CMPM_Field; + -- Read-only. Comparison 0 Update + CMPU : PWM_PWM_ISR2_CMPU_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PWM_PWM_ISR2_Register use record + WRDY at 0 range 0 .. 0; + Reserved_1_2 at 0 range 1 .. 2; + UNRE at 0 range 3 .. 3; + Reserved_4_7 at 0 range 4 .. 7; + CMPM at 0 range 8 .. 15; + CMPU at 0 range 16 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- PWM_PWM_OOV_OOVH array + type PWM_PWM_OOV_OOVH_Field_Array is array (0 .. 3) of Boolean + with Component_Size => 1, Size => 4; + + -- Type definition for PWM_PWM_OOV_OOVH + type PWM_PWM_OOV_OOVH_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- OOVH as a value + Val : HAL.UInt4; + when True => + -- OOVH as an array + Arr : PWM_PWM_OOV_OOVH_Field_Array; + end case; + end record + with Unchecked_Union, Size => 4; + + for PWM_PWM_OOV_OOVH_Field use record + Val at 0 range 0 .. 3; + Arr at 0 range 0 .. 3; + end record; + + -- PWM_PWM_OOV_OOVL array + type PWM_PWM_OOV_OOVL_Field_Array is array (0 .. 3) of Boolean + with Component_Size => 1, Size => 4; + + -- Type definition for PWM_PWM_OOV_OOVL + type PWM_PWM_OOV_OOVL_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- OOVL as a value + Val : HAL.UInt4; + when True => + -- OOVL as an array + Arr : PWM_PWM_OOV_OOVL_Field_Array; + end case; + end record + with Unchecked_Union, Size => 4; + + for PWM_PWM_OOV_OOVL_Field use record + Val at 0 range 0 .. 3; + Arr at 0 range 0 .. 3; + end record; + + -- PWM Output Override Value Register + type PWM_PWM_OOV_Register is record + -- Output Override Value for PWMH output of the channel 0 + OOVH : PWM_PWM_OOV_OOVH_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_4_15 : HAL.UInt12 := 16#0#; + -- Output Override Value for PWML output of the channel 0 + OOVL : PWM_PWM_OOV_OOVL_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_20_31 : HAL.UInt12 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PWM_PWM_OOV_Register use record + OOVH at 0 range 0 .. 3; + Reserved_4_15 at 0 range 4 .. 15; + OOVL at 0 range 16 .. 19; + Reserved_20_31 at 0 range 20 .. 31; + end record; + + -- PWM_PWM_OS_OSH array + type PWM_PWM_OS_OSH_Field_Array is array (0 .. 3) of Boolean + with Component_Size => 1, Size => 4; + + -- Type definition for PWM_PWM_OS_OSH + type PWM_PWM_OS_OSH_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- OSH as a value + Val : HAL.UInt4; + when True => + -- OSH as an array + Arr : PWM_PWM_OS_OSH_Field_Array; + end case; + end record + with Unchecked_Union, Size => 4; + + for PWM_PWM_OS_OSH_Field use record + Val at 0 range 0 .. 3; + Arr at 0 range 0 .. 3; + end record; + + -- PWM_PWM_OS_OSL array + type PWM_PWM_OS_OSL_Field_Array is array (0 .. 3) of Boolean + with Component_Size => 1, Size => 4; + + -- Type definition for PWM_PWM_OS_OSL + type PWM_PWM_OS_OSL_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- OSL as a value + Val : HAL.UInt4; + when True => + -- OSL as an array + Arr : PWM_PWM_OS_OSL_Field_Array; + end case; + end record + with Unchecked_Union, Size => 4; + + for PWM_PWM_OS_OSL_Field use record + Val at 0 range 0 .. 3; + Arr at 0 range 0 .. 3; + end record; + + -- PWM Output Selection Register + type PWM_PWM_OS_Register is record + -- Output Selection for PWMH output of the channel 0 + OSH : PWM_PWM_OS_OSH_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_4_15 : HAL.UInt12 := 16#0#; + -- Output Selection for PWML output of the channel 0 + OSL : PWM_PWM_OS_OSL_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_20_31 : HAL.UInt12 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PWM_PWM_OS_Register use record + OSH at 0 range 0 .. 3; + Reserved_4_15 at 0 range 4 .. 15; + OSL at 0 range 16 .. 19; + Reserved_20_31 at 0 range 20 .. 31; + end record; + + -- PWM_PWM_OSS_OSSH array + type PWM_PWM_OSS_OSSH_Field_Array is array (0 .. 3) of Boolean + with Component_Size => 1, Size => 4; + + -- Type definition for PWM_PWM_OSS_OSSH + type PWM_PWM_OSS_OSSH_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- OSSH as a value + Val : HAL.UInt4; + when True => + -- OSSH as an array + Arr : PWM_PWM_OSS_OSSH_Field_Array; + end case; + end record + with Unchecked_Union, Size => 4; + + for PWM_PWM_OSS_OSSH_Field use record + Val at 0 range 0 .. 3; + Arr at 0 range 0 .. 3; + end record; + + -- PWM_PWM_OSS_OSSL array + type PWM_PWM_OSS_OSSL_Field_Array is array (0 .. 3) of Boolean + with Component_Size => 1, Size => 4; + + -- Type definition for PWM_PWM_OSS_OSSL + type PWM_PWM_OSS_OSSL_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- OSSL as a value + Val : HAL.UInt4; + when True => + -- OSSL as an array + Arr : PWM_PWM_OSS_OSSL_Field_Array; + end case; + end record + with Unchecked_Union, Size => 4; + + for PWM_PWM_OSS_OSSL_Field use record + Val at 0 range 0 .. 3; + Arr at 0 range 0 .. 3; + end record; + + -- PWM Output Selection Set Register + type PWM_PWM_OSS_Register is record + -- Write-only. Output Selection Set for PWMH output of the channel 0 + OSSH : PWM_PWM_OSS_OSSH_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_4_15 : HAL.UInt12 := 16#0#; + -- Write-only. Output Selection Set for PWML output of the channel 0 + OSSL : PWM_PWM_OSS_OSSL_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_20_31 : HAL.UInt12 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PWM_PWM_OSS_Register use record + OSSH at 0 range 0 .. 3; + Reserved_4_15 at 0 range 4 .. 15; + OSSL at 0 range 16 .. 19; + Reserved_20_31 at 0 range 20 .. 31; + end record; + + -- PWM_PWM_OSC_OSCH array + type PWM_PWM_OSC_OSCH_Field_Array is array (0 .. 3) of Boolean + with Component_Size => 1, Size => 4; + + -- Type definition for PWM_PWM_OSC_OSCH + type PWM_PWM_OSC_OSCH_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- OSCH as a value + Val : HAL.UInt4; + when True => + -- OSCH as an array + Arr : PWM_PWM_OSC_OSCH_Field_Array; + end case; + end record + with Unchecked_Union, Size => 4; + + for PWM_PWM_OSC_OSCH_Field use record + Val at 0 range 0 .. 3; + Arr at 0 range 0 .. 3; + end record; + + -- PWM_PWM_OSC_OSCL array + type PWM_PWM_OSC_OSCL_Field_Array is array (0 .. 3) of Boolean + with Component_Size => 1, Size => 4; + + -- Type definition for PWM_PWM_OSC_OSCL + type PWM_PWM_OSC_OSCL_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- OSCL as a value + Val : HAL.UInt4; + when True => + -- OSCL as an array + Arr : PWM_PWM_OSC_OSCL_Field_Array; + end case; + end record + with Unchecked_Union, Size => 4; + + for PWM_PWM_OSC_OSCL_Field use record + Val at 0 range 0 .. 3; + Arr at 0 range 0 .. 3; + end record; + + -- PWM Output Selection Clear Register + type PWM_PWM_OSC_Register is record + -- Write-only. Output Selection Clear for PWMH output of the channel 0 + OSCH : PWM_PWM_OSC_OSCH_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_4_15 : HAL.UInt12 := 16#0#; + -- Write-only. Output Selection Clear for PWML output of the channel 0 + OSCL : PWM_PWM_OSC_OSCL_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_20_31 : HAL.UInt12 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PWM_PWM_OSC_Register use record + OSCH at 0 range 0 .. 3; + Reserved_4_15 at 0 range 4 .. 15; + OSCL at 0 range 16 .. 19; + Reserved_20_31 at 0 range 20 .. 31; + end record; + + -- PWM_PWM_OSSUPD_OSSUPH array + type PWM_PWM_OSSUPD_OSSUPH_Field_Array is array (0 .. 3) of Boolean + with Component_Size => 1, Size => 4; + + -- Type definition for PWM_PWM_OSSUPD_OSSUPH + type PWM_PWM_OSSUPD_OSSUPH_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- OSSUPH as a value + Val : HAL.UInt4; + when True => + -- OSSUPH as an array + Arr : PWM_PWM_OSSUPD_OSSUPH_Field_Array; + end case; + end record + with Unchecked_Union, Size => 4; + + for PWM_PWM_OSSUPD_OSSUPH_Field use record + Val at 0 range 0 .. 3; + Arr at 0 range 0 .. 3; + end record; + + -- PWM_PWM_OSSUPD_OSSUPL array + type PWM_PWM_OSSUPD_OSSUPL_Field_Array is array (0 .. 3) of Boolean + with Component_Size => 1, Size => 4; + + -- Type definition for PWM_PWM_OSSUPD_OSSUPL + type PWM_PWM_OSSUPD_OSSUPL_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- OSSUPL as a value + Val : HAL.UInt4; + when True => + -- OSSUPL as an array + Arr : PWM_PWM_OSSUPD_OSSUPL_Field_Array; + end case; + end record + with Unchecked_Union, Size => 4; + + for PWM_PWM_OSSUPD_OSSUPL_Field use record + Val at 0 range 0 .. 3; + Arr at 0 range 0 .. 3; + end record; + + -- PWM Output Selection Set Update Register + type PWM_PWM_OSSUPD_Register is record + -- Write-only. Output Selection Set for PWMH output of the channel 0 + OSSUPH : PWM_PWM_OSSUPD_OSSUPH_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_4_15 : HAL.UInt12 := 16#0#; + -- Write-only. Output Selection Set for PWML output of the channel 0 + OSSUPL : PWM_PWM_OSSUPD_OSSUPL_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_20_31 : HAL.UInt12 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PWM_PWM_OSSUPD_Register use record + OSSUPH at 0 range 0 .. 3; + Reserved_4_15 at 0 range 4 .. 15; + OSSUPL at 0 range 16 .. 19; + Reserved_20_31 at 0 range 20 .. 31; + end record; + + -- PWM_PWM_OSCUPD_OSCUPH array + type PWM_PWM_OSCUPD_OSCUPH_Field_Array is array (0 .. 3) of Boolean + with Component_Size => 1, Size => 4; + + -- Type definition for PWM_PWM_OSCUPD_OSCUPH + type PWM_PWM_OSCUPD_OSCUPH_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- OSCUPH as a value + Val : HAL.UInt4; + when True => + -- OSCUPH as an array + Arr : PWM_PWM_OSCUPD_OSCUPH_Field_Array; + end case; + end record + with Unchecked_Union, Size => 4; + + for PWM_PWM_OSCUPD_OSCUPH_Field use record + Val at 0 range 0 .. 3; + Arr at 0 range 0 .. 3; + end record; + + -- PWM_PWM_OSCUPD_OSCUPL array + type PWM_PWM_OSCUPD_OSCUPL_Field_Array is array (0 .. 3) of Boolean + with Component_Size => 1, Size => 4; + + -- Type definition for PWM_PWM_OSCUPD_OSCUPL + type PWM_PWM_OSCUPD_OSCUPL_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- OSCUPL as a value + Val : HAL.UInt4; + when True => + -- OSCUPL as an array + Arr : PWM_PWM_OSCUPD_OSCUPL_Field_Array; + end case; + end record + with Unchecked_Union, Size => 4; + + for PWM_PWM_OSCUPD_OSCUPL_Field use record + Val at 0 range 0 .. 3; + Arr at 0 range 0 .. 3; + end record; + + -- PWM Output Selection Clear Update Register + type PWM_PWM_OSCUPD_Register is record + -- Write-only. Output Selection Clear for PWMH output of the channel 0 + OSCUPH : PWM_PWM_OSCUPD_OSCUPH_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_4_15 : HAL.UInt12 := 16#0#; + -- Write-only. Output Selection Clear for PWML output of the channel 0 + OSCUPL : PWM_PWM_OSCUPD_OSCUPL_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_20_31 : HAL.UInt12 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PWM_PWM_OSCUPD_Register use record + OSCUPH at 0 range 0 .. 3; + Reserved_4_15 at 0 range 4 .. 15; + OSCUPL at 0 range 16 .. 19; + Reserved_20_31 at 0 range 20 .. 31; + end record; + + subtype PWM_PWM_FMR_FPOL_Field is HAL.UInt8; + subtype PWM_PWM_FMR_FMOD_Field is HAL.UInt8; + subtype PWM_PWM_FMR_FFIL_Field is HAL.UInt8; + + -- PWM Fault Mode Register + type PWM_PWM_FMR_Register is record + -- Fault Polarity + FPOL : PWM_PWM_FMR_FPOL_Field := 16#0#; + -- Fault Activation Mode + FMOD : PWM_PWM_FMR_FMOD_Field := 16#0#; + -- Fault Filtering + FFIL : PWM_PWM_FMR_FFIL_Field := 16#0#; + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PWM_PWM_FMR_Register use record + FPOL at 0 range 0 .. 7; + FMOD at 0 range 8 .. 15; + FFIL at 0 range 16 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype PWM_PWM_FSR_FIV_Field is HAL.UInt8; + subtype PWM_PWM_FSR_FS_Field is HAL.UInt8; + + -- PWM Fault Status Register + type PWM_PWM_FSR_Register is record + -- Read-only. Fault Input Value + FIV : PWM_PWM_FSR_FIV_Field; + -- Read-only. Fault Status + FS : PWM_PWM_FSR_FS_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PWM_PWM_FSR_Register use record + FIV at 0 range 0 .. 7; + FS at 0 range 8 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype PWM_PWM_FCR_FCLR_Field is HAL.UInt8; + + -- PWM Fault Clear Register + type PWM_PWM_FCR_Register is record + -- Write-only. Fault Clear + FCLR : PWM_PWM_FCR_FCLR_Field := 16#0#; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PWM_PWM_FCR_Register use record + FCLR at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- PWM_PWM_FPV1_FPVH array + type PWM_PWM_FPV1_FPVH_Field_Array is array (0 .. 3) of Boolean + with Component_Size => 1, Size => 4; + + -- Type definition for PWM_PWM_FPV1_FPVH + type PWM_PWM_FPV1_FPVH_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- FPVH as a value + Val : HAL.UInt4; + when True => + -- FPVH as an array + Arr : PWM_PWM_FPV1_FPVH_Field_Array; + end case; + end record + with Unchecked_Union, Size => 4; + + for PWM_PWM_FPV1_FPVH_Field use record + Val at 0 range 0 .. 3; + Arr at 0 range 0 .. 3; + end record; + + -- PWM_PWM_FPV1_FPVL array + type PWM_PWM_FPV1_FPVL_Field_Array is array (0 .. 3) of Boolean + with Component_Size => 1, Size => 4; + + -- Type definition for PWM_PWM_FPV1_FPVL + type PWM_PWM_FPV1_FPVL_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- FPVL as a value + Val : HAL.UInt4; + when True => + -- FPVL as an array + Arr : PWM_PWM_FPV1_FPVL_Field_Array; + end case; + end record + with Unchecked_Union, Size => 4; + + for PWM_PWM_FPV1_FPVL_Field use record + Val at 0 range 0 .. 3; + Arr at 0 range 0 .. 3; + end record; + + -- PWM Fault Protection Value Register 1 + type PWM_PWM_FPV1_Register is record + -- Fault Protection Value for PWMH output on channel 0 + FPVH : PWM_PWM_FPV1_FPVH_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_4_15 : HAL.UInt12 := 16#0#; + -- Fault Protection Value for PWML output on channel 0 + FPVL : PWM_PWM_FPV1_FPVL_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_20_31 : HAL.UInt12 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PWM_PWM_FPV1_Register use record + FPVH at 0 range 0 .. 3; + Reserved_4_15 at 0 range 4 .. 15; + FPVL at 0 range 16 .. 19; + Reserved_20_31 at 0 range 20 .. 31; + end record; + + -- PWM_PWM_FPE_FPE array element + subtype PWM_PWM_FPE_FPE_Element is HAL.UInt8; + + -- PWM_PWM_FPE_FPE array + type PWM_PWM_FPE_FPE_Field_Array is array (0 .. 3) + of PWM_PWM_FPE_FPE_Element + with Component_Size => 8, Size => 32; + + -- PWM Fault Protection Enable Register + type PWM_PWM_FPE_Register + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- FPE as a value + Val : HAL.UInt32; + when True => + -- FPE as an array + Arr : PWM_PWM_FPE_FPE_Field_Array; + end case; + end record + with Unchecked_Union, Size => 32, Volatile_Full_Access, + Bit_Order => System.Low_Order_First; + + for PWM_PWM_FPE_Register use record + Val at 0 range 0 .. 31; + Arr at 0 range 0 .. 31; + end record; + + -- PWM_PWM_ELMR_CSEL array + type PWM_PWM_ELMR_CSEL_Field_Array is array (0 .. 7) of Boolean + with Component_Size => 1, Size => 8; + + -- Type definition for PWM_PWM_ELMR_CSEL + type PWM_PWM_ELMR_CSEL_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CSEL as a value + Val : HAL.UInt8; + when True => + -- CSEL as an array + Arr : PWM_PWM_ELMR_CSEL_Field_Array; + end case; + end record + with Unchecked_Union, Size => 8; + + for PWM_PWM_ELMR_CSEL_Field use record + Val at 0 range 0 .. 7; + Arr at 0 range 0 .. 7; + end record; + + -- PWM Event Line 0 Mode Register 0 + type PWM_PWM_ELMR_Register is record + -- Comparison 0 Selection + CSEL : PWM_PWM_ELMR_CSEL_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PWM_PWM_ELMR_Register use record + CSEL at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- PWM Event Line 0 Mode Register 0 + type PWM_PWM_ELMR_Registers is array (0 .. 1) of PWM_PWM_ELMR_Register + with Volatile; + + subtype PWM_PWM_SSPR_SPRD_Field is HAL.UInt24; + + -- PWM Spread Spectrum Register + type PWM_PWM_SSPR_Register is record + -- Spread Spectrum Limit Value + SPRD : PWM_PWM_SSPR_SPRD_Field := 16#0#; + -- Spread Spectrum Counter Mode + SPRDM : Boolean := False; + -- unspecified + Reserved_25_31 : HAL.UInt7 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PWM_PWM_SSPR_Register use record + SPRD at 0 range 0 .. 23; + SPRDM at 0 range 24 .. 24; + Reserved_25_31 at 0 range 25 .. 31; + end record; + + subtype PWM_PWM_SSPUP_SPRDUP_Field is HAL.UInt24; + + -- PWM Spread Spectrum Update Register + type PWM_PWM_SSPUP_Register is record + -- Write-only. Spread Spectrum Limit Value Update + SPRDUP : PWM_PWM_SSPUP_SPRDUP_Field := 16#0#; + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PWM_PWM_SSPUP_Register use record + SPRDUP at 0 range 0 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- PWM_PWM_SMMR_GCEN array + type PWM_PWM_SMMR_GCEN_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for PWM_PWM_SMMR_GCEN + type PWM_PWM_SMMR_GCEN_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- GCEN as a value + Val : HAL.UInt2; + when True => + -- GCEN as an array + Arr : PWM_PWM_SMMR_GCEN_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for PWM_PWM_SMMR_GCEN_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- PWM_PWM_SMMR_DOWN array + type PWM_PWM_SMMR_DOWN_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for PWM_PWM_SMMR_DOWN + type PWM_PWM_SMMR_DOWN_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- DOWN as a value + Val : HAL.UInt2; + when True => + -- DOWN as an array + Arr : PWM_PWM_SMMR_DOWN_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for PWM_PWM_SMMR_DOWN_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- PWM Stepper Motor Mode Register + type PWM_PWM_SMMR_Register is record + -- Gray Count ENable + GCEN : PWM_PWM_SMMR_GCEN_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_2_15 : HAL.UInt14 := 16#0#; + -- DOWN Count + DOWN : PWM_PWM_SMMR_DOWN_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_18_31 : HAL.UInt14 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PWM_PWM_SMMR_Register use record + GCEN at 0 range 0 .. 1; + Reserved_2_15 at 0 range 2 .. 15; + DOWN at 0 range 16 .. 17; + Reserved_18_31 at 0 range 18 .. 31; + end record; + + -- PWM_PWM_FPV2_FPZH array + type PWM_PWM_FPV2_FPZH_Field_Array is array (0 .. 3) of Boolean + with Component_Size => 1, Size => 4; + + -- Type definition for PWM_PWM_FPV2_FPZH + type PWM_PWM_FPV2_FPZH_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- FPZH as a value + Val : HAL.UInt4; + when True => + -- FPZH as an array + Arr : PWM_PWM_FPV2_FPZH_Field_Array; + end case; + end record + with Unchecked_Union, Size => 4; + + for PWM_PWM_FPV2_FPZH_Field use record + Val at 0 range 0 .. 3; + Arr at 0 range 0 .. 3; + end record; + + -- PWM_PWM_FPV2_FPZL array + type PWM_PWM_FPV2_FPZL_Field_Array is array (0 .. 3) of Boolean + with Component_Size => 1, Size => 4; + + -- Type definition for PWM_PWM_FPV2_FPZL + type PWM_PWM_FPV2_FPZL_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- FPZL as a value + Val : HAL.UInt4; + when True => + -- FPZL as an array + Arr : PWM_PWM_FPV2_FPZL_Field_Array; + end case; + end record + with Unchecked_Union, Size => 4; + + for PWM_PWM_FPV2_FPZL_Field use record + Val at 0 range 0 .. 3; + Arr at 0 range 0 .. 3; + end record; + + -- PWM Fault Protection Value 2 Register + type PWM_PWM_FPV2_Register is record + -- Fault Protection to Hi-Z for PWMH output on channel 0 + FPZH : PWM_PWM_FPV2_FPZH_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_4_15 : HAL.UInt12 := 16#0#; + -- Fault Protection to Hi-Z for PWML output on channel 0 + FPZL : PWM_PWM_FPV2_FPZL_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_20_31 : HAL.UInt12 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PWM_PWM_FPV2_Register use record + FPZH at 0 range 0 .. 3; + Reserved_4_15 at 0 range 4 .. 15; + FPZL at 0 range 16 .. 19; + Reserved_20_31 at 0 range 20 .. 31; + end record; + + -- Write Protection Command + type PWM_WPCR_WPCMD_Field is + ( + -- Disables the software write protection of the register groups of + -- which the bit WPRGx is at '1'. + Disable_Sw_Prot, + -- Enables the software write protection of the register groups of which + -- the bit WPRGx is at '1'. + Enable_Sw_Prot, + -- Enables the hardware write protection of the register groups of which + -- the bit WPRGx is at '1'. Only a hardware reset of the PWM controller + -- can disable the hardware write protection. Moreover, to meet security + -- requirements, the PIO lines associated with the PWM can not be + -- configured through the PIO interface. + Enable_Hw_Prot) + with Size => 2; + for PWM_WPCR_WPCMD_Field use + (Disable_Sw_Prot => 0, + Enable_Sw_Prot => 1, + Enable_Hw_Prot => 2); + + -- PWM_PWM_WPCR_WPRG array + type PWM_PWM_WPCR_WPRG_Field_Array is array (0 .. 5) of Boolean + with Component_Size => 1, Size => 6; + + -- Type definition for PWM_PWM_WPCR_WPRG + type PWM_PWM_WPCR_WPRG_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- WPRG as a value + Val : HAL.UInt6; + when True => + -- WPRG as an array + Arr : PWM_PWM_WPCR_WPRG_Field_Array; + end case; + end record + with Unchecked_Union, Size => 6; + + for PWM_PWM_WPCR_WPRG_Field use record + Val at 0 range 0 .. 5; + Arr at 0 range 0 .. 5; + end record; + + -- Write Protection Key + type PWM_WPCR_WPKEY_Field is + ( + -- Reset value for the field + Pwm_Wpcr_Wpkey_Field_Reset, + -- Writing any other value in this field aborts the write operation of + -- the WPCMD field.Always reads as 0 + Passwd) + with Size => 24; + for PWM_WPCR_WPKEY_Field use + (Pwm_Wpcr_Wpkey_Field_Reset => 0, + Passwd => 5265229); + + -- PWM Write Protection Control Register + type PWM_PWM_WPCR_Register is record + -- Write-only. Write Protection Command + WPCMD : PWM_WPCR_WPCMD_Field := SAM_SVD.PWM.Disable_Sw_Prot; + -- Write-only. Write Protection Register Group 0 + WPRG : PWM_PWM_WPCR_WPRG_Field := (As_Array => False, Val => 16#0#); + -- Write-only. Write Protection Key + WPKEY : PWM_WPCR_WPKEY_Field := Pwm_Wpcr_Wpkey_Field_Reset; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PWM_PWM_WPCR_Register use record + WPCMD at 0 range 0 .. 1; + WPRG at 0 range 2 .. 7; + WPKEY at 0 range 8 .. 31; + end record; + + -- PWM_PWM_WPSR_WPSWS array + type PWM_PWM_WPSR_WPSWS_Field_Array is array (0 .. 5) of Boolean + with Component_Size => 1, Size => 6; + + -- Type definition for PWM_PWM_WPSR_WPSWS + type PWM_PWM_WPSR_WPSWS_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- WPSWS as a value + Val : HAL.UInt6; + when True => + -- WPSWS as an array + Arr : PWM_PWM_WPSR_WPSWS_Field_Array; + end case; + end record + with Unchecked_Union, Size => 6; + + for PWM_PWM_WPSR_WPSWS_Field use record + Val at 0 range 0 .. 5; + Arr at 0 range 0 .. 5; + end record; + + -- PWM_PWM_WPSR_WPHWS array + type PWM_PWM_WPSR_WPHWS_Field_Array is array (0 .. 5) of Boolean + with Component_Size => 1, Size => 6; + + -- Type definition for PWM_PWM_WPSR_WPHWS + type PWM_PWM_WPSR_WPHWS_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- WPHWS as a value + Val : HAL.UInt6; + when True => + -- WPHWS as an array + Arr : PWM_PWM_WPSR_WPHWS_Field_Array; + end case; + end record + with Unchecked_Union, Size => 6; + + for PWM_PWM_WPSR_WPHWS_Field use record + Val at 0 range 0 .. 5; + Arr at 0 range 0 .. 5; + end record; + + subtype PWM_PWM_WPSR_WPVSRC_Field is HAL.UInt16; + + -- PWM Write Protection Status Register + type PWM_PWM_WPSR_Register is record + -- Read-only. Write Protect SW Status + WPSWS : PWM_PWM_WPSR_WPSWS_Field; + -- unspecified + Reserved_6_6 : HAL.Bit; + -- Read-only. Write Protect Violation Status + WPVS : Boolean; + -- Read-only. Write Protect HW Status + WPHWS : PWM_PWM_WPSR_WPHWS_Field; + -- unspecified + Reserved_14_15 : HAL.UInt2; + -- Read-only. Write Protect Violation Source + WPVSRC : PWM_PWM_WPSR_WPVSRC_Field; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PWM_PWM_WPSR_Register use record + WPSWS at 0 range 0 .. 5; + Reserved_6_6 at 0 range 6 .. 6; + WPVS at 0 range 7 .. 7; + WPHWS at 0 range 8 .. 13; + Reserved_14_15 at 0 range 14 .. 15; + WPVSRC at 0 range 16 .. 31; + end record; + + subtype PWM_PWM_VERSION_VERSION_Field is HAL.UInt12; + subtype PWM_PWM_VERSION_MFN_Field is HAL.UInt3; + + -- Version Register + type PWM_PWM_VERSION_Register is record + -- Read-only. Version of the Hardware Module + VERSION : PWM_PWM_VERSION_VERSION_Field; + -- unspecified + Reserved_12_15 : HAL.UInt4; + -- Read-only. Metal Fix Number + MFN : PWM_PWM_VERSION_MFN_Field; + -- unspecified + Reserved_19_31 : HAL.UInt13; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PWM_PWM_VERSION_Register use record + VERSION at 0 range 0 .. 11; + Reserved_12_15 at 0 range 12 .. 15; + MFN at 0 range 16 .. 18; + Reserved_19_31 at 0 range 19 .. 31; + end record; + + ------------------------------------- + -- PWM_PWM_CMP cluster's Registers -- + ------------------------------------- + + subtype PWM_PWM_CMPV_PWM_PWM_CMP_CV_Field is HAL.UInt24; + + -- PWM Comparison 0 Value Register + type PWM_PWM_CMPV_PWM_PWM_CMP_Register is record + -- Comparison x Value + CV : PWM_PWM_CMPV_PWM_PWM_CMP_CV_Field := 16#0#; + -- Comparison x Value Mode + CVM : Boolean := False; + -- unspecified + Reserved_25_31 : HAL.UInt7 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PWM_PWM_CMPV_PWM_PWM_CMP_Register use record + CV at 0 range 0 .. 23; + CVM at 0 range 24 .. 24; + Reserved_25_31 at 0 range 25 .. 31; + end record; + + subtype PWM_PWM_CMPVUPD_PWM_PWM_CMP_CVUPD_Field is HAL.UInt24; + + -- PWM Comparison 0 Value Update Register + type PWM_PWM_CMPVUPD_PWM_PWM_CMP_Register is record + -- Write-only. Comparison x Value Update + CVUPD : PWM_PWM_CMPVUPD_PWM_PWM_CMP_CVUPD_Field := 16#0#; + -- Write-only. Comparison x Value Mode Update + CVMUPD : Boolean := False; + -- unspecified + Reserved_25_31 : HAL.UInt7 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PWM_PWM_CMPVUPD_PWM_PWM_CMP_Register use record + CVUPD at 0 range 0 .. 23; + CVMUPD at 0 range 24 .. 24; + Reserved_25_31 at 0 range 25 .. 31; + end record; + + subtype PWM_PWM_CMPM_PWM_PWM_CMP_CTR_Field is HAL.UInt4; + subtype PWM_PWM_CMPM_PWM_PWM_CMP_CPR_Field is HAL.UInt4; + subtype PWM_PWM_CMPM_PWM_PWM_CMP_CPRCNT_Field is HAL.UInt4; + subtype PWM_PWM_CMPM_PWM_PWM_CMP_CUPR_Field is HAL.UInt4; + subtype PWM_PWM_CMPM_PWM_PWM_CMP_CUPRCNT_Field is HAL.UInt4; + + -- PWM Comparison 0 Mode Register + type PWM_PWM_CMPM_PWM_PWM_CMP_Register is record + -- Comparison x Enable + CEN : Boolean := False; + -- unspecified + Reserved_1_3 : HAL.UInt3 := 16#0#; + -- Comparison x Trigger + CTR : PWM_PWM_CMPM_PWM_PWM_CMP_CTR_Field := 16#0#; + -- Comparison x Period + CPR : PWM_PWM_CMPM_PWM_PWM_CMP_CPR_Field := 16#0#; + -- Comparison x Period Counter + CPRCNT : PWM_PWM_CMPM_PWM_PWM_CMP_CPRCNT_Field := 16#0#; + -- Comparison x Update Period + CUPR : PWM_PWM_CMPM_PWM_PWM_CMP_CUPR_Field := 16#0#; + -- Comparison x Update Period Counter + CUPRCNT : PWM_PWM_CMPM_PWM_PWM_CMP_CUPRCNT_Field := 16#0#; + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PWM_PWM_CMPM_PWM_PWM_CMP_Register use record + CEN at 0 range 0 .. 0; + Reserved_1_3 at 0 range 1 .. 3; + CTR at 0 range 4 .. 7; + CPR at 0 range 8 .. 11; + CPRCNT at 0 range 12 .. 15; + CUPR at 0 range 16 .. 19; + CUPRCNT at 0 range 20 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype PWM_PWM_CMPMUPD_PWM_PWM_CMP_CTRUPD_Field is HAL.UInt4; + subtype PWM_PWM_CMPMUPD_PWM_PWM_CMP_CPRUPD_Field is HAL.UInt4; + subtype PWM_PWM_CMPMUPD_PWM_PWM_CMP_CUPRUPD_Field is HAL.UInt4; + + -- PWM Comparison 0 Mode Update Register + type PWM_PWM_CMPMUPD_PWM_PWM_CMP_Register is record + -- Write-only. Comparison x Enable Update + CENUPD : Boolean := False; + -- unspecified + Reserved_1_3 : HAL.UInt3 := 16#0#; + -- Write-only. Comparison x Trigger Update + CTRUPD : PWM_PWM_CMPMUPD_PWM_PWM_CMP_CTRUPD_Field := 16#0#; + -- Write-only. Comparison x Period Update + CPRUPD : PWM_PWM_CMPMUPD_PWM_PWM_CMP_CPRUPD_Field := 16#0#; + -- unspecified + Reserved_12_15 : HAL.UInt4 := 16#0#; + -- Write-only. Comparison x Update Period Update + CUPRUPD : PWM_PWM_CMPMUPD_PWM_PWM_CMP_CUPRUPD_Field := 16#0#; + -- unspecified + Reserved_20_31 : HAL.UInt12 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PWM_PWM_CMPMUPD_PWM_PWM_CMP_Register use record + CENUPD at 0 range 0 .. 0; + Reserved_1_3 at 0 range 1 .. 3; + CTRUPD at 0 range 4 .. 7; + CPRUPD at 0 range 8 .. 11; + Reserved_12_15 at 0 range 12 .. 15; + CUPRUPD at 0 range 16 .. 19; + Reserved_20_31 at 0 range 20 .. 31; + end record; + + -- PWM Comparison 0 Value Register + type PWM_PWM_CMP_Cluster is record + -- PWM Comparison 0 Value Register + PWM_CMPV : aliased PWM_PWM_CMPV_PWM_PWM_CMP_Register; + -- PWM Comparison 0 Value Update Register + PWM_CMPVUPD : aliased PWM_PWM_CMPVUPD_PWM_PWM_CMP_Register; + -- PWM Comparison 0 Mode Register + PWM_CMPM : aliased PWM_PWM_CMPM_PWM_PWM_CMP_Register; + -- PWM Comparison 0 Mode Update Register + PWM_CMPMUPD : aliased PWM_PWM_CMPMUPD_PWM_PWM_CMP_Register; + end record + with Volatile, Size => 128; + + for PWM_PWM_CMP_Cluster use record + PWM_CMPV at 16#0# range 0 .. 31; + PWM_CMPVUPD at 16#4# range 0 .. 31; + PWM_CMPM at 16#8# range 0 .. 31; + PWM_CMPMUPD at 16#C# range 0 .. 31; + end record; + + -- PWM Comparison 0 Value Register + type PWM_PWM_CMP_Clusters is array (0 .. 7) of PWM_PWM_CMP_Cluster; + + ---------------------------------------- + -- PWM_PWM_CH_NUM cluster's Registers -- + ---------------------------------------- + + -- Channel Pre-scaler + type PWM_CMR_CPRE_Field is + ( + -- Peripheral clock + Mck, + -- Peripheral clock/2 + Mck_Div_2, + -- Peripheral clock/4 + Mck_Div_4, + -- Peripheral clock/8 + Mck_Div_8, + -- Peripheral clock/16 + Mck_Div_16, + -- Peripheral clock/32 + Mck_Div_32, + -- Peripheral clock/64 + Mck_Div_64, + -- Peripheral clock/128 + Mck_Div_128, + -- Peripheral clock/256 + Mck_Div_256, + -- Peripheral clock/512 + Mck_Div_512, + -- Peripheral clock/1024 + Mck_Div_1024, + -- Clock A + Clka, + -- Clock B + Clkb) + with Size => 4; + for PWM_CMR_CPRE_Field use + (Mck => 0, + Mck_Div_2 => 1, + Mck_Div_4 => 2, + Mck_Div_8 => 3, + Mck_Div_16 => 4, + Mck_Div_32 => 5, + Mck_Div_64 => 6, + Mck_Div_128 => 7, + Mck_Div_256 => 8, + Mck_Div_512 => 9, + Mck_Div_1024 => 10, + Clka => 11, + Clkb => 12); + + -- PWM Channel Mode Register (ch_num = 0) + type PWM_PWM_CMR_PWM_PWM_CH_NUM_Register is record + -- Channel Pre-scaler + CPRE : PWM_CMR_CPRE_Field := SAM_SVD.PWM.Mck; + -- unspecified + Reserved_4_7 : HAL.UInt4 := 16#0#; + -- Channel Alignment + CALG : Boolean := False; + -- Channel Polarity + CPOL : Boolean := False; + -- Counter Event Selection + CES : Boolean := False; + -- Update Selection + UPDS : Boolean := False; + -- Disabled Polarity Inverted + DPOLI : Boolean := False; + -- Timer Counter Trigger Selection + TCTS : Boolean := False; + -- unspecified + Reserved_14_15 : HAL.UInt2 := 16#0#; + -- Dead-Time Generator Enable + DTE : Boolean := False; + -- Dead-Time PWMHx Output Inverted + DTHI : Boolean := False; + -- Dead-Time PWMLx Output Inverted + DTLI : Boolean := False; + -- Push-Pull Mode + PPM : Boolean := False; + -- unspecified + Reserved_20_31 : HAL.UInt12 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PWM_PWM_CMR_PWM_PWM_CH_NUM_Register use record + CPRE at 0 range 0 .. 3; + Reserved_4_7 at 0 range 4 .. 7; + CALG at 0 range 8 .. 8; + CPOL at 0 range 9 .. 9; + CES at 0 range 10 .. 10; + UPDS at 0 range 11 .. 11; + DPOLI at 0 range 12 .. 12; + TCTS at 0 range 13 .. 13; + Reserved_14_15 at 0 range 14 .. 15; + DTE at 0 range 16 .. 16; + DTHI at 0 range 17 .. 17; + DTLI at 0 range 18 .. 18; + PPM at 0 range 19 .. 19; + Reserved_20_31 at 0 range 20 .. 31; + end record; + + subtype PWM_PWM_CDTY_PWM_PWM_CH_NUM_CDTY_Field is HAL.UInt24; + + -- PWM Channel Duty Cycle Register (ch_num = 0) + type PWM_PWM_CDTY_PWM_PWM_CH_NUM_Register is record + -- Channel Duty-Cycle + CDTY : PWM_PWM_CDTY_PWM_PWM_CH_NUM_CDTY_Field := 16#0#; + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PWM_PWM_CDTY_PWM_PWM_CH_NUM_Register use record + CDTY at 0 range 0 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype PWM_PWM_CDTYUPD_PWM_PWM_CH_NUM_CDTYUPD_Field is HAL.UInt24; + + -- PWM Channel Duty Cycle Update Register (ch_num = 0) + type PWM_PWM_CDTYUPD_PWM_PWM_CH_NUM_Register is record + -- Write-only. Channel Duty-Cycle Update + CDTYUPD : PWM_PWM_CDTYUPD_PWM_PWM_CH_NUM_CDTYUPD_Field := 16#0#; + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PWM_PWM_CDTYUPD_PWM_PWM_CH_NUM_Register use record + CDTYUPD at 0 range 0 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype PWM_PWM_CPRD_PWM_PWM_CH_NUM_CPRD_Field is HAL.UInt24; + + -- PWM Channel Period Register (ch_num = 0) + type PWM_PWM_CPRD_PWM_PWM_CH_NUM_Register is record + -- Channel Period + CPRD : PWM_PWM_CPRD_PWM_PWM_CH_NUM_CPRD_Field := 16#0#; + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PWM_PWM_CPRD_PWM_PWM_CH_NUM_Register use record + CPRD at 0 range 0 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype PWM_PWM_CPRDUPD_PWM_PWM_CH_NUM_CPRDUPD_Field is HAL.UInt24; + + -- PWM Channel Period Update Register (ch_num = 0) + type PWM_PWM_CPRDUPD_PWM_PWM_CH_NUM_Register is record + -- Write-only. Channel Period Update + CPRDUPD : PWM_PWM_CPRDUPD_PWM_PWM_CH_NUM_CPRDUPD_Field := 16#0#; + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PWM_PWM_CPRDUPD_PWM_PWM_CH_NUM_Register use record + CPRDUPD at 0 range 0 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype PWM_PWM_CCNT_PWM_PWM_CH_NUM_CNT_Field is HAL.UInt24; + + -- PWM Channel Counter Register (ch_num = 0) + type PWM_PWM_CCNT_PWM_PWM_CH_NUM_Register is record + -- Read-only. Channel Counter Register + CNT : PWM_PWM_CCNT_PWM_PWM_CH_NUM_CNT_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PWM_PWM_CCNT_PWM_PWM_CH_NUM_Register use record + CNT at 0 range 0 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype PWM_PWM_DT_PWM_PWM_CH_NUM_DTH_Field is HAL.UInt16; + subtype PWM_PWM_DT_PWM_PWM_CH_NUM_DTL_Field is HAL.UInt16; + + -- PWM Channel Dead Time Register (ch_num = 0) + type PWM_PWM_DT_PWM_PWM_CH_NUM_Register is record + -- Dead-Time Value for PWMHx Output + DTH : PWM_PWM_DT_PWM_PWM_CH_NUM_DTH_Field := 16#0#; + -- Dead-Time Value for PWMLx Output + DTL : PWM_PWM_DT_PWM_PWM_CH_NUM_DTL_Field := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PWM_PWM_DT_PWM_PWM_CH_NUM_Register use record + DTH at 0 range 0 .. 15; + DTL at 0 range 16 .. 31; + end record; + + subtype PWM_PWM_DTUPD_PWM_PWM_CH_NUM_DTHUPD_Field is HAL.UInt16; + subtype PWM_PWM_DTUPD_PWM_PWM_CH_NUM_DTLUPD_Field is HAL.UInt16; + + -- PWM Channel Dead Time Update Register (ch_num = 0) + type PWM_PWM_DTUPD_PWM_PWM_CH_NUM_Register is record + -- Write-only. Dead-Time Value Update for PWMHx Output + DTHUPD : PWM_PWM_DTUPD_PWM_PWM_CH_NUM_DTHUPD_Field := 16#0#; + -- Write-only. Dead-Time Value Update for PWMLx Output + DTLUPD : PWM_PWM_DTUPD_PWM_PWM_CH_NUM_DTLUPD_Field := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PWM_PWM_DTUPD_PWM_PWM_CH_NUM_Register use record + DTHUPD at 0 range 0 .. 15; + DTLUPD at 0 range 16 .. 31; + end record; + + -- PWM Channel Mode Register (ch_num = 0) + type PWM_PWM_CH_NUM_Cluster is record + -- PWM Channel Mode Register (ch_num = 0) + PWM_CMR : aliased PWM_PWM_CMR_PWM_PWM_CH_NUM_Register; + -- PWM Channel Duty Cycle Register (ch_num = 0) + PWM_CDTY : aliased PWM_PWM_CDTY_PWM_PWM_CH_NUM_Register; + -- PWM Channel Duty Cycle Update Register (ch_num = 0) + PWM_CDTYUPD : aliased PWM_PWM_CDTYUPD_PWM_PWM_CH_NUM_Register; + -- PWM Channel Period Register (ch_num = 0) + PWM_CPRD : aliased PWM_PWM_CPRD_PWM_PWM_CH_NUM_Register; + -- PWM Channel Period Update Register (ch_num = 0) + PWM_CPRDUPD : aliased PWM_PWM_CPRDUPD_PWM_PWM_CH_NUM_Register; + -- PWM Channel Counter Register (ch_num = 0) + PWM_CCNT : aliased PWM_PWM_CCNT_PWM_PWM_CH_NUM_Register; + -- PWM Channel Dead Time Register (ch_num = 0) + PWM_DT : aliased PWM_PWM_DT_PWM_PWM_CH_NUM_Register; + -- PWM Channel Dead Time Update Register (ch_num = 0) + PWM_DTUPD : aliased PWM_PWM_DTUPD_PWM_PWM_CH_NUM_Register; + end record + with Volatile, Size => 256; + + for PWM_PWM_CH_NUM_Cluster use record + PWM_CMR at 16#0# range 0 .. 31; + PWM_CDTY at 16#4# range 0 .. 31; + PWM_CDTYUPD at 16#8# range 0 .. 31; + PWM_CPRD at 16#C# range 0 .. 31; + PWM_CPRDUPD at 16#10# range 0 .. 31; + PWM_CCNT at 16#14# range 0 .. 31; + PWM_DT at 16#18# range 0 .. 31; + PWM_DTUPD at 16#1C# range 0 .. 31; + end record; + + -- PWM Channel Mode Register (ch_num = 0) + type PWM_PWM_CH_NUM_Clusters is array (0 .. 3) of PWM_PWM_CH_NUM_Cluster; + + -- PWM Channel Mode Update Register (ch_num = 0) + type PWM_CMUPD_Register is record + -- unspecified + Reserved_0_8 : HAL.UInt9 := 16#0#; + -- Write-only. Channel Polarity Update + CPOLUP : Boolean := False; + -- unspecified + Reserved_10_12 : HAL.UInt3 := 16#0#; + -- Write-only. Channel Polarity Inversion Update + CPOLINVUP : Boolean := False; + -- unspecified + Reserved_14_31 : HAL.UInt18 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PWM_CMUPD_Register use record + Reserved_0_8 at 0 range 0 .. 8; + CPOLUP at 0 range 9 .. 9; + Reserved_10_12 at 0 range 10 .. 12; + CPOLINVUP at 0 range 13 .. 13; + Reserved_14_31 at 0 range 14 .. 31; + end record; + + subtype PWM_ETRG_MAXCNT_Field is HAL.UInt24; + + -- External Trigger Mode + type PWM_ETRG1_TRGMODE_Field is + ( + -- External trigger is not enabled. + Off, + -- External PWM Reset Mode + Mode1, + -- External PWM Start Mode + Mode2, + -- Cycle-by-cycle Duty Mode + Mode3) + with Size => 2; + for PWM_ETRG1_TRGMODE_Field use + (Off => 0, + Mode1 => 1, + Mode2 => 2, + Mode3 => 3); + + -- Edge Selection + type PWM_ETRG1_TRGEDGE_Field is + ( + -- TRGMODE = 1: TRGINx event detection on falling edge.TRGMODE = 2, 3: + -- TRGINx active level is 0 + Falling_Zero, + -- TRGMODE = 1: TRGINx event detection on rising edge.TRGMODE = 2, 3: + -- TRGINx active level is 1 + Rising_One) + with Size => 1; + for PWM_ETRG1_TRGEDGE_Field use + (Falling_Zero => 0, + Rising_One => 1); + + -- PWM External Trigger Register (trg_num = 1) + type PWM_ETRG_Register is record + -- Maximum Counter value + MAXCNT : PWM_ETRG_MAXCNT_Field := 16#0#; + -- External Trigger Mode + TRGMODE : PWM_ETRG1_TRGMODE_Field := SAM_SVD.PWM.Off; + -- unspecified + Reserved_26_27 : HAL.UInt2 := 16#0#; + -- Edge Selection + TRGEDGE : PWM_ETRG1_TRGEDGE_Field := SAM_SVD.PWM.Falling_Zero; + -- Filtered input + TRGFILT : Boolean := False; + -- Trigger Source + TRGSRC : Boolean := False; + -- Recoverable Fault Enable + RFEN : Boolean := False; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PWM_ETRG_Register use record + MAXCNT at 0 range 0 .. 23; + TRGMODE at 0 range 24 .. 25; + Reserved_26_27 at 0 range 26 .. 27; + TRGEDGE at 0 range 28 .. 28; + TRGFILT at 0 range 29 .. 29; + TRGSRC at 0 range 30 .. 30; + RFEN at 0 range 31 .. 31; + end record; + + subtype PWM_LEBR_LEBDELAY_Field is HAL.UInt7; + + -- PWM Leading-Edge Blanking Register (trg_num = 1) + type PWM_LEBR_Register is record + -- Leading-Edge Blanking Delay for TRGINx + LEBDELAY : PWM_LEBR_LEBDELAY_Field := 16#0#; + -- unspecified + Reserved_7_15 : HAL.UInt9 := 16#0#; + -- PWML Falling Edge Enable + PWMLFEN : Boolean := False; + -- PWML Rising Edge Enable + PWMLREN : Boolean := False; + -- PWMH Falling Edge Enable + PWMHFEN : Boolean := False; + -- PWMH Rising Edge Enable + PWMHREN : Boolean := False; + -- unspecified + Reserved_20_31 : HAL.UInt12 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for PWM_LEBR_Register use record + LEBDELAY at 0 range 0 .. 6; + Reserved_7_15 at 0 range 7 .. 15; + PWMLFEN at 0 range 16 .. 16; + PWMLREN at 0 range 17 .. 17; + PWMHFEN at 0 range 18 .. 18; + PWMHREN at 0 range 19 .. 19; + Reserved_20_31 at 0 range 20 .. 31; + end record; + + ------------------------------------- + -- PWM_PWM_CMP cluster's Registers -- + ------------------------------------- + + ---------------------------------------- + -- PWM_PWM_CH_NUM cluster's Registers -- + ---------------------------------------- + + ----------------- + -- Peripherals -- + ----------------- + + -- Pulse Width Modulation Controller + type PWM_Peripheral is record + -- PWM Clock Register + PWM_CLK : aliased PWM_PWM_CLK_Register; + -- PWM Enable Register + PWM_ENA : aliased PWM_PWM_ENA_Register; + -- PWM Disable Register + PWM_DIS : aliased PWM_PWM_DIS_Register; + -- PWM Status Register + PWM_SR : aliased PWM_PWM_SR_Register; + -- PWM Interrupt Enable Register 1 + PWM_IER1 : aliased PWM_PWM_IER1_Register; + -- PWM Interrupt Disable Register 1 + PWM_IDR1 : aliased PWM_PWM_IDR1_Register; + -- PWM Interrupt Mask Register 1 + PWM_IMR1 : aliased PWM_PWM_IMR1_Register; + -- PWM Interrupt Status Register 1 + PWM_ISR1 : aliased PWM_PWM_ISR1_Register; + -- PWM Sync Channels Mode Register + PWM_SCM : aliased PWM_PWM_SCM_Register; + -- PWM DMA Register + PWM_DMAR : aliased PWM_PWM_DMAR_Register; + -- PWM Sync Channels Update Control Register + PWM_SCUC : aliased PWM_PWM_SCUC_Register; + -- PWM Sync Channels Update Period Register + PWM_SCUP : aliased PWM_PWM_SCUP_Register; + -- PWM Sync Channels Update Period Update Register + PWM_SCUPUPD : aliased PWM_PWM_SCUPUPD_Register; + -- PWM Interrupt Enable Register 2 + PWM_IER2 : aliased PWM_PWM_IER2_Register; + -- PWM Interrupt Disable Register 2 + PWM_IDR2 : aliased PWM_PWM_IDR2_Register; + -- PWM Interrupt Mask Register 2 + PWM_IMR2 : aliased PWM_PWM_IMR2_Register; + -- PWM Interrupt Status Register 2 + PWM_ISR2 : aliased PWM_PWM_ISR2_Register; + -- PWM Output Override Value Register + PWM_OOV : aliased PWM_PWM_OOV_Register; + -- PWM Output Selection Register + PWM_OS : aliased PWM_PWM_OS_Register; + -- PWM Output Selection Set Register + PWM_OSS : aliased PWM_PWM_OSS_Register; + -- PWM Output Selection Clear Register + PWM_OSC : aliased PWM_PWM_OSC_Register; + -- PWM Output Selection Set Update Register + PWM_OSSUPD : aliased PWM_PWM_OSSUPD_Register; + -- PWM Output Selection Clear Update Register + PWM_OSCUPD : aliased PWM_PWM_OSCUPD_Register; + -- PWM Fault Mode Register + PWM_FMR : aliased PWM_PWM_FMR_Register; + -- PWM Fault Status Register + PWM_FSR : aliased PWM_PWM_FSR_Register; + -- PWM Fault Clear Register + PWM_FCR : aliased PWM_PWM_FCR_Register; + -- PWM Fault Protection Value Register 1 + PWM_FPV1 : aliased PWM_PWM_FPV1_Register; + -- PWM Fault Protection Enable Register + PWM_FPE : aliased PWM_PWM_FPE_Register; + -- PWM Event Line 0 Mode Register 0 + PWM_ELMR : aliased PWM_PWM_ELMR_Registers; + -- PWM Spread Spectrum Register + PWM_SSPR : aliased PWM_PWM_SSPR_Register; + -- PWM Spread Spectrum Update Register + PWM_SSPUP : aliased PWM_PWM_SSPUP_Register; + -- PWM Stepper Motor Mode Register + PWM_SMMR : aliased PWM_PWM_SMMR_Register; + -- PWM Fault Protection Value 2 Register + PWM_FPV2 : aliased PWM_PWM_FPV2_Register; + -- PWM Write Protection Control Register + PWM_WPCR : aliased PWM_PWM_WPCR_Register; + -- PWM Write Protection Status Register + PWM_WPSR : aliased PWM_PWM_WPSR_Register; + -- Version Register + PWM_VERSION : aliased PWM_PWM_VERSION_Register; + -- PWM Comparison 0 Value Register + PWM_PWM_CMP : aliased PWM_PWM_CMP_Clusters; + -- PWM Channel Mode Register (ch_num = 0) + PWM_PWM_CH_NUM : aliased PWM_PWM_CH_NUM_Clusters; + -- PWM Channel Mode Update Register (ch_num = 0) + PWM_CMUPD0 : aliased PWM_CMUPD_Register; + -- PWM Channel Mode Update Register (ch_num = 1) + PWM_CMUPD1 : aliased PWM_CMUPD_Register; + -- PWM External Trigger Register (trg_num = 1) + PWM_ETRG1 : aliased PWM_ETRG_Register; + -- PWM Leading-Edge Blanking Register (trg_num = 1) + PWM_LEBR1 : aliased PWM_LEBR_Register; + -- PWM Channel Mode Update Register (ch_num = 2) + PWM_CMUPD2 : aliased PWM_CMUPD_Register; + -- PWM External Trigger Register (trg_num = 2) + PWM_ETRG2 : aliased PWM_ETRG_Register; + -- PWM Leading-Edge Blanking Register (trg_num = 2) + PWM_LEBR2 : aliased PWM_LEBR_Register; + -- PWM Channel Mode Update Register (ch_num = 3) + PWM_CMUPD3 : aliased PWM_CMUPD_Register; + end record + with Volatile; + + for PWM_Peripheral use record + PWM_CLK at 16#0# range 0 .. 31; + PWM_ENA at 16#4# range 0 .. 31; + PWM_DIS at 16#8# range 0 .. 31; + PWM_SR at 16#C# range 0 .. 31; + PWM_IER1 at 16#10# range 0 .. 31; + PWM_IDR1 at 16#14# range 0 .. 31; + PWM_IMR1 at 16#18# range 0 .. 31; + PWM_ISR1 at 16#1C# range 0 .. 31; + PWM_SCM at 16#20# range 0 .. 31; + PWM_DMAR at 16#24# range 0 .. 31; + PWM_SCUC at 16#28# range 0 .. 31; + PWM_SCUP at 16#2C# range 0 .. 31; + PWM_SCUPUPD at 16#30# range 0 .. 31; + PWM_IER2 at 16#34# range 0 .. 31; + PWM_IDR2 at 16#38# range 0 .. 31; + PWM_IMR2 at 16#3C# range 0 .. 31; + PWM_ISR2 at 16#40# range 0 .. 31; + PWM_OOV at 16#44# range 0 .. 31; + PWM_OS at 16#48# range 0 .. 31; + PWM_OSS at 16#4C# range 0 .. 31; + PWM_OSC at 16#50# range 0 .. 31; + PWM_OSSUPD at 16#54# range 0 .. 31; + PWM_OSCUPD at 16#58# range 0 .. 31; + PWM_FMR at 16#5C# range 0 .. 31; + PWM_FSR at 16#60# range 0 .. 31; + PWM_FCR at 16#64# range 0 .. 31; + PWM_FPV1 at 16#68# range 0 .. 31; + PWM_FPE at 16#6C# range 0 .. 31; + PWM_ELMR at 16#7C# range 0 .. 63; + PWM_SSPR at 16#A0# range 0 .. 31; + PWM_SSPUP at 16#A4# range 0 .. 31; + PWM_SMMR at 16#B0# range 0 .. 31; + PWM_FPV2 at 16#C0# range 0 .. 31; + PWM_WPCR at 16#E4# range 0 .. 31; + PWM_WPSR at 16#E8# range 0 .. 31; + PWM_VERSION at 16#FC# range 0 .. 31; + PWM_PWM_CMP at 16#130# range 0 .. 1023; + PWM_PWM_CH_NUM at 16#200# range 0 .. 1023; + PWM_CMUPD0 at 16#400# range 0 .. 31; + PWM_CMUPD1 at 16#420# range 0 .. 31; + PWM_ETRG1 at 16#42C# range 0 .. 31; + PWM_LEBR1 at 16#430# range 0 .. 31; + PWM_CMUPD2 at 16#440# range 0 .. 31; + PWM_ETRG2 at 16#44C# range 0 .. 31; + PWM_LEBR2 at 16#450# range 0 .. 31; + PWM_CMUPD3 at 16#460# range 0 .. 31; + end record; + + -- Pulse Width Modulation Controller + PWM0_Periph : aliased PWM_Peripheral + with Import, Address => System'To_Address (16#40020000#); + + -- Pulse Width Modulation Controller + PWM1_Periph : aliased PWM_Peripheral + with Import, Address => System'To_Address (16#4005C000#); + +end SAM_SVD.PWM; diff --git a/arch/ARM/SAM/svd/atsamv71/sam_svd-qspi.ads b/arch/ARM/SAM/svd/atsamv71/sam_svd-qspi.ads new file mode 100644 index 000000000..eef1a70c6 --- /dev/null +++ b/arch/ARM/SAM/svd/atsamv71/sam_svd-qspi.ads @@ -0,0 +1,720 @@ +-- This spec has been automatically generated from ATSAMV71Q21.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package SAM_SVD.QSPI is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + -- Control Register + type QSPI_QSPI_CR_Register is record + -- Write-only. QSPI Enable + QSPIEN : Boolean := False; + -- Write-only. QSPI Disable + QSPIDIS : Boolean := False; + -- unspecified + Reserved_2_6 : HAL.UInt5 := 16#0#; + -- Write-only. QSPI Software Reset + SWRST : Boolean := False; + -- unspecified + Reserved_8_23 : HAL.UInt16 := 16#0#; + -- Write-only. Last Transfer + LASTXFER : Boolean := False; + -- unspecified + Reserved_25_31 : HAL.UInt7 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for QSPI_QSPI_CR_Register use record + QSPIEN at 0 range 0 .. 0; + QSPIDIS at 0 range 1 .. 1; + Reserved_2_6 at 0 range 2 .. 6; + SWRST at 0 range 7 .. 7; + Reserved_8_23 at 0 range 8 .. 23; + LASTXFER at 0 range 24 .. 24; + Reserved_25_31 at 0 range 25 .. 31; + end record; + + -- Serial Memory Mode + type QSPI_MR_SMM_Field is + ( + -- The QSPI is in SPI mode. + Spi, + -- The QSPI is in Serial Memory mode. + Memory) + with Size => 1; + for QSPI_MR_SMM_Field use + (Spi => 0, + Memory => 1); + + -- Local Loopback Enable + type QSPI_MR_LLB_Field is + ( + -- Local loopback path disabled. + Disabled, + -- Local loopback path enabled. + Enabled) + with Size => 1; + for QSPI_MR_LLB_Field use + (Disabled => 0, + Enabled => 1); + + -- Wait Data Read Before Transfer + type QSPI_MR_WDRBT_Field is + ( + -- No effect. In SPI mode, a transfer can be initiated whatever the + -- state of the QSPI_RDR is. + Disabled, + -- In SPI mode, a transfer can start only if the QSPI_RDR is empty, + -- i.e., does not contain any unread data. This mode prevents overrun + -- error in reception. + Enabled) + with Size => 1; + for QSPI_MR_WDRBT_Field use + (Disabled => 0, + Enabled => 1); + + -- Chip Select Mode + type QSPI_MR_CSMODE_Field is + ( + -- The chip select is deasserted if QSPI_TDR.TD has not been reloaded + -- before the end of the current transfer. + Not_Reloaded, + -- The chip select is deasserted when the bit LASTXFER is written at 1 + -- and the character written in QSPI_TDR.TD has been transferred. + Lastxfer, + -- The chip select is deasserted systematically after each transfer. + Systematically) + with Size => 2; + for QSPI_MR_CSMODE_Field use + (Not_Reloaded => 0, + Lastxfer => 1, + Systematically => 2); + + -- Number Of Bits Per Transfer + type QSPI_MR_NBBITS_Field is + ( + -- 8 bits for transfer + Val_8_Bit, + -- 16 bits for transfer + Val_16_Bit) + with Size => 4; + for QSPI_MR_NBBITS_Field use + (Val_8_Bit => 0, + Val_16_Bit => 8); + + subtype QSPI_QSPI_MR_DLYBCT_Field is HAL.UInt8; + subtype QSPI_QSPI_MR_DLYCS_Field is HAL.UInt8; + + -- Mode Register + type QSPI_QSPI_MR_Register is record + -- Serial Memory Mode + SMM : QSPI_MR_SMM_Field := SAM_SVD.QSPI.Spi; + -- Local Loopback Enable + LLB : QSPI_MR_LLB_Field := SAM_SVD.QSPI.Disabled; + -- Wait Data Read Before Transfer + WDRBT : QSPI_MR_WDRBT_Field := SAM_SVD.QSPI.Disabled; + -- unspecified + Reserved_3_3 : HAL.Bit := 16#0#; + -- Chip Select Mode + CSMODE : QSPI_MR_CSMODE_Field := SAM_SVD.QSPI.Not_Reloaded; + -- unspecified + Reserved_6_7 : HAL.UInt2 := 16#0#; + -- Number Of Bits Per Transfer + NBBITS : QSPI_MR_NBBITS_Field := SAM_SVD.QSPI.Val_8_Bit; + -- unspecified + Reserved_12_15 : HAL.UInt4 := 16#0#; + -- Delay Between Consecutive Transfers + DLYBCT : QSPI_QSPI_MR_DLYBCT_Field := 16#0#; + -- Minimum Inactive QCS Delay + DLYCS : QSPI_QSPI_MR_DLYCS_Field := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for QSPI_QSPI_MR_Register use record + SMM at 0 range 0 .. 0; + LLB at 0 range 1 .. 1; + WDRBT at 0 range 2 .. 2; + Reserved_3_3 at 0 range 3 .. 3; + CSMODE at 0 range 4 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + NBBITS at 0 range 8 .. 11; + Reserved_12_15 at 0 range 12 .. 15; + DLYBCT at 0 range 16 .. 23; + DLYCS at 0 range 24 .. 31; + end record; + + subtype QSPI_QSPI_RDR_RD_Field is HAL.UInt16; + + -- Receive Data Register + type QSPI_QSPI_RDR_Register is record + -- Read-only. Receive Data + RD : QSPI_QSPI_RDR_RD_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for QSPI_QSPI_RDR_Register use record + RD at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype QSPI_QSPI_TDR_TD_Field is HAL.UInt16; + + -- Transmit Data Register + type QSPI_QSPI_TDR_Register is record + -- Write-only. Transmit Data + TD : QSPI_QSPI_TDR_TD_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for QSPI_QSPI_TDR_Register use record + TD at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + -- Status Register + type QSPI_QSPI_SR_Register is record + -- Read-only. Receive Data Register Full (cleared by reading SPI_RDR) + RDRF : Boolean; + -- Read-only. Transmit Data Register Empty (cleared by writing SPI_TDR) + TDRE : Boolean; + -- Read-only. Transmission Registers Empty (cleared by writing SPI_TDR) + TXEMPTY : Boolean; + -- Read-only. Overrun Error Status (cleared on read) + OVRES : Boolean; + -- unspecified + Reserved_4_7 : HAL.UInt4; + -- Read-only. Chip Select Rise (cleared on read) + CSR : Boolean; + -- Read-only. Chip Select Status + CSS : Boolean; + -- Read-only. Instruction End Status (cleared on read) + INSTRE : Boolean; + -- unspecified + Reserved_11_23 : HAL.UInt13; + -- Read-only. QSPI Enable Status + QSPIENS : Boolean; + -- unspecified + Reserved_25_31 : HAL.UInt7; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for QSPI_QSPI_SR_Register use record + RDRF at 0 range 0 .. 0; + TDRE at 0 range 1 .. 1; + TXEMPTY at 0 range 2 .. 2; + OVRES at 0 range 3 .. 3; + Reserved_4_7 at 0 range 4 .. 7; + CSR at 0 range 8 .. 8; + CSS at 0 range 9 .. 9; + INSTRE at 0 range 10 .. 10; + Reserved_11_23 at 0 range 11 .. 23; + QSPIENS at 0 range 24 .. 24; + Reserved_25_31 at 0 range 25 .. 31; + end record; + + -- Interrupt Enable Register + type QSPI_QSPI_IER_Register is record + -- Write-only. Receive Data Register Full Interrupt Enable + RDRF : Boolean := False; + -- Write-only. Transmit Data Register Empty Interrupt Enable + TDRE : Boolean := False; + -- Write-only. Transmission Registers Empty Enable + TXEMPTY : Boolean := False; + -- Write-only. Overrun Error Interrupt Enable + OVRES : Boolean := False; + -- unspecified + Reserved_4_7 : HAL.UInt4 := 16#0#; + -- Write-only. Chip Select Rise Interrupt Enable + CSR : Boolean := False; + -- Write-only. Chip Select Status Interrupt Enable + CSS : Boolean := False; + -- Write-only. Instruction End Interrupt Enable + INSTRE : Boolean := False; + -- unspecified + Reserved_11_31 : HAL.UInt21 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for QSPI_QSPI_IER_Register use record + RDRF at 0 range 0 .. 0; + TDRE at 0 range 1 .. 1; + TXEMPTY at 0 range 2 .. 2; + OVRES at 0 range 3 .. 3; + Reserved_4_7 at 0 range 4 .. 7; + CSR at 0 range 8 .. 8; + CSS at 0 range 9 .. 9; + INSTRE at 0 range 10 .. 10; + Reserved_11_31 at 0 range 11 .. 31; + end record; + + -- Interrupt Disable Register + type QSPI_QSPI_IDR_Register is record + -- Write-only. Receive Data Register Full Interrupt Disable + RDRF : Boolean := False; + -- Write-only. Transmit Data Register Empty Interrupt Disable + TDRE : Boolean := False; + -- Write-only. Transmission Registers Empty Disable + TXEMPTY : Boolean := False; + -- Write-only. Overrun Error Interrupt Disable + OVRES : Boolean := False; + -- unspecified + Reserved_4_7 : HAL.UInt4 := 16#0#; + -- Write-only. Chip Select Rise Interrupt Disable + CSR : Boolean := False; + -- Write-only. Chip Select Status Interrupt Disable + CSS : Boolean := False; + -- Write-only. Instruction End Interrupt Disable + INSTRE : Boolean := False; + -- unspecified + Reserved_11_31 : HAL.UInt21 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for QSPI_QSPI_IDR_Register use record + RDRF at 0 range 0 .. 0; + TDRE at 0 range 1 .. 1; + TXEMPTY at 0 range 2 .. 2; + OVRES at 0 range 3 .. 3; + Reserved_4_7 at 0 range 4 .. 7; + CSR at 0 range 8 .. 8; + CSS at 0 range 9 .. 9; + INSTRE at 0 range 10 .. 10; + Reserved_11_31 at 0 range 11 .. 31; + end record; + + -- Interrupt Mask Register + type QSPI_QSPI_IMR_Register is record + -- Read-only. Receive Data Register Full Interrupt Mask + RDRF : Boolean; + -- Read-only. Transmit Data Register Empty Interrupt Mask + TDRE : Boolean; + -- Read-only. Transmission Registers Empty Mask + TXEMPTY : Boolean; + -- Read-only. Overrun Error Interrupt Mask + OVRES : Boolean; + -- unspecified + Reserved_4_7 : HAL.UInt4; + -- Read-only. Chip Select Rise Interrupt Mask + CSR : Boolean; + -- Read-only. Chip Select Status Interrupt Mask + CSS : Boolean; + -- Read-only. Instruction End Interrupt Mask + INSTRE : Boolean; + -- unspecified + Reserved_11_31 : HAL.UInt21; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for QSPI_QSPI_IMR_Register use record + RDRF at 0 range 0 .. 0; + TDRE at 0 range 1 .. 1; + TXEMPTY at 0 range 2 .. 2; + OVRES at 0 range 3 .. 3; + Reserved_4_7 at 0 range 4 .. 7; + CSR at 0 range 8 .. 8; + CSS at 0 range 9 .. 9; + INSTRE at 0 range 10 .. 10; + Reserved_11_31 at 0 range 11 .. 31; + end record; + + subtype QSPI_QSPI_SCR_SCBR_Field is HAL.UInt8; + subtype QSPI_QSPI_SCR_DLYBS_Field is HAL.UInt8; + + -- Serial Clock Register + type QSPI_QSPI_SCR_Register is record + -- Clock Polarity + CPOL : Boolean := False; + -- Clock Phase + CPHA : Boolean := False; + -- unspecified + Reserved_2_7 : HAL.UInt6 := 16#0#; + -- Serial Clock Baud Rate + SCBR : QSPI_QSPI_SCR_SCBR_Field := 16#0#; + -- Delay Before QSCK + DLYBS : QSPI_QSPI_SCR_DLYBS_Field := 16#0#; + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for QSPI_QSPI_SCR_Register use record + CPOL at 0 range 0 .. 0; + CPHA at 0 range 1 .. 1; + Reserved_2_7 at 0 range 2 .. 7; + SCBR at 0 range 8 .. 15; + DLYBS at 0 range 16 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype QSPI_QSPI_ICR_INST_Field is HAL.UInt8; + subtype QSPI_QSPI_ICR_OPT_Field is HAL.UInt8; + + -- Instruction Code Register + type QSPI_QSPI_ICR_Register is record + -- Instruction Code + INST : QSPI_QSPI_ICR_INST_Field := 16#0#; + -- unspecified + Reserved_8_15 : HAL.UInt8 := 16#0#; + -- Option Code + OPT : QSPI_QSPI_ICR_OPT_Field := 16#0#; + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for QSPI_QSPI_ICR_Register use record + INST at 0 range 0 .. 7; + Reserved_8_15 at 0 range 8 .. 15; + OPT at 0 range 16 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- Width of Instruction Code, Address, Option Code and Data + type QSPI_IFR_WIDTH_Field is + ( + -- Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: + -- Single-bit SPI + Single_Bit_Spi, + -- Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: + -- Dual SPI + Dual_Output, + -- Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: + -- Quad SPI + Quad_Output, + -- Instruction: Single-bit SPI / Address-Option: Dual SPI / Data: Dual + -- SPI + Dual_Io, + -- Instruction: Single-bit SPI / Address-Option: Quad SPI / Data: Quad + -- SPI + Quad_Io, + -- Instruction: Dual SPI / Address-Option: Dual SPI / Data: Dual SPI + Dual_Cmd, + -- Instruction: Quad SPI / Address-Option: Quad SPI / Data: Quad SPI + Quad_Cmd) + with Size => 3; + for QSPI_IFR_WIDTH_Field use + (Single_Bit_Spi => 0, + Dual_Output => 1, + Quad_Output => 2, + Dual_Io => 3, + Quad_Io => 4, + Dual_Cmd => 5, + Quad_Cmd => 6); + + -- Option Code Length + type QSPI_IFR_OPTL_Field is + ( + -- The option code is 1 bit long. + Option_1Bit, + -- The option code is 2 bits long. + Option_2Bit, + -- The option code is 4 bits long. + Option_4Bit, + -- The option code is 8 bits long. + Option_8Bit) + with Size => 2; + for QSPI_IFR_OPTL_Field use + (Option_1Bit => 0, + Option_2Bit => 1, + Option_4Bit => 2, + Option_8Bit => 3); + + -- Address Length + type QSPI_IFR_ADDRL_Field is + ( + -- The address is 24 bits long. + Val_24_Bit, + -- The address is 32 bits long. + Val_32_Bit) + with Size => 1; + for QSPI_IFR_ADDRL_Field use + (Val_24_Bit => 0, + Val_32_Bit => 1); + + -- Data Transfer Type + type QSPI_IFR_TFRTYP_Field is + ( + -- Read transfer from the serial memory.Scrambling is not performed.Read + -- at random location (fetch) in the serial Flash memory is not + -- possible. + Trsfr_Read, + -- Read data transfer from the serial memory.If enabled, scrambling is + -- performed.Read at random location (fetch) in the serial Flash memory + -- is possible. + Trsfr_Read_Memory, + -- Write transfer into the serial memory.Scrambling is not performed. + Trsfr_Write, + -- Write data transfer into the serial memory.If enabled, scrambling is + -- performed. + Trsfr_Write_Memory) + with Size => 2; + for QSPI_IFR_TFRTYP_Field use + (Trsfr_Read => 0, + Trsfr_Read_Memory => 1, + Trsfr_Write => 2, + Trsfr_Write_Memory => 3); + + -- Continuous Read Mode + type QSPI_IFR_CRM_Field is + ( + -- The Continuous Read mode is disabled. + Disabled, + -- The Continuous Read mode is enabled. + Enabled) + with Size => 1; + for QSPI_IFR_CRM_Field use + (Disabled => 0, + Enabled => 1); + + subtype QSPI_QSPI_IFR_NBDUM_Field is HAL.UInt5; + + -- Instruction Frame Register + type QSPI_QSPI_IFR_Register is record + -- Width of Instruction Code, Address, Option Code and Data + WIDTH : QSPI_IFR_WIDTH_Field := SAM_SVD.QSPI.Single_Bit_Spi; + -- unspecified + Reserved_3_3 : HAL.Bit := 16#0#; + -- Instruction Enable + INSTEN : Boolean := False; + -- Address Enable + ADDREN : Boolean := False; + -- Option Enable + OPTEN : Boolean := False; + -- Data Enable + DATAEN : Boolean := False; + -- Option Code Length + OPTL : QSPI_IFR_OPTL_Field := SAM_SVD.QSPI.Option_1Bit; + -- Address Length + ADDRL : QSPI_IFR_ADDRL_Field := SAM_SVD.QSPI.Val_24_Bit; + -- unspecified + Reserved_11_11 : HAL.Bit := 16#0#; + -- Data Transfer Type + TFRTYP : QSPI_IFR_TFRTYP_Field := SAM_SVD.QSPI.Trsfr_Read; + -- Continuous Read Mode + CRM : QSPI_IFR_CRM_Field := SAM_SVD.QSPI.Disabled; + -- unspecified + Reserved_15_15 : HAL.Bit := 16#0#; + -- Number Of Dummy Cycles + NBDUM : QSPI_QSPI_IFR_NBDUM_Field := 16#0#; + -- unspecified + Reserved_21_31 : HAL.UInt11 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for QSPI_QSPI_IFR_Register use record + WIDTH at 0 range 0 .. 2; + Reserved_3_3 at 0 range 3 .. 3; + INSTEN at 0 range 4 .. 4; + ADDREN at 0 range 5 .. 5; + OPTEN at 0 range 6 .. 6; + DATAEN at 0 range 7 .. 7; + OPTL at 0 range 8 .. 9; + ADDRL at 0 range 10 .. 10; + Reserved_11_11 at 0 range 11 .. 11; + TFRTYP at 0 range 12 .. 13; + CRM at 0 range 14 .. 14; + Reserved_15_15 at 0 range 15 .. 15; + NBDUM at 0 range 16 .. 20; + Reserved_21_31 at 0 range 21 .. 31; + end record; + + -- Scrambling/Unscrambling Enable + type QSPI_SMR_SCREN_Field is + ( + -- The scrambling/unscrambling is disabled. + Disabled, + -- The scrambling/unscrambling is enabled. + Enabled) + with Size => 1; + for QSPI_SMR_SCREN_Field use + (Disabled => 0, + Enabled => 1); + + -- Scrambling Mode Register + type QSPI_QSPI_SMR_Register is record + -- Scrambling/Unscrambling Enable + SCREN : QSPI_SMR_SCREN_Field := SAM_SVD.QSPI.Disabled; + -- Scrambling/Unscrambling Random Value Disable + RVDIS : Boolean := False; + -- unspecified + Reserved_2_31 : HAL.UInt30 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for QSPI_QSPI_SMR_Register use record + SCREN at 0 range 0 .. 0; + RVDIS at 0 range 1 .. 1; + Reserved_2_31 at 0 range 2 .. 31; + end record; + + -- Write Protection Key + type QSPI_WPMR_WPKEY_Field is + ( + -- Reset value for the field + Qspi_Wpmr_Wpkey_Field_Reset, + -- Writing any other value in this field aborts the write operation of + -- the WPEN bit. Always reads as 0. + Passwd) + with Size => 24; + for QSPI_WPMR_WPKEY_Field use + (Qspi_Wpmr_Wpkey_Field_Reset => 0, + Passwd => 5329744); + + -- Write Protection Mode Register + type QSPI_QSPI_WPMR_Register is record + -- Write Protection Enable + WPEN : Boolean := False; + -- unspecified + Reserved_1_7 : HAL.UInt7 := 16#0#; + -- Write Protection Key + WPKEY : QSPI_WPMR_WPKEY_Field := Qspi_Wpmr_Wpkey_Field_Reset; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for QSPI_QSPI_WPMR_Register use record + WPEN at 0 range 0 .. 0; + Reserved_1_7 at 0 range 1 .. 7; + WPKEY at 0 range 8 .. 31; + end record; + + subtype QSPI_QSPI_WPSR_WPVSRC_Field is HAL.UInt8; + + -- Write Protection Status Register + type QSPI_QSPI_WPSR_Register is record + -- Read-only. Write Protection Violation Status + WPVS : Boolean; + -- unspecified + Reserved_1_7 : HAL.UInt7; + -- Read-only. Write Protection Violation Source + WPVSRC : QSPI_QSPI_WPSR_WPVSRC_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for QSPI_QSPI_WPSR_Register use record + WPVS at 0 range 0 .. 0; + Reserved_1_7 at 0 range 1 .. 7; + WPVSRC at 0 range 8 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype QSPI_QSPI_VERSION_VERSION_Field is HAL.UInt12; + subtype QSPI_QSPI_VERSION_MFN_Field is HAL.UInt3; + + -- Version Register + type QSPI_QSPI_VERSION_Register is record + -- Read-only. Hardware Module Version + VERSION : QSPI_QSPI_VERSION_VERSION_Field; + -- unspecified + Reserved_12_15 : HAL.UInt4; + -- Read-only. Metal Fix Number + MFN : QSPI_QSPI_VERSION_MFN_Field; + -- unspecified + Reserved_19_31 : HAL.UInt13; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for QSPI_QSPI_VERSION_Register use record + VERSION at 0 range 0 .. 11; + Reserved_12_15 at 0 range 12 .. 15; + MFN at 0 range 16 .. 18; + Reserved_19_31 at 0 range 19 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- Quad Serial Peripheral Interface + type QSPI_Peripheral is record + -- Control Register + QSPI_CR : aliased QSPI_QSPI_CR_Register; + -- Mode Register + QSPI_MR : aliased QSPI_QSPI_MR_Register; + -- Receive Data Register + QSPI_RDR : aliased QSPI_QSPI_RDR_Register; + -- Transmit Data Register + QSPI_TDR : aliased QSPI_QSPI_TDR_Register; + -- Status Register + QSPI_SR : aliased QSPI_QSPI_SR_Register; + -- Interrupt Enable Register + QSPI_IER : aliased QSPI_QSPI_IER_Register; + -- Interrupt Disable Register + QSPI_IDR : aliased QSPI_QSPI_IDR_Register; + -- Interrupt Mask Register + QSPI_IMR : aliased QSPI_QSPI_IMR_Register; + -- Serial Clock Register + QSPI_SCR : aliased QSPI_QSPI_SCR_Register; + -- Instruction Address Register + QSPI_IAR : aliased HAL.UInt32; + -- Instruction Code Register + QSPI_ICR : aliased QSPI_QSPI_ICR_Register; + -- Instruction Frame Register + QSPI_IFR : aliased QSPI_QSPI_IFR_Register; + -- Scrambling Mode Register + QSPI_SMR : aliased QSPI_QSPI_SMR_Register; + -- Scrambling Key Register + QSPI_SKR : aliased HAL.UInt32; + -- Write Protection Mode Register + QSPI_WPMR : aliased QSPI_QSPI_WPMR_Register; + -- Write Protection Status Register + QSPI_WPSR : aliased QSPI_QSPI_WPSR_Register; + -- Version Register + QSPI_VERSION : aliased QSPI_QSPI_VERSION_Register; + end record + with Volatile; + + for QSPI_Peripheral use record + QSPI_CR at 16#0# range 0 .. 31; + QSPI_MR at 16#4# range 0 .. 31; + QSPI_RDR at 16#8# range 0 .. 31; + QSPI_TDR at 16#C# range 0 .. 31; + QSPI_SR at 16#10# range 0 .. 31; + QSPI_IER at 16#14# range 0 .. 31; + QSPI_IDR at 16#18# range 0 .. 31; + QSPI_IMR at 16#1C# range 0 .. 31; + QSPI_SCR at 16#20# range 0 .. 31; + QSPI_IAR at 16#30# range 0 .. 31; + QSPI_ICR at 16#34# range 0 .. 31; + QSPI_IFR at 16#38# range 0 .. 31; + QSPI_SMR at 16#40# range 0 .. 31; + QSPI_SKR at 16#44# range 0 .. 31; + QSPI_WPMR at 16#E4# range 0 .. 31; + QSPI_WPSR at 16#E8# range 0 .. 31; + QSPI_VERSION at 16#FC# range 0 .. 31; + end record; + + -- Quad Serial Peripheral Interface + QSPI_Periph : aliased QSPI_Peripheral + with Import, Address => System'To_Address (16#4007C000#); + +end SAM_SVD.QSPI; diff --git a/arch/ARM/SAM/svd/atsamv71/sam_svd-rstc.ads b/arch/ARM/SAM/svd/atsamv71/sam_svd-rstc.ads new file mode 100644 index 000000000..ab05be220 --- /dev/null +++ b/arch/ARM/SAM/svd/atsamv71/sam_svd-rstc.ads @@ -0,0 +1,174 @@ +-- This spec has been automatically generated from ATSAMV71Q21.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package SAM_SVD.RSTC is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + -- System Reset Key + type RSTC_CR_KEY_Field is + ( + -- Reset value for the field + Rstc_Cr_Key_Field_Reset, + -- Writing any other value in this field aborts the write operation. + Passwd) + with Size => 8; + for RSTC_CR_KEY_Field use + (Rstc_Cr_Key_Field_Reset => 0, + Passwd => 165); + + -- Control Register + type RSTC_RSTC_CR_Register is record + -- Write-only. Processor Reset + PROCRST : Boolean := False; + -- unspecified + Reserved_1_2 : HAL.UInt2 := 16#0#; + -- Write-only. External Reset + EXTRST : Boolean := False; + -- unspecified + Reserved_4_23 : HAL.UInt20 := 16#0#; + -- Write-only. System Reset Key + KEY : RSTC_CR_KEY_Field := Rstc_Cr_Key_Field_Reset; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for RSTC_RSTC_CR_Register use record + PROCRST at 0 range 0 .. 0; + Reserved_1_2 at 0 range 1 .. 2; + EXTRST at 0 range 3 .. 3; + Reserved_4_23 at 0 range 4 .. 23; + KEY at 0 range 24 .. 31; + end record; + + -- Reset Type + type RSTC_SR_RSTTYP_Field is + ( + -- First powerup reset + General_Rst, + -- Return from Backup mode + Backup_Rst, + -- Watchdog fault occurred + Wdt_Rst, + -- Processor reset required by the software + Soft_Rst, + -- NRST pin detected low + User_Rst) + with Size => 3; + for RSTC_SR_RSTTYP_Field use + (General_Rst => 0, + Backup_Rst => 1, + Wdt_Rst => 2, + Soft_Rst => 3, + User_Rst => 4); + + -- Status Register + type RSTC_RSTC_SR_Register is record + -- Read-only. User Reset Status + URSTS : Boolean; + -- unspecified + Reserved_1_7 : HAL.UInt7; + -- Read-only. Reset Type + RSTTYP : RSTC_SR_RSTTYP_Field; + -- unspecified + Reserved_11_15 : HAL.UInt5; + -- Read-only. NRST Pin Level + NRSTL : Boolean; + -- Read-only. Software Reset Command in Progress + SRCMP : Boolean; + -- unspecified + Reserved_18_31 : HAL.UInt14; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for RSTC_RSTC_SR_Register use record + URSTS at 0 range 0 .. 0; + Reserved_1_7 at 0 range 1 .. 7; + RSTTYP at 0 range 8 .. 10; + Reserved_11_15 at 0 range 11 .. 15; + NRSTL at 0 range 16 .. 16; + SRCMP at 0 range 17 .. 17; + Reserved_18_31 at 0 range 18 .. 31; + end record; + + subtype RSTC_RSTC_MR_ERSTL_Field is HAL.UInt4; + + -- Write Access Password + type RSTC_MR_KEY_Field is + ( + -- Reset value for the field + Rstc_Mr_Key_Field_Reset, + -- Writing any other value in this field aborts the write + -- operation.Always reads as 0. + Passwd) + with Size => 8; + for RSTC_MR_KEY_Field use + (Rstc_Mr_Key_Field_Reset => 0, + Passwd => 165); + + -- Mode Register + type RSTC_RSTC_MR_Register is record + -- User Reset Enable + URSTEN : Boolean := False; + -- unspecified + Reserved_1_3 : HAL.UInt3 := 16#0#; + -- User Reset Interrupt Enable + URSTIEN : Boolean := False; + -- unspecified + Reserved_5_7 : HAL.UInt3 := 16#0#; + -- External Reset Length + ERSTL : RSTC_RSTC_MR_ERSTL_Field := 16#0#; + -- unspecified + Reserved_12_23 : HAL.UInt12 := 16#0#; + -- Write Access Password + KEY : RSTC_MR_KEY_Field := Rstc_Mr_Key_Field_Reset; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for RSTC_RSTC_MR_Register use record + URSTEN at 0 range 0 .. 0; + Reserved_1_3 at 0 range 1 .. 3; + URSTIEN at 0 range 4 .. 4; + Reserved_5_7 at 0 range 5 .. 7; + ERSTL at 0 range 8 .. 11; + Reserved_12_23 at 0 range 12 .. 23; + KEY at 0 range 24 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- Reset Controller + type RSTC_Peripheral is record + -- Control Register + RSTC_CR : aliased RSTC_RSTC_CR_Register; + -- Status Register + RSTC_SR : aliased RSTC_RSTC_SR_Register; + -- Mode Register + RSTC_MR : aliased RSTC_RSTC_MR_Register; + end record + with Volatile; + + for RSTC_Peripheral use record + RSTC_CR at 16#0# range 0 .. 31; + RSTC_SR at 16#4# range 0 .. 31; + RSTC_MR at 16#8# range 0 .. 31; + end record; + + -- Reset Controller + RSTC_Periph : aliased RSTC_Peripheral + with Import, Address => System'To_Address (16#400E1800#); + +end SAM_SVD.RSTC; diff --git a/arch/ARM/SAM/svd/atsamv71/sam_svd-rswdt.ads b/arch/ARM/SAM/svd/atsamv71/sam_svd-rswdt.ads new file mode 100644 index 000000000..3b06d731d --- /dev/null +++ b/arch/ARM/SAM/svd/atsamv71/sam_svd-rswdt.ads @@ -0,0 +1,126 @@ +-- This spec has been automatically generated from ATSAMV71Q21.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package SAM_SVD.RSWDT is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + -- Password + type RSWDT_CR_KEY_Field is + ( + -- Reset value for the field + Rswdt_Cr_Key_Field_Reset, + -- Writing any other value in this field aborts the write operation. + Passwd) + with Size => 8; + for RSWDT_CR_KEY_Field use + (Rswdt_Cr_Key_Field_Reset => 0, + Passwd => 196); + + -- Control Register + type RSWDT_RSWDT_CR_Register is record + -- Write-only. Watchdog Restart + WDRSTT : Boolean := False; + -- unspecified + Reserved_1_23 : HAL.UInt23 := 16#0#; + -- Write-only. Password + KEY : RSWDT_CR_KEY_Field := Rswdt_Cr_Key_Field_Reset; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for RSWDT_RSWDT_CR_Register use record + WDRSTT at 0 range 0 .. 0; + Reserved_1_23 at 0 range 1 .. 23; + KEY at 0 range 24 .. 31; + end record; + + subtype RSWDT_RSWDT_MR_WDV_Field is HAL.UInt12; + subtype RSWDT_RSWDT_MR_ALLONES_Field is HAL.UInt12; + + -- Mode Register + type RSWDT_RSWDT_MR_Register is record + -- Watchdog Counter Value + WDV : RSWDT_RSWDT_MR_WDV_Field := 16#0#; + -- Watchdog Fault Interrupt Enable + WDFIEN : Boolean := False; + -- Watchdog Reset Enable + WDRSTEN : Boolean := False; + -- unspecified + Reserved_14_14 : HAL.Bit := 16#0#; + -- Watchdog Disable + WDDIS : Boolean := False; + -- Must Always Be Written with 0xFFF + ALLONES : RSWDT_RSWDT_MR_ALLONES_Field := 16#0#; + -- Watchdog Debug Halt + WDDBGHLT : Boolean := False; + -- Watchdog Idle Halt + WDIDLEHLT : Boolean := False; + -- unspecified + Reserved_30_31 : HAL.UInt2 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for RSWDT_RSWDT_MR_Register use record + WDV at 0 range 0 .. 11; + WDFIEN at 0 range 12 .. 12; + WDRSTEN at 0 range 13 .. 13; + Reserved_14_14 at 0 range 14 .. 14; + WDDIS at 0 range 15 .. 15; + ALLONES at 0 range 16 .. 27; + WDDBGHLT at 0 range 28 .. 28; + WDIDLEHLT at 0 range 29 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + -- Status Register + type RSWDT_RSWDT_SR_Register is record + -- Read-only. Watchdog Underflow + WDUNF : Boolean; + -- unspecified + Reserved_1_31 : HAL.UInt31; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for RSWDT_RSWDT_SR_Register use record + WDUNF at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- Reinforced Safety Watchdog Timer + type RSWDT_Peripheral is record + -- Control Register + RSWDT_CR : aliased RSWDT_RSWDT_CR_Register; + -- Mode Register + RSWDT_MR : aliased RSWDT_RSWDT_MR_Register; + -- Status Register + RSWDT_SR : aliased RSWDT_RSWDT_SR_Register; + end record + with Volatile; + + for RSWDT_Peripheral use record + RSWDT_CR at 16#0# range 0 .. 31; + RSWDT_MR at 16#4# range 0 .. 31; + RSWDT_SR at 16#8# range 0 .. 31; + end record; + + -- Reinforced Safety Watchdog Timer + RSWDT_Periph : aliased RSWDT_Peripheral + with Import, Address => System'To_Address (16#400E1900#); + +end SAM_SVD.RSWDT; diff --git a/arch/ARM/SAM/svd/atsamv71/sam_svd-rtc.ads b/arch/ARM/SAM/svd/atsamv71/sam_svd-rtc.ads new file mode 100644 index 000000000..e6ee34a1e --- /dev/null +++ b/arch/ARM/SAM/svd/atsamv71/sam_svd-rtc.ads @@ -0,0 +1,712 @@ +-- This spec has been automatically generated from ATSAMV71Q21.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package SAM_SVD.RTC is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + -- Time Event Selection + type RTC_CR_TIMEVSEL_Field is + ( + -- Minute change + Minute, + -- Hour change + Hour, + -- Every day at midnight + Midnight, + -- Every day at noon + Noon) + with Size => 2; + for RTC_CR_TIMEVSEL_Field use + (Minute => 0, + Hour => 1, + Midnight => 2, + Noon => 3); + + -- Calendar Event Selection + type RTC_CR_CALEVSEL_Field is + ( + -- Week change (every Monday at time 00:00:00) + Week, + -- Month change (every 01 of each month at time 00:00:00) + Month, + -- Year change (every January 1 at time 00:00:00) + Year) + with Size => 2; + for RTC_CR_CALEVSEL_Field use + (Week => 0, + Month => 1, + Year => 2); + + -- Control Register + type RTC_RTC_CR_Register is record + -- Update Request Time Register + UPDTIM : Boolean := False; + -- Update Request Calendar Register + UPDCAL : Boolean := False; + -- unspecified + Reserved_2_7 : HAL.UInt6 := 16#0#; + -- Time Event Selection + TIMEVSEL : RTC_CR_TIMEVSEL_Field := SAM_SVD.RTC.Minute; + -- unspecified + Reserved_10_15 : HAL.UInt6 := 16#0#; + -- Calendar Event Selection + CALEVSEL : RTC_CR_CALEVSEL_Field := SAM_SVD.RTC.Week; + -- unspecified + Reserved_18_31 : HAL.UInt14 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for RTC_RTC_CR_Register use record + UPDTIM at 0 range 0 .. 0; + UPDCAL at 0 range 1 .. 1; + Reserved_2_7 at 0 range 2 .. 7; + TIMEVSEL at 0 range 8 .. 9; + Reserved_10_15 at 0 range 10 .. 15; + CALEVSEL at 0 range 16 .. 17; + Reserved_18_31 at 0 range 18 .. 31; + end record; + + subtype RTC_RTC_MR_CORRECTION_Field is HAL.UInt7; + + -- RTCOUT0 OutputSource Selection + type RTC_MR_OUT0_Field is + ( + -- No waveform, stuck at '0' + No_Wave, + -- 1 Hz square wave + Freq1Hz, + -- 32 Hz square wave + Freq32Hz, + -- 64 Hz square wave + Freq64Hz, + -- 512 Hz square wave + Freq512Hz, + -- Output toggles when alarm flag rises + Alarm_Toggle, + -- Output is a copy of the alarm flag + Alarm_Flag, + -- Duty cycle programmable pulse + Prog_Pulse) + with Size => 3; + for RTC_MR_OUT0_Field use + (No_Wave => 0, + Freq1Hz => 1, + Freq32Hz => 2, + Freq64Hz => 3, + Freq512Hz => 4, + Alarm_Toggle => 5, + Alarm_Flag => 6, + Prog_Pulse => 7); + + -- RTCOUT1 Output Source Selection + type RTC_MR_OUT1_Field is + ( + -- No waveform, stuck at '0' + No_Wave, + -- 1 Hz square wave + Freq1Hz, + -- 32 Hz square wave + Freq32Hz, + -- 64 Hz square wave + Freq64Hz, + -- 512 Hz square wave + Freq512Hz, + -- Output toggles when alarm flag rises + Alarm_Toggle, + -- Output is a copy of the alarm flag + Alarm_Flag, + -- Duty cycle programmable pulse + Prog_Pulse) + with Size => 3; + for RTC_MR_OUT1_Field use + (No_Wave => 0, + Freq1Hz => 1, + Freq32Hz => 2, + Freq64Hz => 3, + Freq512Hz => 4, + Alarm_Toggle => 5, + Alarm_Flag => 6, + Prog_Pulse => 7); + + -- High Duration of the Output Pulse + type RTC_MR_THIGH_Field is + ( + -- 31.2 ms + H_31Ms, + -- 15.6 ms + H_16Ms, + -- 3.91 ms + H_4Ms, + -- 976 us + H_976Us, + -- 488 us + H_488Us, + -- 122 us + H_122Us, + -- 30.5 us + H_30Us, + -- 15.2 us + H_15Us) + with Size => 3; + for RTC_MR_THIGH_Field use + (H_31Ms => 0, + H_16Ms => 1, + H_4Ms => 2, + H_976Us => 3, + H_488Us => 4, + H_122Us => 5, + H_30Us => 6, + H_15Us => 7); + + -- Period of the Output Pulse + type RTC_MR_TPERIOD_Field is + ( + -- 1 second + P_1S, + -- 500 ms + P_500Ms, + -- 250 ms + P_250Ms, + -- 125 ms + P_125Ms) + with Size => 2; + for RTC_MR_TPERIOD_Field use + (P_1S => 0, + P_500Ms => 1, + P_250Ms => 2, + P_125Ms => 3); + + -- Mode Register + type RTC_RTC_MR_Register is record + -- 12-/24-hour Mode + HRMOD : Boolean := False; + -- PERSIAN Calendar + PERSIAN : Boolean := False; + -- unspecified + Reserved_2_3 : HAL.UInt2 := 16#0#; + -- NEGative PPM Correction + NEGPPM : Boolean := False; + -- unspecified + Reserved_5_7 : HAL.UInt3 := 16#0#; + -- Slow Clock Correction + CORRECTION : RTC_RTC_MR_CORRECTION_Field := 16#0#; + -- HIGH PPM Correction + HIGHPPM : Boolean := False; + -- RTCOUT0 OutputSource Selection + OUT0 : RTC_MR_OUT0_Field := SAM_SVD.RTC.No_Wave; + -- unspecified + Reserved_19_19 : HAL.Bit := 16#0#; + -- RTCOUT1 Output Source Selection + OUT1 : RTC_MR_OUT1_Field := SAM_SVD.RTC.No_Wave; + -- unspecified + Reserved_23_23 : HAL.Bit := 16#0#; + -- High Duration of the Output Pulse + THIGH : RTC_MR_THIGH_Field := SAM_SVD.RTC.H_31Ms; + -- unspecified + Reserved_27_27 : HAL.Bit := 16#0#; + -- Period of the Output Pulse + TPERIOD : RTC_MR_TPERIOD_Field := SAM_SVD.RTC.P_1S; + -- unspecified + Reserved_30_31 : HAL.UInt2 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for RTC_RTC_MR_Register use record + HRMOD at 0 range 0 .. 0; + PERSIAN at 0 range 1 .. 1; + Reserved_2_3 at 0 range 2 .. 3; + NEGPPM at 0 range 4 .. 4; + Reserved_5_7 at 0 range 5 .. 7; + CORRECTION at 0 range 8 .. 14; + HIGHPPM at 0 range 15 .. 15; + OUT0 at 0 range 16 .. 18; + Reserved_19_19 at 0 range 19 .. 19; + OUT1 at 0 range 20 .. 22; + Reserved_23_23 at 0 range 23 .. 23; + THIGH at 0 range 24 .. 26; + Reserved_27_27 at 0 range 27 .. 27; + TPERIOD at 0 range 28 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + subtype RTC_RTC_TIMR_SEC_Field is HAL.UInt7; + subtype RTC_RTC_TIMR_MIN_Field is HAL.UInt7; + subtype RTC_RTC_TIMR_HOUR_Field is HAL.UInt6; + + -- Time Register + type RTC_RTC_TIMR_Register is record + -- Current Second + SEC : RTC_RTC_TIMR_SEC_Field := 16#0#; + -- unspecified + Reserved_7_7 : HAL.Bit := 16#0#; + -- Current Minute + MIN : RTC_RTC_TIMR_MIN_Field := 16#0#; + -- unspecified + Reserved_15_15 : HAL.Bit := 16#0#; + -- Current Hour + HOUR : RTC_RTC_TIMR_HOUR_Field := 16#0#; + -- Ante Meridiem Post Meridiem Indicator + AMPM : Boolean := False; + -- unspecified + Reserved_23_31 : HAL.UInt9 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for RTC_RTC_TIMR_Register use record + SEC at 0 range 0 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + MIN at 0 range 8 .. 14; + Reserved_15_15 at 0 range 15 .. 15; + HOUR at 0 range 16 .. 21; + AMPM at 0 range 22 .. 22; + Reserved_23_31 at 0 range 23 .. 31; + end record; + + subtype RTC_RTC_CALR_CENT_Field is HAL.UInt7; + subtype RTC_RTC_CALR_YEAR_Field is HAL.UInt8; + subtype RTC_RTC_CALR_MONTH_Field is HAL.UInt5; + subtype RTC_RTC_CALR_DAY_Field is HAL.UInt3; + subtype RTC_RTC_CALR_DATE_Field is HAL.UInt6; + + -- Calendar Register + type RTC_RTC_CALR_Register is record + -- Current Century + CENT : RTC_RTC_CALR_CENT_Field := 16#0#; + -- unspecified + Reserved_7_7 : HAL.Bit := 16#0#; + -- Current Year + YEAR : RTC_RTC_CALR_YEAR_Field := 16#0#; + -- Current Month + MONTH : RTC_RTC_CALR_MONTH_Field := 16#0#; + -- Current Day in Current Week + DAY : RTC_RTC_CALR_DAY_Field := 16#0#; + -- Current Day in Current Month + DATE : RTC_RTC_CALR_DATE_Field := 16#0#; + -- unspecified + Reserved_30_31 : HAL.UInt2 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for RTC_RTC_CALR_Register use record + CENT at 0 range 0 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + YEAR at 0 range 8 .. 15; + MONTH at 0 range 16 .. 20; + DAY at 0 range 21 .. 23; + DATE at 0 range 24 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + subtype RTC_RTC_TIMALR_SEC_Field is HAL.UInt7; + subtype RTC_RTC_TIMALR_MIN_Field is HAL.UInt7; + subtype RTC_RTC_TIMALR_HOUR_Field is HAL.UInt6; + + -- Time Alarm Register + type RTC_RTC_TIMALR_Register is record + -- Second Alarm + SEC : RTC_RTC_TIMALR_SEC_Field := 16#0#; + -- Second Alarm Enable + SECEN : Boolean := False; + -- Minute Alarm + MIN : RTC_RTC_TIMALR_MIN_Field := 16#0#; + -- Minute Alarm Enable + MINEN : Boolean := False; + -- Hour Alarm + HOUR : RTC_RTC_TIMALR_HOUR_Field := 16#0#; + -- AM/PM Indicator + AMPM : Boolean := False; + -- Hour Alarm Enable + HOUREN : Boolean := False; + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for RTC_RTC_TIMALR_Register use record + SEC at 0 range 0 .. 6; + SECEN at 0 range 7 .. 7; + MIN at 0 range 8 .. 14; + MINEN at 0 range 15 .. 15; + HOUR at 0 range 16 .. 21; + AMPM at 0 range 22 .. 22; + HOUREN at 0 range 23 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype RTC_RTC_CALALR_MONTH_Field is HAL.UInt5; + subtype RTC_RTC_CALALR_DATE_Field is HAL.UInt6; + + -- Calendar Alarm Register + type RTC_RTC_CALALR_Register is record + -- unspecified + Reserved_0_15 : HAL.UInt16 := 16#0#; + -- Month Alarm + MONTH : RTC_RTC_CALALR_MONTH_Field := 16#0#; + -- unspecified + Reserved_21_22 : HAL.UInt2 := 16#0#; + -- Month Alarm Enable + MTHEN : Boolean := False; + -- Date Alarm + DATE : RTC_RTC_CALALR_DATE_Field := 16#0#; + -- unspecified + Reserved_30_30 : HAL.Bit := 16#0#; + -- Date Alarm Enable + DATEEN : Boolean := False; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for RTC_RTC_CALALR_Register use record + Reserved_0_15 at 0 range 0 .. 15; + MONTH at 0 range 16 .. 20; + Reserved_21_22 at 0 range 21 .. 22; + MTHEN at 0 range 23 .. 23; + DATE at 0 range 24 .. 29; + Reserved_30_30 at 0 range 30 .. 30; + DATEEN at 0 range 31 .. 31; + end record; + + -- Acknowledge for Update + type RTC_SR_ACKUPD_Field is + ( + -- Time and calendar registers cannot be updated. + Freerun, + -- Time and calendar registers can be updated. + Update) + with Size => 1; + for RTC_SR_ACKUPD_Field use + (Freerun => 0, + Update => 1); + + -- Alarm Flag + type RTC_SR_ALARM_Field is + ( + -- No alarm matching condition occurred. + No_Alarmevent, + -- An alarm matching condition has occurred. + Alarmevent) + with Size => 1; + for RTC_SR_ALARM_Field use + (No_Alarmevent => 0, + Alarmevent => 1); + + -- Second Event + type RTC_SR_SEC_Field is + ( + -- No second event has occurred since the last clear. + No_Secevent, + -- At least one second event has occurred since the last clear. + Secevent) + with Size => 1; + for RTC_SR_SEC_Field use + (No_Secevent => 0, + Secevent => 1); + + -- Time Event + type RTC_SR_TIMEV_Field is + ( + -- No time event has occurred since the last clear. + No_Timevent, + -- At least one time event has occurred since the last clear. + Timevent) + with Size => 1; + for RTC_SR_TIMEV_Field use + (No_Timevent => 0, + Timevent => 1); + + -- Calendar Event + type RTC_SR_CALEV_Field is + ( + -- No calendar event has occurred since the last clear. + No_Calevent, + -- At least one calendar event has occurred since the last clear. + Calevent) + with Size => 1; + for RTC_SR_CALEV_Field use + (No_Calevent => 0, + Calevent => 1); + + -- Time and/or Date Free Running Error + type RTC_SR_TDERR_Field is + ( + -- The internal free running counters are carrying valid values since + -- the last read of the Status Register (RTC_SR). + Correct, + -- The internal free running counters have been corrupted (invalid date + -- or time, non-BCD values) since the last read and/or they are still + -- invalid. + Err_Timedate) + with Size => 1; + for RTC_SR_TDERR_Field use + (Correct => 0, + Err_Timedate => 1); + + -- Status Register + type RTC_RTC_SR_Register is record + -- Read-only. Acknowledge for Update + ACKUPD : RTC_SR_ACKUPD_Field; + -- Read-only. Alarm Flag + ALARM : RTC_SR_ALARM_Field; + -- Read-only. Second Event + SEC : RTC_SR_SEC_Field; + -- Read-only. Time Event + TIMEV : RTC_SR_TIMEV_Field; + -- Read-only. Calendar Event + CALEV : RTC_SR_CALEV_Field; + -- Read-only. Time and/or Date Free Running Error + TDERR : RTC_SR_TDERR_Field; + -- unspecified + Reserved_6_31 : HAL.UInt26; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for RTC_RTC_SR_Register use record + ACKUPD at 0 range 0 .. 0; + ALARM at 0 range 1 .. 1; + SEC at 0 range 2 .. 2; + TIMEV at 0 range 3 .. 3; + CALEV at 0 range 4 .. 4; + TDERR at 0 range 5 .. 5; + Reserved_6_31 at 0 range 6 .. 31; + end record; + + -- Status Clear Command Register + type RTC_RTC_SCCR_Register is record + -- Write-only. Acknowledge Clear + ACKCLR : Boolean := False; + -- Write-only. Alarm Clear + ALRCLR : Boolean := False; + -- Write-only. Second Clear + SECCLR : Boolean := False; + -- Write-only. Time Clear + TIMCLR : Boolean := False; + -- Write-only. Calendar Clear + CALCLR : Boolean := False; + -- Write-only. Time and/or Date Free Running Error Clear + TDERRCLR : Boolean := False; + -- unspecified + Reserved_6_31 : HAL.UInt26 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for RTC_RTC_SCCR_Register use record + ACKCLR at 0 range 0 .. 0; + ALRCLR at 0 range 1 .. 1; + SECCLR at 0 range 2 .. 2; + TIMCLR at 0 range 3 .. 3; + CALCLR at 0 range 4 .. 4; + TDERRCLR at 0 range 5 .. 5; + Reserved_6_31 at 0 range 6 .. 31; + end record; + + -- Interrupt Enable Register + type RTC_RTC_IER_Register is record + -- Write-only. Acknowledge Update Interrupt Enable + ACKEN : Boolean := False; + -- Write-only. Alarm Interrupt Enable + ALREN : Boolean := False; + -- Write-only. Second Event Interrupt Enable + SECEN : Boolean := False; + -- Write-only. Time Event Interrupt Enable + TIMEN : Boolean := False; + -- Write-only. Calendar Event Interrupt Enable + CALEN : Boolean := False; + -- Write-only. Time and/or Date Error Interrupt Enable + TDERREN : Boolean := False; + -- unspecified + Reserved_6_31 : HAL.UInt26 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for RTC_RTC_IER_Register use record + ACKEN at 0 range 0 .. 0; + ALREN at 0 range 1 .. 1; + SECEN at 0 range 2 .. 2; + TIMEN at 0 range 3 .. 3; + CALEN at 0 range 4 .. 4; + TDERREN at 0 range 5 .. 5; + Reserved_6_31 at 0 range 6 .. 31; + end record; + + -- Interrupt Disable Register + type RTC_RTC_IDR_Register is record + -- Write-only. Acknowledge Update Interrupt Disable + ACKDIS : Boolean := False; + -- Write-only. Alarm Interrupt Disable + ALRDIS : Boolean := False; + -- Write-only. Second Event Interrupt Disable + SECDIS : Boolean := False; + -- Write-only. Time Event Interrupt Disable + TIMDIS : Boolean := False; + -- Write-only. Calendar Event Interrupt Disable + CALDIS : Boolean := False; + -- Write-only. Time and/or Date Error Interrupt Disable + TDERRDIS : Boolean := False; + -- unspecified + Reserved_6_31 : HAL.UInt26 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for RTC_RTC_IDR_Register use record + ACKDIS at 0 range 0 .. 0; + ALRDIS at 0 range 1 .. 1; + SECDIS at 0 range 2 .. 2; + TIMDIS at 0 range 3 .. 3; + CALDIS at 0 range 4 .. 4; + TDERRDIS at 0 range 5 .. 5; + Reserved_6_31 at 0 range 6 .. 31; + end record; + + -- Interrupt Mask Register + type RTC_RTC_IMR_Register is record + -- Read-only. Acknowledge Update Interrupt Mask + ACK : Boolean; + -- Read-only. Alarm Interrupt Mask + ALR : Boolean; + -- Read-only. Second Event Interrupt Mask + SEC : Boolean; + -- Read-only. Time Event Interrupt Mask + TIM : Boolean; + -- Read-only. Calendar Event Interrupt Mask + CAL : Boolean; + -- Read-only. Time and/or Date Error Mask + TDERR : Boolean; + -- unspecified + Reserved_6_31 : HAL.UInt26; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for RTC_RTC_IMR_Register use record + ACK at 0 range 0 .. 0; + ALR at 0 range 1 .. 1; + SEC at 0 range 2 .. 2; + TIM at 0 range 3 .. 3; + CAL at 0 range 4 .. 4; + TDERR at 0 range 5 .. 5; + Reserved_6_31 at 0 range 6 .. 31; + end record; + + -- Valid Entry Register + type RTC_RTC_VER_Register is record + -- Read-only. Non-valid Time + NVTIM : Boolean; + -- Read-only. Non-valid Calendar + NVCAL : Boolean; + -- Read-only. Non-valid Time Alarm + NVTIMALR : Boolean; + -- Read-only. Non-valid Calendar Alarm + NVCALALR : Boolean; + -- unspecified + Reserved_4_31 : HAL.UInt28; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for RTC_RTC_VER_Register use record + NVTIM at 0 range 0 .. 0; + NVCAL at 0 range 1 .. 1; + NVTIMALR at 0 range 2 .. 2; + NVCALALR at 0 range 3 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + subtype RTC_RTC_VERSION_VERSION_Field is HAL.UInt12; + subtype RTC_RTC_VERSION_MFN_Field is HAL.UInt3; + + -- Version Register + type RTC_RTC_VERSION_Register is record + -- Read-only. Version of the Hardware Module + VERSION : RTC_RTC_VERSION_VERSION_Field; + -- unspecified + Reserved_12_15 : HAL.UInt4; + -- Read-only. Metal Fix Number + MFN : RTC_RTC_VERSION_MFN_Field; + -- unspecified + Reserved_19_31 : HAL.UInt13; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for RTC_RTC_VERSION_Register use record + VERSION at 0 range 0 .. 11; + Reserved_12_15 at 0 range 12 .. 15; + MFN at 0 range 16 .. 18; + Reserved_19_31 at 0 range 19 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- Real-time Clock + type RTC_Peripheral is record + -- Control Register + RTC_CR : aliased RTC_RTC_CR_Register; + -- Mode Register + RTC_MR : aliased RTC_RTC_MR_Register; + -- Time Register + RTC_TIMR : aliased RTC_RTC_TIMR_Register; + -- Calendar Register + RTC_CALR : aliased RTC_RTC_CALR_Register; + -- Time Alarm Register + RTC_TIMALR : aliased RTC_RTC_TIMALR_Register; + -- Calendar Alarm Register + RTC_CALALR : aliased RTC_RTC_CALALR_Register; + -- Status Register + RTC_SR : aliased RTC_RTC_SR_Register; + -- Status Clear Command Register + RTC_SCCR : aliased RTC_RTC_SCCR_Register; + -- Interrupt Enable Register + RTC_IER : aliased RTC_RTC_IER_Register; + -- Interrupt Disable Register + RTC_IDR : aliased RTC_RTC_IDR_Register; + -- Interrupt Mask Register + RTC_IMR : aliased RTC_RTC_IMR_Register; + -- Valid Entry Register + RTC_VER : aliased RTC_RTC_VER_Register; + -- Version Register + RTC_VERSION : aliased RTC_RTC_VERSION_Register; + end record + with Volatile; + + for RTC_Peripheral use record + RTC_CR at 16#0# range 0 .. 31; + RTC_MR at 16#4# range 0 .. 31; + RTC_TIMR at 16#8# range 0 .. 31; + RTC_CALR at 16#C# range 0 .. 31; + RTC_TIMALR at 16#10# range 0 .. 31; + RTC_CALALR at 16#14# range 0 .. 31; + RTC_SR at 16#18# range 0 .. 31; + RTC_SCCR at 16#1C# range 0 .. 31; + RTC_IER at 16#20# range 0 .. 31; + RTC_IDR at 16#24# range 0 .. 31; + RTC_IMR at 16#28# range 0 .. 31; + RTC_VER at 16#2C# range 0 .. 31; + RTC_VERSION at 16#FC# range 0 .. 31; + end record; + + -- Real-time Clock + RTC_Periph : aliased RTC_Peripheral + with Import, Address => System'To_Address (16#400E1860#); + +end SAM_SVD.RTC; diff --git a/arch/ARM/SAM/svd/atsamv71/sam_svd-rtt.ads b/arch/ARM/SAM/svd/atsamv71/sam_svd-rtt.ads new file mode 100644 index 000000000..e7ada3947 --- /dev/null +++ b/arch/ARM/SAM/svd/atsamv71/sam_svd-rtt.ads @@ -0,0 +1,101 @@ +-- This spec has been automatically generated from ATSAMV71Q21.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package SAM_SVD.RTT is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + subtype RTT_RTT_MR_RTPRES_Field is HAL.UInt16; + + -- Mode Register + type RTT_RTT_MR_Register is record + -- Real-time Timer Prescaler Value + RTPRES : RTT_RTT_MR_RTPRES_Field := 16#0#; + -- Alarm Interrupt Enable + ALMIEN : Boolean := False; + -- Real-time Timer Increment Interrupt Enable + RTTINCIEN : Boolean := False; + -- Real-time Timer Restart + RTTRST : Boolean := False; + -- unspecified + Reserved_19_19 : HAL.Bit := 16#0#; + -- Real-time Timer Disable + RTTDIS : Boolean := False; + -- unspecified + Reserved_21_23 : HAL.UInt3 := 16#0#; + -- Real-Time Clock 1Hz Clock Selection + RTC1HZ : Boolean := False; + -- unspecified + Reserved_25_31 : HAL.UInt7 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for RTT_RTT_MR_Register use record + RTPRES at 0 range 0 .. 15; + ALMIEN at 0 range 16 .. 16; + RTTINCIEN at 0 range 17 .. 17; + RTTRST at 0 range 18 .. 18; + Reserved_19_19 at 0 range 19 .. 19; + RTTDIS at 0 range 20 .. 20; + Reserved_21_23 at 0 range 21 .. 23; + RTC1HZ at 0 range 24 .. 24; + Reserved_25_31 at 0 range 25 .. 31; + end record; + + -- Status Register + type RTT_RTT_SR_Register is record + -- Read-only. Real-time Alarm Status (cleared on read) + ALMS : Boolean; + -- Read-only. Prescaler Roll-over Status (cleared on read) + RTTINC : Boolean; + -- unspecified + Reserved_2_31 : HAL.UInt30; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for RTT_RTT_SR_Register use record + ALMS at 0 range 0 .. 0; + RTTINC at 0 range 1 .. 1; + Reserved_2_31 at 0 range 2 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- Real-time Timer + type RTT_Peripheral is record + -- Mode Register + RTT_MR : aliased RTT_RTT_MR_Register; + -- Alarm Register + RTT_AR : aliased HAL.UInt32; + -- Value Register + RTT_VR : aliased HAL.UInt32; + -- Status Register + RTT_SR : aliased RTT_RTT_SR_Register; + end record + with Volatile; + + for RTT_Peripheral use record + RTT_MR at 16#0# range 0 .. 31; + RTT_AR at 16#4# range 0 .. 31; + RTT_VR at 16#8# range 0 .. 31; + RTT_SR at 16#C# range 0 .. 31; + end record; + + -- Real-time Timer + RTT_Periph : aliased RTT_Peripheral + with Import, Address => System'To_Address (16#400E1830#); + +end SAM_SVD.RTT; diff --git a/arch/ARM/SAM/svd/atsamv71/sam_svd-sdramc.ads b/arch/ARM/SAM/svd/atsamv71/sam_svd-sdramc.ads new file mode 100644 index 000000000..f2d6d92b5 --- /dev/null +++ b/arch/ARM/SAM/svd/atsamv71/sam_svd-sdramc.ads @@ -0,0 +1,502 @@ +-- This spec has been automatically generated from ATSAMV71Q21.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package SAM_SVD.SDRAMC is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + -- SDRAMC Command Mode + type SDRAMC_MR_MODE_Field is + ( + -- Normal mode. Any access to the SDRAM is decoded normally. To activate + -- this mode, the command must be followed by a write to the SDRAM. + Normal, + -- The SDRAMC issues a NOP command when the SDRAM device is accessed + -- regardless of the cycle. To activate this mode, the command must be + -- followed by a write to the SDRAM. + Nop, + -- The SDRAMC issues an "All Banks Precharge" command when the SDRAM + -- device is accessed regardless of the cycle. To activate this mode, + -- the command must be followed by a write to the SDRAM. + Allbanks_Precharge, + -- The SDRAMC issues a "Load Mode Register" command when the SDRAM + -- device is accessed regardless of the cycle. To activate this mode, + -- the command must be followed by a write to the SDRAM. + Load_Modereg, + -- The SDRAMC issues an "Auto-Refresh" Command when the SDRAM device is + -- accessed regardless of the cycle. Previously, an "All Banks + -- Precharge" command must be issued. To activate this mode, the command + -- must be followed by a write to the SDRAM. + Auto_Refresh, + -- The SDRAMC issues an "Extended Load Mode Register" command when the + -- SDRAM device is accessed regardless of the cycle. To activate this + -- mode, the "Extended Load Mode Register" command must be followed by a + -- write to the SDRAM. The write in the SDRAM must be done in the + -- appropriate bank; most low-power SDRAM devices use the bank 1. + Ext_Load_Modereg, + -- Deep Power-down mode. Enters Deep Power-down mode. + Deep_Powerdown) + with Size => 3; + for SDRAMC_MR_MODE_Field use + (Normal => 0, + Nop => 1, + Allbanks_Precharge => 2, + Load_Modereg => 3, + Auto_Refresh => 4, + Ext_Load_Modereg => 5, + Deep_Powerdown => 6); + + -- SDRAMC Mode Register + type SDRAMC_SDRAMC_MR_Register is record + -- SDRAMC Command Mode + MODE : SDRAMC_MR_MODE_Field := SAM_SVD.SDRAMC.Normal; + -- unspecified + Reserved_3_31 : HAL.UInt29 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for SDRAMC_SDRAMC_MR_Register use record + MODE at 0 range 0 .. 2; + Reserved_3_31 at 0 range 3 .. 31; + end record; + + subtype SDRAMC_SDRAMC_TR_COUNT_Field is HAL.UInt12; + + -- SDRAMC Refresh Timer Register + type SDRAMC_SDRAMC_TR_Register is record + -- SDRAMC Refresh Timer Count + COUNT : SDRAMC_SDRAMC_TR_COUNT_Field := 16#0#; + -- unspecified + Reserved_12_31 : HAL.UInt20 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for SDRAMC_SDRAMC_TR_Register use record + COUNT at 0 range 0 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + -- Number of Column Bits + type SDRAMC_CR_NC_Field is + ( + -- 8 column bits + Col8, + -- 9 column bits + Col9, + -- 10 column bits + Col10, + -- 11 column bits + Col11) + with Size => 2; + for SDRAMC_CR_NC_Field use + (Col8 => 0, + Col9 => 1, + Col10 => 2, + Col11 => 3); + + -- Number of Row Bits + type SDRAMC_CR_NR_Field is + ( + -- 11 row bits + Row11, + -- 12 row bits + Row12, + -- 13 row bits + Row13) + with Size => 2; + for SDRAMC_CR_NR_Field use + (Row11 => 0, + Row12 => 1, + Row13 => 2); + + -- Number of Banks + type SDRAMC_CR_NB_Field is + ( + -- 2 banks + Bank2, + -- 4 banks + Bank4) + with Size => 1; + for SDRAMC_CR_NB_Field use + (Bank2 => 0, + Bank4 => 1); + + -- CAS Latency + type SDRAMC_CR_CAS_Field is + ( + -- Reset value for the field + Sdramc_Cr_Cas_Field_Reset, + -- 1 cycle latency + Latency1, + -- 2 cycle latency + Latency2, + -- 3 cycle latency + Latency3) + with Size => 2; + for SDRAMC_CR_CAS_Field use + (Sdramc_Cr_Cas_Field_Reset => 0, + Latency1 => 1, + Latency2 => 2, + Latency3 => 3); + + subtype SDRAMC_SDRAMC_CR_TWR_Field is HAL.UInt4; + subtype SDRAMC_SDRAMC_CR_TRC_TRFC_Field is HAL.UInt4; + subtype SDRAMC_SDRAMC_CR_TRP_Field is HAL.UInt4; + subtype SDRAMC_SDRAMC_CR_TRCD_Field is HAL.UInt4; + subtype SDRAMC_SDRAMC_CR_TRAS_Field is HAL.UInt4; + subtype SDRAMC_SDRAMC_CR_TXSR_Field is HAL.UInt4; + + -- SDRAMC Configuration Register + type SDRAMC_SDRAMC_CR_Register is record + -- Number of Column Bits + NC : SDRAMC_CR_NC_Field := SAM_SVD.SDRAMC.Col8; + -- Number of Row Bits + NR : SDRAMC_CR_NR_Field := SAM_SVD.SDRAMC.Row11; + -- Number of Banks + NB : SDRAMC_CR_NB_Field := SAM_SVD.SDRAMC.Bank2; + -- CAS Latency + CAS : SDRAMC_CR_CAS_Field := Sdramc_Cr_Cas_Field_Reset; + -- Data Bus Width + DBW : Boolean := False; + -- Write Recovery Delay + TWR : SDRAMC_SDRAMC_CR_TWR_Field := 16#0#; + -- Row Cycle Delay and Row Refresh Cycle + TRC_TRFC : SDRAMC_SDRAMC_CR_TRC_TRFC_Field := 16#0#; + -- Row Precharge Delay + TRP : SDRAMC_SDRAMC_CR_TRP_Field := 16#0#; + -- Row to Column Delay + TRCD : SDRAMC_SDRAMC_CR_TRCD_Field := 16#0#; + -- Active to Precharge Delay + TRAS : SDRAMC_SDRAMC_CR_TRAS_Field := 16#0#; + -- Exit Self-Refresh to Active Delay + TXSR : SDRAMC_SDRAMC_CR_TXSR_Field := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for SDRAMC_SDRAMC_CR_Register use record + NC at 0 range 0 .. 1; + NR at 0 range 2 .. 3; + NB at 0 range 4 .. 4; + CAS at 0 range 5 .. 6; + DBW at 0 range 7 .. 7; + TWR at 0 range 8 .. 11; + TRC_TRFC at 0 range 12 .. 15; + TRP at 0 range 16 .. 19; + TRCD at 0 range 20 .. 23; + TRAS at 0 range 24 .. 27; + TXSR at 0 range 28 .. 31; + end record; + + -- Low-power Configuration Bits + type SDRAMC_LPR_LPCB_Field is + ( + -- The low-power feature is inhibited: no Power-down, Self-refresh or + -- Deep Power-down command is issued to the SDRAM device. + Disabled, + -- The SDRAMC issues a Self-refresh command to the SDRAM device, the + -- SDCK clock is deactivated and the SDCKE signal is set low. The SDRAM + -- device leaves the Self-refresh mode when accessed and enters it after + -- the access. + Self_Refresh, + -- The SDRAMC issues a Power-down Command to the SDRAM device after each + -- access, the SDCKE signal is set to low. The SDRAM device leaves the + -- Power-down mode when accessed and enters it after the access. + Power_Down, + -- The SDRAMC issues a Deep Power-down command to the SDRAM device. This + -- mode is unique to low-power SDRAM. + Deep_Power_Down) + with Size => 2; + for SDRAMC_LPR_LPCB_Field use + (Disabled => 0, + Self_Refresh => 1, + Power_Down => 2, + Deep_Power_Down => 3); + + subtype SDRAMC_SDRAMC_LPR_PASR_Field is HAL.UInt3; + subtype SDRAMC_SDRAMC_LPR_TCSR_Field is HAL.UInt2; + subtype SDRAMC_SDRAMC_LPR_DS_Field is HAL.UInt2; + + -- Time to Define When Low-power Mode Is Enabled + type SDRAMC_LPR_TIMEOUT_Field is + ( + -- The SDRAMC activates the SDRAM Low-power mode immediately after the + -- end of the last transfer. + Lp_Last_Xfer, + -- The SDRAMC activates the SDRAM Low-power mode 64 clock cycles after + -- the end of the last transfer. + Lp_Last_Xfer_64, + -- The SDRAMC activates the SDRAM Low-power mode 128 clock cycles after + -- the end of the last transfer. + Lp_Last_Xfer_128) + with Size => 2; + for SDRAMC_LPR_TIMEOUT_Field use + (Lp_Last_Xfer => 0, + Lp_Last_Xfer_64 => 1, + Lp_Last_Xfer_128 => 2); + + -- SDRAMC Low Power Register + type SDRAMC_SDRAMC_LPR_Register is record + -- Low-power Configuration Bits + LPCB : SDRAMC_LPR_LPCB_Field := SAM_SVD.SDRAMC.Disabled; + -- unspecified + Reserved_2_3 : HAL.UInt2 := 16#0#; + -- Partial Array Self-refresh (only for low-power SDRAM) + PASR : SDRAMC_SDRAMC_LPR_PASR_Field := 16#0#; + -- unspecified + Reserved_7_7 : HAL.Bit := 16#0#; + -- Temperature Compensated Self-Refresh (only for low-power SDRAM) + TCSR : SDRAMC_SDRAMC_LPR_TCSR_Field := 16#0#; + -- Drive Strength (only for low-power SDRAM) + DS : SDRAMC_SDRAMC_LPR_DS_Field := 16#0#; + -- Time to Define When Low-power Mode Is Enabled + TIMEOUT : SDRAMC_LPR_TIMEOUT_Field := + SAM_SVD.SDRAMC.Lp_Last_Xfer; + -- unspecified + Reserved_14_31 : HAL.UInt18 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for SDRAMC_SDRAMC_LPR_Register use record + LPCB at 0 range 0 .. 1; + Reserved_2_3 at 0 range 2 .. 3; + PASR at 0 range 4 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + TCSR at 0 range 8 .. 9; + DS at 0 range 10 .. 11; + TIMEOUT at 0 range 12 .. 13; + Reserved_14_31 at 0 range 14 .. 31; + end record; + + -- SDRAMC Interrupt Enable Register + type SDRAMC_SDRAMC_IER_Register is record + -- Write-only. Refresh Error Interrupt Enable + RES : Boolean := False; + -- unspecified + Reserved_1_31 : HAL.UInt31 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for SDRAMC_SDRAMC_IER_Register use record + RES at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + -- SDRAMC Interrupt Disable Register + type SDRAMC_SDRAMC_IDR_Register is record + -- Write-only. Refresh Error Interrupt Disable + RES : Boolean := False; + -- unspecified + Reserved_1_31 : HAL.UInt31 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for SDRAMC_SDRAMC_IDR_Register use record + RES at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + -- SDRAMC Interrupt Mask Register + type SDRAMC_SDRAMC_IMR_Register is record + -- Read-only. Refresh Error Interrupt Mask + RES : Boolean; + -- unspecified + Reserved_1_31 : HAL.UInt31; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for SDRAMC_SDRAMC_IMR_Register use record + RES at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + -- SDRAMC Interrupt Status Register + type SDRAMC_SDRAMC_ISR_Register is record + -- Read-only. Refresh Error Status (cleared on read) + RES : Boolean; + -- unspecified + Reserved_1_31 : HAL.UInt31; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for SDRAMC_SDRAMC_ISR_Register use record + RES at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + -- Memory Device Type + type SDRAMC_MDR_MD_Field is + ( + -- SDRAM + Sdram, + -- Low-power SDRAM + Lpsdram) + with Size => 2; + for SDRAMC_MDR_MD_Field use + (Sdram => 0, + Lpsdram => 1); + + -- SDRAMC Memory Device Register + type SDRAMC_SDRAMC_MDR_Register is record + -- Memory Device Type + MD : SDRAMC_MDR_MD_Field := SAM_SVD.SDRAMC.Sdram; + -- unspecified + Reserved_2_31 : HAL.UInt30 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for SDRAMC_SDRAMC_MDR_Register use record + MD at 0 range 0 .. 1; + Reserved_2_31 at 0 range 2 .. 31; + end record; + + subtype SDRAMC_SDRAMC_CFR1_TMRD_Field is HAL.UInt4; + + -- Support Unaligned Access + type SDRAMC_CFR1_UNAL_Field is + ( + -- Unaligned access is not supported. + Unsupported, + -- Unaligned access is supported. + Supported) + with Size => 1; + for SDRAMC_CFR1_UNAL_Field use + (Unsupported => 0, + Supported => 1); + + -- SDRAMC Configuration Register 1 + type SDRAMC_SDRAMC_CFR1_Register is record + -- Load Mode Register Command to Active or Refresh Command + TMRD : SDRAMC_SDRAMC_CFR1_TMRD_Field := 16#0#; + -- unspecified + Reserved_4_7 : HAL.UInt4 := 16#0#; + -- Support Unaligned Access + UNAL : SDRAMC_CFR1_UNAL_Field := SAM_SVD.SDRAMC.Unsupported; + -- unspecified + Reserved_9_31 : HAL.UInt23 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for SDRAMC_SDRAMC_CFR1_Register use record + TMRD at 0 range 0 .. 3; + Reserved_4_7 at 0 range 4 .. 7; + UNAL at 0 range 8 .. 8; + Reserved_9_31 at 0 range 9 .. 31; + end record; + + -- SDRAMC OCMS Register + type SDRAMC_SDRAMC_OCMS_Register is record + -- SDRAM Memory Controller Scrambling Enable + SDR_SE : Boolean := False; + -- unspecified + Reserved_1_31 : HAL.UInt31 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for SDRAMC_SDRAMC_OCMS_Register use record + SDR_SE at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + subtype SDRAMC_SDRAMC_VERSION_VERSION_Field is HAL.UInt12; + subtype SDRAMC_SDRAMC_VERSION_MFN_Field is HAL.UInt3; + + -- SDRAMC Version Register + type SDRAMC_SDRAMC_VERSION_Register is record + -- Read-only. Version of the Hardware Module + VERSION : SDRAMC_SDRAMC_VERSION_VERSION_Field; + -- unspecified + Reserved_12_15 : HAL.UInt4; + -- Read-only. Metal Fix Number + MFN : SDRAMC_SDRAMC_VERSION_MFN_Field; + -- unspecified + Reserved_19_31 : HAL.UInt13; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for SDRAMC_SDRAMC_VERSION_Register use record + VERSION at 0 range 0 .. 11; + Reserved_12_15 at 0 range 12 .. 15; + MFN at 0 range 16 .. 18; + Reserved_19_31 at 0 range 19 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- SDRAM Controller + type SDRAMC_Peripheral is record + -- SDRAMC Mode Register + SDRAMC_MR : aliased SDRAMC_SDRAMC_MR_Register; + -- SDRAMC Refresh Timer Register + SDRAMC_TR : aliased SDRAMC_SDRAMC_TR_Register; + -- SDRAMC Configuration Register + SDRAMC_CR : aliased SDRAMC_SDRAMC_CR_Register; + -- SDRAMC Low Power Register + SDRAMC_LPR : aliased SDRAMC_SDRAMC_LPR_Register; + -- SDRAMC Interrupt Enable Register + SDRAMC_IER : aliased SDRAMC_SDRAMC_IER_Register; + -- SDRAMC Interrupt Disable Register + SDRAMC_IDR : aliased SDRAMC_SDRAMC_IDR_Register; + -- SDRAMC Interrupt Mask Register + SDRAMC_IMR : aliased SDRAMC_SDRAMC_IMR_Register; + -- SDRAMC Interrupt Status Register + SDRAMC_ISR : aliased SDRAMC_SDRAMC_ISR_Register; + -- SDRAMC Memory Device Register + SDRAMC_MDR : aliased SDRAMC_SDRAMC_MDR_Register; + -- SDRAMC Configuration Register 1 + SDRAMC_CFR1 : aliased SDRAMC_SDRAMC_CFR1_Register; + -- SDRAMC OCMS Register + SDRAMC_OCMS : aliased SDRAMC_SDRAMC_OCMS_Register; + -- SDRAMC OCMS KEY1 Register + SDRAMC_OCMS_KEY1 : aliased HAL.UInt32; + -- SDRAMC OCMS KEY2 Register + SDRAMC_OCMS_KEY2 : aliased HAL.UInt32; + -- SDRAMC Version Register + SDRAMC_VERSION : aliased SDRAMC_SDRAMC_VERSION_Register; + end record + with Volatile; + + for SDRAMC_Peripheral use record + SDRAMC_MR at 16#0# range 0 .. 31; + SDRAMC_TR at 16#4# range 0 .. 31; + SDRAMC_CR at 16#8# range 0 .. 31; + SDRAMC_LPR at 16#10# range 0 .. 31; + SDRAMC_IER at 16#14# range 0 .. 31; + SDRAMC_IDR at 16#18# range 0 .. 31; + SDRAMC_IMR at 16#1C# range 0 .. 31; + SDRAMC_ISR at 16#20# range 0 .. 31; + SDRAMC_MDR at 16#24# range 0 .. 31; + SDRAMC_CFR1 at 16#28# range 0 .. 31; + SDRAMC_OCMS at 16#2C# range 0 .. 31; + SDRAMC_OCMS_KEY1 at 16#30# range 0 .. 31; + SDRAMC_OCMS_KEY2 at 16#34# range 0 .. 31; + SDRAMC_VERSION at 16#FC# range 0 .. 31; + end record; + + -- SDRAM Controller + SDRAMC_Periph : aliased SDRAMC_Peripheral + with Import, Address => System'To_Address (16#40084000#); + +end SAM_SVD.SDRAMC; diff --git a/arch/ARM/SAM/svd/atsamv71/sam_svd-smc.ads b/arch/ARM/SAM/svd/atsamv71/sam_svd-smc.ads new file mode 100644 index 000000000..ac6281e78 --- /dev/null +++ b/arch/ARM/SAM/svd/atsamv71/sam_svd-smc.ads @@ -0,0 +1,426 @@ +-- This spec has been automatically generated from ATSAMV71Q21.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package SAM_SVD.SMC is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + ------------------------------------------- + -- SMC_SMC_CS_NUMBER cluster's Registers -- + ------------------------------------------- + + subtype SMC_SMC_SETUP_SMC_SMC_CS_NUMBER_NWE_SETUP_Field is HAL.UInt6; + subtype SMC_SMC_SETUP_SMC_SMC_CS_NUMBER_NCS_WR_SETUP_Field is HAL.UInt6; + subtype SMC_SMC_SETUP_SMC_SMC_CS_NUMBER_NRD_SETUP_Field is HAL.UInt6; + subtype SMC_SMC_SETUP_SMC_SMC_CS_NUMBER_NCS_RD_SETUP_Field is HAL.UInt6; + + -- SMC Setup Register (CS_number = 0) + type SMC_SMC_SETUP_SMC_SMC_CS_NUMBER_Register is record + -- NWE Setup Length + NWE_SETUP : SMC_SMC_SETUP_SMC_SMC_CS_NUMBER_NWE_SETUP_Field := + 16#0#; + -- unspecified + Reserved_6_7 : HAL.UInt2 := 16#0#; + -- NCS Setup Length in WRITE Access + NCS_WR_SETUP : SMC_SMC_SETUP_SMC_SMC_CS_NUMBER_NCS_WR_SETUP_Field := + 16#0#; + -- unspecified + Reserved_14_15 : HAL.UInt2 := 16#0#; + -- NRD Setup Length + NRD_SETUP : SMC_SMC_SETUP_SMC_SMC_CS_NUMBER_NRD_SETUP_Field := + 16#0#; + -- unspecified + Reserved_22_23 : HAL.UInt2 := 16#0#; + -- NCS Setup Length in READ Access + NCS_RD_SETUP : SMC_SMC_SETUP_SMC_SMC_CS_NUMBER_NCS_RD_SETUP_Field := + 16#0#; + -- unspecified + Reserved_30_31 : HAL.UInt2 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for SMC_SMC_SETUP_SMC_SMC_CS_NUMBER_Register use record + NWE_SETUP at 0 range 0 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + NCS_WR_SETUP at 0 range 8 .. 13; + Reserved_14_15 at 0 range 14 .. 15; + NRD_SETUP at 0 range 16 .. 21; + Reserved_22_23 at 0 range 22 .. 23; + NCS_RD_SETUP at 0 range 24 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + subtype SMC_SMC_PULSE_SMC_SMC_CS_NUMBER_NWE_PULSE_Field is HAL.UInt7; + subtype SMC_SMC_PULSE_SMC_SMC_CS_NUMBER_NCS_WR_PULSE_Field is HAL.UInt7; + subtype SMC_SMC_PULSE_SMC_SMC_CS_NUMBER_NRD_PULSE_Field is HAL.UInt7; + subtype SMC_SMC_PULSE_SMC_SMC_CS_NUMBER_NCS_RD_PULSE_Field is HAL.UInt7; + + -- SMC Pulse Register (CS_number = 0) + type SMC_SMC_PULSE_SMC_SMC_CS_NUMBER_Register is record + -- NWE Pulse Length + NWE_PULSE : SMC_SMC_PULSE_SMC_SMC_CS_NUMBER_NWE_PULSE_Field := + 16#0#; + -- unspecified + Reserved_7_7 : HAL.Bit := 16#0#; + -- NCS Pulse Length in WRITE Access + NCS_WR_PULSE : SMC_SMC_PULSE_SMC_SMC_CS_NUMBER_NCS_WR_PULSE_Field := + 16#0#; + -- unspecified + Reserved_15_15 : HAL.Bit := 16#0#; + -- NRD Pulse Length + NRD_PULSE : SMC_SMC_PULSE_SMC_SMC_CS_NUMBER_NRD_PULSE_Field := + 16#0#; + -- unspecified + Reserved_23_23 : HAL.Bit := 16#0#; + -- NCS Pulse Length in READ Access + NCS_RD_PULSE : SMC_SMC_PULSE_SMC_SMC_CS_NUMBER_NCS_RD_PULSE_Field := + 16#0#; + -- unspecified + Reserved_31_31 : HAL.Bit := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for SMC_SMC_PULSE_SMC_SMC_CS_NUMBER_Register use record + NWE_PULSE at 0 range 0 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + NCS_WR_PULSE at 0 range 8 .. 14; + Reserved_15_15 at 0 range 15 .. 15; + NRD_PULSE at 0 range 16 .. 22; + Reserved_23_23 at 0 range 23 .. 23; + NCS_RD_PULSE at 0 range 24 .. 30; + Reserved_31_31 at 0 range 31 .. 31; + end record; + + subtype SMC_SMC_CYCLE_SMC_SMC_CS_NUMBER_NWE_CYCLE_Field is HAL.UInt9; + subtype SMC_SMC_CYCLE_SMC_SMC_CS_NUMBER_NRD_CYCLE_Field is HAL.UInt9; + + -- SMC Cycle Register (CS_number = 0) + type SMC_SMC_CYCLE_SMC_SMC_CS_NUMBER_Register is record + -- Total Write Cycle Length + NWE_CYCLE : SMC_SMC_CYCLE_SMC_SMC_CS_NUMBER_NWE_CYCLE_Field := + 16#0#; + -- unspecified + Reserved_9_15 : HAL.UInt7 := 16#0#; + -- Total Read Cycle Length + NRD_CYCLE : SMC_SMC_CYCLE_SMC_SMC_CS_NUMBER_NRD_CYCLE_Field := + 16#0#; + -- unspecified + Reserved_25_31 : HAL.UInt7 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for SMC_SMC_CYCLE_SMC_SMC_CS_NUMBER_Register use record + NWE_CYCLE at 0 range 0 .. 8; + Reserved_9_15 at 0 range 9 .. 15; + NRD_CYCLE at 0 range 16 .. 24; + Reserved_25_31 at 0 range 25 .. 31; + end record; + + -- NWAIT Mode + type SMC_MODE_EXNW_MODE_Field is + ( + -- Disabled-The NWAIT input signal is ignored on the corresponding chip + -- select. + Disabled, + -- Frozen Mode-If asserted, the NWAIT signal freezes the current read or + -- write cycle. After deassertion, the read/write cycle is resumed from + -- the point where it was stopped. + Frozen, + -- Ready Mode-The NWAIT signal indicates the availability of the + -- external device at the end of the pulse of the controlling read or + -- write signal, to complete the access. If high, the access normally + -- completes. If low, the access is extended until NWAIT returns high. + Ready) + with Size => 2; + for SMC_MODE_EXNW_MODE_Field use + (Disabled => 0, + Frozen => 2, + Ready => 3); + + -- Byte Access Type + type SMC_MODE_BAT_Field is + ( + -- Byte select access type:- Write operation is controlled using NCS, + -- NWE, NBS0, NBS1.- Read operation is controlled using NCS, NRD, NBS0, + -- NBS1. + Byte_Select, + -- Byte write access type:- Write operation is controlled using NCS, + -- NWR0, NWR1.- Read operation is controlled using NCS and NRD. + Byte_Write) + with Size => 1; + for SMC_MODE_BAT_Field use + (Byte_Select => 0, + Byte_Write => 1); + + -- Data Bus Width + type SMC_MODE_DBW_Field is + ( + -- 8-bit Data Bus + Val_8_Bit, + -- 16-bit Data Bus + Val_16_Bit) + with Size => 1; + for SMC_MODE_DBW_Field use + (Val_8_Bit => 0, + Val_16_Bit => 1); + + subtype SMC_SMC_MODE_SMC_SMC_CS_NUMBER_TDF_CYCLES_Field is HAL.UInt4; + + -- Page Size + type SMC_MODE_PS_Field is + ( + -- 4-byte page + Val_4_Byte, + -- 8-byte page + Val_8_Byte, + -- 16-byte page + Val_16_Byte, + -- 32-byte page + Val_32_Byte) + with Size => 2; + for SMC_MODE_PS_Field use + (Val_4_Byte => 0, + Val_8_Byte => 1, + Val_16_Byte => 2, + Val_32_Byte => 3); + + -- SMC Mode Register (CS_number = 0) + type SMC_SMC_MODE_SMC_SMC_CS_NUMBER_Register is record + -- Read Mode + READ_MODE : Boolean := False; + -- Write Mode + WRITE_MODE : Boolean := False; + -- unspecified + Reserved_2_3 : HAL.UInt2 := 16#0#; + -- NWAIT Mode + EXNW_MODE : SMC_MODE_EXNW_MODE_Field := SAM_SVD.SMC.Disabled; + -- unspecified + Reserved_6_7 : HAL.UInt2 := 16#0#; + -- Byte Access Type + BAT : SMC_MODE_BAT_Field := SAM_SVD.SMC.Byte_Select; + -- unspecified + Reserved_9_11 : HAL.UInt3 := 16#0#; + -- Data Bus Width + DBW : SMC_MODE_DBW_Field := SAM_SVD.SMC.Val_8_Bit; + -- unspecified + Reserved_13_15 : HAL.UInt3 := 16#0#; + -- Data Float Time + TDF_CYCLES : SMC_SMC_MODE_SMC_SMC_CS_NUMBER_TDF_CYCLES_Field := + 16#0#; + -- TDF Optimization + TDF_MODE : Boolean := False; + -- unspecified + Reserved_21_23 : HAL.UInt3 := 16#0#; + -- Page Mode Enabled + PMEN : Boolean := False; + -- unspecified + Reserved_25_27 : HAL.UInt3 := 16#0#; + -- Page Size + PS : SMC_MODE_PS_Field := SAM_SVD.SMC.Val_4_Byte; + -- unspecified + Reserved_30_31 : HAL.UInt2 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for SMC_SMC_MODE_SMC_SMC_CS_NUMBER_Register use record + READ_MODE at 0 range 0 .. 0; + WRITE_MODE at 0 range 1 .. 1; + Reserved_2_3 at 0 range 2 .. 3; + EXNW_MODE at 0 range 4 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + BAT at 0 range 8 .. 8; + Reserved_9_11 at 0 range 9 .. 11; + DBW at 0 range 12 .. 12; + Reserved_13_15 at 0 range 13 .. 15; + TDF_CYCLES at 0 range 16 .. 19; + TDF_MODE at 0 range 20 .. 20; + Reserved_21_23 at 0 range 21 .. 23; + PMEN at 0 range 24 .. 24; + Reserved_25_27 at 0 range 25 .. 27; + PS at 0 range 28 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + -- SMC Setup Register (CS_number = 0) + type SMC_SMC_CS_NUMBER_Cluster is record + -- SMC Setup Register (CS_number = 0) + SMC_SETUP : aliased SMC_SMC_SETUP_SMC_SMC_CS_NUMBER_Register; + -- SMC Pulse Register (CS_number = 0) + SMC_PULSE : aliased SMC_SMC_PULSE_SMC_SMC_CS_NUMBER_Register; + -- SMC Cycle Register (CS_number = 0) + SMC_CYCLE : aliased SMC_SMC_CYCLE_SMC_SMC_CS_NUMBER_Register; + -- SMC Mode Register (CS_number = 0) + SMC_MODE : aliased SMC_SMC_MODE_SMC_SMC_CS_NUMBER_Register; + end record + with Volatile, Size => 128; + + for SMC_SMC_CS_NUMBER_Cluster use record + SMC_SETUP at 16#0# range 0 .. 31; + SMC_PULSE at 16#4# range 0 .. 31; + SMC_CYCLE at 16#8# range 0 .. 31; + SMC_MODE at 16#C# range 0 .. 31; + end record; + + -- SMC Setup Register (CS_number = 0) + type SMC_SMC_CS_NUMBER_Clusters is array (0 .. 3) + of SMC_SMC_CS_NUMBER_Cluster; + + -- SMC Off-Chip Memory Scrambling Register + type SMC_SMC_OCMS_Register is record + -- Static Memory Controller Scrambling Enable + SMSE : Boolean := False; + -- unspecified + Reserved_1_7 : HAL.UInt7 := 16#0#; + -- Chip Select (x = 0 to 3) Scrambling Enable + CS0SE : Boolean := False; + -- Chip Select (x = 0 to 3) Scrambling Enable + CS1SE : Boolean := False; + -- Chip Select (x = 0 to 3) Scrambling Enable + CS2SE : Boolean := False; + -- Chip Select (x = 0 to 3) Scrambling Enable + CS3SE : Boolean := False; + -- unspecified + Reserved_12_31 : HAL.UInt20 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for SMC_SMC_OCMS_Register use record + SMSE at 0 range 0 .. 0; + Reserved_1_7 at 0 range 1 .. 7; + CS0SE at 0 range 8 .. 8; + CS1SE at 0 range 9 .. 9; + CS2SE at 0 range 10 .. 10; + CS3SE at 0 range 11 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + -- Write Protection Key + type SMC_WPMR_WPKEY_Field is + ( + -- Reset value for the field + Smc_Wpmr_Wpkey_Field_Reset, + -- Writing any other value in this field aborts the write operation of + -- the WPEN bit. Always reads as 0. + Passwd) + with Size => 24; + for SMC_WPMR_WPKEY_Field use + (Smc_Wpmr_Wpkey_Field_Reset => 0, + Passwd => 5459267); + + -- SMC Write Protection Mode Register + type SMC_SMC_WPMR_Register is record + -- Write Protect Enable + WPEN : Boolean := False; + -- unspecified + Reserved_1_7 : HAL.UInt7 := 16#0#; + -- Write Protection Key + WPKEY : SMC_WPMR_WPKEY_Field := Smc_Wpmr_Wpkey_Field_Reset; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for SMC_SMC_WPMR_Register use record + WPEN at 0 range 0 .. 0; + Reserved_1_7 at 0 range 1 .. 7; + WPKEY at 0 range 8 .. 31; + end record; + + subtype SMC_SMC_WPSR_WPVSRC_Field is HAL.UInt16; + + -- SMC Write Protection Status Register + type SMC_SMC_WPSR_Register is record + -- Read-only. Write Protection Violation Status + WPVS : Boolean; + -- unspecified + Reserved_1_7 : HAL.UInt7; + -- Read-only. Write Protection Violation Source + WPVSRC : SMC_SMC_WPSR_WPVSRC_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for SMC_SMC_WPSR_Register use record + WPVS at 0 range 0 .. 0; + Reserved_1_7 at 0 range 1 .. 7; + WPVSRC at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype SMC_SMC_VERSION_VERSION_Field is HAL.UInt12; + subtype SMC_SMC_VERSION_MFN_Field is HAL.UInt3; + + -- SMC Version Register + type SMC_SMC_VERSION_Register is record + -- Read-only. Hardware Module Version + VERSION : SMC_SMC_VERSION_VERSION_Field; + -- unspecified + Reserved_12_15 : HAL.UInt4; + -- Read-only. Metal Fix Number + MFN : SMC_SMC_VERSION_MFN_Field; + -- unspecified + Reserved_19_31 : HAL.UInt13; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for SMC_SMC_VERSION_Register use record + VERSION at 0 range 0 .. 11; + Reserved_12_15 at 0 range 12 .. 15; + MFN at 0 range 16 .. 18; + Reserved_19_31 at 0 range 19 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- Static Memory Controller + type SMC_Peripheral is record + -- SMC Setup Register (CS_number = 0) + SMC_SMC_CS_NUMBER : aliased SMC_SMC_CS_NUMBER_Clusters; + -- SMC Off-Chip Memory Scrambling Register + SMC_OCMS : aliased SMC_SMC_OCMS_Register; + -- SMC Off-Chip Memory Scrambling KEY1 Register + SMC_KEY1 : aliased HAL.UInt32; + -- SMC Off-Chip Memory Scrambling KEY2 Register + SMC_KEY2 : aliased HAL.UInt32; + -- SMC Write Protection Mode Register + SMC_WPMR : aliased SMC_SMC_WPMR_Register; + -- SMC Write Protection Status Register + SMC_WPSR : aliased SMC_SMC_WPSR_Register; + -- SMC Version Register + SMC_VERSION : aliased SMC_SMC_VERSION_Register; + end record + with Volatile; + + for SMC_Peripheral use record + SMC_SMC_CS_NUMBER at 16#0# range 0 .. 511; + SMC_OCMS at 16#80# range 0 .. 31; + SMC_KEY1 at 16#84# range 0 .. 31; + SMC_KEY2 at 16#88# range 0 .. 31; + SMC_WPMR at 16#E4# range 0 .. 31; + SMC_WPSR at 16#E8# range 0 .. 31; + SMC_VERSION at 16#FC# range 0 .. 31; + end record; + + -- Static Memory Controller + SMC_Periph : aliased SMC_Peripheral + with Import, Address => System'To_Address (16#40080000#); + +end SAM_SVD.SMC; diff --git a/arch/ARM/SAM/svd/atsamv71/sam_svd-spi.ads b/arch/ARM/SAM/svd/atsamv71/sam_svd-spi.ads new file mode 100644 index 000000000..8d0ef18a9 --- /dev/null +++ b/arch/ARM/SAM/svd/atsamv71/sam_svd-spi.ads @@ -0,0 +1,528 @@ +-- This spec has been automatically generated from ATSAMV71Q21.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package SAM_SVD.SPI is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + -- Control Register + type SPI_SPI_CR_Register is record + -- Write-only. SPI Enable + SPIEN : Boolean := False; + -- Write-only. SPI Disable + SPIDIS : Boolean := False; + -- unspecified + Reserved_2_6 : HAL.UInt5 := 16#0#; + -- Write-only. SPI Software Reset + SWRST : Boolean := False; + -- unspecified + Reserved_8_11 : HAL.UInt4 := 16#0#; + -- Write-only. Request to Clear the Comparison Trigger + REQCLR : Boolean := False; + -- unspecified + Reserved_13_15 : HAL.UInt3 := 16#0#; + -- Write-only. Transmit FIFO Clear + TXFCLR : Boolean := False; + -- Write-only. Receive FIFO Clear + RXFCLR : Boolean := False; + -- unspecified + Reserved_18_23 : HAL.UInt6 := 16#0#; + -- Write-only. Last Transfer + LASTXFER : Boolean := False; + -- unspecified + Reserved_25_29 : HAL.UInt5 := 16#0#; + -- Write-only. FIFO Enable + FIFOEN : Boolean := False; + -- Write-only. FIFO Disable + FIFODIS : Boolean := False; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for SPI_SPI_CR_Register use record + SPIEN at 0 range 0 .. 0; + SPIDIS at 0 range 1 .. 1; + Reserved_2_6 at 0 range 2 .. 6; + SWRST at 0 range 7 .. 7; + Reserved_8_11 at 0 range 8 .. 11; + REQCLR at 0 range 12 .. 12; + Reserved_13_15 at 0 range 13 .. 15; + TXFCLR at 0 range 16 .. 16; + RXFCLR at 0 range 17 .. 17; + Reserved_18_23 at 0 range 18 .. 23; + LASTXFER at 0 range 24 .. 24; + Reserved_25_29 at 0 range 25 .. 29; + FIFOEN at 0 range 30 .. 30; + FIFODIS at 0 range 31 .. 31; + end record; + + subtype SPI_SPI_MR_PCS_Field is HAL.UInt4; + subtype SPI_SPI_MR_DLYBCS_Field is HAL.UInt8; + + -- Mode Register + type SPI_SPI_MR_Register is record + -- Master/Slave Mode + MSTR : Boolean := False; + -- Peripheral Select + PS : Boolean := False; + -- Chip Select Decode + PCSDEC : Boolean := False; + -- unspecified + Reserved_3_3 : HAL.Bit := 16#0#; + -- Mode Fault Detection + MODFDIS : Boolean := False; + -- Wait Data Read Before Transfer + WDRBT : Boolean := False; + -- unspecified + Reserved_6_6 : HAL.Bit := 16#0#; + -- Local Loopback Enable + LLB : Boolean := False; + -- unspecified + Reserved_8_15 : HAL.UInt8 := 16#0#; + -- Peripheral Chip Select + PCS : SPI_SPI_MR_PCS_Field := 16#0#; + -- unspecified + Reserved_20_23 : HAL.UInt4 := 16#0#; + -- Delay Between Chip Selects + DLYBCS : SPI_SPI_MR_DLYBCS_Field := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for SPI_SPI_MR_Register use record + MSTR at 0 range 0 .. 0; + PS at 0 range 1 .. 1; + PCSDEC at 0 range 2 .. 2; + Reserved_3_3 at 0 range 3 .. 3; + MODFDIS at 0 range 4 .. 4; + WDRBT at 0 range 5 .. 5; + Reserved_6_6 at 0 range 6 .. 6; + LLB at 0 range 7 .. 7; + Reserved_8_15 at 0 range 8 .. 15; + PCS at 0 range 16 .. 19; + Reserved_20_23 at 0 range 20 .. 23; + DLYBCS at 0 range 24 .. 31; + end record; + + subtype SPI_SPI_RDR_RD_Field is HAL.UInt16; + subtype SPI_SPI_RDR_PCS_Field is HAL.UInt4; + + -- Receive Data Register + type SPI_SPI_RDR_Register is record + -- Read-only. Receive Data + RD : SPI_SPI_RDR_RD_Field; + -- Read-only. Peripheral Chip Select + PCS : SPI_SPI_RDR_PCS_Field; + -- unspecified + Reserved_20_31 : HAL.UInt12; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for SPI_SPI_RDR_Register use record + RD at 0 range 0 .. 15; + PCS at 0 range 16 .. 19; + Reserved_20_31 at 0 range 20 .. 31; + end record; + + subtype SPI_SPI_TDR_TD_Field is HAL.UInt16; + subtype SPI_SPI_TDR_PCS_Field is HAL.UInt4; + + -- Transmit Data Register + type SPI_SPI_TDR_Register is record + -- Write-only. Transmit Data + TD : SPI_SPI_TDR_TD_Field := 16#0#; + -- Write-only. Peripheral Chip Select + PCS : SPI_SPI_TDR_PCS_Field := 16#0#; + -- unspecified + Reserved_20_23 : HAL.UInt4 := 16#0#; + -- Write-only. Last Transfer + LASTXFER : Boolean := False; + -- unspecified + Reserved_25_31 : HAL.UInt7 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for SPI_SPI_TDR_Register use record + TD at 0 range 0 .. 15; + PCS at 0 range 16 .. 19; + Reserved_20_23 at 0 range 20 .. 23; + LASTXFER at 0 range 24 .. 24; + Reserved_25_31 at 0 range 25 .. 31; + end record; + + -- Status Register + type SPI_SPI_SR_Register is record + -- Read-only. Receive Data Register Full (cleared by reading SPI_RDR) + RDRF : Boolean; + -- Read-only. Transmit Data Register Empty (cleared by writing SPI_TDR) + TDRE : Boolean; + -- Read-only. Mode Fault Error (cleared on read) + MODF : Boolean; + -- Read-only. Overrun Error Status (cleared on read) + OVRES : Boolean; + -- unspecified + Reserved_4_7 : HAL.UInt4; + -- Read-only. NSS Rising (cleared on read) + NSSR : Boolean; + -- Read-only. Transmission Registers Empty (cleared by writing SPI_TDR) + TXEMPTY : Boolean; + -- Read-only. Underrun Error Status (Slave mode only) (cleared on read) + UNDES : Boolean; + -- unspecified + Reserved_11_15 : HAL.UInt5; + -- Read-only. SPI Enable Status + SPIENS : Boolean; + -- unspecified + Reserved_17_31 : HAL.UInt15; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for SPI_SPI_SR_Register use record + RDRF at 0 range 0 .. 0; + TDRE at 0 range 1 .. 1; + MODF at 0 range 2 .. 2; + OVRES at 0 range 3 .. 3; + Reserved_4_7 at 0 range 4 .. 7; + NSSR at 0 range 8 .. 8; + TXEMPTY at 0 range 9 .. 9; + UNDES at 0 range 10 .. 10; + Reserved_11_15 at 0 range 11 .. 15; + SPIENS at 0 range 16 .. 16; + Reserved_17_31 at 0 range 17 .. 31; + end record; + + -- Interrupt Enable Register + type SPI_SPI_IER_Register is record + -- Write-only. Receive Data Register Full Interrupt Enable + RDRF : Boolean := False; + -- Write-only. SPI Transmit Data Register Empty Interrupt Enable + TDRE : Boolean := False; + -- Write-only. Mode Fault Error Interrupt Enable + MODF : Boolean := False; + -- Write-only. Overrun Error Interrupt Enable + OVRES : Boolean := False; + -- unspecified + Reserved_4_7 : HAL.UInt4 := 16#0#; + -- Write-only. NSS Rising Interrupt Enable + NSSR : Boolean := False; + -- Write-only. Transmission Registers Empty Enable + TXEMPTY : Boolean := False; + -- Write-only. Underrun Error Interrupt Enable + UNDES : Boolean := False; + -- unspecified + Reserved_11_31 : HAL.UInt21 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for SPI_SPI_IER_Register use record + RDRF at 0 range 0 .. 0; + TDRE at 0 range 1 .. 1; + MODF at 0 range 2 .. 2; + OVRES at 0 range 3 .. 3; + Reserved_4_7 at 0 range 4 .. 7; + NSSR at 0 range 8 .. 8; + TXEMPTY at 0 range 9 .. 9; + UNDES at 0 range 10 .. 10; + Reserved_11_31 at 0 range 11 .. 31; + end record; + + -- Interrupt Disable Register + type SPI_SPI_IDR_Register is record + -- Write-only. Receive Data Register Full Interrupt Disable + RDRF : Boolean := False; + -- Write-only. SPI Transmit Data Register Empty Interrupt Disable + TDRE : Boolean := False; + -- Write-only. Mode Fault Error Interrupt Disable + MODF : Boolean := False; + -- Write-only. Overrun Error Interrupt Disable + OVRES : Boolean := False; + -- unspecified + Reserved_4_7 : HAL.UInt4 := 16#0#; + -- Write-only. NSS Rising Interrupt Disable + NSSR : Boolean := False; + -- Write-only. Transmission Registers Empty Disable + TXEMPTY : Boolean := False; + -- Write-only. Underrun Error Interrupt Disable + UNDES : Boolean := False; + -- unspecified + Reserved_11_31 : HAL.UInt21 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for SPI_SPI_IDR_Register use record + RDRF at 0 range 0 .. 0; + TDRE at 0 range 1 .. 1; + MODF at 0 range 2 .. 2; + OVRES at 0 range 3 .. 3; + Reserved_4_7 at 0 range 4 .. 7; + NSSR at 0 range 8 .. 8; + TXEMPTY at 0 range 9 .. 9; + UNDES at 0 range 10 .. 10; + Reserved_11_31 at 0 range 11 .. 31; + end record; + + -- Interrupt Mask Register + type SPI_SPI_IMR_Register is record + -- Read-only. Receive Data Register Full Interrupt Mask + RDRF : Boolean; + -- Read-only. SPI Transmit Data Register Empty Interrupt Mask + TDRE : Boolean; + -- Read-only. Mode Fault Error Interrupt Mask + MODF : Boolean; + -- Read-only. Overrun Error Interrupt Mask + OVRES : Boolean; + -- unspecified + Reserved_4_7 : HAL.UInt4; + -- Read-only. NSS Rising Interrupt Mask + NSSR : Boolean; + -- Read-only. Transmission Registers Empty Mask + TXEMPTY : Boolean; + -- Read-only. Underrun Error Interrupt Mask + UNDES : Boolean; + -- unspecified + Reserved_11_31 : HAL.UInt21; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for SPI_SPI_IMR_Register use record + RDRF at 0 range 0 .. 0; + TDRE at 0 range 1 .. 1; + MODF at 0 range 2 .. 2; + OVRES at 0 range 3 .. 3; + Reserved_4_7 at 0 range 4 .. 7; + NSSR at 0 range 8 .. 8; + TXEMPTY at 0 range 9 .. 9; + UNDES at 0 range 10 .. 10; + Reserved_11_31 at 0 range 11 .. 31; + end record; + + -- Bits Per Transfer + type SPI_CSR_BITS_Field is + ( + -- 8 bits for transfer + Val_8_Bit, + -- 9 bits for transfer + Val_9_Bit, + -- 10 bits for transfer + Val_10_Bit, + -- 11 bits for transfer + Val_11_Bit, + -- 12 bits for transfer + Val_12_Bit, + -- 13 bits for transfer + Val_13_Bit, + -- 14 bits for transfer + Val_14_Bit, + -- 15 bits for transfer + Val_15_Bit, + -- 16 bits for transfer + Val_16_Bit) + with Size => 4; + for SPI_CSR_BITS_Field use + (Val_8_Bit => 0, + Val_9_Bit => 1, + Val_10_Bit => 2, + Val_11_Bit => 3, + Val_12_Bit => 4, + Val_13_Bit => 5, + Val_14_Bit => 6, + Val_15_Bit => 7, + Val_16_Bit => 8); + + subtype SPI_SPI_CSR_SCBR_Field is HAL.UInt8; + subtype SPI_SPI_CSR_DLYBS_Field is HAL.UInt8; + subtype SPI_SPI_CSR_DLYBCT_Field is HAL.UInt8; + + -- Chip Select Register (CS_number = 0) 0 + type SPI_SPI_CSR_Register is record + -- Clock Polarity + CPOL : Boolean := False; + -- Clock Phase + NCPHA : Boolean := False; + -- Chip Select Not Active After Transfer (Ignored if CSAAT = 1) + CSNAAT : Boolean := False; + -- Chip Select Active After Transfer + CSAAT : Boolean := False; + -- Bits Per Transfer + BITS : SPI_CSR_BITS_Field := SAM_SVD.SPI.Val_8_Bit; + -- Serial Clock Bit Rate + SCBR : SPI_SPI_CSR_SCBR_Field := 16#0#; + -- Delay Before SPCK + DLYBS : SPI_SPI_CSR_DLYBS_Field := 16#0#; + -- Delay Between Consecutive Transfers + DLYBCT : SPI_SPI_CSR_DLYBCT_Field := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for SPI_SPI_CSR_Register use record + CPOL at 0 range 0 .. 0; + NCPHA at 0 range 1 .. 1; + CSNAAT at 0 range 2 .. 2; + CSAAT at 0 range 3 .. 3; + BITS at 0 range 4 .. 7; + SCBR at 0 range 8 .. 15; + DLYBS at 0 range 16 .. 23; + DLYBCT at 0 range 24 .. 31; + end record; + + -- Chip Select Register (CS_number = 0) 0 + type SPI_SPI_CSR_Registers is array (0 .. 3) of SPI_SPI_CSR_Register + with Volatile; + + -- Write Protection Key + type SPI_WPMR_WPKEY_Field is + ( + -- Reset value for the field + Spi_Wpmr_Wpkey_Field_Reset, + -- Writing any other value in this field aborts the write operation of + -- the WPEN bit.Always reads as 0. + Passwd) + with Size => 24; + for SPI_WPMR_WPKEY_Field use + (Spi_Wpmr_Wpkey_Field_Reset => 0, + Passwd => 16#535049#); + + -- Write Protection Mode Register + type SPI_SPI_WPMR_Register is record + -- Write Protection Enable + WPEN : Boolean := False; + -- Write Protection Interrupt Enable + WPITEN : Boolean := False; + -- Write Protection Control Register Enable + WPCREN : Boolean := False; + -- unspecified + Reserved_3_7 : HAL.UInt5 := 16#0#; + -- Write Protection Key + WPKEY : SPI_WPMR_WPKEY_Field := Spi_Wpmr_Wpkey_Field_Reset; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for SPI_SPI_WPMR_Register use record + WPEN at 0 range 0 .. 0; + WPITEN at 0 range 1 .. 1; + WPCREN at 0 range 2 .. 2; + Reserved_3_7 at 0 range 3 .. 7; + WPKEY at 0 range 8 .. 31; + end record; + + subtype SPI_SPI_WPSR_WPVSRC_Field is HAL.UInt8; + + -- Write Protection Status Register + type SPI_SPI_WPSR_Register is record + -- Read-only. Write Protection Violation Status + WPVS : Boolean; + -- unspecified + Reserved_1_7 : HAL.UInt7; + -- Read-only. Write Protection Violation Source + WPVSRC : SPI_SPI_WPSR_WPVSRC_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for SPI_SPI_WPSR_Register use record + WPVS at 0 range 0 .. 0; + Reserved_1_7 at 0 range 1 .. 7; + WPVSRC at 0 range 8 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype SPI_SPI_VERSION_VERSION_Field is HAL.UInt12; + subtype SPI_SPI_VERSION_MFN_Field is HAL.UInt3; + + -- Version Register + type SPI_SPI_VERSION_Register is record + -- Read-only. Version of the Hardware Module + VERSION : SPI_SPI_VERSION_VERSION_Field; + -- unspecified + Reserved_12_15 : HAL.UInt4; + -- Read-only. Metal Fix Number + MFN : SPI_SPI_VERSION_MFN_Field; + -- unspecified + Reserved_19_31 : HAL.UInt13; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for SPI_SPI_VERSION_Register use record + VERSION at 0 range 0 .. 11; + Reserved_12_15 at 0 range 12 .. 15; + MFN at 0 range 16 .. 18; + Reserved_19_31 at 0 range 19 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- Serial Peripheral Interface + type SPI_Peripheral is record + -- Control Register + SPI_CR : aliased SPI_SPI_CR_Register; + -- Mode Register + SPI_MR : aliased SPI_SPI_MR_Register; + -- Receive Data Register + SPI_RDR : aliased SPI_SPI_RDR_Register; + -- Transmit Data Register + SPI_TDR : aliased SPI_SPI_TDR_Register; + -- Status Register + SPI_SR : aliased SPI_SPI_SR_Register; + -- Interrupt Enable Register + SPI_IER : aliased SPI_SPI_IER_Register; + -- Interrupt Disable Register + SPI_IDR : aliased SPI_SPI_IDR_Register; + -- Interrupt Mask Register + SPI_IMR : aliased SPI_SPI_IMR_Register; + -- Chip Select Register (CS_number = 0) 0 + SPI_CSR : aliased SPI_SPI_CSR_Registers; + -- Write Protection Mode Register + SPI_WPMR : aliased SPI_SPI_WPMR_Register; + -- Write Protection Status Register + SPI_WPSR : aliased SPI_SPI_WPSR_Register; + -- Version Register + SPI_VERSION : aliased SPI_SPI_VERSION_Register; + end record + with Volatile; + + for SPI_Peripheral use record + SPI_CR at 16#0# range 0 .. 31; + SPI_MR at 16#4# range 0 .. 31; + SPI_RDR at 16#8# range 0 .. 31; + SPI_TDR at 16#C# range 0 .. 31; + SPI_SR at 16#10# range 0 .. 31; + SPI_IER at 16#14# range 0 .. 31; + SPI_IDR at 16#18# range 0 .. 31; + SPI_IMR at 16#1C# range 0 .. 31; + SPI_CSR at 16#30# range 0 .. 127; + SPI_WPMR at 16#E4# range 0 .. 31; + SPI_WPSR at 16#E8# range 0 .. 31; + SPI_VERSION at 16#FC# range 0 .. 31; + end record; + + -- Serial Peripheral Interface + SPI0_Periph : aliased SPI_Peripheral + with Import, Address => System'To_Address (16#40008000#); + + -- Serial Peripheral Interface + SPI1_Periph : aliased SPI_Peripheral + with Import, Address => System'To_Address (16#40058000#); + +end SAM_SVD.SPI; diff --git a/arch/ARM/SAM/svd/atsamv71/sam_svd-ssc.ads b/arch/ARM/SAM/svd/atsamv71/sam_svd-ssc.ads new file mode 100644 index 000000000..4752f3c24 --- /dev/null +++ b/arch/ARM/SAM/svd/atsamv71/sam_svd-ssc.ads @@ -0,0 +1,951 @@ +-- This spec has been automatically generated from ATSAMV71Q21.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package SAM_SVD.SSC is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + -- Control Register + type SSC_SSC_CR_Register is record + -- Write-only. Receive Enable + RXEN : Boolean := False; + -- Write-only. Receive Disable + RXDIS : Boolean := False; + -- unspecified + Reserved_2_7 : HAL.UInt6 := 16#0#; + -- Write-only. Transmit Enable + TXEN : Boolean := False; + -- Write-only. Transmit Disable + TXDIS : Boolean := False; + -- unspecified + Reserved_10_14 : HAL.UInt5 := 16#0#; + -- Write-only. Software Reset + SWRST : Boolean := False; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for SSC_SSC_CR_Register use record + RXEN at 0 range 0 .. 0; + RXDIS at 0 range 1 .. 1; + Reserved_2_7 at 0 range 2 .. 7; + TXEN at 0 range 8 .. 8; + TXDIS at 0 range 9 .. 9; + Reserved_10_14 at 0 range 10 .. 14; + SWRST at 0 range 15 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype SSC_SSC_CMR_DIV_Field is HAL.UInt12; + + -- Clock Mode Register + type SSC_SSC_CMR_Register is record + -- Clock Divider + DIV : SSC_SSC_CMR_DIV_Field := 16#0#; + -- unspecified + Reserved_12_31 : HAL.UInt20 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for SSC_SSC_CMR_Register use record + DIV at 0 range 0 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + -- Receive Clock Selection + type SSC_RCMR_CKS_Field is + ( + -- Divided Clock + Mck, + -- TK Clock signal + Tk, + -- RK pin + Rk) + with Size => 2; + for SSC_RCMR_CKS_Field use + (Mck => 0, + Tk => 1, + Rk => 2); + + -- Receive Clock Output Mode Selection + type SSC_RCMR_CKO_Field is + ( + -- None, RK pin is an input + None, + -- Continuous Receive Clock, RK pin is an output + Continuous, + -- Receive Clock only during data transfers, RK pin is an output + Transfer) + with Size => 3; + for SSC_RCMR_CKO_Field use + (None => 0, + Continuous => 1, + Transfer => 2); + + -- Receive Clock Gating Selection + type SSC_RCMR_CKG_Field is + ( + -- None + Continuous, + -- Receive Clock enabled only if RF Low + En_Rf_Low, + -- Receive Clock enabled only if RF High + En_Rf_High) + with Size => 2; + for SSC_RCMR_CKG_Field use + (Continuous => 0, + En_Rf_Low => 1, + En_Rf_High => 2); + + -- Receive Start Selection + type SSC_RCMR_START_Field is + ( + -- Continuous, as soon as the receiver is enabled, and immediately after + -- the end of transfer of the previous data. + Continuous, + -- Transmit start + Transmit, + -- Detection of a low level on RF signal + Rf_Low, + -- Detection of a high level on RF signal + Rf_High, + -- Detection of a falling edge on RF signal + Rf_Falling, + -- Detection of a rising edge on RF signal + Rf_Rising, + -- Detection of any level change on RF signal + Rf_Level, + -- Detection of any edge on RF signal + Rf_Edge, + -- Compare 0 + Cmp_0) + with Size => 4; + for SSC_RCMR_START_Field use + (Continuous => 0, + Transmit => 1, + Rf_Low => 2, + Rf_High => 3, + Rf_Falling => 4, + Rf_Rising => 5, + Rf_Level => 6, + Rf_Edge => 7, + Cmp_0 => 8); + + subtype SSC_SSC_RCMR_STTDLY_Field is HAL.UInt8; + subtype SSC_SSC_RCMR_PERIOD_Field is HAL.UInt8; + + -- Receive Clock Mode Register + type SSC_SSC_RCMR_Register is record + -- Receive Clock Selection + CKS : SSC_RCMR_CKS_Field := SAM_SVD.SSC.Mck; + -- Receive Clock Output Mode Selection + CKO : SSC_RCMR_CKO_Field := SAM_SVD.SSC.None; + -- Receive Clock Inversion + CKI : Boolean := False; + -- Receive Clock Gating Selection + CKG : SSC_RCMR_CKG_Field := SAM_SVD.SSC.Continuous; + -- Receive Start Selection + START : SSC_RCMR_START_Field := SAM_SVD.SSC.Continuous; + -- Receive Stop Selection + STOP : Boolean := False; + -- unspecified + Reserved_13_15 : HAL.UInt3 := 16#0#; + -- Receive Start Delay + STTDLY : SSC_SSC_RCMR_STTDLY_Field := 16#0#; + -- Receive Period Divider Selection + PERIOD : SSC_SSC_RCMR_PERIOD_Field := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for SSC_SSC_RCMR_Register use record + CKS at 0 range 0 .. 1; + CKO at 0 range 2 .. 4; + CKI at 0 range 5 .. 5; + CKG at 0 range 6 .. 7; + START at 0 range 8 .. 11; + STOP at 0 range 12 .. 12; + Reserved_13_15 at 0 range 13 .. 15; + STTDLY at 0 range 16 .. 23; + PERIOD at 0 range 24 .. 31; + end record; + + subtype SSC_SSC_RFMR_DATLEN_Field is HAL.UInt5; + subtype SSC_SSC_RFMR_DATNB_Field is HAL.UInt4; + subtype SSC_SSC_RFMR_FSLEN_Field is HAL.UInt4; + + -- Receive Frame Sync Output Selection + type SSC_RFMR_FSOS_Field is + ( + -- None, RF pin is an input + None, + -- Negative Pulse, RF pin is an output + Negative, + -- Positive Pulse, RF pin is an output + Positive, + -- Driven Low during data transfer, RF pin is an output + Low, + -- Driven High during data transfer, RF pin is an output + High, + -- Toggling at each start of data transfer, RF pin is an output + Toggling) + with Size => 3; + for SSC_RFMR_FSOS_Field use + (None => 0, + Negative => 1, + Positive => 2, + Low => 3, + High => 4, + Toggling => 5); + + -- Frame Sync Edge Detection + type SSC_RFMR_FSEDGE_Field is + ( + -- Positive Edge Detection + Positive, + -- Negative Edge Detection + Negative) + with Size => 1; + for SSC_RFMR_FSEDGE_Field use + (Positive => 0, + Negative => 1); + + subtype SSC_SSC_RFMR_FSLEN_EXT_Field is HAL.UInt4; + + -- Receive Frame Mode Register + type SSC_SSC_RFMR_Register is record + -- Data Length + DATLEN : SSC_SSC_RFMR_DATLEN_Field := 16#0#; + -- Loop Mode + LOOP_k : Boolean := False; + -- unspecified + Reserved_6_6 : HAL.Bit := 16#0#; + -- Most Significant Bit First + MSBF : Boolean := False; + -- Data Number per Frame + DATNB : SSC_SSC_RFMR_DATNB_Field := 16#0#; + -- unspecified + Reserved_12_15 : HAL.UInt4 := 16#0#; + -- Receive Frame Sync Length + FSLEN : SSC_SSC_RFMR_FSLEN_Field := 16#0#; + -- Receive Frame Sync Output Selection + FSOS : SSC_RFMR_FSOS_Field := SAM_SVD.SSC.None; + -- unspecified + Reserved_23_23 : HAL.Bit := 16#0#; + -- Frame Sync Edge Detection + FSEDGE : SSC_RFMR_FSEDGE_Field := SAM_SVD.SSC.Positive; + -- unspecified + Reserved_25_27 : HAL.UInt3 := 16#0#; + -- FSLEN Field Extension + FSLEN_EXT : SSC_SSC_RFMR_FSLEN_EXT_Field := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for SSC_SSC_RFMR_Register use record + DATLEN at 0 range 0 .. 4; + LOOP_k at 0 range 5 .. 5; + Reserved_6_6 at 0 range 6 .. 6; + MSBF at 0 range 7 .. 7; + DATNB at 0 range 8 .. 11; + Reserved_12_15 at 0 range 12 .. 15; + FSLEN at 0 range 16 .. 19; + FSOS at 0 range 20 .. 22; + Reserved_23_23 at 0 range 23 .. 23; + FSEDGE at 0 range 24 .. 24; + Reserved_25_27 at 0 range 25 .. 27; + FSLEN_EXT at 0 range 28 .. 31; + end record; + + -- Transmit Clock Selection + type SSC_TCMR_CKS_Field is + ( + -- Divided Clock + Mck, + -- RK Clock signal + Rk, + -- TK pin + Tk) + with Size => 2; + for SSC_TCMR_CKS_Field use + (Mck => 0, + Rk => 1, + Tk => 2); + + -- Transmit Clock Output Mode Selection + type SSC_TCMR_CKO_Field is + ( + -- None, TK pin is an input + None, + -- Continuous Transmit Clock, TK pin is an output + Continuous, + -- Transmit Clock only during data transfers, TK pin is an output + Transfer) + with Size => 3; + for SSC_TCMR_CKO_Field use + (None => 0, + Continuous => 1, + Transfer => 2); + + -- Transmit Clock Gating Selection + type SSC_TCMR_CKG_Field is + ( + -- None + Continuous, + -- Transmit Clock enabled only if TF Low + En_Tf_Low, + -- Transmit Clock enabled only if TF High + En_Tf_High) + with Size => 2; + for SSC_TCMR_CKG_Field use + (Continuous => 0, + En_Tf_Low => 1, + En_Tf_High => 2); + + -- Transmit Start Selection + type SSC_TCMR_START_Field is + ( + -- Continuous, as soon as a word is written in the SSC_THR (if Transmit + -- is enabled), and immediately after the end of transfer of the + -- previous data + Continuous, + -- Receive start + Receive, + -- Detection of a low level on TF signal + Tf_Low, + -- Detection of a high level on TF signal + Tf_High, + -- Detection of a falling edge on TF signal + Tf_Falling, + -- Detection of a rising edge on TF signal + Tf_Rising, + -- Detection of any level change on TF signal + Tf_Level, + -- Detection of any edge on TF signal + Tf_Edge) + with Size => 4; + for SSC_TCMR_START_Field use + (Continuous => 0, + Receive => 1, + Tf_Low => 2, + Tf_High => 3, + Tf_Falling => 4, + Tf_Rising => 5, + Tf_Level => 6, + Tf_Edge => 7); + + subtype SSC_SSC_TCMR_STTDLY_Field is HAL.UInt8; + subtype SSC_SSC_TCMR_PERIOD_Field is HAL.UInt8; + + -- Transmit Clock Mode Register + type SSC_SSC_TCMR_Register is record + -- Transmit Clock Selection + CKS : SSC_TCMR_CKS_Field := SAM_SVD.SSC.Mck; + -- Transmit Clock Output Mode Selection + CKO : SSC_TCMR_CKO_Field := SAM_SVD.SSC.None; + -- Transmit Clock Inversion + CKI : Boolean := False; + -- Transmit Clock Gating Selection + CKG : SSC_TCMR_CKG_Field := SAM_SVD.SSC.Continuous; + -- Transmit Start Selection + START : SSC_TCMR_START_Field := SAM_SVD.SSC.Continuous; + -- unspecified + Reserved_12_15 : HAL.UInt4 := 16#0#; + -- Transmit Start Delay + STTDLY : SSC_SSC_TCMR_STTDLY_Field := 16#0#; + -- Transmit Period Divider Selection + PERIOD : SSC_SSC_TCMR_PERIOD_Field := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for SSC_SSC_TCMR_Register use record + CKS at 0 range 0 .. 1; + CKO at 0 range 2 .. 4; + CKI at 0 range 5 .. 5; + CKG at 0 range 6 .. 7; + START at 0 range 8 .. 11; + Reserved_12_15 at 0 range 12 .. 15; + STTDLY at 0 range 16 .. 23; + PERIOD at 0 range 24 .. 31; + end record; + + subtype SSC_SSC_TFMR_DATLEN_Field is HAL.UInt5; + subtype SSC_SSC_TFMR_DATNB_Field is HAL.UInt4; + subtype SSC_SSC_TFMR_FSLEN_Field is HAL.UInt4; + + -- Transmit Frame Sync Output Selection + type SSC_TFMR_FSOS_Field is + ( + -- None, TF pin is an input + None, + -- Negative Pulse, TF pin is an output + Negative, + -- Positive Pulse, TF pin is an output + Positive, + -- Driven Low during data transfer + Low, + -- Driven High during data transfer + High, + -- Toggling at each start of data transfer + Toggling) + with Size => 3; + for SSC_TFMR_FSOS_Field use + (None => 0, + Negative => 1, + Positive => 2, + Low => 3, + High => 4, + Toggling => 5); + + -- Frame Sync Edge Detection + type SSC_TFMR_FSEDGE_Field is + ( + -- Positive Edge Detection + Positive, + -- Negative Edge Detection + Negative) + with Size => 1; + for SSC_TFMR_FSEDGE_Field use + (Positive => 0, + Negative => 1); + + subtype SSC_SSC_TFMR_FSLEN_EXT_Field is HAL.UInt4; + + -- Transmit Frame Mode Register + type SSC_SSC_TFMR_Register is record + -- Data Length + DATLEN : SSC_SSC_TFMR_DATLEN_Field := 16#0#; + -- Data Default Value + DATDEF : Boolean := False; + -- unspecified + Reserved_6_6 : HAL.Bit := 16#0#; + -- Most Significant Bit First + MSBF : Boolean := False; + -- Data Number per Frame + DATNB : SSC_SSC_TFMR_DATNB_Field := 16#0#; + -- unspecified + Reserved_12_15 : HAL.UInt4 := 16#0#; + -- Transmit Frame Sync Length + FSLEN : SSC_SSC_TFMR_FSLEN_Field := 16#0#; + -- Transmit Frame Sync Output Selection + FSOS : SSC_TFMR_FSOS_Field := SAM_SVD.SSC.None; + -- Frame Sync Data Enable + FSDEN : Boolean := False; + -- Frame Sync Edge Detection + FSEDGE : SSC_TFMR_FSEDGE_Field := SAM_SVD.SSC.Positive; + -- unspecified + Reserved_25_27 : HAL.UInt3 := 16#0#; + -- FSLEN Field Extension + FSLEN_EXT : SSC_SSC_TFMR_FSLEN_EXT_Field := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for SSC_SSC_TFMR_Register use record + DATLEN at 0 range 0 .. 4; + DATDEF at 0 range 5 .. 5; + Reserved_6_6 at 0 range 6 .. 6; + MSBF at 0 range 7 .. 7; + DATNB at 0 range 8 .. 11; + Reserved_12_15 at 0 range 12 .. 15; + FSLEN at 0 range 16 .. 19; + FSOS at 0 range 20 .. 22; + FSDEN at 0 range 23 .. 23; + FSEDGE at 0 range 24 .. 24; + Reserved_25_27 at 0 range 25 .. 27; + FSLEN_EXT at 0 range 28 .. 31; + end record; + + subtype SSC_SSC_RSHR_RSDAT_Field is HAL.UInt16; + + -- Receive Sync. Holding Register + type SSC_SSC_RSHR_Register is record + -- Read-only. Receive Synchronization Data + RSDAT : SSC_SSC_RSHR_RSDAT_Field; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for SSC_SSC_RSHR_Register use record + RSDAT at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype SSC_SSC_TSHR_TSDAT_Field is HAL.UInt16; + + -- Transmit Sync. Holding Register + type SSC_SSC_TSHR_Register is record + -- Transmit Synchronization Data + TSDAT : SSC_SSC_TSHR_TSDAT_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for SSC_SSC_TSHR_Register use record + TSDAT at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype SSC_SSC_RC0R_CP0_Field is HAL.UInt16; + + -- Receive Compare 0 Register + type SSC_SSC_RC0R_Register is record + -- Receive Compare Data 0 + CP0 : SSC_SSC_RC0R_CP0_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for SSC_SSC_RC0R_Register use record + CP0 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype SSC_SSC_RC1R_CP1_Field is HAL.UInt16; + + -- Receive Compare 1 Register + type SSC_SSC_RC1R_Register is record + -- Receive Compare Data 1 + CP1 : SSC_SSC_RC1R_CP1_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for SSC_SSC_RC1R_Register use record + CP1 at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + -- SSC_SSC_SR_CP array + type SSC_SSC_SR_CP_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for SSC_SSC_SR_CP + type SSC_SSC_SR_CP_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CP as a value + Val : HAL.UInt2; + when True => + -- CP as an array + Arr : SSC_SSC_SR_CP_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for SSC_SSC_SR_CP_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- Status Register + type SSC_SSC_SR_Register is record + -- Read-only. Transmit Ready + TXRDY : Boolean; + -- Read-only. Transmit Empty + TXEMPTY : Boolean; + -- unspecified + Reserved_2_3 : HAL.UInt2; + -- Read-only. Receive Ready + RXRDY : Boolean; + -- Read-only. Receive Overrun + OVRUN : Boolean; + -- unspecified + Reserved_6_7 : HAL.UInt2; + -- Read-only. Compare 0 + CP : SSC_SSC_SR_CP_Field; + -- Read-only. Transmit Sync + TXSYN : Boolean; + -- Read-only. Receive Sync + RXSYN : Boolean; + -- unspecified + Reserved_12_15 : HAL.UInt4; + -- Read-only. Transmit Enable + TXEN : Boolean; + -- Read-only. Receive Enable + RXEN : Boolean; + -- unspecified + Reserved_18_31 : HAL.UInt14; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for SSC_SSC_SR_Register use record + TXRDY at 0 range 0 .. 0; + TXEMPTY at 0 range 1 .. 1; + Reserved_2_3 at 0 range 2 .. 3; + RXRDY at 0 range 4 .. 4; + OVRUN at 0 range 5 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + CP at 0 range 8 .. 9; + TXSYN at 0 range 10 .. 10; + RXSYN at 0 range 11 .. 11; + Reserved_12_15 at 0 range 12 .. 15; + TXEN at 0 range 16 .. 16; + RXEN at 0 range 17 .. 17; + Reserved_18_31 at 0 range 18 .. 31; + end record; + + -- SSC_SSC_IER_CP array + type SSC_SSC_IER_CP_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for SSC_SSC_IER_CP + type SSC_SSC_IER_CP_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CP as a value + Val : HAL.UInt2; + when True => + -- CP as an array + Arr : SSC_SSC_IER_CP_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for SSC_SSC_IER_CP_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- Interrupt Enable Register + type SSC_SSC_IER_Register is record + -- Write-only. Transmit Ready Interrupt Enable + TXRDY : Boolean := False; + -- Write-only. Transmit Empty Interrupt Enable + TXEMPTY : Boolean := False; + -- unspecified + Reserved_2_3 : HAL.UInt2 := 16#0#; + -- Write-only. Receive Ready Interrupt Enable + RXRDY : Boolean := False; + -- Write-only. Receive Overrun Interrupt Enable + OVRUN : Boolean := False; + -- unspecified + Reserved_6_7 : HAL.UInt2 := 16#0#; + -- Write-only. Compare 0 Interrupt Enable + CP : SSC_SSC_IER_CP_Field := + (As_Array => False, Val => 16#0#); + -- Write-only. Tx Sync Interrupt Enable + TXSYN : Boolean := False; + -- Write-only. Rx Sync Interrupt Enable + RXSYN : Boolean := False; + -- unspecified + Reserved_12_31 : HAL.UInt20 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for SSC_SSC_IER_Register use record + TXRDY at 0 range 0 .. 0; + TXEMPTY at 0 range 1 .. 1; + Reserved_2_3 at 0 range 2 .. 3; + RXRDY at 0 range 4 .. 4; + OVRUN at 0 range 5 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + CP at 0 range 8 .. 9; + TXSYN at 0 range 10 .. 10; + RXSYN at 0 range 11 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + -- SSC_SSC_IDR_CP array + type SSC_SSC_IDR_CP_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for SSC_SSC_IDR_CP + type SSC_SSC_IDR_CP_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CP as a value + Val : HAL.UInt2; + when True => + -- CP as an array + Arr : SSC_SSC_IDR_CP_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for SSC_SSC_IDR_CP_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- Interrupt Disable Register + type SSC_SSC_IDR_Register is record + -- Write-only. Transmit Ready Interrupt Disable + TXRDY : Boolean := False; + -- Write-only. Transmit Empty Interrupt Disable + TXEMPTY : Boolean := False; + -- unspecified + Reserved_2_3 : HAL.UInt2 := 16#0#; + -- Write-only. Receive Ready Interrupt Disable + RXRDY : Boolean := False; + -- Write-only. Receive Overrun Interrupt Disable + OVRUN : Boolean := False; + -- unspecified + Reserved_6_7 : HAL.UInt2 := 16#0#; + -- Write-only. Compare 0 Interrupt Disable + CP : SSC_SSC_IDR_CP_Field := + (As_Array => False, Val => 16#0#); + -- Write-only. Tx Sync Interrupt Enable + TXSYN : Boolean := False; + -- Write-only. Rx Sync Interrupt Enable + RXSYN : Boolean := False; + -- unspecified + Reserved_12_31 : HAL.UInt20 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for SSC_SSC_IDR_Register use record + TXRDY at 0 range 0 .. 0; + TXEMPTY at 0 range 1 .. 1; + Reserved_2_3 at 0 range 2 .. 3; + RXRDY at 0 range 4 .. 4; + OVRUN at 0 range 5 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + CP at 0 range 8 .. 9; + TXSYN at 0 range 10 .. 10; + RXSYN at 0 range 11 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + -- SSC_SSC_IMR_CP array + type SSC_SSC_IMR_CP_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for SSC_SSC_IMR_CP + type SSC_SSC_IMR_CP_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CP as a value + Val : HAL.UInt2; + when True => + -- CP as an array + Arr : SSC_SSC_IMR_CP_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for SSC_SSC_IMR_CP_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- Interrupt Mask Register + type SSC_SSC_IMR_Register is record + -- Read-only. Transmit Ready Interrupt Mask + TXRDY : Boolean; + -- Read-only. Transmit Empty Interrupt Mask + TXEMPTY : Boolean; + -- unspecified + Reserved_2_3 : HAL.UInt2; + -- Read-only. Receive Ready Interrupt Mask + RXRDY : Boolean; + -- Read-only. Receive Overrun Interrupt Mask + OVRUN : Boolean; + -- unspecified + Reserved_6_7 : HAL.UInt2; + -- Read-only. Compare 0 Interrupt Mask + CP : SSC_SSC_IMR_CP_Field; + -- Read-only. Tx Sync Interrupt Mask + TXSYN : Boolean; + -- Read-only. Rx Sync Interrupt Mask + RXSYN : Boolean; + -- unspecified + Reserved_12_31 : HAL.UInt20; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for SSC_SSC_IMR_Register use record + TXRDY at 0 range 0 .. 0; + TXEMPTY at 0 range 1 .. 1; + Reserved_2_3 at 0 range 2 .. 3; + RXRDY at 0 range 4 .. 4; + OVRUN at 0 range 5 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + CP at 0 range 8 .. 9; + TXSYN at 0 range 10 .. 10; + RXSYN at 0 range 11 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + -- Write Protection Key + type SSC_WPMR_WPKEY_Field is + ( + -- Reset value for the field + Ssc_Wpmr_Wpkey_Field_Reset, + -- Writing any other value in this field aborts the write operation of + -- the WPEN bit.Always reads as 0. + Passwd) + with Size => 24; + for SSC_WPMR_WPKEY_Field use + (Ssc_Wpmr_Wpkey_Field_Reset => 0, + Passwd => 5460803); + + -- Write Protection Mode Register + type SSC_SSC_WPMR_Register is record + -- Write Protection Enable + WPEN : Boolean := False; + -- unspecified + Reserved_1_7 : HAL.UInt7 := 16#0#; + -- Write Protection Key + WPKEY : SSC_WPMR_WPKEY_Field := Ssc_Wpmr_Wpkey_Field_Reset; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for SSC_SSC_WPMR_Register use record + WPEN at 0 range 0 .. 0; + Reserved_1_7 at 0 range 1 .. 7; + WPKEY at 0 range 8 .. 31; + end record; + + subtype SSC_SSC_WPSR_WPVSRC_Field is HAL.UInt16; + + -- Write Protection Status Register + type SSC_SSC_WPSR_Register is record + -- Read-only. Write Protection Violation Status + WPVS : Boolean; + -- unspecified + Reserved_1_7 : HAL.UInt7; + -- Read-only. Write Protect Violation Source + WPVSRC : SSC_SSC_WPSR_WPVSRC_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for SSC_SSC_WPSR_Register use record + WPVS at 0 range 0 .. 0; + Reserved_1_7 at 0 range 1 .. 7; + WPVSRC at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype SSC_SSC_VERSION_VERSION_Field is HAL.UInt16; + subtype SSC_SSC_VERSION_MFN_Field is HAL.UInt3; + + -- Version Register + type SSC_SSC_VERSION_Register is record + -- Read-only. Version of the Hardware Module + VERSION : SSC_SSC_VERSION_VERSION_Field; + -- Read-only. Metal Fix Number + MFN : SSC_SSC_VERSION_MFN_Field; + -- unspecified + Reserved_19_31 : HAL.UInt13; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for SSC_SSC_VERSION_Register use record + VERSION at 0 range 0 .. 15; + MFN at 0 range 16 .. 18; + Reserved_19_31 at 0 range 19 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- Synchronous Serial Controller + type SSC_Peripheral is record + -- Control Register + SSC_CR : aliased SSC_SSC_CR_Register; + -- Clock Mode Register + SSC_CMR : aliased SSC_SSC_CMR_Register; + -- Receive Clock Mode Register + SSC_RCMR : aliased SSC_SSC_RCMR_Register; + -- Receive Frame Mode Register + SSC_RFMR : aliased SSC_SSC_RFMR_Register; + -- Transmit Clock Mode Register + SSC_TCMR : aliased SSC_SSC_TCMR_Register; + -- Transmit Frame Mode Register + SSC_TFMR : aliased SSC_SSC_TFMR_Register; + -- Receive Holding Register + SSC_RHR : aliased HAL.UInt32; + -- Transmit Holding Register + SSC_THR : aliased HAL.UInt32; + -- Receive Sync. Holding Register + SSC_RSHR : aliased SSC_SSC_RSHR_Register; + -- Transmit Sync. Holding Register + SSC_TSHR : aliased SSC_SSC_TSHR_Register; + -- Receive Compare 0 Register + SSC_RC0R : aliased SSC_SSC_RC0R_Register; + -- Receive Compare 1 Register + SSC_RC1R : aliased SSC_SSC_RC1R_Register; + -- Status Register + SSC_SR : aliased SSC_SSC_SR_Register; + -- Interrupt Enable Register + SSC_IER : aliased SSC_SSC_IER_Register; + -- Interrupt Disable Register + SSC_IDR : aliased SSC_SSC_IDR_Register; + -- Interrupt Mask Register + SSC_IMR : aliased SSC_SSC_IMR_Register; + -- Write Protection Mode Register + SSC_WPMR : aliased SSC_SSC_WPMR_Register; + -- Write Protection Status Register + SSC_WPSR : aliased SSC_SSC_WPSR_Register; + -- Version Register + SSC_VERSION : aliased SSC_SSC_VERSION_Register; + end record + with Volatile; + + for SSC_Peripheral use record + SSC_CR at 16#0# range 0 .. 31; + SSC_CMR at 16#4# range 0 .. 31; + SSC_RCMR at 16#10# range 0 .. 31; + SSC_RFMR at 16#14# range 0 .. 31; + SSC_TCMR at 16#18# range 0 .. 31; + SSC_TFMR at 16#1C# range 0 .. 31; + SSC_RHR at 16#20# range 0 .. 31; + SSC_THR at 16#24# range 0 .. 31; + SSC_RSHR at 16#30# range 0 .. 31; + SSC_TSHR at 16#34# range 0 .. 31; + SSC_RC0R at 16#38# range 0 .. 31; + SSC_RC1R at 16#3C# range 0 .. 31; + SSC_SR at 16#40# range 0 .. 31; + SSC_IER at 16#44# range 0 .. 31; + SSC_IDR at 16#48# range 0 .. 31; + SSC_IMR at 16#4C# range 0 .. 31; + SSC_WPMR at 16#E4# range 0 .. 31; + SSC_WPSR at 16#E8# range 0 .. 31; + SSC_VERSION at 16#FC# range 0 .. 31; + end record; + + -- Synchronous Serial Controller + SSC_Periph : aliased SSC_Peripheral + with Import, Address => System'To_Address (16#40004000#); + +end SAM_SVD.SSC; diff --git a/arch/ARM/SAM/svd/atsamv71/sam_svd-supc.ads b/arch/ARM/SAM/svd/atsamv71/sam_svd-supc.ads new file mode 100644 index 000000000..99131a24e --- /dev/null +++ b/arch/ARM/SAM/svd/atsamv71/sam_svd-supc.ads @@ -0,0 +1,821 @@ +-- This spec has been automatically generated from ATSAMV71Q21.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package SAM_SVD.SUPC is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + -- Voltage Regulator Off + type SUPC_CR_VROFF_Field is + ( + -- No effect. + No_Effect, + -- If KEY is correct, VROFF asserts the vddcore_nreset and stops the + -- voltage regulator. + Stop_Vreg) + with Size => 1; + for SUPC_CR_VROFF_Field use + (No_Effect => 0, + Stop_Vreg => 1); + + -- Crystal Oscillator Select + type SUPC_CR_XTALSEL_Field is + ( + -- No effect. + No_Effect, + -- If KEY is correct, XTALSEL switches the slow clock on the crystal + -- oscillator output. + Crystal_Sel) + with Size => 1; + for SUPC_CR_XTALSEL_Field use + (No_Effect => 0, + Crystal_Sel => 1); + + -- Password + type SUPC_CR_KEY_Field is + ( + -- Reset value for the field + Supc_Cr_Key_Field_Reset, + -- Writing any other value in this field aborts the write operation. + Passwd) + with Size => 8; + for SUPC_CR_KEY_Field use + (Supc_Cr_Key_Field_Reset => 0, + Passwd => 165); + + -- Supply Controller Control Register + type SUPC_SUPC_CR_Register is record + -- unspecified + Reserved_0_1 : HAL.UInt2 := 16#0#; + -- Write-only. Voltage Regulator Off + VROFF : SUPC_CR_VROFF_Field := SAM_SVD.SUPC.No_Effect; + -- Write-only. Crystal Oscillator Select + XTALSEL : SUPC_CR_XTALSEL_Field := SAM_SVD.SUPC.No_Effect; + -- unspecified + Reserved_4_23 : HAL.UInt20 := 16#0#; + -- Write-only. Password + KEY : SUPC_CR_KEY_Field := Supc_Cr_Key_Field_Reset; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for SUPC_SUPC_CR_Register use record + Reserved_0_1 at 0 range 0 .. 1; + VROFF at 0 range 2 .. 2; + XTALSEL at 0 range 3 .. 3; + Reserved_4_23 at 0 range 4 .. 23; + KEY at 0 range 24 .. 31; + end record; + + subtype SUPC_SUPC_SMMR_SMTH_Field is HAL.UInt4; + + -- Supply Monitor Sampling Period + type SUPC_SMMR_SMSMPL_Field is + ( + -- Supply Monitor disabled + Smd, + -- Continuous Supply Monitor + Csm, + -- Supply Monitor enabled one SLCK period every 32 SLCK periods + Val_32Slck, + -- Supply Monitor enabled one SLCK period every 256 SLCK periods + Val_256Slck, + -- Supply Monitor enabled one SLCK period every 2,048 SLCK periods + Val_2048Slck) + with Size => 3; + for SUPC_SMMR_SMSMPL_Field use + (Smd => 0, + Csm => 1, + Val_32Slck => 2, + Val_256Slck => 3, + Val_2048Slck => 4); + + -- Supply Monitor Reset Enable + type SUPC_SMMR_SMRSTEN_Field is + ( + -- The core reset signal vddcore_nreset is not affected when a supply + -- monitor detection occurs. + Not_Enable, + -- The core reset signal, vddcore_nreset is asserted when a supply + -- monitor detection occurs. + Enable) + with Size => 1; + for SUPC_SMMR_SMRSTEN_Field use + (Not_Enable => 0, + Enable => 1); + + -- Supply Monitor Interrupt Enable + type SUPC_SMMR_SMIEN_Field is + ( + -- The SUPC interrupt signal is not affected when a supply monitor + -- detection occurs. + Not_Enable, + -- The SUPC interrupt signal is asserted when a supply monitor detection + -- occurs. + Enable) + with Size => 1; + for SUPC_SMMR_SMIEN_Field use + (Not_Enable => 0, + Enable => 1); + + -- Supply Controller Supply Monitor Mode Register + type SUPC_SUPC_SMMR_Register is record + -- Supply Monitor Threshold + SMTH : SUPC_SUPC_SMMR_SMTH_Field := 16#0#; + -- unspecified + Reserved_4_7 : HAL.UInt4 := 16#0#; + -- Supply Monitor Sampling Period + SMSMPL : SUPC_SMMR_SMSMPL_Field := SAM_SVD.SUPC.Smd; + -- unspecified + Reserved_11_11 : HAL.Bit := 16#0#; + -- Supply Monitor Reset Enable + SMRSTEN : SUPC_SMMR_SMRSTEN_Field := SAM_SVD.SUPC.Not_Enable; + -- Supply Monitor Interrupt Enable + SMIEN : SUPC_SMMR_SMIEN_Field := SAM_SVD.SUPC.Not_Enable; + -- unspecified + Reserved_14_31 : HAL.UInt18 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for SUPC_SUPC_SMMR_Register use record + SMTH at 0 range 0 .. 3; + Reserved_4_7 at 0 range 4 .. 7; + SMSMPL at 0 range 8 .. 10; + Reserved_11_11 at 0 range 11 .. 11; + SMRSTEN at 0 range 12 .. 12; + SMIEN at 0 range 13 .. 13; + Reserved_14_31 at 0 range 14 .. 31; + end record; + + -- Brownout Detector Reset Enable + type SUPC_MR_BODRSTEN_Field is + ( + -- The core reset signal vddcore_nreset is not affected when a brownout + -- detection occurs. + Not_Enable, + -- The core reset signal, vddcore_nreset is asserted when a brownout + -- detection occurs. + Enable) + with Size => 1; + for SUPC_MR_BODRSTEN_Field use + (Not_Enable => 0, + Enable => 1); + + -- Brownout Detector Disable + type SUPC_MR_BODDIS_Field is + ( + -- The core brownout detector is enabled. + Enable, + -- The core brownout detector is disabled. + Disable) + with Size => 1; + for SUPC_MR_BODDIS_Field use + (Enable => 0, + Disable => 1); + + -- Voltage Regulator Enable + type SUPC_MR_ONREG_Field is + ( + -- Internal voltage regulator is not used (external power supply is + -- used). + Onreg_Unused, + -- Internal voltage regulator is used. + Onreg_Used) + with Size => 1; + for SUPC_MR_ONREG_Field use + (Onreg_Unused => 0, + Onreg_Used => 1); + + -- Oscillator Bypass + type SUPC_MR_OSCBYPASS_Field is + ( + -- No effect. Clock selection depends on the value of XTALSEL (SUPC_CR). + No_Effect, + -- The 32 kHz crystal oscillator is bypassed if XTALSEL (SUPC_CR) is + -- set. OSCBYPASS must be set prior to setting XTALSEL. + Bypass) + with Size => 1; + for SUPC_MR_OSCBYPASS_Field use + (No_Effect => 0, + Bypass => 1); + + -- Password Key + type SUPC_MR_KEY_Field is + ( + -- Reset value for the field + Supc_Mr_Key_Field_Reset, + -- Writing any other value in this field aborts the write operation. + Passwd) + with Size => 8; + for SUPC_MR_KEY_Field use + (Supc_Mr_Key_Field_Reset => 0, + Passwd => 165); + + -- Supply Controller Mode Register + type SUPC_SUPC_MR_Register is record + -- unspecified + Reserved_0_11 : HAL.UInt12 := 16#0#; + -- Brownout Detector Reset Enable + BODRSTEN : SUPC_MR_BODRSTEN_Field := SAM_SVD.SUPC.Not_Enable; + -- Brownout Detector Disable + BODDIS : SUPC_MR_BODDIS_Field := SAM_SVD.SUPC.Enable; + -- Voltage Regulator Enable + ONREG : SUPC_MR_ONREG_Field := SAM_SVD.SUPC.Onreg_Unused; + -- unspecified + Reserved_15_16 : HAL.UInt2 := 16#0#; + -- SRAM On In Backup Mode + BKUPRETON : Boolean := False; + -- unspecified + Reserved_18_19 : HAL.UInt2 := 16#0#; + -- Oscillator Bypass + OSCBYPASS : SUPC_MR_OSCBYPASS_Field := SAM_SVD.SUPC.No_Effect; + -- unspecified + Reserved_21_23 : HAL.UInt3 := 16#0#; + -- Password Key + KEY : SUPC_MR_KEY_Field := Supc_Mr_Key_Field_Reset; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for SUPC_SUPC_MR_Register use record + Reserved_0_11 at 0 range 0 .. 11; + BODRSTEN at 0 range 12 .. 12; + BODDIS at 0 range 13 .. 13; + ONREG at 0 range 14 .. 14; + Reserved_15_16 at 0 range 15 .. 16; + BKUPRETON at 0 range 17 .. 17; + Reserved_18_19 at 0 range 18 .. 19; + OSCBYPASS at 0 range 20 .. 20; + Reserved_21_23 at 0 range 21 .. 23; + KEY at 0 range 24 .. 31; + end record; + + -- Supply Monitor Wakeup Enable + type SUPC_WUMR_SMEN_Field is + ( + -- The supply monitor detection has no wakeup effect. + Not_Enable, + -- The supply monitor detection forces the wakeup of the core power + -- supply. + Enable) + with Size => 1; + for SUPC_WUMR_SMEN_Field use + (Not_Enable => 0, + Enable => 1); + + -- Real-time Timer Wakeup Enable + type SUPC_WUMR_RTTEN_Field is + ( + -- The RTT alarm signal has no wakeup effect. + Not_Enable, + -- The RTT alarm signal forces the wakeup of the core power supply. + Enable) + with Size => 1; + for SUPC_WUMR_RTTEN_Field use + (Not_Enable => 0, + Enable => 1); + + -- Real-time Clock Wakeup Enable + type SUPC_WUMR_RTCEN_Field is + ( + -- The RTC alarm signal has no wakeup effect. + Not_Enable, + -- The RTC alarm signal forces the wakeup of the core power supply. + Enable) + with Size => 1; + for SUPC_WUMR_RTCEN_Field use + (Not_Enable => 0, + Enable => 1); + + -- Low-power Debouncer Enable WKUP0 + type SUPC_WUMR_LPDBCEN0_Field is + ( + -- The WKUP0 input pin is not connected to the low-power debouncer. + Not_Enable, + -- The WKUP0 input pin is connected to the low-power debouncer and + -- forces a system wakeup. + Enable) + with Size => 1; + for SUPC_WUMR_LPDBCEN0_Field use + (Not_Enable => 0, + Enable => 1); + + -- Low-power Debouncer Enable WKUP1 + type SUPC_WUMR_LPDBCEN1_Field is + ( + -- The WKUP1 input pin is not connected to the low-power debouncer. + Not_Enable, + -- The WKUP1 input pin is connected to the low-power debouncer and + -- forces a system wakeup. + Enable) + with Size => 1; + for SUPC_WUMR_LPDBCEN1_Field use + (Not_Enable => 0, + Enable => 1); + + -- Low-power Debouncer Clear + type SUPC_WUMR_LPDBCCLR_Field is + ( + -- A low-power debounce event does not create an immediate clear on the + -- first half of GPBR registers. + Not_Enable, + -- A low-power debounce event on WKUP0 or WKUP1 generates an immediate + -- clear on the first half of GPBR registers. + Enable) + with Size => 1; + for SUPC_WUMR_LPDBCCLR_Field use + (Not_Enable => 0, + Enable => 1); + + -- Wakeup Inputs Debouncer Period + type SUPC_WUMR_WKUPDBC_Field is + ( + -- Immediate, no debouncing, detected active at least on one Slow Clock + -- edge. + Immediate, + -- WKUPx shall be in its active state for at least 3 SLCK periods + Val_3_Slck, + -- WKUPx shall be in its active state for at least 32 SLCK periods + Val_32_Slck, + -- WKUPx shall be in its active state for at least 512 SLCK periods + Val_512_Slck, + -- WKUPx shall be in its active state for at least 4,096 SLCK periods + Val_4096_Slck, + -- WKUPx shall be in its active state for at least 32,768 SLCK periods + Val_32768_Slck) + with Size => 3; + for SUPC_WUMR_WKUPDBC_Field use + (Immediate => 0, + Val_3_Slck => 1, + Val_32_Slck => 2, + Val_512_Slck => 3, + Val_4096_Slck => 4, + Val_32768_Slck => 5); + + -- Low-power Debouncer Period + type SUPC_WUMR_LPDBC_Field is + ( + -- Disables the low-power debouncers. + Disable, + -- WKUP0/1 in active state for at least 2 RTCOUTx clock periods + Val_2_Rtcout, + -- WKUP0/1 in active state for at least 3 RTCOUTx clock periods + Val_3_Rtcout, + -- WKUP0/1 in active state for at least 4 RTCOUTx clock periods + Val_4_Rtcout, + -- WKUP0/1 in active state for at least 5 RTCOUTx clock periods + Val_5_Rtcout, + -- WKUP0/1 in active state for at least 6 RTCOUTx clock periods + Val_6_Rtcout, + -- WKUP0/1 in active state for at least 7 RTCOUTx clock periods + Val_7_Rtcout, + -- WKUP0/1 in active state for at least 8 RTCOUTx clock periods + Val_8_Rtcout) + with Size => 3; + for SUPC_WUMR_LPDBC_Field use + (Disable => 0, + Val_2_Rtcout => 1, + Val_3_Rtcout => 2, + Val_4_Rtcout => 3, + Val_5_Rtcout => 4, + Val_6_Rtcout => 5, + Val_7_Rtcout => 6, + Val_8_Rtcout => 7); + + -- Supply Controller Wakeup Mode Register + type SUPC_SUPC_WUMR_Register is record + -- unspecified + Reserved_0_0 : HAL.Bit := 16#0#; + -- Supply Monitor Wakeup Enable + SMEN : SUPC_WUMR_SMEN_Field := SAM_SVD.SUPC.Not_Enable; + -- Real-time Timer Wakeup Enable + RTTEN : SUPC_WUMR_RTTEN_Field := SAM_SVD.SUPC.Not_Enable; + -- Real-time Clock Wakeup Enable + RTCEN : SUPC_WUMR_RTCEN_Field := SAM_SVD.SUPC.Not_Enable; + -- unspecified + Reserved_4_4 : HAL.Bit := 16#0#; + -- Low-power Debouncer Enable WKUP0 + LPDBCEN0 : SUPC_WUMR_LPDBCEN0_Field := SAM_SVD.SUPC.Not_Enable; + -- Low-power Debouncer Enable WKUP1 + LPDBCEN1 : SUPC_WUMR_LPDBCEN1_Field := SAM_SVD.SUPC.Not_Enable; + -- Low-power Debouncer Clear + LPDBCCLR : SUPC_WUMR_LPDBCCLR_Field := SAM_SVD.SUPC.Not_Enable; + -- unspecified + Reserved_8_11 : HAL.UInt4 := 16#0#; + -- Wakeup Inputs Debouncer Period + WKUPDBC : SUPC_WUMR_WKUPDBC_Field := SAM_SVD.SUPC.Immediate; + -- unspecified + Reserved_15_15 : HAL.Bit := 16#0#; + -- Low-power Debouncer Period + LPDBC : SUPC_WUMR_LPDBC_Field := SAM_SVD.SUPC.Disable; + -- unspecified + Reserved_19_31 : HAL.UInt13 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for SUPC_SUPC_WUMR_Register use record + Reserved_0_0 at 0 range 0 .. 0; + SMEN at 0 range 1 .. 1; + RTTEN at 0 range 2 .. 2; + RTCEN at 0 range 3 .. 3; + Reserved_4_4 at 0 range 4 .. 4; + LPDBCEN0 at 0 range 5 .. 5; + LPDBCEN1 at 0 range 6 .. 6; + LPDBCCLR at 0 range 7 .. 7; + Reserved_8_11 at 0 range 8 .. 11; + WKUPDBC at 0 range 12 .. 14; + Reserved_15_15 at 0 range 15 .. 15; + LPDBC at 0 range 16 .. 18; + Reserved_19_31 at 0 range 19 .. 31; + end record; + + -- Wakeup Input Enable 0 to 0 + type SUPC_WUIR_WKUPEN0_Field is + ( + -- The corresponding wakeup input has no wakeup effect. + Disable, + -- The corresponding wakeup input is enabled for a wakeup of the core + -- power supply. + Enable) + with Size => 1; + for SUPC_WUIR_WKUPEN0_Field use + (Disable => 0, + Enable => 1); + + -- SUPC_SUPC_WUIR_WKUPEN array + type SUPC_SUPC_WUIR_WKUPEN_Field_Array is array (0 .. 13) + of SUPC_WUIR_WKUPEN0_Field + with Component_Size => 1, Size => 14; + + -- Type definition for SUPC_SUPC_WUIR_WKUPEN + type SUPC_SUPC_WUIR_WKUPEN_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- WKUPEN as a value + Val : HAL.UInt14; + when True => + -- WKUPEN as an array + Arr : SUPC_SUPC_WUIR_WKUPEN_Field_Array; + end case; + end record + with Unchecked_Union, Size => 14; + + for SUPC_SUPC_WUIR_WKUPEN_Field use record + Val at 0 range 0 .. 13; + Arr at 0 range 0 .. 13; + end record; + + -- Wakeup Input Type 0 to 0 + type SUPC_WUIR_WKUPT0_Field is + ( + -- A falling edge followed by a low level for a period defined by + -- WKUPDBC on the corre-sponding wakeup input forces the wakeup of the + -- core power supply. + Low, + -- A rising edge followed by a high level for a period defined by + -- WKUPDBC on the cor-responding wakeup input forces the wakeup of the + -- core power supply. + High) + with Size => 1; + for SUPC_WUIR_WKUPT0_Field use + (Low => 0, + High => 1); + + -- SUPC_SUPC_WUIR_WKUPT array + type SUPC_SUPC_WUIR_WKUPT_Field_Array is array (0 .. 13) + of SUPC_WUIR_WKUPT0_Field + with Component_Size => 1, Size => 14; + + -- Type definition for SUPC_SUPC_WUIR_WKUPT + type SUPC_SUPC_WUIR_WKUPT_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- WKUPT as a value + Val : HAL.UInt14; + when True => + -- WKUPT as an array + Arr : SUPC_SUPC_WUIR_WKUPT_Field_Array; + end case; + end record + with Unchecked_Union, Size => 14; + + for SUPC_SUPC_WUIR_WKUPT_Field use record + Val at 0 range 0 .. 13; + Arr at 0 range 0 .. 13; + end record; + + -- Supply Controller Wakeup Inputs Register + type SUPC_SUPC_WUIR_Register is record + -- Wakeup Input Enable 0 to 0 + WKUPEN : SUPC_SUPC_WUIR_WKUPEN_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_14_15 : HAL.UInt2 := 16#0#; + -- Wakeup Input Type 0 to 0 + WKUPT : SUPC_SUPC_WUIR_WKUPT_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_30_31 : HAL.UInt2 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for SUPC_SUPC_WUIR_Register use record + WKUPEN at 0 range 0 .. 13; + Reserved_14_15 at 0 range 14 .. 15; + WKUPT at 0 range 16 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + -- WKUP Wakeup Status (cleared on read) + type SUPC_SR_WKUPS_Field is + ( + -- No wakeup due to the assertion of the WKUP pins has occurred since + -- the last read of SUPC_SR. + No, + -- At least one wakeup due to the assertion of the WKUP pins has + -- occurred since the last read of SUPC_SR. + Present) + with Size => 1; + for SUPC_SR_WKUPS_Field use + (No => 0, + Present => 1); + + -- Supply Monitor Detection Wakeup Status (cleared on read) + type SUPC_SR_SMWS_Field is + ( + -- No wakeup due to a supply monitor detection has occurred since the + -- last read of SUPC_SR. + No, + -- At least one wakeup due to a supply monitor detection has occurred + -- since the last read of SUPC_SR. + Present) + with Size => 1; + for SUPC_SR_SMWS_Field use + (No => 0, + Present => 1); + + -- Brownout Detector Reset Status (cleared on read) + type SUPC_SR_BODRSTS_Field is + ( + -- No core brownout rising edge event has been detected since the last + -- read of the SUPC_SR. + No, + -- At least one brownout output rising edge event has been detected + -- since the last read of the SUPC_SR. + Present) + with Size => 1; + for SUPC_SR_BODRSTS_Field use + (No => 0, + Present => 1); + + -- Supply Monitor Reset Status (cleared on read) + type SUPC_SR_SMRSTS_Field is + ( + -- No supply monitor detection has generated a core reset since the last + -- read of the SUPC_SR. + No, + -- At least one supply monitor detection has generated a core reset + -- since the last read of the SUPC_SR. + Present) + with Size => 1; + for SUPC_SR_SMRSTS_Field use + (No => 0, + Present => 1); + + -- Supply Monitor Status (cleared on read) + type SUPC_SR_SMS_Field is + ( + -- No supply monitor detection since the last read of SUPC_SR. + No, + -- At least one supply monitor detection since the last read of SUPC_SR. + Present) + with Size => 1; + for SUPC_SR_SMS_Field use + (No => 0, + Present => 1); + + -- Supply Monitor Output Status + type SUPC_SR_SMOS_Field is + ( + -- The supply monitor detected VDDIO higher than its threshold at its + -- last measurement. + High, + -- The supply monitor detected VDDIO lower than its threshold at its + -- last measurement. + Low) + with Size => 1; + for SUPC_SR_SMOS_Field use + (High => 0, + Low => 1); + + -- 32-kHz Oscillator Selection Status + type SUPC_SR_OSCSEL_Field is + ( + -- The slow clock, SLCK, is generated by the embedded 32 kHz RC + -- oscillator. + Rc, + -- The slow clock, SLCK, is generated by the 32 kHz crystal oscillator. + Cryst) + with Size => 1; + for SUPC_SR_OSCSEL_Field use + (Rc => 0, + Cryst => 1); + + -- Low-power Debouncer Wakeup Status on WKUP0 (cleared on read) + type SUPC_SR_LPDBCS0_Field is + ( + -- No wakeup due to the assertion of the WKUP0 pin has occurred since + -- the last read of SUPC_SR. + No, + -- At least one wakeup due to the assertion of the WKUP0 pin has + -- occurred since the last read of SUPC_SR. + Present) + with Size => 1; + for SUPC_SR_LPDBCS0_Field use + (No => 0, + Present => 1); + + -- Low-power Debouncer Wakeup Status on WKUP1 (cleared on read) + type SUPC_SR_LPDBCS1_Field is + ( + -- No wakeup due to the assertion of the WKUP1 pin has occurred since + -- the last read of SUPC_SR. + No, + -- At least one wakeup due to the assertion of the WKUP1 pin has + -- occurred since the last read of SUPC_SR. + Present) + with Size => 1; + for SUPC_SR_LPDBCS1_Field use + (No => 0, + Present => 1); + + -- WKUPx Input Status (cleared on read) + type SUPC_SR_WKUPIS0_Field is + ( + -- The corresponding wakeup input is disabled, or was inactive at the + -- time the debouncer triggered a wakeup event. + Dis, + -- The corresponding wakeup input was active at the time the debouncer + -- triggered a wakeup event since the last read of SUPC_SR. + En) + with Size => 1; + for SUPC_SR_WKUPIS0_Field use + (Dis => 0, + En => 1); + + -- SUPC_SUPC_SR_WKUPIS array + type SUPC_SUPC_SR_WKUPIS_Field_Array is array (0 .. 13) + of SUPC_SR_WKUPIS0_Field + with Component_Size => 1, Size => 14; + + -- Type definition for SUPC_SUPC_SR_WKUPIS + type SUPC_SUPC_SR_WKUPIS_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- WKUPIS as a value + Val : HAL.UInt14; + when True => + -- WKUPIS as an array + Arr : SUPC_SUPC_SR_WKUPIS_Field_Array; + end case; + end record + with Unchecked_Union, Size => 14; + + for SUPC_SUPC_SR_WKUPIS_Field use record + Val at 0 range 0 .. 13; + Arr at 0 range 0 .. 13; + end record; + + -- Supply Controller Status Register + type SUPC_SUPC_SR_Register is record + -- unspecified + Reserved_0_0 : HAL.Bit; + -- Read-only. WKUP Wakeup Status (cleared on read) + WKUPS : SUPC_SR_WKUPS_Field; + -- Read-only. Supply Monitor Detection Wakeup Status (cleared on read) + SMWS : SUPC_SR_SMWS_Field; + -- Read-only. Brownout Detector Reset Status (cleared on read) + BODRSTS : SUPC_SR_BODRSTS_Field; + -- Read-only. Supply Monitor Reset Status (cleared on read) + SMRSTS : SUPC_SR_SMRSTS_Field; + -- Read-only. Supply Monitor Status (cleared on read) + SMS : SUPC_SR_SMS_Field; + -- Read-only. Supply Monitor Output Status + SMOS : SUPC_SR_SMOS_Field; + -- Read-only. 32-kHz Oscillator Selection Status + OSCSEL : SUPC_SR_OSCSEL_Field; + -- unspecified + Reserved_8_12 : HAL.UInt5; + -- Read-only. Low-power Debouncer Wakeup Status on WKUP0 (cleared on + -- read) + LPDBCS0 : SUPC_SR_LPDBCS0_Field; + -- Read-only. Low-power Debouncer Wakeup Status on WKUP1 (cleared on + -- read) + LPDBCS1 : SUPC_SR_LPDBCS1_Field; + -- unspecified + Reserved_15_15 : HAL.Bit; + -- Read-only. WKUPx Input Status (cleared on read) + WKUPIS : SUPC_SUPC_SR_WKUPIS_Field; + -- unspecified + Reserved_30_31 : HAL.UInt2; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for SUPC_SUPC_SR_Register use record + Reserved_0_0 at 0 range 0 .. 0; + WKUPS at 0 range 1 .. 1; + SMWS at 0 range 2 .. 2; + BODRSTS at 0 range 3 .. 3; + SMRSTS at 0 range 4 .. 4; + SMS at 0 range 5 .. 5; + SMOS at 0 range 6 .. 6; + OSCSEL at 0 range 7 .. 7; + Reserved_8_12 at 0 range 8 .. 12; + LPDBCS0 at 0 range 13 .. 13; + LPDBCS1 at 0 range 14 .. 14; + Reserved_15_15 at 0 range 15 .. 15; + WKUPIS at 0 range 16 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + subtype SUPC_SYSC_VERSION_VERSION_Field is HAL.UInt12; + subtype SUPC_SYSC_VERSION_MFN_Field is HAL.UInt3; + + -- Version Register + type SUPC_SYSC_VERSION_Register is record + -- Read-only. Version of the Hardware Module + VERSION : SUPC_SYSC_VERSION_VERSION_Field; + -- unspecified + Reserved_12_15 : HAL.UInt4; + -- Read-only. Metal Fix Number + MFN : SUPC_SYSC_VERSION_MFN_Field; + -- unspecified + Reserved_19_31 : HAL.UInt13; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for SUPC_SYSC_VERSION_Register use record + VERSION at 0 range 0 .. 11; + Reserved_12_15 at 0 range 12 .. 15; + MFN at 0 range 16 .. 18; + Reserved_19_31 at 0 range 19 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- Supply Controller + type SUPC_Peripheral is record + -- Supply Controller Control Register + SUPC_CR : aliased SUPC_SUPC_CR_Register; + -- Supply Controller Supply Monitor Mode Register + SUPC_SMMR : aliased SUPC_SUPC_SMMR_Register; + -- Supply Controller Mode Register + SUPC_MR : aliased SUPC_SUPC_MR_Register; + -- Supply Controller Wakeup Mode Register + SUPC_WUMR : aliased SUPC_SUPC_WUMR_Register; + -- Supply Controller Wakeup Inputs Register + SUPC_WUIR : aliased SUPC_SUPC_WUIR_Register; + -- Supply Controller Status Register + SUPC_SR : aliased SUPC_SUPC_SR_Register; + -- Version Register + SYSC_VERSION : aliased SUPC_SYSC_VERSION_Register; + end record + with Volatile; + + for SUPC_Peripheral use record + SUPC_CR at 16#0# range 0 .. 31; + SUPC_SMMR at 16#4# range 0 .. 31; + SUPC_MR at 16#8# range 0 .. 31; + SUPC_WUMR at 16#C# range 0 .. 31; + SUPC_WUIR at 16#10# range 0 .. 31; + SUPC_SR at 16#14# range 0 .. 31; + SYSC_VERSION at 16#FC# range 0 .. 31; + end record; + + -- Supply Controller + SUPC_Periph : aliased SUPC_Peripheral + with Import, Address => System'To_Address (16#400E1810#); + +end SAM_SVD.SUPC; diff --git a/arch/ARM/SAM/svd/atsamv71/sam_svd-systemcontrol.ads b/arch/ARM/SAM/svd/atsamv71/sam_svd-systemcontrol.ads new file mode 100644 index 000000000..504ac3f8e --- /dev/null +++ b/arch/ARM/SAM/svd/atsamv71/sam_svd-systemcontrol.ads @@ -0,0 +1,1350 @@ +-- This spec has been automatically generated from ATSAMV71Q21.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package SAM_SVD.SystemControl is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + -- Auxiliary Control Register, + type SystemControl_ACTLR_Register is record + -- Disables interruption of multi-cycle instructions. + DISMCYCINT : Boolean := False; + -- Disables write buffer use during default memory map accesses. + DISDEFWBUF : Boolean := False; + -- Disables folding of IT instructions. + DISFOLD : Boolean := False; + -- unspecified + Reserved_3_31 : HAL.UInt29 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for SystemControl_ACTLR_Register use record + DISMCYCINT at 0 range 0 .. 0; + DISDEFWBUF at 0 range 1 .. 1; + DISFOLD at 0 range 2 .. 2; + Reserved_3_31 at 0 range 3 .. 31; + end record; + + subtype SystemControl_CPUID_REVISION_Field is HAL.UInt4; + subtype SystemControl_CPUID_PARTNO_Field is HAL.UInt12; + subtype SystemControl_CPUID_VARIANT_Field is HAL.UInt4; + subtype SystemControl_CPUID_IMPLEMENTER_Field is HAL.UInt8; + + -- CPUID Base Register + type SystemControl_CPUID_Register is record + -- Indicates patch release: 0x0 = Patch 0 + REVISION : SystemControl_CPUID_REVISION_Field := 16#0#; + -- Indicates part number + PARTNO : SystemControl_CPUID_PARTNO_Field := 16#0#; + -- unspecified + Reserved_16_19 : HAL.UInt4 := 16#0#; + -- Indicates processor revision: 0x2 = Revision 2 + VARIANT : SystemControl_CPUID_VARIANT_Field := 16#0#; + -- Implementer code + IMPLEMENTER : SystemControl_CPUID_IMPLEMENTER_Field := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for SystemControl_CPUID_Register use record + REVISION at 0 range 0 .. 3; + PARTNO at 0 range 4 .. 15; + Reserved_16_19 at 0 range 16 .. 19; + VARIANT at 0 range 20 .. 23; + IMPLEMENTER at 0 range 24 .. 31; + end record; + + subtype SystemControl_ICSR_VECTACTIVE_Field is HAL.UInt9; + + -- no description available + type ICSR_RETTOBASE_Field is + ( + -- there are preempted active exceptions to execute + Value_0, + -- there are no active exceptions, or the currently-executing exception + -- is the only active exception + Value_1) + with Size => 1; + for ICSR_RETTOBASE_Field use + (Value_0 => 0, + Value_1 => 1); + + subtype SystemControl_ICSR_VECTPENDING_Field is HAL.UInt6; + + -- no description available + type ICSR_ISRPREEMPT_Field is + ( + -- Will not service + Value_0, + -- Will service a pending exception + Value_1) + with Size => 1; + for ICSR_ISRPREEMPT_Field use + (Value_0 => 0, + Value_1 => 1); + + -- no description available + type ICSR_PENDSTCLR_Field is + ( + -- no effect + Value_0, + -- removes the pending state from the SysTick exception + Value_1) + with Size => 1; + for ICSR_PENDSTCLR_Field use + (Value_0 => 0, + Value_1 => 1); + + -- no description available + type ICSR_PENDSTSET_Field is + ( + -- write: no effect; read: SysTick exception is not pending + Value_0, + -- write: changes SysTick exception state to pending; read: SysTick + -- exception is pending + Value_1) + with Size => 1; + for ICSR_PENDSTSET_Field use + (Value_0 => 0, + Value_1 => 1); + + -- no description available + type ICSR_PENDSVCLR_Field is + ( + -- no effect + Value_0, + -- removes the pending state from the PendSV exception + Value_1) + with Size => 1; + for ICSR_PENDSVCLR_Field use + (Value_0 => 0, + Value_1 => 1); + + -- no description available + type ICSR_PENDSVSET_Field is + ( + -- write: no effect; read: PendSV exception is not pending + Value_0, + -- write: changes PendSV exception state to pending; read: PendSV + -- exception is pending + Value_1) + with Size => 1; + for ICSR_PENDSVSET_Field use + (Value_0 => 0, + Value_1 => 1); + + -- no description available + type ICSR_NMIPENDSET_Field is + ( + -- write: no effect; read: NMI exception is not pending + Value_0, + -- write: changes NMI exception state to pending; read: NMI exception is + -- pending + Value_1) + with Size => 1; + for ICSR_NMIPENDSET_Field use + (Value_0 => 0, + Value_1 => 1); + + -- Interrupt Control and State Register + type SystemControl_ICSR_Register is record + -- Active exception number + VECTACTIVE : SystemControl_ICSR_VECTACTIVE_Field := 16#0#; + -- unspecified + Reserved_9_10 : HAL.UInt2 := 16#0#; + -- no description available + RETTOBASE : ICSR_RETTOBASE_Field := SAM_SVD.SystemControl.Value_0; + -- Exception number of the highest priority pending enabled exception + VECTPENDING : SystemControl_ICSR_VECTPENDING_Field := 16#0#; + -- unspecified + Reserved_18_21 : HAL.UInt4 := 16#0#; + -- no description available + ISRPENDING : Boolean := False; + -- no description available + ISRPREEMPT : ICSR_ISRPREEMPT_Field := SAM_SVD.SystemControl.Value_0; + -- unspecified + Reserved_24_24 : HAL.Bit := 16#0#; + -- no description available + PENDSTCLR : ICSR_PENDSTCLR_Field := SAM_SVD.SystemControl.Value_0; + -- no description available + PENDSTSET : ICSR_PENDSTSET_Field := SAM_SVD.SystemControl.Value_0; + -- no description available + PENDSVCLR : ICSR_PENDSVCLR_Field := SAM_SVD.SystemControl.Value_0; + -- no description available + PENDSVSET : ICSR_PENDSVSET_Field := SAM_SVD.SystemControl.Value_0; + -- unspecified + Reserved_29_30 : HAL.UInt2 := 16#0#; + -- no description available + NMIPENDSET : ICSR_NMIPENDSET_Field := SAM_SVD.SystemControl.Value_0; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for SystemControl_ICSR_Register use record + VECTACTIVE at 0 range 0 .. 8; + Reserved_9_10 at 0 range 9 .. 10; + RETTOBASE at 0 range 11 .. 11; + VECTPENDING at 0 range 12 .. 17; + Reserved_18_21 at 0 range 18 .. 21; + ISRPENDING at 0 range 22 .. 22; + ISRPREEMPT at 0 range 23 .. 23; + Reserved_24_24 at 0 range 24 .. 24; + PENDSTCLR at 0 range 25 .. 25; + PENDSTSET at 0 range 26 .. 26; + PENDSVCLR at 0 range 27 .. 27; + PENDSVSET at 0 range 28 .. 28; + Reserved_29_30 at 0 range 29 .. 30; + NMIPENDSET at 0 range 31 .. 31; + end record; + + subtype SystemControl_VTOR_TBLOFF_Field is HAL.UInt25; + + -- Vector Table Offset Register + type SystemControl_VTOR_Register is record + -- unspecified + Reserved_0_6 : HAL.UInt7 := 16#0#; + -- Vector table base offset + TBLOFF : SystemControl_VTOR_TBLOFF_Field := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for SystemControl_VTOR_Register use record + Reserved_0_6 at 0 range 0 .. 6; + TBLOFF at 0 range 7 .. 31; + end record; + + -- no description available + type AIRCR_SYSRESETREQ_Field is + ( + -- no system reset request + Value_0, + -- asserts a signal to the outer system that requests a reset + Value_1) + with Size => 1; + for AIRCR_SYSRESETREQ_Field use + (Value_0 => 0, + Value_1 => 1); + + subtype SystemControl_AIRCR_PRIGROUP_Field is HAL.UInt3; + + -- no description available + type AIRCR_ENDIANNESS_Field is + ( + -- Little-endian + Value_0, + -- Big-endian + Value_1) + with Size => 1; + for AIRCR_ENDIANNESS_Field use + (Value_0 => 0, + Value_1 => 1); + + subtype SystemControl_AIRCR_VECTKEY_Field is HAL.UInt16; + + -- Application Interrupt and Reset Control Register + type SystemControl_AIRCR_Register is record + -- no description available + VECTRESET : Boolean := False; + -- no description available + VECTCLRACTIVE : Boolean := False; + -- no description available + SYSRESETREQ : AIRCR_SYSRESETREQ_Field := + SAM_SVD.SystemControl.Value_0; + -- unspecified + Reserved_3_7 : HAL.UInt5 := 16#0#; + -- Interrupt priority grouping field. This field determines the split of + -- group priority from subpriority. + PRIGROUP : SystemControl_AIRCR_PRIGROUP_Field := 16#0#; + -- unspecified + Reserved_11_14 : HAL.UInt4 := 16#0#; + -- no description available + ENDIANNESS : AIRCR_ENDIANNESS_Field := + SAM_SVD.SystemControl.Value_0; + -- Register key + VECTKEY : SystemControl_AIRCR_VECTKEY_Field := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for SystemControl_AIRCR_Register use record + VECTRESET at 0 range 0 .. 0; + VECTCLRACTIVE at 0 range 1 .. 1; + SYSRESETREQ at 0 range 2 .. 2; + Reserved_3_7 at 0 range 3 .. 7; + PRIGROUP at 0 range 8 .. 10; + Reserved_11_14 at 0 range 11 .. 14; + ENDIANNESS at 0 range 15 .. 15; + VECTKEY at 0 range 16 .. 31; + end record; + + -- no description available + type SCR_SLEEPONEXIT_Field is + ( + -- o not sleep when returning to Thread mode + Value_0, + -- enter sleep, or deep sleep, on return from an ISR + Value_1) + with Size => 1; + for SCR_SLEEPONEXIT_Field use + (Value_0 => 0, + Value_1 => 1); + + -- no description available + type SCR_SLEEPDEEP_Field is + ( + -- sleep + Value_0, + -- deep sleep + Value_1) + with Size => 1; + for SCR_SLEEPDEEP_Field use + (Value_0 => 0, + Value_1 => 1); + + -- no description available + type SCR_SEVONPEND_Field is + ( + -- only enabled interrupts or events can wakeup the processor, disabled + -- interrupts are excluded + Value_0, + -- enabled events and all interrupts, including disabled interrupts, can + -- wakeup the processor + Value_1) + with Size => 1; + for SCR_SEVONPEND_Field use + (Value_0 => 0, + Value_1 => 1); + + -- System Control Register + type SystemControl_SCR_Register is record + -- unspecified + Reserved_0_0 : HAL.Bit := 16#0#; + -- no description available + SLEEPONEXIT : SCR_SLEEPONEXIT_Field := SAM_SVD.SystemControl.Value_0; + -- no description available + SLEEPDEEP : SCR_SLEEPDEEP_Field := SAM_SVD.SystemControl.Value_0; + -- unspecified + Reserved_3_3 : HAL.Bit := 16#0#; + -- no description available + SEVONPEND : SCR_SEVONPEND_Field := SAM_SVD.SystemControl.Value_0; + -- unspecified + Reserved_5_31 : HAL.UInt27 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for SystemControl_SCR_Register use record + Reserved_0_0 at 0 range 0 .. 0; + SLEEPONEXIT at 0 range 1 .. 1; + SLEEPDEEP at 0 range 2 .. 2; + Reserved_3_3 at 0 range 3 .. 3; + SEVONPEND at 0 range 4 .. 4; + Reserved_5_31 at 0 range 5 .. 31; + end record; + + -- no description available + type CCR_NONBASETHRDENA_Field is + ( + -- processor can enter Thread mode only when no exception is active + Value_0, + -- processor can enter Thread mode from any level under the control of + -- an EXC_RETURN value + Value_1) + with Size => 1; + for CCR_NONBASETHRDENA_Field use + (Value_0 => 0, + Value_1 => 1); + + -- Enables unprivileged software access to the STIR + type CCR_USERSETMPEND_Field is + ( + -- disable + Value_0, + -- enable + Value_1) + with Size => 1; + for CCR_USERSETMPEND_Field use + (Value_0 => 0, + Value_1 => 1); + + -- Enables unaligned access traps + type CCR_UNALIGN_TRP_Field is + ( + -- do not trap unaligned halfword and word accesses + Value_0, + -- trap unaligned halfword and word accesses + Value_1) + with Size => 1; + for CCR_UNALIGN_TRP_Field use + (Value_0 => 0, + Value_1 => 1); + + -- Enables faulting or halting when the processor executes an SDIV or UDIV + -- instruction with a divisor of 0 + type CCR_DIV_0_TRP_Field is + ( + -- do not trap divide by 0 + Value_0, + -- trap divide by 0 + Value_1) + with Size => 1; + for CCR_DIV_0_TRP_Field use + (Value_0 => 0, + Value_1 => 1); + + -- Enables handlers with priority -1 or -2 to ignore data BusFaults caused + -- by load and store instructions. + type CCR_BFHFNMIGN_Field is + ( + -- data bus faults caused by load and store instructions cause a lock-up + Value_0, + -- handlers running at priority -1 and -2 ignore data bus faults caused + -- by load and store instructions + Value_1) + with Size => 1; + for CCR_BFHFNMIGN_Field use + (Value_0 => 0, + Value_1 => 1); + + -- Indicates stack alignment on exception entry + type CCR_STKALIGN_Field is + ( + -- 4-byte aligned + Value_0, + -- 8-byte aligned + Value_1) + with Size => 1; + for CCR_STKALIGN_Field use + (Value_0 => 0, + Value_1 => 1); + + -- Configuration and Control Register + type SystemControl_CCR_Register is record + -- no description available + NONBASETHRDENA : CCR_NONBASETHRDENA_Field := + SAM_SVD.SystemControl.Value_0; + -- Enables unprivileged software access to the STIR + USERSETMPEND : CCR_USERSETMPEND_Field := + SAM_SVD.SystemControl.Value_0; + -- unspecified + Reserved_2_2 : HAL.Bit := 16#0#; + -- Enables unaligned access traps + UNALIGN_TRP : CCR_UNALIGN_TRP_Field := SAM_SVD.SystemControl.Value_0; + -- Enables faulting or halting when the processor executes an SDIV or + -- UDIV instruction with a divisor of 0 + DIV_0_TRP : CCR_DIV_0_TRP_Field := SAM_SVD.SystemControl.Value_0; + -- unspecified + Reserved_5_7 : HAL.UInt3 := 16#0#; + -- Enables handlers with priority -1 or -2 to ignore data BusFaults + -- caused by load and store instructions. + BFHFNMIGN : CCR_BFHFNMIGN_Field := SAM_SVD.SystemControl.Value_0; + -- Indicates stack alignment on exception entry + STKALIGN : CCR_STKALIGN_Field := SAM_SVD.SystemControl.Value_0; + -- unspecified + Reserved_10_31 : HAL.UInt22 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for SystemControl_CCR_Register use record + NONBASETHRDENA at 0 range 0 .. 0; + USERSETMPEND at 0 range 1 .. 1; + Reserved_2_2 at 0 range 2 .. 2; + UNALIGN_TRP at 0 range 3 .. 3; + DIV_0_TRP at 0 range 4 .. 4; + Reserved_5_7 at 0 range 5 .. 7; + BFHFNMIGN at 0 range 8 .. 8; + STKALIGN at 0 range 9 .. 9; + Reserved_10_31 at 0 range 10 .. 31; + end record; + + subtype SystemControl_SHPR1_PRI_4_Field is HAL.UInt8; + subtype SystemControl_SHPR1_PRI_5_Field is HAL.UInt8; + subtype SystemControl_SHPR1_PRI_6_Field is HAL.UInt8; + + -- System Handler Priority Register 1 + type SystemControl_SHPR1_Register is record + -- Priority of system handler 4, MemManage + PRI_4 : SystemControl_SHPR1_PRI_4_Field := 16#0#; + -- Priority of system handler 5, BusFault + PRI_5 : SystemControl_SHPR1_PRI_5_Field := 16#0#; + -- Priority of system handler 6, UsageFault + PRI_6 : SystemControl_SHPR1_PRI_6_Field := 16#0#; + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for SystemControl_SHPR1_Register use record + PRI_4 at 0 range 0 .. 7; + PRI_5 at 0 range 8 .. 15; + PRI_6 at 0 range 16 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype SystemControl_SHPR2_PRI_11_Field is HAL.UInt8; + + -- System Handler Priority Register 2 + type SystemControl_SHPR2_Register is record + -- unspecified + Reserved_0_23 : HAL.UInt24 := 16#0#; + -- Priority of system handler 11, SVCall + PRI_11 : SystemControl_SHPR2_PRI_11_Field := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for SystemControl_SHPR2_Register use record + Reserved_0_23 at 0 range 0 .. 23; + PRI_11 at 0 range 24 .. 31; + end record; + + subtype SystemControl_SHPR3_PRI_14_Field is HAL.UInt8; + subtype SystemControl_SHPR3_PRI_15_Field is HAL.UInt8; + + -- System Handler Priority Register 3 + type SystemControl_SHPR3_Register is record + -- unspecified + Reserved_0_15 : HAL.UInt16 := 16#0#; + -- Priority of system handler 14, PendSV + PRI_14 : SystemControl_SHPR3_PRI_14_Field := 16#0#; + -- Priority of system handler 15, SysTick exception + PRI_15 : SystemControl_SHPR3_PRI_15_Field := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for SystemControl_SHPR3_Register use record + Reserved_0_15 at 0 range 0 .. 15; + PRI_14 at 0 range 16 .. 23; + PRI_15 at 0 range 24 .. 31; + end record; + + -- no description available + type SHCSR_MEMFAULTACT_Field is + ( + -- exception is not active + Value_0, + -- exception is active + Value_1) + with Size => 1; + for SHCSR_MEMFAULTACT_Field use + (Value_0 => 0, + Value_1 => 1); + + -- no description available + type SHCSR_BUSFAULTACT_Field is + ( + -- exception is not active + Value_0, + -- exception is active + Value_1) + with Size => 1; + for SHCSR_BUSFAULTACT_Field use + (Value_0 => 0, + Value_1 => 1); + + -- no description available + type SHCSR_USGFAULTACT_Field is + ( + -- exception is not active + Value_0, + -- exception is active + Value_1) + with Size => 1; + for SHCSR_USGFAULTACT_Field use + (Value_0 => 0, + Value_1 => 1); + + -- no description available + type SHCSR_SVCALLACT_Field is + ( + -- exception is not active + Value_0, + -- exception is active + Value_1) + with Size => 1; + for SHCSR_SVCALLACT_Field use + (Value_0 => 0, + Value_1 => 1); + + -- no description available + type SHCSR_MONITORACT_Field is + ( + -- exception is not active + Value_0, + -- exception is active + Value_1) + with Size => 1; + for SHCSR_MONITORACT_Field use + (Value_0 => 0, + Value_1 => 1); + + -- no description available + type SHCSR_PENDSVACT_Field is + ( + -- exception is not active + Value_0, + -- exception is active + Value_1) + with Size => 1; + for SHCSR_PENDSVACT_Field use + (Value_0 => 0, + Value_1 => 1); + + -- no description available + type SHCSR_SYSTICKACT_Field is + ( + -- exception is not active + Value_0, + -- exception is active + Value_1) + with Size => 1; + for SHCSR_SYSTICKACT_Field use + (Value_0 => 0, + Value_1 => 1); + + -- no description available + type SHCSR_USGFAULTPENDED_Field is + ( + -- exception is not pending + Value_0, + -- exception is pending + Value_1) + with Size => 1; + for SHCSR_USGFAULTPENDED_Field use + (Value_0 => 0, + Value_1 => 1); + + -- no description available + type SHCSR_MEMFAULTPENDED_Field is + ( + -- exception is not pending + Value_0, + -- exception is pending + Value_1) + with Size => 1; + for SHCSR_MEMFAULTPENDED_Field use + (Value_0 => 0, + Value_1 => 1); + + -- no description available + type SHCSR_BUSFAULTPENDED_Field is + ( + -- exception is not pending + Value_0, + -- exception is pending + Value_1) + with Size => 1; + for SHCSR_BUSFAULTPENDED_Field use + (Value_0 => 0, + Value_1 => 1); + + -- no description available + type SHCSR_SVCALLPENDED_Field is + ( + -- exception is not pending + Value_0, + -- exception is pending + Value_1) + with Size => 1; + for SHCSR_SVCALLPENDED_Field use + (Value_0 => 0, + Value_1 => 1); + + -- no description available + type SHCSR_MEMFAULTENA_Field is + ( + -- disable the exception + Value_0, + -- enable the exception + Value_1) + with Size => 1; + for SHCSR_MEMFAULTENA_Field use + (Value_0 => 0, + Value_1 => 1); + + -- no description available + type SHCSR_BUSFAULTENA_Field is + ( + -- disable the exception + Value_0, + -- enable the exception + Value_1) + with Size => 1; + for SHCSR_BUSFAULTENA_Field use + (Value_0 => 0, + Value_1 => 1); + + -- no description available + type SHCSR_USGFAULTENA_Field is + ( + -- disable the exception + Value_0, + -- enable the exception + Value_1) + with Size => 1; + for SHCSR_USGFAULTENA_Field use + (Value_0 => 0, + Value_1 => 1); + + -- System Handler Control and State Register + type SystemControl_SHCSR_Register is record + -- no description available + MEMFAULTACT : SHCSR_MEMFAULTACT_Field := + SAM_SVD.SystemControl.Value_0; + -- no description available + BUSFAULTACT : SHCSR_BUSFAULTACT_Field := + SAM_SVD.SystemControl.Value_0; + -- unspecified + Reserved_2_2 : HAL.Bit := 16#0#; + -- no description available + USGFAULTACT : SHCSR_USGFAULTACT_Field := + SAM_SVD.SystemControl.Value_0; + -- unspecified + Reserved_4_6 : HAL.UInt3 := 16#0#; + -- no description available + SVCALLACT : SHCSR_SVCALLACT_Field := SAM_SVD.SystemControl.Value_0; + -- no description available + MONITORACT : SHCSR_MONITORACT_Field := + SAM_SVD.SystemControl.Value_0; + -- unspecified + Reserved_9_9 : HAL.Bit := 16#0#; + -- no description available + PENDSVACT : SHCSR_PENDSVACT_Field := SAM_SVD.SystemControl.Value_0; + -- no description available + SYSTICKACT : SHCSR_SYSTICKACT_Field := + SAM_SVD.SystemControl.Value_0; + -- no description available + USGFAULTPENDED : SHCSR_USGFAULTPENDED_Field := + SAM_SVD.SystemControl.Value_0; + -- no description available + MEMFAULTPENDED : SHCSR_MEMFAULTPENDED_Field := + SAM_SVD.SystemControl.Value_0; + -- no description available + BUSFAULTPENDED : SHCSR_BUSFAULTPENDED_Field := + SAM_SVD.SystemControl.Value_0; + -- no description available + SVCALLPENDED : SHCSR_SVCALLPENDED_Field := + SAM_SVD.SystemControl.Value_0; + -- no description available + MEMFAULTENA : SHCSR_MEMFAULTENA_Field := + SAM_SVD.SystemControl.Value_0; + -- no description available + BUSFAULTENA : SHCSR_BUSFAULTENA_Field := + SAM_SVD.SystemControl.Value_0; + -- no description available + USGFAULTENA : SHCSR_USGFAULTENA_Field := + SAM_SVD.SystemControl.Value_0; + -- unspecified + Reserved_19_31 : HAL.UInt13 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for SystemControl_SHCSR_Register use record + MEMFAULTACT at 0 range 0 .. 0; + BUSFAULTACT at 0 range 1 .. 1; + Reserved_2_2 at 0 range 2 .. 2; + USGFAULTACT at 0 range 3 .. 3; + Reserved_4_6 at 0 range 4 .. 6; + SVCALLACT at 0 range 7 .. 7; + MONITORACT at 0 range 8 .. 8; + Reserved_9_9 at 0 range 9 .. 9; + PENDSVACT at 0 range 10 .. 10; + SYSTICKACT at 0 range 11 .. 11; + USGFAULTPENDED at 0 range 12 .. 12; + MEMFAULTPENDED at 0 range 13 .. 13; + BUSFAULTPENDED at 0 range 14 .. 14; + SVCALLPENDED at 0 range 15 .. 15; + MEMFAULTENA at 0 range 16 .. 16; + BUSFAULTENA at 0 range 17 .. 17; + USGFAULTENA at 0 range 18 .. 18; + Reserved_19_31 at 0 range 19 .. 31; + end record; + + -- no description available + type CFSR_IACCVIOL_Field is + ( + -- no instruction access violation fault + Value_0, + -- the processor attempted an instruction fetch from a location that + -- does not permit execution + Value_1) + with Size => 1; + for CFSR_IACCVIOL_Field use + (Value_0 => 0, + Value_1 => 1); + + -- no description available + type CFSR_DACCVIOL_Field is + ( + -- no data access violation fault + Value_0, + -- the processor attempted a load or store at a location that does not + -- permit the operation + Value_1) + with Size => 1; + for CFSR_DACCVIOL_Field use + (Value_0 => 0, + Value_1 => 1); + + -- no description available + type CFSR_MUNSTKERR_Field is + ( + -- no unstacking fault + Value_0, + -- unstack for an exception return has caused one or more access + -- violations + Value_1) + with Size => 1; + for CFSR_MUNSTKERR_Field use + (Value_0 => 0, + Value_1 => 1); + + -- no description available + type CFSR_MSTKERR_Field is + ( + -- no stacking fault + Value_0, + -- stacking for an exception entry has caused one or more access + -- violations + Value_1) + with Size => 1; + for CFSR_MSTKERR_Field use + (Value_0 => 0, + Value_1 => 1); + + -- no description available + type CFSR_MLSPERR_Field is + ( + -- No MemManage fault occurred during floating-point lazy state + -- preservation + Value_0, + -- A MemManage fault occurred during floating-point lazy state + -- preservation + Value_1) + with Size => 1; + for CFSR_MLSPERR_Field use + (Value_0 => 0, + Value_1 => 1); + + -- no description available + type CFSR_MMARVALID_Field is + ( + -- value in MMAR is not a valid fault address + Value_0, + -- MMAR holds a valid fault address + Value_1) + with Size => 1; + for CFSR_MMARVALID_Field use + (Value_0 => 0, + Value_1 => 1); + + -- no description available + type CFSR_IBUSERR_Field is + ( + -- no instruction bus error + Value_0, + -- instruction bus error + Value_1) + with Size => 1; + for CFSR_IBUSERR_Field use + (Value_0 => 0, + Value_1 => 1); + + -- no description available + type CFSR_PRECISERR_Field is + ( + -- no precise data bus error + Value_0, + -- a data bus error has occurred, and the PC value stacked for the + -- exception return points to the instruction that caused the fault + Value_1) + with Size => 1; + for CFSR_PRECISERR_Field use + (Value_0 => 0, + Value_1 => 1); + + -- no description available + type CFSR_IMPRECISERR_Field is + ( + -- no imprecise data bus error + Value_0, + -- a data bus error has occurred, but the return address in the stack + -- frame is not related to the instruction that caused the error + Value_1) + with Size => 1; + for CFSR_IMPRECISERR_Field use + (Value_0 => 0, + Value_1 => 1); + + -- no description available + type CFSR_UNSTKERR_Field is + ( + -- no unstacking fault + Value_0, + -- unstack for an exception return has caused one or more BusFaults + Value_1) + with Size => 1; + for CFSR_UNSTKERR_Field use + (Value_0 => 0, + Value_1 => 1); + + -- no description available + type CFSR_STKERR_Field is + ( + -- no stacking fault + Value_0, + -- stacking for an exception entry has caused one or more BusFaults + Value_1) + with Size => 1; + for CFSR_STKERR_Field use + (Value_0 => 0, + Value_1 => 1); + + -- no description available + type CFSR_LSPERR_Field is + ( + -- No bus fault occurred during floating-point lazy state preservation + Value_0, + -- A bus fault occurred during floating-point lazy state preservation + Value_1) + with Size => 1; + for CFSR_LSPERR_Field use + (Value_0 => 0, + Value_1 => 1); + + -- no description available + type CFSR_BFARVALID_Field is + ( + -- value in BFAR is not a valid fault address + Value_0, + -- BFAR holds a valid fault address + Value_1) + with Size => 1; + for CFSR_BFARVALID_Field use + (Value_0 => 0, + Value_1 => 1); + + -- no description available + type CFSR_UNDEFINSTR_Field is + ( + -- no undefined instruction UsageFault + Value_0, + -- the processor has attempted to execute an undefined instruction + Value_1) + with Size => 1; + for CFSR_UNDEFINSTR_Field use + (Value_0 => 0, + Value_1 => 1); + + -- no description available + type CFSR_INVSTATE_Field is + ( + -- no invalid state UsageFault + Value_0, + -- the processor has attempted to execute an instruction that makes + -- illegal use of the EPSR + Value_1) + with Size => 1; + for CFSR_INVSTATE_Field use + (Value_0 => 0, + Value_1 => 1); + + -- no description available + type CFSR_INVPC_Field is + ( + -- no invalid PC load UsageFault + Value_0, + -- the processor has attempted an illegal load of EXC_RETURN to the PC + Value_1) + with Size => 1; + for CFSR_INVPC_Field use + (Value_0 => 0, + Value_1 => 1); + + -- no description available + type CFSR_NOCP_Field is + ( + -- no UsageFault caused by attempting to access a coprocessor + Value_0, + -- the processor has attempted to access a coprocessor + Value_1) + with Size => 1; + for CFSR_NOCP_Field use + (Value_0 => 0, + Value_1 => 1); + + -- no description available + type CFSR_UNALIGNED_Field is + ( + -- no unaligned access fault, or unaligned access trapping not enabled + Value_0, + -- the processor has made an unaligned memory access + Value_1) + with Size => 1; + for CFSR_UNALIGNED_Field use + (Value_0 => 0, + Value_1 => 1); + + -- no description available + type CFSR_DIVBYZERO_Field is + ( + -- no divide by zero fault, or divide by zero trapping not enabled + Value_0, + -- the processor has executed an SDIV or UDIV instruction with a divisor + -- of 0 + Value_1) + with Size => 1; + for CFSR_DIVBYZERO_Field use + (Value_0 => 0, + Value_1 => 1); + + -- Configurable Fault Status Registers + type SystemControl_CFSR_Register is record + -- no description available + IACCVIOL : CFSR_IACCVIOL_Field := SAM_SVD.SystemControl.Value_0; + -- no description available + DACCVIOL : CFSR_DACCVIOL_Field := SAM_SVD.SystemControl.Value_0; + -- unspecified + Reserved_2_2 : HAL.Bit := 16#0#; + -- no description available + MUNSTKERR : CFSR_MUNSTKERR_Field := SAM_SVD.SystemControl.Value_0; + -- no description available + MSTKERR : CFSR_MSTKERR_Field := SAM_SVD.SystemControl.Value_0; + -- no description available + MLSPERR : CFSR_MLSPERR_Field := SAM_SVD.SystemControl.Value_0; + -- unspecified + Reserved_6_6 : HAL.Bit := 16#0#; + -- no description available + MMARVALID : CFSR_MMARVALID_Field := SAM_SVD.SystemControl.Value_0; + -- no description available + IBUSERR : CFSR_IBUSERR_Field := SAM_SVD.SystemControl.Value_0; + -- no description available + PRECISERR : CFSR_PRECISERR_Field := SAM_SVD.SystemControl.Value_0; + -- no description available + IMPRECISERR : CFSR_IMPRECISERR_Field := + SAM_SVD.SystemControl.Value_0; + -- no description available + UNSTKERR : CFSR_UNSTKERR_Field := SAM_SVD.SystemControl.Value_0; + -- no description available + STKERR : CFSR_STKERR_Field := SAM_SVD.SystemControl.Value_0; + -- no description available + LSPERR : CFSR_LSPERR_Field := SAM_SVD.SystemControl.Value_0; + -- unspecified + Reserved_14_14 : HAL.Bit := 16#0#; + -- no description available + BFARVALID : CFSR_BFARVALID_Field := SAM_SVD.SystemControl.Value_0; + -- no description available + UNDEFINSTR : CFSR_UNDEFINSTR_Field := SAM_SVD.SystemControl.Value_0; + -- no description available + INVSTATE : CFSR_INVSTATE_Field := SAM_SVD.SystemControl.Value_0; + -- no description available + INVPC : CFSR_INVPC_Field := SAM_SVD.SystemControl.Value_0; + -- no description available + NOCP : CFSR_NOCP_Field := SAM_SVD.SystemControl.Value_0; + -- unspecified + Reserved_20_23 : HAL.UInt4 := 16#0#; + -- no description available + UNALIGNED : CFSR_UNALIGNED_Field := SAM_SVD.SystemControl.Value_0; + -- no description available + DIVBYZERO : CFSR_DIVBYZERO_Field := SAM_SVD.SystemControl.Value_0; + -- unspecified + Reserved_26_31 : HAL.UInt6 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for SystemControl_CFSR_Register use record + IACCVIOL at 0 range 0 .. 0; + DACCVIOL at 0 range 1 .. 1; + Reserved_2_2 at 0 range 2 .. 2; + MUNSTKERR at 0 range 3 .. 3; + MSTKERR at 0 range 4 .. 4; + MLSPERR at 0 range 5 .. 5; + Reserved_6_6 at 0 range 6 .. 6; + MMARVALID at 0 range 7 .. 7; + IBUSERR at 0 range 8 .. 8; + PRECISERR at 0 range 9 .. 9; + IMPRECISERR at 0 range 10 .. 10; + UNSTKERR at 0 range 11 .. 11; + STKERR at 0 range 12 .. 12; + LSPERR at 0 range 13 .. 13; + Reserved_14_14 at 0 range 14 .. 14; + BFARVALID at 0 range 15 .. 15; + UNDEFINSTR at 0 range 16 .. 16; + INVSTATE at 0 range 17 .. 17; + INVPC at 0 range 18 .. 18; + NOCP at 0 range 19 .. 19; + Reserved_20_23 at 0 range 20 .. 23; + UNALIGNED at 0 range 24 .. 24; + DIVBYZERO at 0 range 25 .. 25; + Reserved_26_31 at 0 range 26 .. 31; + end record; + + -- no description available + type HFSR_VECTTBL_Field is + ( + -- no BusFault on vector table read + Value_0, + -- BusFault on vector table read + Value_1) + with Size => 1; + for HFSR_VECTTBL_Field use + (Value_0 => 0, + Value_1 => 1); + + -- no description available + type HFSR_FORCED_Field is + ( + -- no forced HardFault + Value_0, + -- forced HardFault + Value_1) + with Size => 1; + for HFSR_FORCED_Field use + (Value_0 => 0, + Value_1 => 1); + + -- HardFault Status register + type SystemControl_HFSR_Register is record + -- unspecified + Reserved_0_0 : HAL.Bit := 16#0#; + -- no description available + VECTTBL : HFSR_VECTTBL_Field := SAM_SVD.SystemControl.Value_0; + -- unspecified + Reserved_2_29 : HAL.UInt28 := 16#0#; + -- no description available + FORCED : HFSR_FORCED_Field := SAM_SVD.SystemControl.Value_0; + -- no description available + DEBUGEVT : Boolean := False; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for SystemControl_HFSR_Register use record + Reserved_0_0 at 0 range 0 .. 0; + VECTTBL at 0 range 1 .. 1; + Reserved_2_29 at 0 range 2 .. 29; + FORCED at 0 range 30 .. 30; + DEBUGEVT at 0 range 31 .. 31; + end record; + + -- no description available + type DFSR_HALTED_Field is + ( + -- No active halt request debug event + Value_0, + -- Halt request debug event active + Value_1) + with Size => 1; + for DFSR_HALTED_Field use + (Value_0 => 0, + Value_1 => 1); + + -- no description available + type DFSR_BKPT_Field is + ( + -- No current breakpoint debug event + Value_0, + -- At least one current breakpoint debug event + Value_1) + with Size => 1; + for DFSR_BKPT_Field use + (Value_0 => 0, + Value_1 => 1); + + -- no description available + type DFSR_DWTTRAP_Field is + ( + -- No current debug events generated by the DWT + Value_0, + -- At least one current debug event generated by the DWT + Value_1) + with Size => 1; + for DFSR_DWTTRAP_Field use + (Value_0 => 0, + Value_1 => 1); + + -- no description available + type DFSR_VCATCH_Field is + ( + -- No Vector catch triggered + Value_0, + -- Vector catch triggered + Value_1) + with Size => 1; + for DFSR_VCATCH_Field use + (Value_0 => 0, + Value_1 => 1); + + -- no description available + type DFSR_EXTERNAL_Field is + ( + -- No EDBGRQ debug event + Value_0, + -- EDBGRQ debug event + Value_1) + with Size => 1; + for DFSR_EXTERNAL_Field use + (Value_0 => 0, + Value_1 => 1); + + -- Debug Fault Status Register + type SystemControl_DFSR_Register is record + -- no description available + HALTED : DFSR_HALTED_Field := SAM_SVD.SystemControl.Value_0; + -- no description available + BKPT : DFSR_BKPT_Field := SAM_SVD.SystemControl.Value_0; + -- no description available + DWTTRAP : DFSR_DWTTRAP_Field := SAM_SVD.SystemControl.Value_0; + -- no description available + VCATCH : DFSR_VCATCH_Field := SAM_SVD.SystemControl.Value_0; + -- no description available + EXTERNAL : DFSR_EXTERNAL_Field := SAM_SVD.SystemControl.Value_0; + -- unspecified + Reserved_5_31 : HAL.UInt27 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for SystemControl_DFSR_Register use record + HALTED at 0 range 0 .. 0; + BKPT at 0 range 1 .. 1; + DWTTRAP at 0 range 2 .. 2; + VCATCH at 0 range 3 .. 3; + EXTERNAL at 0 range 4 .. 4; + Reserved_5_31 at 0 range 5 .. 31; + end record; + + -- SystemControl_CPACR_CP array element + subtype SystemControl_CPACR_CP_Element is HAL.UInt2; + + -- SystemControl_CPACR_CP array + type SystemControl_CPACR_CP_Field_Array is array (10 .. 11) + of SystemControl_CPACR_CP_Element + with Component_Size => 2, Size => 4; + + -- Type definition for SystemControl_CPACR_CP + type SystemControl_CPACR_CP_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- CP as a value + Val : HAL.UInt4; + when True => + -- CP as an array + Arr : SystemControl_CPACR_CP_Field_Array; + end case; + end record + with Unchecked_Union, Size => 4; + + for SystemControl_CPACR_CP_Field use record + Val at 0 range 0 .. 3; + Arr at 0 range 0 .. 3; + end record; + + -- Coprocessor Access Control Register + type SystemControl_CPACR_Register is record + -- unspecified + Reserved_0_19 : HAL.UInt20 := 16#0#; + -- Access privileges for coprocessor 10. + CP : SystemControl_CPACR_CP_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for SystemControl_CPACR_Register use record + Reserved_0_19 at 0 range 0 .. 19; + CP at 0 range 20 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- System Control Registers + type SystemControl_Peripheral is record + -- Auxiliary Control Register, + ACTLR : aliased SystemControl_ACTLR_Register; + -- CPUID Base Register + CPUID : aliased SystemControl_CPUID_Register; + -- Interrupt Control and State Register + ICSR : aliased SystemControl_ICSR_Register; + -- Vector Table Offset Register + VTOR : aliased SystemControl_VTOR_Register; + -- Application Interrupt and Reset Control Register + AIRCR : aliased SystemControl_AIRCR_Register; + -- System Control Register + SCR : aliased SystemControl_SCR_Register; + -- Configuration and Control Register + CCR : aliased SystemControl_CCR_Register; + -- System Handler Priority Register 1 + SHPR1 : aliased SystemControl_SHPR1_Register; + -- System Handler Priority Register 2 + SHPR2 : aliased SystemControl_SHPR2_Register; + -- System Handler Priority Register 3 + SHPR3 : aliased SystemControl_SHPR3_Register; + -- System Handler Control and State Register + SHCSR : aliased SystemControl_SHCSR_Register; + -- Configurable Fault Status Registers + CFSR : aliased SystemControl_CFSR_Register; + -- HardFault Status register + HFSR : aliased SystemControl_HFSR_Register; + -- Debug Fault Status Register + DFSR : aliased SystemControl_DFSR_Register; + -- MemManage Address Register + MMFAR : aliased HAL.UInt32; + -- BusFault Address Register + BFAR : aliased HAL.UInt32; + -- Auxiliary Fault Status Register + AFSR : aliased HAL.UInt32; + -- Coprocessor Access Control Register + CPACR : aliased SystemControl_CPACR_Register; + end record + with Volatile; + + for SystemControl_Peripheral use record + ACTLR at 16#8# range 0 .. 31; + CPUID at 16#D00# range 0 .. 31; + ICSR at 16#D04# range 0 .. 31; + VTOR at 16#D08# range 0 .. 31; + AIRCR at 16#D0C# range 0 .. 31; + SCR at 16#D10# range 0 .. 31; + CCR at 16#D14# range 0 .. 31; + SHPR1 at 16#D18# range 0 .. 31; + SHPR2 at 16#D1C# range 0 .. 31; + SHPR3 at 16#D20# range 0 .. 31; + SHCSR at 16#D24# range 0 .. 31; + CFSR at 16#D28# range 0 .. 31; + HFSR at 16#D2C# range 0 .. 31; + DFSR at 16#D30# range 0 .. 31; + MMFAR at 16#D34# range 0 .. 31; + BFAR at 16#D38# range 0 .. 31; + AFSR at 16#D3C# range 0 .. 31; + CPACR at 16#D88# range 0 .. 31; + end record; + + -- System Control Registers + SystemControl_Periph : aliased SystemControl_Peripheral + with Import, Address => System'To_Address (16#E000E000#); + +end SAM_SVD.SystemControl; diff --git a/arch/ARM/SAM/svd/atsamv71/sam_svd-systick.ads b/arch/ARM/SAM/svd/atsamv71/sam_svd-systick.ads new file mode 100644 index 000000000..d23dadd04 --- /dev/null +++ b/arch/ARM/SAM/svd/atsamv71/sam_svd-systick.ads @@ -0,0 +1,190 @@ +-- This spec has been automatically generated from ATSAMV71Q21.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package SAM_SVD.SysTick is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + -- no description available + type CSR_ENABLE_Field is + ( + -- counter disabled + Value_0, + -- counter enabled + Value_1) + with Size => 1; + for CSR_ENABLE_Field use + (Value_0 => 0, + Value_1 => 1); + + -- no description available + type CSR_TICKINT_Field is + ( + -- counting down to 0 does not assert the SysTick exception request + Value_0, + -- counting down to 0 asserts the SysTick exception request + Value_1) + with Size => 1; + for CSR_TICKINT_Field use + (Value_0 => 0, + Value_1 => 1); + + -- no description available + type CSR_CLKSOURCE_Field is + ( + -- external clock + Value_0, + -- processor clock + Value_1) + with Size => 1; + for CSR_CLKSOURCE_Field use + (Value_0 => 0, + Value_1 => 1); + + -- SysTick Control and Status Register + type SysTick_CSR_Register is record + -- no description available + ENABLE : CSR_ENABLE_Field := SAM_SVD.SysTick.Value_0; + -- no description available + TICKINT : CSR_TICKINT_Field := SAM_SVD.SysTick.Value_0; + -- no description available + CLKSOURCE : CSR_CLKSOURCE_Field := SAM_SVD.SysTick.Value_0; + -- unspecified + Reserved_3_15 : HAL.UInt13 := 16#0#; + -- no description available + COUNTFLAG : Boolean := False; + -- unspecified + Reserved_17_31 : HAL.UInt15 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for SysTick_CSR_Register use record + ENABLE at 0 range 0 .. 0; + TICKINT at 0 range 1 .. 1; + CLKSOURCE at 0 range 2 .. 2; + Reserved_3_15 at 0 range 3 .. 15; + COUNTFLAG at 0 range 16 .. 16; + Reserved_17_31 at 0 range 17 .. 31; + end record; + + subtype SysTick_RVR_RELOAD_Field is HAL.UInt24; + + -- SysTick Reload Value Register + type SysTick_RVR_Register is record + -- Value to load into the SysTick Current Value Register when the + -- counter reaches 0 + RELOAD : SysTick_RVR_RELOAD_Field := 16#0#; + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for SysTick_RVR_Register use record + RELOAD at 0 range 0 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype SysTick_CVR_CURRENT_Field is HAL.UInt24; + + -- SysTick Current Value Register + type SysTick_CVR_Register is record + -- Current value at the time the register is accessed + CURRENT : SysTick_CVR_CURRENT_Field := 16#0#; + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for SysTick_CVR_Register use record + CURRENT at 0 range 0 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype SysTick_CALIB_TENMS_Field is HAL.UInt24; + + -- no description available + type CALIB_SKEW_Field is + ( + -- 10ms calibration value is exact + Value_0, + -- 10ms calibration value is inexact, because of the clock frequency + Value_1) + with Size => 1; + for CALIB_SKEW_Field use + (Value_0 => 0, + Value_1 => 1); + + -- no description available + type CALIB_NOREF_Field is + ( + -- The reference clock is provided + Value_0, + -- The reference clock is not provided + Value_1) + with Size => 1; + for CALIB_NOREF_Field use + (Value_0 => 0, + Value_1 => 1); + + -- SysTick Calibration Value Register + type SysTick_CALIB_Register is record + -- Reload value to use for 10ms timing + TENMS : SysTick_CALIB_TENMS_Field := 16#0#; + -- unspecified + Reserved_24_29 : HAL.UInt6 := 16#0#; + -- no description available + SKEW : CALIB_SKEW_Field := SAM_SVD.SysTick.Value_0; + -- no description available + NOREF : CALIB_NOREF_Field := SAM_SVD.SysTick.Value_0; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for SysTick_CALIB_Register use record + TENMS at 0 range 0 .. 23; + Reserved_24_29 at 0 range 24 .. 29; + SKEW at 0 range 30 .. 30; + NOREF at 0 range 31 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- System timer + type SysTick_Peripheral is record + -- SysTick Control and Status Register + CSR : aliased SysTick_CSR_Register; + -- SysTick Reload Value Register + RVR : aliased SysTick_RVR_Register; + -- SysTick Current Value Register + CVR : aliased SysTick_CVR_Register; + -- SysTick Calibration Value Register + CALIB : aliased SysTick_CALIB_Register; + end record + with Volatile; + + for SysTick_Peripheral use record + CSR at 16#0# range 0 .. 31; + RVR at 16#4# range 0 .. 31; + CVR at 16#8# range 0 .. 31; + CALIB at 16#C# range 0 .. 31; + end record; + + -- System timer + SysTick_Periph : aliased SysTick_Peripheral + with Import, Address => System'To_Address (16#E000E010#); + +end SAM_SVD.SysTick; diff --git a/arch/ARM/SAM/svd/atsamv71/sam_svd-tc.ads b/arch/ARM/SAM/svd/atsamv71/sam_svd-tc.ads new file mode 100644 index 000000000..7c3a5ed35 --- /dev/null +++ b/arch/ARM/SAM/svd/atsamv71/sam_svd-tc.ads @@ -0,0 +1,876 @@ +-- This spec has been automatically generated from ATSAMV71Q21.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package SAM_SVD.TC is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + --------------------------------------- + -- TC_TC_CHANNEL cluster's Registers -- + --------------------------------------- + + -- Channel Control Register (channel = 0) + type TC_TC_CCR_TC_TC_CHANNEL_Register is record + -- Write-only. Counter Clock Enable Command + CLKEN : Boolean := False; + -- Write-only. Counter Clock Disable Command + CLKDIS : Boolean := False; + -- Write-only. Software Trigger Command + SWTRG : Boolean := False; + -- unspecified + Reserved_3_31 : HAL.UInt29 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for TC_TC_CCR_TC_TC_CHANNEL_Register use record + CLKEN at 0 range 0 .. 0; + CLKDIS at 0 range 1 .. 1; + SWTRG at 0 range 2 .. 2; + Reserved_3_31 at 0 range 3 .. 31; + end record; + + -- Clock Selection + type TC_CMR_TCCLKS_Field is + ( + -- Clock selected: internal PCK6 clock signal (from PMC) + Timer_Clock1, + -- Clock selected: internal MCK/8 clock signal (from PMC) + Timer_Clock2, + -- Clock selected: internal MCK/32 clock signal (from PMC) + Timer_Clock3, + -- Clock selected: internal MCK/128 clock signal (from PMC) + Timer_Clock4, + -- Clock selected: internal SLCK clock signal (from PMC) + Timer_Clock5, + -- Clock selected: XC0 + Xc0, + -- Clock selected: XC1 + Xc1, + -- Clock selected: XC2 + Xc2) + with Size => 3; + for TC_CMR_TCCLKS_Field use + (Timer_Clock1 => 0, + Timer_Clock2 => 1, + Timer_Clock3 => 2, + Timer_Clock4 => 3, + Timer_Clock5 => 4, + Xc0 => 5, + Xc1 => 6, + Xc2 => 7); + + -- Burst Signal Selection + type TC_CMR_BURST_Field is + ( + -- The clock is not gated by an external signal. + None, + -- XC0 is ANDed with the selected clock. + Xc0, + -- XC1 is ANDed with the selected clock. + Xc1, + -- XC2 is ANDed with the selected clock. + Xc2) + with Size => 2; + for TC_CMR_BURST_Field use + (None => 0, + Xc0 => 1, + Xc1 => 2, + Xc2 => 3); + + -- External Trigger Edge Selection + type TC_CMR_ETRGEDG_Field is + ( + -- The clock is not gated by an external signal. + None, + -- Rising edge + Rising, + -- Falling edge + Falling, + -- Each edge + Edge) + with Size => 2; + for TC_CMR_ETRGEDG_Field use + (None => 0, + Rising => 1, + Falling => 2, + Edge => 3); + + -- RA Loading Edge Selection + type TC_CMR_LDRA_Field is + ( + -- None + None, + -- Rising edge of TIOAx + Rising, + -- Falling edge of TIOAx + Falling, + -- Each edge of TIOAx + Edge) + with Size => 2; + for TC_CMR_LDRA_Field use + (None => 0, + Rising => 1, + Falling => 2, + Edge => 3); + + -- RB Loading Edge Selection + type TC_CMR_LDRB_Field is + ( + -- None + None, + -- Rising edge of TIOAx + Rising, + -- Falling edge of TIOAx + Falling, + -- Each edge of TIOAx + Edge) + with Size => 2; + for TC_CMR_LDRB_Field use + (None => 0, + Rising => 1, + Falling => 2, + Edge => 3); + + -- Loading Edge Subsampling Ratio + type TC_CMR_SBSMPLR_Field is + ( + -- Load a Capture Register each selected edge + One, + -- Load a Capture Register every 2 selected edges + Half, + -- Load a Capture Register every 4 selected edges + Fourth, + -- Load a Capture Register every 8 selected edges + Eighth, + -- Load a Capture Register every 16 selected edges + Sixteenth) + with Size => 3; + for TC_CMR_SBSMPLR_Field use + (One => 0, + Half => 1, + Fourth => 2, + Eighth => 3, + Sixteenth => 4); + + -- Channel Mode Register (channel = 0) + type TC_TC_CMR_TC_TC_CHANNEL_Register is record + -- Clock Selection + TCCLKS : TC_CMR_TCCLKS_Field := SAM_SVD.TC.Timer_Clock1; + -- Clock Invert + CLKI : Boolean := False; + -- Burst Signal Selection + BURST : TC_CMR_BURST_Field := SAM_SVD.TC.None; + -- Counter Clock Stopped with RB Loading + LDBSTOP : Boolean := False; + -- Counter Clock Disable with RB Loading + LDBDIS : Boolean := False; + -- External Trigger Edge Selection + ETRGEDG : TC_CMR_ETRGEDG_Field := SAM_SVD.TC.None; + -- TIOAx or TIOBx External Trigger Selection + ABETRG : Boolean := False; + -- unspecified + Reserved_11_13 : HAL.UInt3 := 16#0#; + -- RC Compare Trigger Enable + CPCTRG : Boolean := False; + -- Waveform Mode + WAVE : Boolean := False; + -- RA Loading Edge Selection + LDRA : TC_CMR_LDRA_Field := SAM_SVD.TC.None; + -- RB Loading Edge Selection + LDRB : TC_CMR_LDRB_Field := SAM_SVD.TC.None; + -- Loading Edge Subsampling Ratio + SBSMPLR : TC_CMR_SBSMPLR_Field := SAM_SVD.TC.One; + -- unspecified + Reserved_23_31 : HAL.UInt9 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for TC_TC_CMR_TC_TC_CHANNEL_Register use record + TCCLKS at 0 range 0 .. 2; + CLKI at 0 range 3 .. 3; + BURST at 0 range 4 .. 5; + LDBSTOP at 0 range 6 .. 6; + LDBDIS at 0 range 7 .. 7; + ETRGEDG at 0 range 8 .. 9; + ABETRG at 0 range 10 .. 10; + Reserved_11_13 at 0 range 11 .. 13; + CPCTRG at 0 range 14 .. 14; + WAVE at 0 range 15 .. 15; + LDRA at 0 range 16 .. 17; + LDRB at 0 range 18 .. 19; + SBSMPLR at 0 range 20 .. 22; + Reserved_23_31 at 0 range 23 .. 31; + end record; + + -- Stepper Motor Mode Register (channel = 0) + type TC_TC_SMMR_TC_TC_CHANNEL_Register is record + -- Gray Count Enable + GCEN : Boolean := False; + -- Down Count + DOWN : Boolean := False; + -- unspecified + Reserved_2_31 : HAL.UInt30 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for TC_TC_SMMR_TC_TC_CHANNEL_Register use record + GCEN at 0 range 0 .. 0; + DOWN at 0 range 1 .. 1; + Reserved_2_31 at 0 range 2 .. 31; + end record; + + -- Status Register (channel = 0) + type TC_TC_SR_TC_TC_CHANNEL_Register is record + -- Read-only. Counter Overflow Status (cleared on read) + COVFS : Boolean; + -- Read-only. Load Overrun Status (cleared on read) + LOVRS : Boolean; + -- Read-only. RA Compare Status (cleared on read) + CPAS : Boolean; + -- Read-only. RB Compare Status (cleared on read) + CPBS : Boolean; + -- Read-only. RC Compare Status (cleared on read) + CPCS : Boolean; + -- Read-only. RA Loading Status (cleared on read) + LDRAS : Boolean; + -- Read-only. RB Loading Status (cleared on read) + LDRBS : Boolean; + -- Read-only. External Trigger Status (cleared on read) + ETRGS : Boolean; + -- unspecified + Reserved_8_15 : HAL.UInt8; + -- Read-only. Clock Enabling Status + CLKSTA : Boolean; + -- Read-only. TIOAx Mirror + MTIOA : Boolean; + -- Read-only. TIOBx Mirror + MTIOB : Boolean; + -- unspecified + Reserved_19_31 : HAL.UInt13; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for TC_TC_SR_TC_TC_CHANNEL_Register use record + COVFS at 0 range 0 .. 0; + LOVRS at 0 range 1 .. 1; + CPAS at 0 range 2 .. 2; + CPBS at 0 range 3 .. 3; + CPCS at 0 range 4 .. 4; + LDRAS at 0 range 5 .. 5; + LDRBS at 0 range 6 .. 6; + ETRGS at 0 range 7 .. 7; + Reserved_8_15 at 0 range 8 .. 15; + CLKSTA at 0 range 16 .. 16; + MTIOA at 0 range 17 .. 17; + MTIOB at 0 range 18 .. 18; + Reserved_19_31 at 0 range 19 .. 31; + end record; + + -- Interrupt Enable Register (channel = 0) + type TC_TC_IER_TC_TC_CHANNEL_Register is record + -- Write-only. Counter Overflow + COVFS : Boolean := False; + -- Write-only. Load Overrun + LOVRS : Boolean := False; + -- Write-only. RA Compare + CPAS : Boolean := False; + -- Write-only. RB Compare + CPBS : Boolean := False; + -- Write-only. RC Compare + CPCS : Boolean := False; + -- Write-only. RA Loading + LDRAS : Boolean := False; + -- Write-only. RB Loading + LDRBS : Boolean := False; + -- Write-only. External Trigger + ETRGS : Boolean := False; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for TC_TC_IER_TC_TC_CHANNEL_Register use record + COVFS at 0 range 0 .. 0; + LOVRS at 0 range 1 .. 1; + CPAS at 0 range 2 .. 2; + CPBS at 0 range 3 .. 3; + CPCS at 0 range 4 .. 4; + LDRAS at 0 range 5 .. 5; + LDRBS at 0 range 6 .. 6; + ETRGS at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- Interrupt Disable Register (channel = 0) + type TC_TC_IDR_TC_TC_CHANNEL_Register is record + -- Write-only. Counter Overflow + COVFS : Boolean := False; + -- Write-only. Load Overrun + LOVRS : Boolean := False; + -- Write-only. RA Compare + CPAS : Boolean := False; + -- Write-only. RB Compare + CPBS : Boolean := False; + -- Write-only. RC Compare + CPCS : Boolean := False; + -- Write-only. RA Loading + LDRAS : Boolean := False; + -- Write-only. RB Loading + LDRBS : Boolean := False; + -- Write-only. External Trigger + ETRGS : Boolean := False; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for TC_TC_IDR_TC_TC_CHANNEL_Register use record + COVFS at 0 range 0 .. 0; + LOVRS at 0 range 1 .. 1; + CPAS at 0 range 2 .. 2; + CPBS at 0 range 3 .. 3; + CPCS at 0 range 4 .. 4; + LDRAS at 0 range 5 .. 5; + LDRBS at 0 range 6 .. 6; + ETRGS at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- Interrupt Mask Register (channel = 0) + type TC_TC_IMR_TC_TC_CHANNEL_Register is record + -- Read-only. Counter Overflow + COVFS : Boolean; + -- Read-only. Load Overrun + LOVRS : Boolean; + -- Read-only. RA Compare + CPAS : Boolean; + -- Read-only. RB Compare + CPBS : Boolean; + -- Read-only. RC Compare + CPCS : Boolean; + -- Read-only. RA Loading + LDRAS : Boolean; + -- Read-only. RB Loading + LDRBS : Boolean; + -- Read-only. External Trigger + ETRGS : Boolean; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for TC_TC_IMR_TC_TC_CHANNEL_Register use record + COVFS at 0 range 0 .. 0; + LOVRS at 0 range 1 .. 1; + CPAS at 0 range 2 .. 2; + CPBS at 0 range 3 .. 3; + CPCS at 0 range 4 .. 4; + LDRAS at 0 range 5 .. 5; + LDRBS at 0 range 6 .. 6; + ETRGS at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- Trigger Source for Input A + type TC_EMR_TRIGSRCA_Field is + ( + -- The trigger/capture input A is driven by external pin TIOAx + External_Tioax, + -- The trigger/capture input A is driven internally by PWMx + Pwmx) + with Size => 2; + for TC_EMR_TRIGSRCA_Field use + (External_Tioax => 0, + Pwmx => 1); + + -- Trigger Source for Input B + type TC_EMR_TRIGSRCB_Field is + ( + -- The trigger/capture input B is driven by external pin TIOBx + External_Tiobx, + -- For TC0 to TC10: The trigger/capture input B is driven internally by + -- the comparator output (see Figure 7-16) of the PWMx.For TC11: The + -- trigger/capture input B is driven internally by the GTSUCOMP signal + -- of the Ethernet MAC (GMAC). + Pwmx) + with Size => 2; + for TC_EMR_TRIGSRCB_Field use + (External_Tiobx => 0, + Pwmx => 1); + + -- Extended Mode Register (channel = 0) + type TC_TC_EMR_TC_TC_CHANNEL_Register is record + -- Trigger Source for Input A + TRIGSRCA : TC_EMR_TRIGSRCA_Field := SAM_SVD.TC.External_Tioax; + -- unspecified + Reserved_2_3 : HAL.UInt2 := 16#0#; + -- Trigger Source for Input B + TRIGSRCB : TC_EMR_TRIGSRCB_Field := SAM_SVD.TC.External_Tiobx; + -- unspecified + Reserved_6_7 : HAL.UInt2 := 16#0#; + -- No Divided Clock + NODIVCLK : Boolean := False; + -- unspecified + Reserved_9_31 : HAL.UInt23 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for TC_TC_EMR_TC_TC_CHANNEL_Register use record + TRIGSRCA at 0 range 0 .. 1; + Reserved_2_3 at 0 range 2 .. 3; + TRIGSRCB at 0 range 4 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + NODIVCLK at 0 range 8 .. 8; + Reserved_9_31 at 0 range 9 .. 31; + end record; + + type TC_TC_RESERVED_Region is array (1 .. 3) of HAL.UInt32; + + -- Channel Control Register (channel = 0) + type TC_TC_CHANNEL_Cluster is record + -- Channel Control Register (channel = 0) + TC_CCR : aliased TC_TC_CCR_TC_TC_CHANNEL_Register; + -- Channel Mode Register (channel = 0) + TC_CMR : aliased TC_TC_CMR_TC_TC_CHANNEL_Register; + -- Stepper Motor Mode Register (channel = 0) + TC_SMMR : aliased TC_TC_SMMR_TC_TC_CHANNEL_Register; + -- Register AB (channel = 0) + TC_RAB : aliased HAL.UInt32; + -- Counter Value (channel = 0) + TC_CV : aliased HAL.UInt32; + -- Register A (channel = 0) + TC_RA : aliased HAL.UInt32; + -- Register B (channel = 0) + TC_RB : aliased HAL.UInt32; + -- Register C (channel = 0) + TC_RC : aliased HAL.UInt32; + -- Status Register (channel = 0) + TC_SR : aliased TC_TC_SR_TC_TC_CHANNEL_Register; + -- Interrupt Enable Register (channel = 0) + TC_IER : aliased TC_TC_IER_TC_TC_CHANNEL_Register; + -- Interrupt Disable Register (channel = 0) + TC_IDR : aliased TC_TC_IDR_TC_TC_CHANNEL_Register; + -- Interrupt Mask Register (channel = 0) + TC_IMR : aliased TC_TC_IMR_TC_TC_CHANNEL_Register; + -- Extended Mode Register (channel = 0) + TC_EMR : aliased TC_TC_EMR_TC_TC_CHANNEL_Register; + -- Reserved Regions + Reserved_34_3F : aliased TC_TC_RESERVED_Region; + end record + with Volatile, Size => 512; + + for TC_TC_CHANNEL_Cluster use record + TC_CCR at 16#0# range 0 .. 31; + TC_CMR at 16#4# range 0 .. 31; + TC_SMMR at 16#8# range 0 .. 31; + TC_RAB at 16#C# range 0 .. 31; + TC_CV at 16#10# range 0 .. 31; + TC_RA at 16#14# range 0 .. 31; + TC_RB at 16#18# range 0 .. 31; + TC_RC at 16#1C# range 0 .. 31; + TC_SR at 16#20# range 0 .. 31; + TC_IER at 16#24# range 0 .. 31; + TC_IDR at 16#28# range 0 .. 31; + TC_IMR at 16#2C# range 0 .. 31; + TC_EMR at 16#30# range 0 .. 31; + Reserved_34_3F at 16#34# range 0 .. 95; + end record; + + -- Channel Control Register (channel = 0) + type TC_TC_CHANNEL_Clusters is array (0 .. 2) of TC_TC_CHANNEL_Cluster; + + -- Block Control Register + type TC_TC_BCR_Register is record + -- Write-only. Synchro Command + SYNC : Boolean := False; + -- unspecified + Reserved_1_31 : HAL.UInt31 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for TC_TC_BCR_Register use record + SYNC at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + -- External Clock Signal 0 Selection + type TC_BMR_TC0XC0S_Field is + ( + -- Signal connected to XC0: TCLK0 + Tclk0, + -- Signal connected to XC0: TIOA1 + Tioa1, + -- Signal connected to XC0: TIOA2 + Tioa2) + with Size => 2; + for TC_BMR_TC0XC0S_Field use + (Tclk0 => 0, + Tioa1 => 2, + Tioa2 => 3); + + -- External Clock Signal 1 Selection + type TC_BMR_TC1XC1S_Field is + ( + -- Signal connected to XC1: TCLK1 + Tclk1, + -- Signal connected to XC1: TIOA0 + Tioa0, + -- Signal connected to XC1: TIOA2 + Tioa2) + with Size => 2; + for TC_BMR_TC1XC1S_Field use + (Tclk1 => 0, + Tioa0 => 2, + Tioa2 => 3); + + -- External Clock Signal 2 Selection + type TC_BMR_TC2XC2S_Field is + ( + -- Signal connected to XC2: TCLK2 + Tclk2, + -- Signal connected to XC2: TIOA0 + Tioa0, + -- Signal connected to XC2: TIOA1 + Tioa1) + with Size => 2; + for TC_BMR_TC2XC2S_Field use + (Tclk2 => 0, + Tioa0 => 2, + Tioa1 => 3); + + subtype TC_TC_BMR_MAXFILT_Field is HAL.UInt6; + + -- Block Mode Register + type TC_TC_BMR_Register is record + -- External Clock Signal 0 Selection + TC0XC0S : TC_BMR_TC0XC0S_Field := SAM_SVD.TC.Tclk0; + -- External Clock Signal 1 Selection + TC1XC1S : TC_BMR_TC1XC1S_Field := SAM_SVD.TC.Tclk1; + -- External Clock Signal 2 Selection + TC2XC2S : TC_BMR_TC2XC2S_Field := SAM_SVD.TC.Tclk2; + -- unspecified + Reserved_6_7 : HAL.UInt2 := 16#0#; + -- Quadrature Decoder Enabled + QDEN : Boolean := False; + -- Position Enabled + POSEN : Boolean := False; + -- Speed Enabled + SPEEDEN : Boolean := False; + -- Quadrature Decoding Transparent + QDTRANS : Boolean := False; + -- Edge on PHA Count Mode + EDGPHA : Boolean := False; + -- Inverted PHA + INVA : Boolean := False; + -- Inverted PHB + INVB : Boolean := False; + -- Inverted Index + INVIDX : Boolean := False; + -- Swap PHA and PHB + SWAP : Boolean := False; + -- Index Pin is PHB Pin + IDXPHB : Boolean := False; + -- unspecified + Reserved_18_19 : HAL.UInt2 := 16#0#; + -- Maximum Filter + MAXFILT : TC_TC_BMR_MAXFILT_Field := 16#0#; + -- unspecified + Reserved_26_31 : HAL.UInt6 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for TC_TC_BMR_Register use record + TC0XC0S at 0 range 0 .. 1; + TC1XC1S at 0 range 2 .. 3; + TC2XC2S at 0 range 4 .. 5; + Reserved_6_7 at 0 range 6 .. 7; + QDEN at 0 range 8 .. 8; + POSEN at 0 range 9 .. 9; + SPEEDEN at 0 range 10 .. 10; + QDTRANS at 0 range 11 .. 11; + EDGPHA at 0 range 12 .. 12; + INVA at 0 range 13 .. 13; + INVB at 0 range 14 .. 14; + INVIDX at 0 range 15 .. 15; + SWAP at 0 range 16 .. 16; + IDXPHB at 0 range 17 .. 17; + Reserved_18_19 at 0 range 18 .. 19; + MAXFILT at 0 range 20 .. 25; + Reserved_26_31 at 0 range 26 .. 31; + end record; + + -- QDEC Interrupt Enable Register + type TC_TC_QIER_Register is record + -- Write-only. Index + IDX : Boolean := False; + -- Write-only. Direction Change + DIRCHG : Boolean := False; + -- Write-only. Quadrature Error + QERR : Boolean := False; + -- unspecified + Reserved_3_31 : HAL.UInt29 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for TC_TC_QIER_Register use record + IDX at 0 range 0 .. 0; + DIRCHG at 0 range 1 .. 1; + QERR at 0 range 2 .. 2; + Reserved_3_31 at 0 range 3 .. 31; + end record; + + -- QDEC Interrupt Disable Register + type TC_TC_QIDR_Register is record + -- Write-only. Index + IDX : Boolean := False; + -- Write-only. Direction Change + DIRCHG : Boolean := False; + -- Write-only. Quadrature Error + QERR : Boolean := False; + -- unspecified + Reserved_3_31 : HAL.UInt29 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for TC_TC_QIDR_Register use record + IDX at 0 range 0 .. 0; + DIRCHG at 0 range 1 .. 1; + QERR at 0 range 2 .. 2; + Reserved_3_31 at 0 range 3 .. 31; + end record; + + -- QDEC Interrupt Mask Register + type TC_TC_QIMR_Register is record + -- Read-only. Index + IDX : Boolean; + -- Read-only. Direction Change + DIRCHG : Boolean; + -- Read-only. Quadrature Error + QERR : Boolean; + -- unspecified + Reserved_3_31 : HAL.UInt29; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for TC_TC_QIMR_Register use record + IDX at 0 range 0 .. 0; + DIRCHG at 0 range 1 .. 1; + QERR at 0 range 2 .. 2; + Reserved_3_31 at 0 range 3 .. 31; + end record; + + -- QDEC Interrupt Status Register + type TC_TC_QISR_Register is record + -- Read-only. Index + IDX : Boolean; + -- Read-only. Direction Change + DIRCHG : Boolean; + -- Read-only. Quadrature Error + QERR : Boolean; + -- unspecified + Reserved_3_7 : HAL.UInt5; + -- Read-only. Direction + DIR : Boolean; + -- unspecified + Reserved_9_31 : HAL.UInt23; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for TC_TC_QISR_Register use record + IDX at 0 range 0 .. 0; + DIRCHG at 0 range 1 .. 1; + QERR at 0 range 2 .. 2; + Reserved_3_7 at 0 range 3 .. 7; + DIR at 0 range 8 .. 8; + Reserved_9_31 at 0 range 9 .. 31; + end record; + + -- TC_TC_FMR_ENCF array + type TC_TC_FMR_ENCF_Field_Array is array (0 .. 1) of Boolean + with Component_Size => 1, Size => 2; + + -- Type definition for TC_TC_FMR_ENCF + type TC_TC_FMR_ENCF_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- ENCF as a value + Val : HAL.UInt2; + when True => + -- ENCF as an array + Arr : TC_TC_FMR_ENCF_Field_Array; + end case; + end record + with Unchecked_Union, Size => 2; + + for TC_TC_FMR_ENCF_Field use record + Val at 0 range 0 .. 1; + Arr at 0 range 0 .. 1; + end record; + + -- Fault Mode Register + type TC_TC_FMR_Register is record + -- Enable Compare Fault Channel 0 + ENCF : TC_TC_FMR_ENCF_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_2_31 : HAL.UInt30 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for TC_TC_FMR_Register use record + ENCF at 0 range 0 .. 1; + Reserved_2_31 at 0 range 2 .. 31; + end record; + + -- Write Protection Key + type TC_WPMR_WPKEY_Field is + ( + -- Reset value for the field + Tc_Wpmr_Wpkey_Field_Reset, + -- Writing any other value in this field aborts the write operation of + -- the WPEN bit.Always reads as 0. + Passwd) + with Size => 24; + for TC_WPMR_WPKEY_Field use + (Tc_Wpmr_Wpkey_Field_Reset => 0, + Passwd => 5523789); + + -- Write Protection Mode Register + type TC_TC_WPMR_Register is record + -- Write Protection Enable + WPEN : Boolean := False; + -- unspecified + Reserved_1_7 : HAL.UInt7 := 16#0#; + -- Write Protection Key + WPKEY : TC_WPMR_WPKEY_Field := Tc_Wpmr_Wpkey_Field_Reset; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for TC_TC_WPMR_Register use record + WPEN at 0 range 0 .. 0; + Reserved_1_7 at 0 range 1 .. 7; + WPKEY at 0 range 8 .. 31; + end record; + + subtype TC_TC_VER_VERSION_Field is HAL.UInt12; + subtype TC_TC_VER_MFN_Field is HAL.UInt3; + + -- Version Register + type TC_TC_VER_Register is record + -- Read-only. Version of the Hardware Module + VERSION : TC_TC_VER_VERSION_Field; + -- unspecified + Reserved_12_15 : HAL.UInt4; + -- Read-only. Metal Fix Number + MFN : TC_TC_VER_MFN_Field; + -- unspecified + Reserved_19_31 : HAL.UInt13; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for TC_TC_VER_Register use record + VERSION at 0 range 0 .. 11; + Reserved_12_15 at 0 range 12 .. 15; + MFN at 0 range 16 .. 18; + Reserved_19_31 at 0 range 19 .. 31; + end record; + + --------------------------------------- + -- TC_TC_CHANNEL cluster's Registers -- + --------------------------------------- + + --------------------------------------- + -- TC_TC_CHANNEL cluster's Registers -- + --------------------------------------- + + --------------------------------------- + -- TC_TC_CHANNEL cluster's Registers -- + --------------------------------------- + + ----------------- + -- Peripherals -- + ----------------- + + -- Timer Counter + type TC_Peripheral is record + -- Channel Control Register (channel = 0) + TC_TC_CHANNEL : aliased TC_TC_CHANNEL_Clusters; + -- Block Control Register + TC_BCR : aliased TC_TC_BCR_Register; + -- Block Mode Register + TC_BMR : aliased TC_TC_BMR_Register; + -- QDEC Interrupt Enable Register + TC_QIER : aliased TC_TC_QIER_Register; + -- QDEC Interrupt Disable Register + TC_QIDR : aliased TC_TC_QIDR_Register; + -- QDEC Interrupt Mask Register + TC_QIMR : aliased TC_TC_QIMR_Register; + -- QDEC Interrupt Status Register + TC_QISR : aliased TC_TC_QISR_Register; + -- Fault Mode Register + TC_FMR : aliased TC_TC_FMR_Register; + -- Write Protection Mode Register + TC_WPMR : aliased TC_TC_WPMR_Register; + -- Version Register + TC_VER : aliased TC_TC_VER_Register; + end record + with Volatile; + + for TC_Peripheral use record + TC_TC_CHANNEL at 16#0# range 0 .. 1535; + TC_BCR at 16#C0# range 0 .. 31; + TC_BMR at 16#C4# range 0 .. 31; + TC_QIER at 16#C8# range 0 .. 31; + TC_QIDR at 16#CC# range 0 .. 31; + TC_QIMR at 16#D0# range 0 .. 31; + TC_QISR at 16#D4# range 0 .. 31; + TC_FMR at 16#D8# range 0 .. 31; + TC_WPMR at 16#E4# range 0 .. 31; + TC_VER at 16#FC# range 0 .. 31; + end record; + + -- Timer Counter + TC0_Periph : aliased TC_Peripheral + with Import, Address => System'To_Address (16#4000C000#); + + -- Timer Counter + TC1_Periph : aliased TC_Peripheral + with Import, Address => System'To_Address (16#40010000#); + + -- Timer Counter + TC2_Periph : aliased TC_Peripheral + with Import, Address => System'To_Address (16#40014000#); + + -- Timer Counter + TC3_Periph : aliased TC_Peripheral + with Import, Address => System'To_Address (16#40054000#); + +end SAM_SVD.TC; diff --git a/arch/ARM/SAM/svd/atsamv71/sam_svd-trng.ads b/arch/ARM/SAM/svd/atsamv71/sam_svd-trng.ads new file mode 100644 index 000000000..ae78d2434 --- /dev/null +++ b/arch/ARM/SAM/svd/atsamv71/sam_svd-trng.ads @@ -0,0 +1,168 @@ +-- This spec has been automatically generated from ATSAMV71Q21.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package SAM_SVD.TRNG is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + -- Security Key + type TRNG_CR_KEY_Field is + ( + -- Reset value for the field + Trng_Cr_Key_Field_Reset, + -- Writing any other value in this field aborts the write operation. + Passwd) + with Size => 24; + for TRNG_CR_KEY_Field use + (Trng_Cr_Key_Field_Reset => 0, + Passwd => 5393991); + + -- Control Register + type TRNG_TRNG_CR_Register is record + -- Write-only. Enables the TRNG to Provide Random Values + ENABLE : Boolean := False; + -- unspecified + Reserved_1_7 : HAL.UInt7 := 16#0#; + -- Write-only. Security Key + KEY : TRNG_CR_KEY_Field := Trng_Cr_Key_Field_Reset; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for TRNG_TRNG_CR_Register use record + ENABLE at 0 range 0 .. 0; + Reserved_1_7 at 0 range 1 .. 7; + KEY at 0 range 8 .. 31; + end record; + + -- Interrupt Enable Register + type TRNG_TRNG_IER_Register is record + -- Write-only. Data Ready Interrupt Enable + DATRDY : Boolean := False; + -- unspecified + Reserved_1_31 : HAL.UInt31 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for TRNG_TRNG_IER_Register use record + DATRDY at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + -- Interrupt Disable Register + type TRNG_TRNG_IDR_Register is record + -- Write-only. Data Ready Interrupt Disable + DATRDY : Boolean := False; + -- unspecified + Reserved_1_31 : HAL.UInt31 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for TRNG_TRNG_IDR_Register use record + DATRDY at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + -- Interrupt Mask Register + type TRNG_TRNG_IMR_Register is record + -- Read-only. Data Ready Interrupt Mask + DATRDY : Boolean; + -- unspecified + Reserved_1_31 : HAL.UInt31; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for TRNG_TRNG_IMR_Register use record + DATRDY at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + -- Interrupt Status Register + type TRNG_TRNG_ISR_Register is record + -- Read-only. Data Ready + DATRDY : Boolean; + -- unspecified + Reserved_1_31 : HAL.UInt31; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for TRNG_TRNG_ISR_Register use record + DATRDY at 0 range 0 .. 0; + Reserved_1_31 at 0 range 1 .. 31; + end record; + + subtype TRNG_TRNG_VERSION_VERSION_Field is HAL.UInt12; + subtype TRNG_TRNG_VERSION_MFN_Field is HAL.UInt3; + + -- Version Register + type TRNG_TRNG_VERSION_Register is record + -- Read-only. Version of the Hardware Module + VERSION : TRNG_TRNG_VERSION_VERSION_Field; + -- unspecified + Reserved_12_15 : HAL.UInt4; + -- Read-only. Metal Fix Number + MFN : TRNG_TRNG_VERSION_MFN_Field; + -- unspecified + Reserved_19_31 : HAL.UInt13; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for TRNG_TRNG_VERSION_Register use record + VERSION at 0 range 0 .. 11; + Reserved_12_15 at 0 range 12 .. 15; + MFN at 0 range 16 .. 18; + Reserved_19_31 at 0 range 19 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- True Random Number Generator + type TRNG_Peripheral is record + -- Control Register + TRNG_CR : aliased TRNG_TRNG_CR_Register; + -- Interrupt Enable Register + TRNG_IER : aliased TRNG_TRNG_IER_Register; + -- Interrupt Disable Register + TRNG_IDR : aliased TRNG_TRNG_IDR_Register; + -- Interrupt Mask Register + TRNG_IMR : aliased TRNG_TRNG_IMR_Register; + -- Interrupt Status Register + TRNG_ISR : aliased TRNG_TRNG_ISR_Register; + -- Output Data Register + TRNG_ODATA : aliased HAL.UInt32; + -- Version Register + TRNG_VERSION : aliased TRNG_TRNG_VERSION_Register; + end record + with Volatile; + + for TRNG_Peripheral use record + TRNG_CR at 16#0# range 0 .. 31; + TRNG_IER at 16#10# range 0 .. 31; + TRNG_IDR at 16#14# range 0 .. 31; + TRNG_IMR at 16#18# range 0 .. 31; + TRNG_ISR at 16#1C# range 0 .. 31; + TRNG_ODATA at 16#50# range 0 .. 31; + TRNG_VERSION at 16#FC# range 0 .. 31; + end record; + + -- True Random Number Generator + TRNG_Periph : aliased TRNG_Peripheral + with Import, Address => System'To_Address (16#40070000#); + +end SAM_SVD.TRNG; diff --git a/arch/ARM/SAM/svd/atsamv71/sam_svd-twihs.ads b/arch/ARM/SAM/svd/atsamv71/sam_svd-twihs.ads new file mode 100644 index 000000000..9bfc4304d --- /dev/null +++ b/arch/ARM/SAM/svd/atsamv71/sam_svd-twihs.ads @@ -0,0 +1,851 @@ +-- This spec has been automatically generated from ATSAMV71Q21.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package SAM_SVD.TWIHS is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + -- Control Register + type TWIHS_TWIHS_CR_Register is record + -- Write-only. Send a START Condition + START : Boolean := False; + -- Write-only. Send a STOP Condition + STOP : Boolean := False; + -- Write-only. TWIHS Master Mode Enabled + MSEN : Boolean := False; + -- Write-only. TWIHS Master Mode Disabled + MSDIS : Boolean := False; + -- Write-only. TWIHS Slave Mode Enabled + SVEN : Boolean := False; + -- Write-only. TWIHS Slave Mode Disabled + SVDIS : Boolean := False; + -- Write-only. SMBus Quick Command + QUICK : Boolean := False; + -- Write-only. Software Reset + SWRST : Boolean := False; + -- Write-only. TWIHS High-Speed Mode Enabled + HSEN : Boolean := False; + -- Write-only. TWIHS High-Speed Mode Disabled + HSDIS : Boolean := False; + -- Write-only. SMBus Mode Enabled + SMBEN : Boolean := False; + -- Write-only. SMBus Mode Disabled + SMBDIS : Boolean := False; + -- Write-only. Packet Error Checking Enable + PECEN : Boolean := False; + -- Write-only. Packet Error Checking Disable + PECDIS : Boolean := False; + -- Write-only. PEC Request + PECRQ : Boolean := False; + -- Write-only. Bus CLEAR Command + CLEAR : Boolean := False; + -- Write-only. Alternative Command Mode Enable + ACMEN : Boolean := False; + -- Write-only. Alternative Command Mode Disable + ACMDIS : Boolean := False; + -- unspecified + Reserved_18_23 : HAL.UInt6 := 16#0#; + -- Write-only. Transmit Holding Register Clear + THRCLR : Boolean := False; + -- unspecified + Reserved_25_25 : HAL.Bit := 16#0#; + -- Write-only. Lock Clear + LOCKCLR : Boolean := False; + -- unspecified + Reserved_27_27 : HAL.Bit := 16#0#; + -- Write-only. FIFO Enable + FIFOEN : Boolean := False; + -- Write-only. FIFO Disable + FIFODIS : Boolean := False; + -- unspecified + Reserved_30_31 : HAL.UInt2 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for TWIHS_TWIHS_CR_Register use record + START at 0 range 0 .. 0; + STOP at 0 range 1 .. 1; + MSEN at 0 range 2 .. 2; + MSDIS at 0 range 3 .. 3; + SVEN at 0 range 4 .. 4; + SVDIS at 0 range 5 .. 5; + QUICK at 0 range 6 .. 6; + SWRST at 0 range 7 .. 7; + HSEN at 0 range 8 .. 8; + HSDIS at 0 range 9 .. 9; + SMBEN at 0 range 10 .. 10; + SMBDIS at 0 range 11 .. 11; + PECEN at 0 range 12 .. 12; + PECDIS at 0 range 13 .. 13; + PECRQ at 0 range 14 .. 14; + CLEAR at 0 range 15 .. 15; + ACMEN at 0 range 16 .. 16; + ACMDIS at 0 range 17 .. 17; + Reserved_18_23 at 0 range 18 .. 23; + THRCLR at 0 range 24 .. 24; + Reserved_25_25 at 0 range 25 .. 25; + LOCKCLR at 0 range 26 .. 26; + Reserved_27_27 at 0 range 27 .. 27; + FIFOEN at 0 range 28 .. 28; + FIFODIS at 0 range 29 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + -- Internal Device Address Size + type TWIHS_MMR_IADRSZ_Field is + ( + -- No internal device address + None, + -- One-byte internal device address + Val_1_Byte, + -- Two-byte internal device address + Val_2_Byte, + -- Three-byte internal device address + Val_3_Byte) + with Size => 2; + for TWIHS_MMR_IADRSZ_Field use + (None => 0, + Val_1_Byte => 1, + Val_2_Byte => 2, + Val_3_Byte => 3); + + subtype TWIHS_TWIHS_MMR_DADR_Field is HAL.UInt7; + + -- Master Mode Register + type TWIHS_TWIHS_MMR_Register is record + -- unspecified + Reserved_0_7 : HAL.UInt8 := 16#0#; + -- Internal Device Address Size + IADRSZ : TWIHS_MMR_IADRSZ_Field := SAM_SVD.TWIHS.None; + -- unspecified + Reserved_10_11 : HAL.UInt2 := 16#0#; + -- Master Read Direction + MREAD : Boolean := False; + -- unspecified + Reserved_13_15 : HAL.UInt3 := 16#0#; + -- Device Address + DADR : TWIHS_TWIHS_MMR_DADR_Field := 16#0#; + -- unspecified + Reserved_23_31 : HAL.UInt9 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for TWIHS_TWIHS_MMR_Register use record + Reserved_0_7 at 0 range 0 .. 7; + IADRSZ at 0 range 8 .. 9; + Reserved_10_11 at 0 range 10 .. 11; + MREAD at 0 range 12 .. 12; + Reserved_13_15 at 0 range 13 .. 15; + DADR at 0 range 16 .. 22; + Reserved_23_31 at 0 range 23 .. 31; + end record; + + subtype TWIHS_TWIHS_SMR_MASK_Field is HAL.UInt7; + subtype TWIHS_TWIHS_SMR_SADR_Field is HAL.UInt7; + + -- Slave Mode Register + type TWIHS_TWIHS_SMR_Register is record + -- Slave Receiver Data Phase NACK enable + NACKEN : Boolean := False; + -- unspecified + Reserved_1_1 : HAL.Bit := 16#0#; + -- SMBus Default Address + SMDA : Boolean := False; + -- SMBus Host Header + SMHH : Boolean := False; + -- unspecified + Reserved_4_5 : HAL.UInt2 := 16#0#; + -- Clock Wait State Disable + SCLWSDIS : Boolean := False; + -- unspecified + Reserved_7_7 : HAL.Bit := 16#0#; + -- Slave Address Mask + MASK : TWIHS_TWIHS_SMR_MASK_Field := 16#0#; + -- unspecified + Reserved_15_15 : HAL.Bit := 16#0#; + -- Slave Address + SADR : TWIHS_TWIHS_SMR_SADR_Field := 16#0#; + -- unspecified + Reserved_23_27 : HAL.UInt5 := 16#0#; + -- Slave Address 1 Enable + SADR1EN : Boolean := False; + -- Slave Address 2 Enable + SADR2EN : Boolean := False; + -- Slave Address 3 Enable + SADR3EN : Boolean := False; + -- Data Matching Enable + DATAMEN : Boolean := False; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for TWIHS_TWIHS_SMR_Register use record + NACKEN at 0 range 0 .. 0; + Reserved_1_1 at 0 range 1 .. 1; + SMDA at 0 range 2 .. 2; + SMHH at 0 range 3 .. 3; + Reserved_4_5 at 0 range 4 .. 5; + SCLWSDIS at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + MASK at 0 range 8 .. 14; + Reserved_15_15 at 0 range 15 .. 15; + SADR at 0 range 16 .. 22; + Reserved_23_27 at 0 range 23 .. 27; + SADR1EN at 0 range 28 .. 28; + SADR2EN at 0 range 29 .. 29; + SADR3EN at 0 range 30 .. 30; + DATAMEN at 0 range 31 .. 31; + end record; + + subtype TWIHS_TWIHS_IADR_IADR_Field is HAL.UInt24; + + -- Internal Address Register + type TWIHS_TWIHS_IADR_Register is record + -- Internal Address + IADR : TWIHS_TWIHS_IADR_IADR_Field := 16#0#; + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for TWIHS_TWIHS_IADR_Register use record + IADR at 0 range 0 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype TWIHS_TWIHS_CWGR_CLDIV_Field is HAL.UInt8; + subtype TWIHS_TWIHS_CWGR_CHDIV_Field is HAL.UInt8; + subtype TWIHS_TWIHS_CWGR_CKDIV_Field is HAL.UInt3; + subtype TWIHS_TWIHS_CWGR_HOLD_Field is HAL.UInt6; + + -- Clock Waveform Generator Register + type TWIHS_TWIHS_CWGR_Register is record + -- Clock Low Divider + CLDIV : TWIHS_TWIHS_CWGR_CLDIV_Field := 16#0#; + -- Clock High Divider + CHDIV : TWIHS_TWIHS_CWGR_CHDIV_Field := 16#0#; + -- Clock Divider + CKDIV : TWIHS_TWIHS_CWGR_CKDIV_Field := 16#0#; + -- unspecified + Reserved_19_23 : HAL.UInt5 := 16#0#; + -- TWD Hold Time Versus TWCK Falling + HOLD : TWIHS_TWIHS_CWGR_HOLD_Field := 16#0#; + -- unspecified + Reserved_30_31 : HAL.UInt2 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for TWIHS_TWIHS_CWGR_Register use record + CLDIV at 0 range 0 .. 7; + CHDIV at 0 range 8 .. 15; + CKDIV at 0 range 16 .. 18; + Reserved_19_23 at 0 range 19 .. 23; + HOLD at 0 range 24 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + -- Status Register + type TWIHS_TWIHS_SR_Register is record + -- Read-only. Transmission Completed (cleared by writing TWIHS_THR) + TXCOMP : Boolean; + -- Read-only. Receive Holding Register Ready (cleared by reading + -- TWIHS_RHR) + RXRDY : Boolean; + -- Read-only. Transmit Holding Register Ready (cleared by writing + -- TWIHS_THR) + TXRDY : Boolean; + -- Read-only. Slave Read + SVREAD : Boolean; + -- Read-only. Slave Access + SVACC : Boolean; + -- Read-only. General Call Access (cleared on read) + GACC : Boolean; + -- Read-only. Overrun Error (cleared on read) + OVRE : Boolean; + -- Read-only. Underrun Error (cleared on read) + UNRE : Boolean; + -- Read-only. Not Acknowledged (cleared on read) + NACK : Boolean; + -- Read-only. Arbitration Lost (cleared on read) + ARBLST : Boolean; + -- Read-only. Clock Wait State + SCLWS : Boolean; + -- Read-only. End Of Slave Access (cleared on read) + EOSACC : Boolean; + -- unspecified + Reserved_12_15 : HAL.UInt4; + -- Read-only. Master Code Acknowledge (cleared on read) + MCACK : Boolean; + -- unspecified + Reserved_17_17 : HAL.Bit; + -- Read-only. Timeout Error (cleared on read) + TOUT : Boolean; + -- Read-only. PEC Error (cleared on read) + PECERR : Boolean; + -- Read-only. SMBus Default Address Match (cleared on read) + SMBDAM : Boolean; + -- Read-only. SMBus Host Header Address Match (cleared on read) + SMBHHM : Boolean; + -- unspecified + Reserved_22_23 : HAL.UInt2; + -- Read-only. SCL Line Value + SCL : Boolean; + -- Read-only. SDA Line Value + SDA : Boolean; + -- unspecified + Reserved_26_31 : HAL.UInt6; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for TWIHS_TWIHS_SR_Register use record + TXCOMP at 0 range 0 .. 0; + RXRDY at 0 range 1 .. 1; + TXRDY at 0 range 2 .. 2; + SVREAD at 0 range 3 .. 3; + SVACC at 0 range 4 .. 4; + GACC at 0 range 5 .. 5; + OVRE at 0 range 6 .. 6; + UNRE at 0 range 7 .. 7; + NACK at 0 range 8 .. 8; + ARBLST at 0 range 9 .. 9; + SCLWS at 0 range 10 .. 10; + EOSACC at 0 range 11 .. 11; + Reserved_12_15 at 0 range 12 .. 15; + MCACK at 0 range 16 .. 16; + Reserved_17_17 at 0 range 17 .. 17; + TOUT at 0 range 18 .. 18; + PECERR at 0 range 19 .. 19; + SMBDAM at 0 range 20 .. 20; + SMBHHM at 0 range 21 .. 21; + Reserved_22_23 at 0 range 22 .. 23; + SCL at 0 range 24 .. 24; + SDA at 0 range 25 .. 25; + Reserved_26_31 at 0 range 26 .. 31; + end record; + + -- Interrupt Enable Register + type TWIHS_TWIHS_IER_Register is record + -- Write-only. Transmission Completed Interrupt Enable + TXCOMP : Boolean := False; + -- Write-only. Receive Holding Register Ready Interrupt Enable + RXRDY : Boolean := False; + -- Write-only. Transmit Holding Register Ready Interrupt Enable + TXRDY : Boolean := False; + -- unspecified + Reserved_3_3 : HAL.Bit := 16#0#; + -- Write-only. Slave Access Interrupt Enable + SVACC : Boolean := False; + -- Write-only. General Call Access Interrupt Enable + GACC : Boolean := False; + -- Write-only. Overrun Error Interrupt Enable + OVRE : Boolean := False; + -- Write-only. Underrun Error Interrupt Enable + UNRE : Boolean := False; + -- Write-only. Not Acknowledge Interrupt Enable + NACK : Boolean := False; + -- Write-only. Arbitration Lost Interrupt Enable + ARBLST : Boolean := False; + -- Write-only. Clock Wait State Interrupt Enable + SCL_WS : Boolean := False; + -- Write-only. End Of Slave Access Interrupt Enable + EOSACC : Boolean := False; + -- unspecified + Reserved_12_15 : HAL.UInt4 := 16#0#; + -- Write-only. Master Code Acknowledge Interrupt Enable + MCACK : Boolean := False; + -- unspecified + Reserved_17_17 : HAL.Bit := 16#0#; + -- Write-only. Timeout Error Interrupt Enable + TOUT : Boolean := False; + -- Write-only. PEC Error Interrupt Enable + PECERR : Boolean := False; + -- Write-only. SMBus Default Address Match Interrupt Enable + SMBDAM : Boolean := False; + -- Write-only. SMBus Host Header Address Match Interrupt Enable + SMBHHM : Boolean := False; + -- unspecified + Reserved_22_31 : HAL.UInt10 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for TWIHS_TWIHS_IER_Register use record + TXCOMP at 0 range 0 .. 0; + RXRDY at 0 range 1 .. 1; + TXRDY at 0 range 2 .. 2; + Reserved_3_3 at 0 range 3 .. 3; + SVACC at 0 range 4 .. 4; + GACC at 0 range 5 .. 5; + OVRE at 0 range 6 .. 6; + UNRE at 0 range 7 .. 7; + NACK at 0 range 8 .. 8; + ARBLST at 0 range 9 .. 9; + SCL_WS at 0 range 10 .. 10; + EOSACC at 0 range 11 .. 11; + Reserved_12_15 at 0 range 12 .. 15; + MCACK at 0 range 16 .. 16; + Reserved_17_17 at 0 range 17 .. 17; + TOUT at 0 range 18 .. 18; + PECERR at 0 range 19 .. 19; + SMBDAM at 0 range 20 .. 20; + SMBHHM at 0 range 21 .. 21; + Reserved_22_31 at 0 range 22 .. 31; + end record; + + -- Interrupt Disable Register + type TWIHS_TWIHS_IDR_Register is record + -- Write-only. Transmission Completed Interrupt Disable + TXCOMP : Boolean := False; + -- Write-only. Receive Holding Register Ready Interrupt Disable + RXRDY : Boolean := False; + -- Write-only. Transmit Holding Register Ready Interrupt Disable + TXRDY : Boolean := False; + -- unspecified + Reserved_3_3 : HAL.Bit := 16#0#; + -- Write-only. Slave Access Interrupt Disable + SVACC : Boolean := False; + -- Write-only. General Call Access Interrupt Disable + GACC : Boolean := False; + -- Write-only. Overrun Error Interrupt Disable + OVRE : Boolean := False; + -- Write-only. Underrun Error Interrupt Disable + UNRE : Boolean := False; + -- Write-only. Not Acknowledge Interrupt Disable + NACK : Boolean := False; + -- Write-only. Arbitration Lost Interrupt Disable + ARBLST : Boolean := False; + -- Write-only. Clock Wait State Interrupt Disable + SCL_WS : Boolean := False; + -- Write-only. End Of Slave Access Interrupt Disable + EOSACC : Boolean := False; + -- unspecified + Reserved_12_15 : HAL.UInt4 := 16#0#; + -- Write-only. Master Code Acknowledge Interrupt Disable + MCACK : Boolean := False; + -- unspecified + Reserved_17_17 : HAL.Bit := 16#0#; + -- Write-only. Timeout Error Interrupt Disable + TOUT : Boolean := False; + -- Write-only. PEC Error Interrupt Disable + PECERR : Boolean := False; + -- Write-only. SMBus Default Address Match Interrupt Disable + SMBDAM : Boolean := False; + -- Write-only. SMBus Host Header Address Match Interrupt Disable + SMBHHM : Boolean := False; + -- unspecified + Reserved_22_31 : HAL.UInt10 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for TWIHS_TWIHS_IDR_Register use record + TXCOMP at 0 range 0 .. 0; + RXRDY at 0 range 1 .. 1; + TXRDY at 0 range 2 .. 2; + Reserved_3_3 at 0 range 3 .. 3; + SVACC at 0 range 4 .. 4; + GACC at 0 range 5 .. 5; + OVRE at 0 range 6 .. 6; + UNRE at 0 range 7 .. 7; + NACK at 0 range 8 .. 8; + ARBLST at 0 range 9 .. 9; + SCL_WS at 0 range 10 .. 10; + EOSACC at 0 range 11 .. 11; + Reserved_12_15 at 0 range 12 .. 15; + MCACK at 0 range 16 .. 16; + Reserved_17_17 at 0 range 17 .. 17; + TOUT at 0 range 18 .. 18; + PECERR at 0 range 19 .. 19; + SMBDAM at 0 range 20 .. 20; + SMBHHM at 0 range 21 .. 21; + Reserved_22_31 at 0 range 22 .. 31; + end record; + + -- Interrupt Mask Register + type TWIHS_TWIHS_IMR_Register is record + -- Read-only. Transmission Completed Interrupt Mask + TXCOMP : Boolean; + -- Read-only. Receive Holding Register Ready Interrupt Mask + RXRDY : Boolean; + -- Read-only. Transmit Holding Register Ready Interrupt Mask + TXRDY : Boolean; + -- unspecified + Reserved_3_3 : HAL.Bit; + -- Read-only. Slave Access Interrupt Mask + SVACC : Boolean; + -- Read-only. General Call Access Interrupt Mask + GACC : Boolean; + -- Read-only. Overrun Error Interrupt Mask + OVRE : Boolean; + -- Read-only. Underrun Error Interrupt Mask + UNRE : Boolean; + -- Read-only. Not Acknowledge Interrupt Mask + NACK : Boolean; + -- Read-only. Arbitration Lost Interrupt Mask + ARBLST : Boolean; + -- Read-only. Clock Wait State Interrupt Mask + SCL_WS : Boolean; + -- Read-only. End Of Slave Access Interrupt Mask + EOSACC : Boolean; + -- unspecified + Reserved_12_15 : HAL.UInt4; + -- Read-only. Master Code Acknowledge Interrupt Mask + MCACK : Boolean; + -- unspecified + Reserved_17_17 : HAL.Bit; + -- Read-only. Timeout Error Interrupt Mask + TOUT : Boolean; + -- Read-only. PEC Error Interrupt Mask + PECERR : Boolean; + -- Read-only. SMBus Default Address Match Interrupt Mask + SMBDAM : Boolean; + -- Read-only. SMBus Host Header Address Match Interrupt Mask + SMBHHM : Boolean; + -- unspecified + Reserved_22_31 : HAL.UInt10; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for TWIHS_TWIHS_IMR_Register use record + TXCOMP at 0 range 0 .. 0; + RXRDY at 0 range 1 .. 1; + TXRDY at 0 range 2 .. 2; + Reserved_3_3 at 0 range 3 .. 3; + SVACC at 0 range 4 .. 4; + GACC at 0 range 5 .. 5; + OVRE at 0 range 6 .. 6; + UNRE at 0 range 7 .. 7; + NACK at 0 range 8 .. 8; + ARBLST at 0 range 9 .. 9; + SCL_WS at 0 range 10 .. 10; + EOSACC at 0 range 11 .. 11; + Reserved_12_15 at 0 range 12 .. 15; + MCACK at 0 range 16 .. 16; + Reserved_17_17 at 0 range 17 .. 17; + TOUT at 0 range 18 .. 18; + PECERR at 0 range 19 .. 19; + SMBDAM at 0 range 20 .. 20; + SMBHHM at 0 range 21 .. 21; + Reserved_22_31 at 0 range 22 .. 31; + end record; + + subtype TWIHS_TWIHS_RHR_RXDATA_Field is HAL.UInt8; + + -- Receive Holding Register + type TWIHS_TWIHS_RHR_Register is record + -- Read-only. Master or Slave Receive Holding Data + RXDATA : TWIHS_TWIHS_RHR_RXDATA_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for TWIHS_TWIHS_RHR_Register use record + RXDATA at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype TWIHS_TWIHS_THR_TXDATA_Field is HAL.UInt8; + + -- Transmit Holding Register + type TWIHS_TWIHS_THR_Register is record + -- Write-only. Master or Slave Transmit Holding Data + TXDATA : TWIHS_TWIHS_THR_TXDATA_Field := 16#0#; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for TWIHS_TWIHS_THR_Register use record + TXDATA at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype TWIHS_TWIHS_SMBTR_PRESC_Field is HAL.UInt4; + subtype TWIHS_TWIHS_SMBTR_TLOWS_Field is HAL.UInt8; + subtype TWIHS_TWIHS_SMBTR_TLOWM_Field is HAL.UInt8; + subtype TWIHS_TWIHS_SMBTR_THMAX_Field is HAL.UInt8; + + -- SMBus Timing Register + type TWIHS_TWIHS_SMBTR_Register is record + -- SMBus Clock Prescaler + PRESC : TWIHS_TWIHS_SMBTR_PRESC_Field := 16#0#; + -- unspecified + Reserved_4_7 : HAL.UInt4 := 16#0#; + -- Slave Clock Stretch Maximum Cycles + TLOWS : TWIHS_TWIHS_SMBTR_TLOWS_Field := 16#0#; + -- Master Clock Stretch Maximum Cycles + TLOWM : TWIHS_TWIHS_SMBTR_TLOWM_Field := 16#0#; + -- Clock High Maximum Cycles + THMAX : TWIHS_TWIHS_SMBTR_THMAX_Field := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for TWIHS_TWIHS_SMBTR_Register use record + PRESC at 0 range 0 .. 3; + Reserved_4_7 at 0 range 4 .. 7; + TLOWS at 0 range 8 .. 15; + TLOWM at 0 range 16 .. 23; + THMAX at 0 range 24 .. 31; + end record; + + subtype TWIHS_TWIHS_FILTR_THRES_Field is HAL.UInt3; + + -- Filter Register + type TWIHS_TWIHS_FILTR_Register is record + -- RX Digital Filter + FILT : Boolean := False; + -- PAD Filter Enable + PADFEN : Boolean := False; + -- PAD Filter Config + PADFCFG : Boolean := False; + -- unspecified + Reserved_3_7 : HAL.UInt5 := 16#0#; + -- Digital Filter Threshold + THRES : TWIHS_TWIHS_FILTR_THRES_Field := 16#0#; + -- unspecified + Reserved_11_31 : HAL.UInt21 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for TWIHS_TWIHS_FILTR_Register use record + FILT at 0 range 0 .. 0; + PADFEN at 0 range 1 .. 1; + PADFCFG at 0 range 2 .. 2; + Reserved_3_7 at 0 range 3 .. 7; + THRES at 0 range 8 .. 10; + Reserved_11_31 at 0 range 11 .. 31; + end record; + + subtype TWIHS_TWIHS_SWMR_SADR1_Field is HAL.UInt7; + subtype TWIHS_TWIHS_SWMR_SADR2_Field is HAL.UInt7; + subtype TWIHS_TWIHS_SWMR_SADR3_Field is HAL.UInt7; + subtype TWIHS_TWIHS_SWMR_DATAM_Field is HAL.UInt8; + + -- SleepWalking Matching Register + type TWIHS_TWIHS_SWMR_Register is record + -- Slave Address 1 + SADR1 : TWIHS_TWIHS_SWMR_SADR1_Field := 16#0#; + -- unspecified + Reserved_7_7 : HAL.Bit := 16#0#; + -- Slave Address 2 + SADR2 : TWIHS_TWIHS_SWMR_SADR2_Field := 16#0#; + -- unspecified + Reserved_15_15 : HAL.Bit := 16#0#; + -- Slave Address 3 + SADR3 : TWIHS_TWIHS_SWMR_SADR3_Field := 16#0#; + -- unspecified + Reserved_23_23 : HAL.Bit := 16#0#; + -- Data Match + DATAM : TWIHS_TWIHS_SWMR_DATAM_Field := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for TWIHS_TWIHS_SWMR_Register use record + SADR1 at 0 range 0 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + SADR2 at 0 range 8 .. 14; + Reserved_15_15 at 0 range 15 .. 15; + SADR3 at 0 range 16 .. 22; + Reserved_23_23 at 0 range 23 .. 23; + DATAM at 0 range 24 .. 31; + end record; + + -- Debug Register + type TWIHS_TWIHS_DR_Register is record + -- Read-only. SleepWalking Enable + SWEN : Boolean; + -- Read-only. Clock Request + CLKRQ : Boolean; + -- Read-only. SleepWalking Match + SWMATCH : Boolean; + -- Read-only. Transfer Pending + TRP : Boolean; + -- unspecified + Reserved_4_31 : HAL.UInt28; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for TWIHS_TWIHS_DR_Register use record + SWEN at 0 range 0 .. 0; + CLKRQ at 0 range 1 .. 1; + SWMATCH at 0 range 2 .. 2; + TRP at 0 range 3 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + -- Write Protection Key + type TWIHS_WPMR_WPKEY_Field is + ( + -- Reset value for the field + Twihs_Wpmr_Wpkey_Field_Reset, + -- Writing any other value in this field aborts the write operation of + -- the WPEN bit.Always reads as 0 + Passwd) + with Size => 24; + for TWIHS_WPMR_WPKEY_Field use + (Twihs_Wpmr_Wpkey_Field_Reset => 0, + Passwd => 5527369); + + -- Write Protection Mode Register + type TWIHS_TWIHS_WPMR_Register is record + -- Write Protection Enable + WPEN : Boolean := False; + -- unspecified + Reserved_1_7 : HAL.UInt7 := 16#0#; + -- Write Protection Key + WPKEY : TWIHS_WPMR_WPKEY_Field := Twihs_Wpmr_Wpkey_Field_Reset; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for TWIHS_TWIHS_WPMR_Register use record + WPEN at 0 range 0 .. 0; + Reserved_1_7 at 0 range 1 .. 7; + WPKEY at 0 range 8 .. 31; + end record; + + subtype TWIHS_TWIHS_WPSR_WPVSRC_Field is HAL.UInt24; + + -- Write Protection Status Register + type TWIHS_TWIHS_WPSR_Register is record + -- Read-only. Write Protection Violation Status + WPVS : Boolean; + -- unspecified + Reserved_1_7 : HAL.UInt7; + -- Read-only. Write Protection Violation Source + WPVSRC : TWIHS_TWIHS_WPSR_WPVSRC_Field; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for TWIHS_TWIHS_WPSR_Register use record + WPVS at 0 range 0 .. 0; + Reserved_1_7 at 0 range 1 .. 7; + WPVSRC at 0 range 8 .. 31; + end record; + + subtype TWIHS_TWIHS_VER_VERSION_Field is HAL.UInt12; + subtype TWIHS_TWIHS_VER_MFN_Field is HAL.UInt3; + + -- Version Register + type TWIHS_TWIHS_VER_Register is record + -- Read-only. Version of the Hardware Module + VERSION : TWIHS_TWIHS_VER_VERSION_Field; + -- unspecified + Reserved_12_15 : HAL.UInt4; + -- Read-only. Metal Fix Number + MFN : TWIHS_TWIHS_VER_MFN_Field; + -- unspecified + Reserved_19_31 : HAL.UInt13; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for TWIHS_TWIHS_VER_Register use record + VERSION at 0 range 0 .. 11; + Reserved_12_15 at 0 range 12 .. 15; + MFN at 0 range 16 .. 18; + Reserved_19_31 at 0 range 19 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- Two-wire Interface High Speed + type TWIHS_Peripheral is record + -- Control Register + TWIHS_CR : aliased TWIHS_TWIHS_CR_Register; + -- Master Mode Register + TWIHS_MMR : aliased TWIHS_TWIHS_MMR_Register; + -- Slave Mode Register + TWIHS_SMR : aliased TWIHS_TWIHS_SMR_Register; + -- Internal Address Register + TWIHS_IADR : aliased TWIHS_TWIHS_IADR_Register; + -- Clock Waveform Generator Register + TWIHS_CWGR : aliased TWIHS_TWIHS_CWGR_Register; + -- Status Register + TWIHS_SR : aliased TWIHS_TWIHS_SR_Register; + -- Interrupt Enable Register + TWIHS_IER : aliased TWIHS_TWIHS_IER_Register; + -- Interrupt Disable Register + TWIHS_IDR : aliased TWIHS_TWIHS_IDR_Register; + -- Interrupt Mask Register + TWIHS_IMR : aliased TWIHS_TWIHS_IMR_Register; + -- Receive Holding Register + TWIHS_RHR : aliased TWIHS_TWIHS_RHR_Register; + -- Transmit Holding Register + TWIHS_THR : aliased TWIHS_TWIHS_THR_Register; + -- SMBus Timing Register + TWIHS_SMBTR : aliased TWIHS_TWIHS_SMBTR_Register; + -- Filter Register + TWIHS_FILTR : aliased TWIHS_TWIHS_FILTR_Register; + -- SleepWalking Matching Register + TWIHS_SWMR : aliased TWIHS_TWIHS_SWMR_Register; + -- Debug Register + TWIHS_DR : aliased TWIHS_TWIHS_DR_Register; + -- Write Protection Mode Register + TWIHS_WPMR : aliased TWIHS_TWIHS_WPMR_Register; + -- Write Protection Status Register + TWIHS_WPSR : aliased TWIHS_TWIHS_WPSR_Register; + -- Version Register + TWIHS_VER : aliased TWIHS_TWIHS_VER_Register; + end record + with Volatile; + + for TWIHS_Peripheral use record + TWIHS_CR at 16#0# range 0 .. 31; + TWIHS_MMR at 16#4# range 0 .. 31; + TWIHS_SMR at 16#8# range 0 .. 31; + TWIHS_IADR at 16#C# range 0 .. 31; + TWIHS_CWGR at 16#10# range 0 .. 31; + TWIHS_SR at 16#20# range 0 .. 31; + TWIHS_IER at 16#24# range 0 .. 31; + TWIHS_IDR at 16#28# range 0 .. 31; + TWIHS_IMR at 16#2C# range 0 .. 31; + TWIHS_RHR at 16#30# range 0 .. 31; + TWIHS_THR at 16#34# range 0 .. 31; + TWIHS_SMBTR at 16#38# range 0 .. 31; + TWIHS_FILTR at 16#44# range 0 .. 31; + TWIHS_SWMR at 16#4C# range 0 .. 31; + TWIHS_DR at 16#D0# range 0 .. 31; + TWIHS_WPMR at 16#E4# range 0 .. 31; + TWIHS_WPSR at 16#E8# range 0 .. 31; + TWIHS_VER at 16#FC# range 0 .. 31; + end record; + + -- Two-wire Interface High Speed + TWIHS0_Periph : aliased TWIHS_Peripheral + with Import, Address => System'To_Address (16#40018000#); + + -- Two-wire Interface High Speed + TWIHS1_Periph : aliased TWIHS_Peripheral + with Import, Address => System'To_Address (16#4001C000#); + + -- Two-wire Interface High Speed + TWIHS2_Periph : aliased TWIHS_Peripheral + with Import, Address => System'To_Address (16#40060000#); + +end SAM_SVD.TWIHS; diff --git a/arch/ARM/SAM/svd/atsamv71/sam_svd-uart.ads b/arch/ARM/SAM/svd/atsamv71/sam_svd-uart.ads new file mode 100644 index 000000000..3598748ea --- /dev/null +++ b/arch/ARM/SAM/svd/atsamv71/sam_svd-uart.ads @@ -0,0 +1,566 @@ +-- This spec has been automatically generated from ATSAMV71Q21.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package SAM_SVD.UART is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + -- Control Register + type UART_UART_CR_Register is record + -- unspecified + Reserved_0_1 : HAL.UInt2 := 16#0#; + -- Write-only. Reset Receiver + RSTRX : Boolean := False; + -- Write-only. Reset Transmitter + RSTTX : Boolean := False; + -- Write-only. Receiver Enable + RXEN : Boolean := False; + -- Write-only. Receiver Disable + RXDIS : Boolean := False; + -- Write-only. Transmitter Enable + TXEN : Boolean := False; + -- Write-only. Transmitter Disable + TXDIS : Boolean := False; + -- Write-only. Reset Status + RSTSTA : Boolean := False; + -- unspecified + Reserved_9_11 : HAL.UInt3 := 16#0#; + -- Write-only. Request Clear + REQCLR : Boolean := False; + -- unspecified + Reserved_13_14 : HAL.UInt2 := 16#0#; + -- Write-only. Debug Enable + DBGE : Boolean := False; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for UART_UART_CR_Register use record + Reserved_0_1 at 0 range 0 .. 1; + RSTRX at 0 range 2 .. 2; + RSTTX at 0 range 3 .. 3; + RXEN at 0 range 4 .. 4; + RXDIS at 0 range 5 .. 5; + TXEN at 0 range 6 .. 6; + TXDIS at 0 range 7 .. 7; + RSTSTA at 0 range 8 .. 8; + Reserved_9_11 at 0 range 9 .. 11; + REQCLR at 0 range 12 .. 12; + Reserved_13_14 at 0 range 13 .. 14; + DBGE at 0 range 15 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + -- Receiver Digital Filter + type UART_MR_FILTER_Field is + ( + -- UART does not filter the receive line. + Disabled, + -- UART filters the receive line using a three-sample filter (16x-bit + -- clock) (2 over 3 majority). + Enabled) + with Size => 1; + for UART_MR_FILTER_Field use + (Disabled => 0, + Enabled => 1); + + -- Parity Type + type UART_MR_PAR_Field is + ( + -- Even Parity + Even, + -- Odd Parity + Odd, + -- Space: parity forced to 0 + Space, + -- Mark: parity forced to 1 + Mark, + -- No parity + No) + with Size => 3; + for UART_MR_PAR_Field use + (Even => 0, + Odd => 1, + Space => 2, + Mark => 3, + No => 4); + + -- Baud Rate Source Clock + type UART_MR_BRSRCCK_Field is + ( + -- The baud rate is driven by the peripheral clock + Periph_Clk, + -- The baud rate is driven by a PMC-programmable clock PCK (see section + -- Power Management Controller (PMC)). + Pmc_Pck) + with Size => 1; + for UART_MR_BRSRCCK_Field use + (Periph_Clk => 0, + Pmc_Pck => 1); + + -- Channel Mode + type UART_MR_CHMODE_Field is + ( + -- Normal mode + Normal, + -- Automatic echo + Automatic, + -- Local loopback + Local_Loopback, + -- Remote loopback + Remote_Loopback) + with Size => 2; + for UART_MR_CHMODE_Field use + (Normal => 0, + Automatic => 1, + Local_Loopback => 2, + Remote_Loopback => 3); + + -- Mode Register + type UART_UART_MR_Register is record + -- unspecified + Reserved_0_3 : HAL.UInt4 := 16#0#; + -- Receiver Digital Filter + FILTER : UART_MR_FILTER_Field := SAM_SVD.UART.Disabled; + -- unspecified + Reserved_5_8 : HAL.UInt4 := 16#0#; + -- Parity Type + PAR : UART_MR_PAR_Field := SAM_SVD.UART.Even; + -- Baud Rate Source Clock + BRSRCCK : UART_MR_BRSRCCK_Field := SAM_SVD.UART.Periph_Clk; + -- unspecified + Reserved_13_13 : HAL.Bit := 16#0#; + -- Channel Mode + CHMODE : UART_MR_CHMODE_Field := SAM_SVD.UART.Normal; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for UART_UART_MR_Register use record + Reserved_0_3 at 0 range 0 .. 3; + FILTER at 0 range 4 .. 4; + Reserved_5_8 at 0 range 5 .. 8; + PAR at 0 range 9 .. 11; + BRSRCCK at 0 range 12 .. 12; + Reserved_13_13 at 0 range 13 .. 13; + CHMODE at 0 range 14 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + -- Interrupt Enable Register + type UART_UART_IER_Register is record + -- Write-only. Enable RXRDY Interrupt + RXRDY : Boolean := False; + -- Write-only. Enable TXRDY Interrupt + TXRDY : Boolean := False; + -- unspecified + Reserved_2_4 : HAL.UInt3 := 16#0#; + -- Write-only. Enable Overrun Error Interrupt + OVRE : Boolean := False; + -- Write-only. Enable Framing Error Interrupt + FRAME : Boolean := False; + -- Write-only. Enable Parity Error Interrupt + PARE : Boolean := False; + -- unspecified + Reserved_8_8 : HAL.Bit := 16#0#; + -- Write-only. Enable TXEMPTY Interrupt + TXEMPTY : Boolean := False; + -- unspecified + Reserved_10_14 : HAL.UInt5 := 16#0#; + -- Write-only. Enable Comparison Interrupt + CMP : Boolean := False; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for UART_UART_IER_Register use record + RXRDY at 0 range 0 .. 0; + TXRDY at 0 range 1 .. 1; + Reserved_2_4 at 0 range 2 .. 4; + OVRE at 0 range 5 .. 5; + FRAME at 0 range 6 .. 6; + PARE at 0 range 7 .. 7; + Reserved_8_8 at 0 range 8 .. 8; + TXEMPTY at 0 range 9 .. 9; + Reserved_10_14 at 0 range 10 .. 14; + CMP at 0 range 15 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + -- Interrupt Disable Register + type UART_UART_IDR_Register is record + -- Write-only. Disable RXRDY Interrupt + RXRDY : Boolean := False; + -- Write-only. Disable TXRDY Interrupt + TXRDY : Boolean := False; + -- unspecified + Reserved_2_4 : HAL.UInt3 := 16#0#; + -- Write-only. Disable Overrun Error Interrupt + OVRE : Boolean := False; + -- Write-only. Disable Framing Error Interrupt + FRAME : Boolean := False; + -- Write-only. Disable Parity Error Interrupt + PARE : Boolean := False; + -- unspecified + Reserved_8_8 : HAL.Bit := 16#0#; + -- Write-only. Disable TXEMPTY Interrupt + TXEMPTY : Boolean := False; + -- unspecified + Reserved_10_14 : HAL.UInt5 := 16#0#; + -- Write-only. Disable Comparison Interrupt + CMP : Boolean := False; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for UART_UART_IDR_Register use record + RXRDY at 0 range 0 .. 0; + TXRDY at 0 range 1 .. 1; + Reserved_2_4 at 0 range 2 .. 4; + OVRE at 0 range 5 .. 5; + FRAME at 0 range 6 .. 6; + PARE at 0 range 7 .. 7; + Reserved_8_8 at 0 range 8 .. 8; + TXEMPTY at 0 range 9 .. 9; + Reserved_10_14 at 0 range 10 .. 14; + CMP at 0 range 15 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + -- Interrupt Mask Register + type UART_UART_IMR_Register is record + -- Read-only. Mask RXRDY Interrupt + RXRDY : Boolean; + -- Read-only. Disable TXRDY Interrupt + TXRDY : Boolean; + -- unspecified + Reserved_2_4 : HAL.UInt3; + -- Read-only. Mask Overrun Error Interrupt + OVRE : Boolean; + -- Read-only. Mask Framing Error Interrupt + FRAME : Boolean; + -- Read-only. Mask Parity Error Interrupt + PARE : Boolean; + -- unspecified + Reserved_8_8 : HAL.Bit; + -- Read-only. Mask TXEMPTY Interrupt + TXEMPTY : Boolean; + -- unspecified + Reserved_10_14 : HAL.UInt5; + -- Read-only. Mask Comparison Interrupt + CMP : Boolean; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for UART_UART_IMR_Register use record + RXRDY at 0 range 0 .. 0; + TXRDY at 0 range 1 .. 1; + Reserved_2_4 at 0 range 2 .. 4; + OVRE at 0 range 5 .. 5; + FRAME at 0 range 6 .. 6; + PARE at 0 range 7 .. 7; + Reserved_8_8 at 0 range 8 .. 8; + TXEMPTY at 0 range 9 .. 9; + Reserved_10_14 at 0 range 10 .. 14; + CMP at 0 range 15 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + -- Status Register + type UART_UART_SR_Register is record + -- Read-only. Receiver Ready + RXRDY : Boolean; + -- Read-only. Transmitter Ready + TXRDY : Boolean; + -- unspecified + Reserved_2_4 : HAL.UInt3; + -- Read-only. Overrun Error + OVRE : Boolean; + -- Read-only. Framing Error + FRAME : Boolean; + -- Read-only. Parity Error + PARE : Boolean; + -- unspecified + Reserved_8_8 : HAL.Bit; + -- Read-only. Transmitter Empty + TXEMPTY : Boolean; + -- unspecified + Reserved_10_14 : HAL.UInt5; + -- Read-only. Comparison Match + CMP : Boolean; + -- unspecified + Reserved_16_20 : HAL.UInt5; + -- Read-only. SleepWalking Enable Status + SWES : Boolean; + -- Read-only. Clock Request + CLKREQ : Boolean; + -- Read-only. Wake-Up Request + WKUPREQ : Boolean; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for UART_UART_SR_Register use record + RXRDY at 0 range 0 .. 0; + TXRDY at 0 range 1 .. 1; + Reserved_2_4 at 0 range 2 .. 4; + OVRE at 0 range 5 .. 5; + FRAME at 0 range 6 .. 6; + PARE at 0 range 7 .. 7; + Reserved_8_8 at 0 range 8 .. 8; + TXEMPTY at 0 range 9 .. 9; + Reserved_10_14 at 0 range 10 .. 14; + CMP at 0 range 15 .. 15; + Reserved_16_20 at 0 range 16 .. 20; + SWES at 0 range 21 .. 21; + CLKREQ at 0 range 22 .. 22; + WKUPREQ at 0 range 23 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype UART_UART_RHR_RXCHR_Field is HAL.UInt8; + + -- Receive Holding Register + type UART_UART_RHR_Register is record + -- Read-only. Received Character + RXCHR : UART_UART_RHR_RXCHR_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for UART_UART_RHR_Register use record + RXCHR at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype UART_UART_THR_TXCHR_Field is HAL.UInt8; + + -- Transmit Holding Register + type UART_UART_THR_Register is record + -- Write-only. Character to be Transmitted + TXCHR : UART_UART_THR_TXCHR_Field := 16#0#; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for UART_UART_THR_Register use record + TXCHR at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype UART_UART_BRGR_CD_Field is HAL.UInt16; + + -- Baud Rate Generator Register + type UART_UART_BRGR_Register is record + -- Clock Divisor + CD : UART_UART_BRGR_CD_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for UART_UART_BRGR_Register use record + CD at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype UART_UART_CMPR_VAL1_Field is HAL.UInt8; + + -- Comparison Mode + type UART_CMPR_CMPMODE_Field is + ( + -- Any character is received and comparison function drives CMP flag. + Flag_Only, + -- Comparison condition must be met to start reception. + Start_Condition) + with Size => 1; + for UART_CMPR_CMPMODE_Field use + (Flag_Only => 0, + Start_Condition => 1); + + subtype UART_UART_CMPR_VAL2_Field is HAL.UInt8; + + -- Comparison Register + type UART_UART_CMPR_Register is record + -- First Comparison Value for Received Character + VAL1 : UART_UART_CMPR_VAL1_Field := 16#0#; + -- unspecified + Reserved_8_11 : HAL.UInt4 := 16#0#; + -- Comparison Mode + CMPMODE : UART_CMPR_CMPMODE_Field := SAM_SVD.UART.Flag_Only; + -- unspecified + Reserved_13_13 : HAL.Bit := 16#0#; + -- Compare Parity + CMPPAR : Boolean := False; + -- unspecified + Reserved_15_15 : HAL.Bit := 16#0#; + -- Second Comparison Value for Received Character + VAL2 : UART_UART_CMPR_VAL2_Field := 16#0#; + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for UART_UART_CMPR_Register use record + VAL1 at 0 range 0 .. 7; + Reserved_8_11 at 0 range 8 .. 11; + CMPMODE at 0 range 12 .. 12; + Reserved_13_13 at 0 range 13 .. 13; + CMPPAR at 0 range 14 .. 14; + Reserved_15_15 at 0 range 15 .. 15; + VAL2 at 0 range 16 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- Write Protection Key + type UART_WPMR_WPKEY_Field is + ( + -- Reset value for the field + Uart_Wpmr_Wpkey_Field_Reset, + -- Writing any other value in this field aborts the write + -- operation.Always reads as 0. + Passwd) + with Size => 24; + for UART_WPMR_WPKEY_Field use + (Uart_Wpmr_Wpkey_Field_Reset => 0, + Passwd => 5587282); + + -- Write Protection Mode Register + type UART_UART_WPMR_Register is record + -- Write Protection Enable + WPEN : Boolean := False; + -- unspecified + Reserved_1_7 : HAL.UInt7 := 16#0#; + -- Write Protection Key + WPKEY : UART_WPMR_WPKEY_Field := Uart_Wpmr_Wpkey_Field_Reset; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for UART_UART_WPMR_Register use record + WPEN at 0 range 0 .. 0; + Reserved_1_7 at 0 range 1 .. 7; + WPKEY at 0 range 8 .. 31; + end record; + + subtype UART_UART_VERSION_VERSION_Field is HAL.UInt12; + subtype UART_UART_VERSION_MFN_Field is HAL.UInt3; + + -- Version Register + type UART_UART_VERSION_Register is record + -- Read-only. Hardware Module Version + VERSION : UART_UART_VERSION_VERSION_Field; + -- unspecified + Reserved_12_15 : HAL.UInt4; + -- Read-only. Metal Fix Number + MFN : UART_UART_VERSION_MFN_Field; + -- unspecified + Reserved_19_31 : HAL.UInt13; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for UART_UART_VERSION_Register use record + VERSION at 0 range 0 .. 11; + Reserved_12_15 at 0 range 12 .. 15; + MFN at 0 range 16 .. 18; + Reserved_19_31 at 0 range 19 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- Universal Asynchronous Receiver Transmitter + type UART_Peripheral is record + -- Control Register + UART_CR : aliased UART_UART_CR_Register; + -- Mode Register + UART_MR : aliased UART_UART_MR_Register; + -- Interrupt Enable Register + UART_IER : aliased UART_UART_IER_Register; + -- Interrupt Disable Register + UART_IDR : aliased UART_UART_IDR_Register; + -- Interrupt Mask Register + UART_IMR : aliased UART_UART_IMR_Register; + -- Status Register + UART_SR : aliased UART_UART_SR_Register; + -- Receive Holding Register + UART_RHR : aliased UART_UART_RHR_Register; + -- Transmit Holding Register + UART_THR : aliased UART_UART_THR_Register; + -- Baud Rate Generator Register + UART_BRGR : aliased UART_UART_BRGR_Register; + -- Comparison Register + UART_CMPR : aliased UART_UART_CMPR_Register; + -- Write Protection Mode Register + UART_WPMR : aliased UART_UART_WPMR_Register; + -- Version Register + UART_VERSION : aliased UART_UART_VERSION_Register; + end record + with Volatile; + + for UART_Peripheral use record + UART_CR at 16#0# range 0 .. 31; + UART_MR at 16#4# range 0 .. 31; + UART_IER at 16#8# range 0 .. 31; + UART_IDR at 16#C# range 0 .. 31; + UART_IMR at 16#10# range 0 .. 31; + UART_SR at 16#14# range 0 .. 31; + UART_RHR at 16#18# range 0 .. 31; + UART_THR at 16#1C# range 0 .. 31; + UART_BRGR at 16#20# range 0 .. 31; + UART_CMPR at 16#24# range 0 .. 31; + UART_WPMR at 16#E4# range 0 .. 31; + UART_VERSION at 16#FC# range 0 .. 31; + end record; + + -- Universal Asynchronous Receiver Transmitter + UART0_Periph : aliased UART_Peripheral + with Import, Address => System'To_Address (16#400E0800#); + + -- Universal Asynchronous Receiver Transmitter + UART1_Periph : aliased UART_Peripheral + with Import, Address => System'To_Address (16#400E0A00#); + + -- Universal Asynchronous Receiver Transmitter + UART2_Periph : aliased UART_Peripheral + with Import, Address => System'To_Address (16#400E1A00#); + + -- Universal Asynchronous Receiver Transmitter + UART3_Periph : aliased UART_Peripheral + with Import, Address => System'To_Address (16#400E1C00#); + + -- Universal Asynchronous Receiver Transmitter + UART4_Periph : aliased UART_Peripheral + with Import, Address => System'To_Address (16#400E1E00#); + +end SAM_SVD.UART; diff --git a/arch/ARM/SAM/svd/atsamv71/sam_svd-usart.ads b/arch/ARM/SAM/svd/atsamv71/sam_svd-usart.ads new file mode 100644 index 000000000..001f14b8d --- /dev/null +++ b/arch/ARM/SAM/svd/atsamv71/sam_svd-usart.ads @@ -0,0 +1,1349 @@ +-- This spec has been automatically generated from ATSAMV71Q21.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package SAM_SVD.USART is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + -- Control Register + type USART_US_CR_Register is record + -- unspecified + Reserved_0_1 : HAL.UInt2 := 16#0#; + -- Write-only. Reset Receiver + RSTRX : Boolean := False; + -- Write-only. Reset Transmitter + RSTTX : Boolean := False; + -- Write-only. Receiver Enable + RXEN : Boolean := False; + -- Write-only. Receiver Disable + RXDIS : Boolean := False; + -- Write-only. Transmitter Enable + TXEN : Boolean := False; + -- Write-only. Transmitter Disable + TXDIS : Boolean := False; + -- Write-only. Reset Status Bits + RSTSTA : Boolean := False; + -- Write-only. Start Break + STTBRK : Boolean := False; + -- Write-only. Stop Break + STPBRK : Boolean := False; + -- Write-only. Clear TIMEOUT Flag and Start Timeout After Next Character + -- Received + STTTO : Boolean := False; + -- Write-only. Send Address + SENDA : Boolean := False; + -- Write-only. Reset Iterations + RSTIT : Boolean := False; + -- Write-only. Reset Non Acknowledge + RSTNACK : Boolean := False; + -- Write-only. Start Timeout Immediately + RETTO : Boolean := False; + -- Write-only. Data Terminal Ready Enable + DTREN : Boolean := False; + -- Write-only. Data Terminal Ready Disable + DTRDIS : Boolean := False; + -- Write-only. Request to Send Pin Control + RTSEN : Boolean := False; + -- Write-only. Request to Send Pin Control + RTSDIS : Boolean := False; + -- Write-only. Abort LIN Transmission + LINABT : Boolean := False; + -- Write-only. Send LIN Wakeup Signal + LINWKUP : Boolean := False; + -- unspecified + Reserved_22_31 : HAL.UInt10 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for USART_US_CR_Register use record + Reserved_0_1 at 0 range 0 .. 1; + RSTRX at 0 range 2 .. 2; + RSTTX at 0 range 3 .. 3; + RXEN at 0 range 4 .. 4; + RXDIS at 0 range 5 .. 5; + TXEN at 0 range 6 .. 6; + TXDIS at 0 range 7 .. 7; + RSTSTA at 0 range 8 .. 8; + STTBRK at 0 range 9 .. 9; + STPBRK at 0 range 10 .. 10; + STTTO at 0 range 11 .. 11; + SENDA at 0 range 12 .. 12; + RSTIT at 0 range 13 .. 13; + RSTNACK at 0 range 14 .. 14; + RETTO at 0 range 15 .. 15; + DTREN at 0 range 16 .. 16; + DTRDIS at 0 range 17 .. 17; + RTSEN at 0 range 18 .. 18; + RTSDIS at 0 range 19 .. 19; + LINABT at 0 range 20 .. 20; + LINWKUP at 0 range 21 .. 21; + Reserved_22_31 at 0 range 22 .. 31; + end record; + + -- USART Mode of Operation + type US_MR_USART_MODE_Field is + ( + -- Normal mode + Normal, + -- RS485 + Rs485, + -- Hardware Handshaking + Hw_Handshaking, + -- Modem + Modem, + -- IS07816 Protocol: T = 0 + Is07816_T_0, + -- IS07816 Protocol: T = 1 + Is07816_T_1, + -- IrDA + Irda, + -- LON + Lon, + -- SPI master mode (CLKO must be written to 1 and USCLKS = 0, 1 or 2) + Spi_Master, + -- SPI Slave mode + Spi_Slave) + with Size => 4; + for US_MR_USART_MODE_Field use + (Normal => 0, + Rs485 => 1, + Hw_Handshaking => 2, + Modem => 3, + Is07816_T_0 => 4, + Is07816_T_1 => 6, + Irda => 8, + Lon => 9, + Spi_Master => 14, + Spi_Slave => 15); + + -- Clock Selection + type US_MR_USCLKS_Field is + ( + -- Peripheral clock is selected + Mck, + -- Peripheral clock divided (DIV=DIV=8) is selected + Div, + -- PMC programmable clock (PCK) is selected. If the SCK pin is driven + -- (CLKO = 1), the CD field must be greater than 1. + Pck, + -- Serial clock (SCK) is selected + Sck) + with Size => 2; + for US_MR_USCLKS_Field use + (Mck => 0, + Div => 1, + Pck => 2, + Sck => 3); + + -- Character Length + type US_MR_CHRL_Field is + ( + -- Character length is 5 bits + Val_5_Bit, + -- Character length is 6 bits + Val_6_Bit, + -- Character length is 7 bits + Val_7_Bit, + -- Character length is 8 bits + Val_8_Bit) + with Size => 2; + for US_MR_CHRL_Field use + (Val_5_Bit => 0, + Val_6_Bit => 1, + Val_7_Bit => 2, + Val_8_Bit => 3); + + -- Parity Type + type US_MR_PAR_Field is + ( + -- Even parity + Even, + -- Odd parity + Odd, + -- Parity forced to 0 (Space) + Space, + -- Parity forced to 1 (Mark) + Mark, + -- No parity + No, + -- Multidrop mode + Multidrop) + with Size => 3; + for US_MR_PAR_Field use + (Even => 0, + Odd => 1, + Space => 2, + Mark => 3, + No => 4, + Multidrop => 6); + + -- Number of Stop Bits + type US_MR_NBSTOP_Field is + ( + -- 1 stop bit + Val_1_Bit, + -- 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) + Val_1_5_Bit, + -- 2 stop bits + Val_2_Bit) + with Size => 2; + for US_MR_NBSTOP_Field use + (Val_1_Bit => 0, + Val_1_5_Bit => 1, + Val_2_Bit => 2); + + -- Channel Mode + type US_MR_CHMODE_Field is + ( + -- Normal mode + Normal, + -- Automatic Echo. Receiver input is connected to the TXD pin. + Automatic, + -- Local Loopback. Transmitter output is connected to the Receiver + -- Input. + Local_Loopback, + -- Remote Loopback. RXD pin is internally connected to the TXD pin. + Remote_Loopback) + with Size => 2; + for US_MR_CHMODE_Field use + (Normal => 0, + Automatic => 1, + Local_Loopback => 2, + Remote_Loopback => 3); + + subtype USART_US_MR_MAX_ITERATION_Field is HAL.UInt3; + + -- Mode Register + type USART_US_MR_Register is record + -- USART Mode of Operation + USART_MODE : US_MR_USART_MODE_Field := SAM_SVD.USART.Normal; + -- Clock Selection + USCLKS : US_MR_USCLKS_Field := SAM_SVD.USART.Mck; + -- Character Length + CHRL : US_MR_CHRL_Field := SAM_SVD.USART.Val_5_Bit; + -- Synchronous Mode Select + SYNC : Boolean := False; + -- Parity Type + PAR : US_MR_PAR_Field := SAM_SVD.USART.Even; + -- Number of Stop Bits + NBSTOP : US_MR_NBSTOP_Field := SAM_SVD.USART.Val_1_Bit; + -- Channel Mode + CHMODE : US_MR_CHMODE_Field := SAM_SVD.USART.Normal; + -- Bit Order + MSBF : Boolean := False; + -- 9-bit Character Length + MODE9 : Boolean := False; + -- Clock Output Select + CLKO : Boolean := False; + -- Oversampling Mode + OVER : Boolean := False; + -- Inhibit Non Acknowledge + INACK : Boolean := False; + -- Disable Successive NACK + DSNACK : Boolean := False; + -- Variable Synchronization of Command/Data Sync Start Frame Delimiter + VAR_SYNC : Boolean := False; + -- Inverted Data + INVDATA : Boolean := False; + -- Maximum Number of Automatic Iteration + MAX_ITERATION : USART_US_MR_MAX_ITERATION_Field := 16#0#; + -- unspecified + Reserved_27_27 : HAL.Bit := 16#0#; + -- Receive Line Filter + FILTER : Boolean := False; + -- Manchester Encoder/Decoder Enable + MAN : Boolean := False; + -- Manchester Synchronization Mode + MODSYNC : Boolean := False; + -- Start Frame Delimiter Selector + ONEBIT : Boolean := False; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for USART_US_MR_Register use record + USART_MODE at 0 range 0 .. 3; + USCLKS at 0 range 4 .. 5; + CHRL at 0 range 6 .. 7; + SYNC at 0 range 8 .. 8; + PAR at 0 range 9 .. 11; + NBSTOP at 0 range 12 .. 13; + CHMODE at 0 range 14 .. 15; + MSBF at 0 range 16 .. 16; + MODE9 at 0 range 17 .. 17; + CLKO at 0 range 18 .. 18; + OVER at 0 range 19 .. 19; + INACK at 0 range 20 .. 20; + DSNACK at 0 range 21 .. 21; + VAR_SYNC at 0 range 22 .. 22; + INVDATA at 0 range 23 .. 23; + MAX_ITERATION at 0 range 24 .. 26; + Reserved_27_27 at 0 range 27 .. 27; + FILTER at 0 range 28 .. 28; + MAN at 0 range 29 .. 29; + MODSYNC at 0 range 30 .. 30; + ONEBIT at 0 range 31 .. 31; + end record; + + -- Interrupt Enable Register + type USART_US_IER_Register is record + -- Write-only. RXRDY Interrupt Enable + RXRDY : Boolean := False; + -- Write-only. TXRDY Interrupt Enable + TXRDY : Boolean := False; + -- Write-only. Receiver Break Interrupt Enable + RXBRK : Boolean := False; + -- unspecified + Reserved_3_4 : HAL.UInt2 := 16#0#; + -- Write-only. Overrun Error Interrupt Enable + OVRE : Boolean := False; + -- Write-only. Framing Error Interrupt Enable + FRAME : Boolean := False; + -- Write-only. Parity Error Interrupt Enable + PARE : Boolean := False; + -- Write-only. Timeout Interrupt Enable + TIMEOUT : Boolean := False; + -- Write-only. TXEMPTY Interrupt Enable + TXEMPTY : Boolean := False; + -- Write-only. Max number of Repetitions Reached Interrupt Enable + ITER : Boolean := False; + -- unspecified + Reserved_11_12 : HAL.UInt2 := 16#0#; + -- Write-only. Non Acknowledge Interrupt Enable + NACK : Boolean := False; + -- unspecified + Reserved_14_15 : HAL.UInt2 := 16#0#; + -- Write-only. Ring Indicator Input Change Enable + RIIC : Boolean := False; + -- Write-only. Data Set Ready Input Change Enable + DSRIC : Boolean := False; + -- Write-only. Data Carrier Detect Input Change Interrupt Enable + DCDIC : Boolean := False; + -- Write-only. Clear to Send Input Change Interrupt Enable + CTSIC : Boolean := False; + -- unspecified + Reserved_20_23 : HAL.UInt4 := 16#0#; + -- Write-only. Manchester Error Interrupt Enable + MANE : Boolean := False; + -- unspecified + Reserved_25_31 : HAL.UInt7 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for USART_US_IER_Register use record + RXRDY at 0 range 0 .. 0; + TXRDY at 0 range 1 .. 1; + RXBRK at 0 range 2 .. 2; + Reserved_3_4 at 0 range 3 .. 4; + OVRE at 0 range 5 .. 5; + FRAME at 0 range 6 .. 6; + PARE at 0 range 7 .. 7; + TIMEOUT at 0 range 8 .. 8; + TXEMPTY at 0 range 9 .. 9; + ITER at 0 range 10 .. 10; + Reserved_11_12 at 0 range 11 .. 12; + NACK at 0 range 13 .. 13; + Reserved_14_15 at 0 range 14 .. 15; + RIIC at 0 range 16 .. 16; + DSRIC at 0 range 17 .. 17; + DCDIC at 0 range 18 .. 18; + CTSIC at 0 range 19 .. 19; + Reserved_20_23 at 0 range 20 .. 23; + MANE at 0 range 24 .. 24; + Reserved_25_31 at 0 range 25 .. 31; + end record; + + -- Interrupt Disable Register + type USART_US_IDR_Register is record + -- Write-only. RXRDY Interrupt Disable + RXRDY : Boolean := False; + -- Write-only. TXRDY Interrupt Disable + TXRDY : Boolean := False; + -- Write-only. Receiver Break Interrupt Disable + RXBRK : Boolean := False; + -- unspecified + Reserved_3_4 : HAL.UInt2 := 16#0#; + -- Write-only. Overrun Error Interrupt Enable + OVRE : Boolean := False; + -- Write-only. Framing Error Interrupt Disable + FRAME : Boolean := False; + -- Write-only. Parity Error Interrupt Disable + PARE : Boolean := False; + -- Write-only. Timeout Interrupt Disable + TIMEOUT : Boolean := False; + -- Write-only. TXEMPTY Interrupt Disable + TXEMPTY : Boolean := False; + -- Write-only. Max Number of Repetitions Reached Interrupt Disable + ITER : Boolean := False; + -- unspecified + Reserved_11_12 : HAL.UInt2 := 16#0#; + -- Write-only. Non Acknowledge Interrupt Disable + NACK : Boolean := False; + -- unspecified + Reserved_14_15 : HAL.UInt2 := 16#0#; + -- Write-only. Ring Indicator Input Change Disable + RIIC : Boolean := False; + -- Write-only. Data Set Ready Input Change Disable + DSRIC : Boolean := False; + -- Write-only. Data Carrier Detect Input Change Interrupt Disable + DCDIC : Boolean := False; + -- Write-only. Clear to Send Input Change Interrupt Disable + CTSIC : Boolean := False; + -- unspecified + Reserved_20_23 : HAL.UInt4 := 16#0#; + -- Write-only. Manchester Error Interrupt Disable + MANE : Boolean := False; + -- unspecified + Reserved_25_31 : HAL.UInt7 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for USART_US_IDR_Register use record + RXRDY at 0 range 0 .. 0; + TXRDY at 0 range 1 .. 1; + RXBRK at 0 range 2 .. 2; + Reserved_3_4 at 0 range 3 .. 4; + OVRE at 0 range 5 .. 5; + FRAME at 0 range 6 .. 6; + PARE at 0 range 7 .. 7; + TIMEOUT at 0 range 8 .. 8; + TXEMPTY at 0 range 9 .. 9; + ITER at 0 range 10 .. 10; + Reserved_11_12 at 0 range 11 .. 12; + NACK at 0 range 13 .. 13; + Reserved_14_15 at 0 range 14 .. 15; + RIIC at 0 range 16 .. 16; + DSRIC at 0 range 17 .. 17; + DCDIC at 0 range 18 .. 18; + CTSIC at 0 range 19 .. 19; + Reserved_20_23 at 0 range 20 .. 23; + MANE at 0 range 24 .. 24; + Reserved_25_31 at 0 range 25 .. 31; + end record; + + -- Interrupt Mask Register + type USART_US_IMR_Register is record + -- Read-only. RXRDY Interrupt Mask + RXRDY : Boolean; + -- Read-only. TXRDY Interrupt Mask + TXRDY : Boolean; + -- Read-only. Receiver Break Interrupt Mask + RXBRK : Boolean; + -- unspecified + Reserved_3_4 : HAL.UInt2; + -- Read-only. Overrun Error Interrupt Mask + OVRE : Boolean; + -- Read-only. Framing Error Interrupt Mask + FRAME : Boolean; + -- Read-only. Parity Error Interrupt Mask + PARE : Boolean; + -- Read-only. Timeout Interrupt Mask + TIMEOUT : Boolean; + -- Read-only. TXEMPTY Interrupt Mask + TXEMPTY : Boolean; + -- Read-only. Max Number of Repetitions Reached Interrupt Mask + ITER : Boolean; + -- unspecified + Reserved_11_12 : HAL.UInt2; + -- Read-only. Non Acknowledge Interrupt Mask + NACK : Boolean; + -- unspecified + Reserved_14_15 : HAL.UInt2; + -- Read-only. Ring Indicator Input Change Mask + RIIC : Boolean; + -- Read-only. Data Set Ready Input Change Mask + DSRIC : Boolean; + -- Read-only. Data Carrier Detect Input Change Interrupt Mask + DCDIC : Boolean; + -- Read-only. Clear to Send Input Change Interrupt Mask + CTSIC : Boolean; + -- unspecified + Reserved_20_23 : HAL.UInt4; + -- Read-only. Manchester Error Interrupt Mask + MANE : Boolean; + -- unspecified + Reserved_25_31 : HAL.UInt7; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for USART_US_IMR_Register use record + RXRDY at 0 range 0 .. 0; + TXRDY at 0 range 1 .. 1; + RXBRK at 0 range 2 .. 2; + Reserved_3_4 at 0 range 3 .. 4; + OVRE at 0 range 5 .. 5; + FRAME at 0 range 6 .. 6; + PARE at 0 range 7 .. 7; + TIMEOUT at 0 range 8 .. 8; + TXEMPTY at 0 range 9 .. 9; + ITER at 0 range 10 .. 10; + Reserved_11_12 at 0 range 11 .. 12; + NACK at 0 range 13 .. 13; + Reserved_14_15 at 0 range 14 .. 15; + RIIC at 0 range 16 .. 16; + DSRIC at 0 range 17 .. 17; + DCDIC at 0 range 18 .. 18; + CTSIC at 0 range 19 .. 19; + Reserved_20_23 at 0 range 20 .. 23; + MANE at 0 range 24 .. 24; + Reserved_25_31 at 0 range 25 .. 31; + end record; + + -- Channel Status Register + type USART_US_CSR_Register is record + -- Read-only. Receiver Ready (cleared by reading US_RHR) + RXRDY : Boolean; + -- Read-only. Transmitter Ready (cleared by writing US_THR) + TXRDY : Boolean; + -- Read-only. Break Received/End of Break (cleared by writing a one to + -- bit US_CR.RSTSTA) + RXBRK : Boolean; + -- unspecified + Reserved_3_4 : HAL.UInt2; + -- Read-only. Overrun Error (cleared by writing a one to bit + -- US_CR.RSTSTA) + OVRE : Boolean; + -- Read-only. Framing Error (cleared by writing a one to bit + -- US_CR.RSTSTA) + FRAME : Boolean; + -- Read-only. Parity Error (cleared by writing a one to bit + -- US_CR.RSTSTA) + PARE : Boolean; + -- Read-only. Receiver Timeout (cleared by writing a one to bit + -- US_CR.STTTO) + TIMEOUT : Boolean; + -- Read-only. Transmitter Empty (cleared by writing US_THR) + TXEMPTY : Boolean; + -- Read-only. Max Number of Repetitions Reached (cleared by writing a + -- one to bit US_CR.RSTIT) + ITER : Boolean; + -- unspecified + Reserved_11_12 : HAL.UInt2; + -- Read-only. Non Acknowledge Interrupt (cleared by writing a one to bit + -- US_CR.RSTNACK) + NACK : Boolean; + -- unspecified + Reserved_14_15 : HAL.UInt2; + -- Read-only. Ring Indicator Input Change Flag (cleared on read) + RIIC : Boolean; + -- Read-only. Data Set Ready Input Change Flag (cleared on read) + DSRIC : Boolean; + -- Read-only. Data Carrier Detect Input Change Flag (cleared on read) + DCDIC : Boolean; + -- Read-only. Clear to Send Input Change Flag (cleared on read) + CTSIC : Boolean; + -- Read-only. Image of RI Input + RI : Boolean; + -- Read-only. Image of DSR Input + DSR : Boolean; + -- Read-only. Image of DCD Input + DCD : Boolean; + -- Read-only. Image of CTS Input + CTS : Boolean; + -- Read-only. Manchester Error (cleared by writing a one to the bit + -- US_CR.RSTSTA) + MANERR : Boolean; + -- unspecified + Reserved_25_31 : HAL.UInt7; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for USART_US_CSR_Register use record + RXRDY at 0 range 0 .. 0; + TXRDY at 0 range 1 .. 1; + RXBRK at 0 range 2 .. 2; + Reserved_3_4 at 0 range 3 .. 4; + OVRE at 0 range 5 .. 5; + FRAME at 0 range 6 .. 6; + PARE at 0 range 7 .. 7; + TIMEOUT at 0 range 8 .. 8; + TXEMPTY at 0 range 9 .. 9; + ITER at 0 range 10 .. 10; + Reserved_11_12 at 0 range 11 .. 12; + NACK at 0 range 13 .. 13; + Reserved_14_15 at 0 range 14 .. 15; + RIIC at 0 range 16 .. 16; + DSRIC at 0 range 17 .. 17; + DCDIC at 0 range 18 .. 18; + CTSIC at 0 range 19 .. 19; + RI at 0 range 20 .. 20; + DSR at 0 range 21 .. 21; + DCD at 0 range 22 .. 22; + CTS at 0 range 23 .. 23; + MANERR at 0 range 24 .. 24; + Reserved_25_31 at 0 range 25 .. 31; + end record; + + subtype USART_US_RHR_RXCHR_Field is HAL.UInt9; + + -- Receive Holding Register + type USART_US_RHR_Register is record + -- Read-only. Received Character + RXCHR : USART_US_RHR_RXCHR_Field; + -- unspecified + Reserved_9_14 : HAL.UInt6; + -- Read-only. Received Sync + RXSYNH : Boolean; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for USART_US_RHR_Register use record + RXCHR at 0 range 0 .. 8; + Reserved_9_14 at 0 range 9 .. 14; + RXSYNH at 0 range 15 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype USART_US_THR_TXCHR_Field is HAL.UInt9; + + -- Transmit Holding Register + type USART_US_THR_Register is record + -- Write-only. Character to be Transmitted + TXCHR : USART_US_THR_TXCHR_Field := 16#0#; + -- unspecified + Reserved_9_14 : HAL.UInt6 := 16#0#; + -- Write-only. Sync Field to be Transmitted + TXSYNH : Boolean := False; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for USART_US_THR_Register use record + TXCHR at 0 range 0 .. 8; + Reserved_9_14 at 0 range 9 .. 14; + TXSYNH at 0 range 15 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype USART_US_BRGR_CD_Field is HAL.UInt16; + subtype USART_US_BRGR_FP_Field is HAL.UInt3; + + -- Baud Rate Generator Register + type USART_US_BRGR_Register is record + -- Clock Divider + CD : USART_US_BRGR_CD_Field := 16#0#; + -- Fractional Part + FP : USART_US_BRGR_FP_Field := 16#0#; + -- unspecified + Reserved_19_31 : HAL.UInt13 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for USART_US_BRGR_Register use record + CD at 0 range 0 .. 15; + FP at 0 range 16 .. 18; + Reserved_19_31 at 0 range 19 .. 31; + end record; + + subtype USART_US_RTOR_TO_Field is HAL.UInt17; + + -- Receiver Timeout Register + type USART_US_RTOR_Register is record + -- Timeout Value + TO : USART_US_RTOR_TO_Field := 16#0#; + -- unspecified + Reserved_17_31 : HAL.UInt15 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for USART_US_RTOR_Register use record + TO at 0 range 0 .. 16; + Reserved_17_31 at 0 range 17 .. 31; + end record; + + subtype USART_US_TTGR_TG_Field is HAL.UInt8; + + -- Transmitter Timeguard Register + type USART_US_TTGR_Register is record + -- Timeguard Value + TG : USART_US_TTGR_TG_Field := 16#0#; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for USART_US_TTGR_Register use record + TG at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype USART_US_FIDI_FI_DI_RATIO_Field is HAL.UInt16; + + -- FI DI Ratio Register + type USART_US_FIDI_Register is record + -- FI Over DI Ratio Value + FI_DI_RATIO : USART_US_FIDI_FI_DI_RATIO_Field := 16#0#; + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for USART_US_FIDI_Register use record + FI_DI_RATIO at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + subtype USART_US_NER_NB_ERRORS_Field is HAL.UInt8; + + -- Number of Errors Register + type USART_US_NER_Register is record + -- Read-only. Number of Errors + NB_ERRORS : USART_US_NER_NB_ERRORS_Field; + -- unspecified + Reserved_8_31 : HAL.UInt24; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for USART_US_NER_Register use record + NB_ERRORS at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype USART_US_IF_IRDA_FILTER_Field is HAL.UInt8; + + -- IrDA Filter Register + type USART_US_IF_Register is record + -- IrDA Filter + IRDA_FILTER : USART_US_IF_IRDA_FILTER_Field := 16#0#; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for USART_US_IF_Register use record + IRDA_FILTER at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype USART_US_MAN_TX_PL_Field is HAL.UInt4; + + -- Transmitter Preamble Pattern + type US_MAN_TX_PP_Field is + ( + -- The preamble is composed of '1's + All_One, + -- The preamble is composed of '0's + All_Zero, + -- The preamble is composed of '01's + Zero_One, + -- The preamble is composed of '10's + One_Zero) + with Size => 2; + for US_MAN_TX_PP_Field use + (All_One => 0, + All_Zero => 1, + Zero_One => 2, + One_Zero => 3); + + subtype USART_US_MAN_RX_PL_Field is HAL.UInt4; + + -- Receiver Preamble Pattern detected + type US_MAN_RX_PP_Field is + ( + -- The preamble is composed of '1's + All_One, + -- The preamble is composed of '0's + All_Zero, + -- The preamble is composed of '01's + Zero_One, + -- The preamble is composed of '10's + One_Zero) + with Size => 2; + for US_MAN_RX_PP_Field use + (All_One => 0, + All_Zero => 1, + Zero_One => 2, + One_Zero => 3); + + -- Manchester Configuration Register + type USART_US_MAN_Register is record + -- Transmitter Preamble Length + TX_PL : USART_US_MAN_TX_PL_Field := 16#0#; + -- unspecified + Reserved_4_7 : HAL.UInt4 := 16#0#; + -- Transmitter Preamble Pattern + TX_PP : US_MAN_TX_PP_Field := SAM_SVD.USART.All_One; + -- unspecified + Reserved_10_11 : HAL.UInt2 := 16#0#; + -- Transmitter Manchester Polarity + TX_MPOL : Boolean := False; + -- unspecified + Reserved_13_15 : HAL.UInt3 := 16#0#; + -- Receiver Preamble Length + RX_PL : USART_US_MAN_RX_PL_Field := 16#0#; + -- unspecified + Reserved_20_23 : HAL.UInt4 := 16#0#; + -- Receiver Preamble Pattern detected + RX_PP : US_MAN_RX_PP_Field := SAM_SVD.USART.All_One; + -- unspecified + Reserved_26_27 : HAL.UInt2 := 16#0#; + -- Receiver Manchester Polarity + RX_MPOL : Boolean := False; + -- Must Be Set to 1 + ONE : Boolean := False; + -- Drift Compensation + DRIFT : Boolean := False; + RXIDLEV : Boolean := False; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for USART_US_MAN_Register use record + TX_PL at 0 range 0 .. 3; + Reserved_4_7 at 0 range 4 .. 7; + TX_PP at 0 range 8 .. 9; + Reserved_10_11 at 0 range 10 .. 11; + TX_MPOL at 0 range 12 .. 12; + Reserved_13_15 at 0 range 13 .. 15; + RX_PL at 0 range 16 .. 19; + Reserved_20_23 at 0 range 20 .. 23; + RX_PP at 0 range 24 .. 25; + Reserved_26_27 at 0 range 26 .. 27; + RX_MPOL at 0 range 28 .. 28; + ONE at 0 range 29 .. 29; + DRIFT at 0 range 30 .. 30; + RXIDLEV at 0 range 31 .. 31; + end record; + + -- LIN Node Action + type US_LINMR_NACT_Field is + ( + -- The USART transmits the response. + Publish, + -- The USART receives the response. + Subscribe, + -- The USART does not transmit and does not receive the response. + Ignore) + with Size => 2; + for US_LINMR_NACT_Field use + (Publish => 0, + Subscribe => 1, + Ignore => 2); + + subtype USART_US_LINMR_DLC_Field is HAL.UInt8; + + -- LIN Mode Register + type USART_US_LINMR_Register is record + -- LIN Node Action + NACT : US_LINMR_NACT_Field := SAM_SVD.USART.Publish; + -- Parity Disable + PARDIS : Boolean := False; + -- Checksum Disable + CHKDIS : Boolean := False; + -- Checksum Type + CHKTYP : Boolean := False; + -- Data Length Mode + DLM : Boolean := False; + -- Frame Slot Mode Disable + FSDIS : Boolean := False; + -- Wakeup Signal Type + WKUPTYP : Boolean := False; + -- Data Length Control + DLC : USART_US_LINMR_DLC_Field := 16#0#; + -- DMAC Mode + PDCM : Boolean := False; + -- Synchronization Disable + SYNCDIS : Boolean := False; + -- unspecified + Reserved_18_31 : HAL.UInt14 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for USART_US_LINMR_Register use record + NACT at 0 range 0 .. 1; + PARDIS at 0 range 2 .. 2; + CHKDIS at 0 range 3 .. 3; + CHKTYP at 0 range 4 .. 4; + DLM at 0 range 5 .. 5; + FSDIS at 0 range 6 .. 6; + WKUPTYP at 0 range 7 .. 7; + DLC at 0 range 8 .. 15; + PDCM at 0 range 16 .. 16; + SYNCDIS at 0 range 17 .. 17; + Reserved_18_31 at 0 range 18 .. 31; + end record; + + subtype USART_US_LINIR_IDCHR_Field is HAL.UInt8; + + -- LIN Identifier Register + type USART_US_LINIR_Register is record + -- Identifier Character + IDCHR : USART_US_LINIR_IDCHR_Field := 16#0#; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for USART_US_LINIR_Register use record + IDCHR at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype USART_US_LINBRR_LINCD_Field is HAL.UInt16; + subtype USART_US_LINBRR_LINFP_Field is HAL.UInt3; + + -- LIN Baud Rate Register + type USART_US_LINBRR_Register is record + -- Read-only. Clock Divider after Synchronization + LINCD : USART_US_LINBRR_LINCD_Field; + -- Read-only. Fractional Part after Synchronization + LINFP : USART_US_LINBRR_LINFP_Field; + -- unspecified + Reserved_19_31 : HAL.UInt13; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for USART_US_LINBRR_Register use record + LINCD at 0 range 0 .. 15; + LINFP at 0 range 16 .. 18; + Reserved_19_31 at 0 range 19 .. 31; + end record; + + subtype USART_US_LONMR_EOFS_Field is HAL.UInt8; + + -- LON Mode Register + type USART_US_LONMR_Register is record + -- LON comm_type Parameter Value + COMMT : Boolean := False; + -- LON Collision Detection Feature + COLDET : Boolean := False; + -- Terminate Frame upon Collision Notification + TCOL : Boolean := False; + -- LON Collision Detection on Frame Tail + CDTAIL : Boolean := False; + -- LON DMA Mode + DMAM : Boolean := False; + -- LON Collision Detection Source + LCDS : Boolean := False; + -- unspecified + Reserved_6_15 : HAL.UInt10 := 16#0#; + -- End of Frame Condition Size + EOFS : USART_US_LONMR_EOFS_Field := 16#0#; + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for USART_US_LONMR_Register use record + COMMT at 0 range 0 .. 0; + COLDET at 0 range 1 .. 1; + TCOL at 0 range 2 .. 2; + CDTAIL at 0 range 3 .. 3; + DMAM at 0 range 4 .. 4; + LCDS at 0 range 5 .. 5; + Reserved_6_15 at 0 range 6 .. 15; + EOFS at 0 range 16 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype USART_US_LONPR_LONPL_Field is HAL.UInt14; + + -- LON Preamble Register + type USART_US_LONPR_Register is record + -- LON Preamble Length + LONPL : USART_US_LONPR_LONPL_Field := 16#0#; + -- unspecified + Reserved_14_31 : HAL.UInt18 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for USART_US_LONPR_Register use record + LONPL at 0 range 0 .. 13; + Reserved_14_31 at 0 range 14 .. 31; + end record; + + subtype USART_US_LONDL_LONDL_Field is HAL.UInt8; + + -- LON Data Length Register + type USART_US_LONDL_Register is record + -- LON Data Length + LONDL : USART_US_LONDL_LONDL_Field := 16#0#; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for USART_US_LONDL_Register use record + LONDL at 0 range 0 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype USART_US_LONL2HDR_BLI_Field is HAL.UInt6; + + -- LON L2HDR Register + type USART_US_LONL2HDR_Register is record + -- LON Backlog Increment + BLI : USART_US_LONL2HDR_BLI_Field := 16#0#; + -- LON Alternate Path Bit + ALTP : Boolean := False; + -- LON Priority Bit + PB : Boolean := False; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for USART_US_LONL2HDR_Register use record + BLI at 0 range 0 .. 5; + ALTP at 0 range 6 .. 6; + PB at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + subtype USART_US_LONBL_LONBL_Field is HAL.UInt6; + + -- LON Backlog Register + type USART_US_LONBL_Register is record + -- Read-only. LON Node Backlog Value + LONBL : USART_US_LONBL_LONBL_Field; + -- unspecified + Reserved_6_31 : HAL.UInt26; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for USART_US_LONBL_Register use record + LONBL at 0 range 0 .. 5; + Reserved_6_31 at 0 range 6 .. 31; + end record; + + subtype USART_US_LONB1TX_BETA1TX_Field is HAL.UInt24; + + -- LON Beta1 Tx Register + type USART_US_LONB1TX_Register is record + -- LON Beta1 Length after Transmission + BETA1TX : USART_US_LONB1TX_BETA1TX_Field := 16#0#; + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for USART_US_LONB1TX_Register use record + BETA1TX at 0 range 0 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype USART_US_LONB1RX_BETA1RX_Field is HAL.UInt24; + + -- LON Beta1 Rx Register + type USART_US_LONB1RX_Register is record + -- LON Beta1 Length after Reception + BETA1RX : USART_US_LONB1RX_BETA1RX_Field := 16#0#; + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for USART_US_LONB1RX_Register use record + BETA1RX at 0 range 0 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype USART_US_LONPRIO_PSNB_Field is HAL.UInt7; + subtype USART_US_LONPRIO_NPS_Field is HAL.UInt7; + + -- LON Priority Register + type USART_US_LONPRIO_Register is record + -- LON Priority Slot Number + PSNB : USART_US_LONPRIO_PSNB_Field := 16#0#; + -- unspecified + Reserved_7_7 : HAL.Bit := 16#0#; + -- LON Node Priority Slot + NPS : USART_US_LONPRIO_NPS_Field := 16#0#; + -- unspecified + Reserved_15_31 : HAL.UInt17 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for USART_US_LONPRIO_Register use record + PSNB at 0 range 0 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + NPS at 0 range 8 .. 14; + Reserved_15_31 at 0 range 15 .. 31; + end record; + + subtype USART_US_IDTTX_IDTTX_Field is HAL.UInt24; + + -- LON IDT Tx Register + type USART_US_IDTTX_Register is record + -- LON Indeterminate Time after Transmission (comm_type = 1 mode only) + IDTTX : USART_US_IDTTX_IDTTX_Field := 16#0#; + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for USART_US_IDTTX_Register use record + IDTTX at 0 range 0 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype USART_US_IDTRX_IDTRX_Field is HAL.UInt24; + + -- LON IDT Rx Register + type USART_US_IDTRX_Register is record + -- LON Indeterminate Time after Reception (comm_type = 1 mode only) + IDTRX : USART_US_IDTRX_IDTRX_Field := 16#0#; + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for USART_US_IDTRX_Register use record + IDTRX at 0 range 0 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype USART_US_ICDIFF_ICDIFF_Field is HAL.UInt4; + + -- IC DIFF Register + type USART_US_ICDIFF_Register is record + -- IC Differentiator Number + ICDIFF : USART_US_ICDIFF_ICDIFF_Field := 16#0#; + -- unspecified + Reserved_4_31 : HAL.UInt28 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for USART_US_ICDIFF_Register use record + ICDIFF at 0 range 0 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + -- Write Protection Key + type US_WPMR_WPKEY_Field is + ( + -- Reset value for the field + Us_Wpmr_Wpkey_Field_Reset, + -- Writing any other value in this field aborts the write operation of + -- the WPEN bit. Always reads as 0. + Passwd) + with Size => 24; + for US_WPMR_WPKEY_Field use + (Us_Wpmr_Wpkey_Field_Reset => 0, + Passwd => 5591873); + + -- Write Protection Mode Register + type USART_US_WPMR_Register is record + -- Write Protection Enable + WPEN : Boolean := False; + -- unspecified + Reserved_1_7 : HAL.UInt7 := 16#0#; + -- Write Protection Key + WPKEY : US_WPMR_WPKEY_Field := Us_Wpmr_Wpkey_Field_Reset; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for USART_US_WPMR_Register use record + WPEN at 0 range 0 .. 0; + Reserved_1_7 at 0 range 1 .. 7; + WPKEY at 0 range 8 .. 31; + end record; + + subtype USART_US_WPSR_WPVSRC_Field is HAL.UInt16; + + -- Write Protection Status Register + type USART_US_WPSR_Register is record + -- Read-only. Write Protection Violation Status + WPVS : Boolean; + -- unspecified + Reserved_1_7 : HAL.UInt7; + -- Read-only. Write Protection Violation Source + WPVSRC : USART_US_WPSR_WPVSRC_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for USART_US_WPSR_Register use record + WPVS at 0 range 0 .. 0; + Reserved_1_7 at 0 range 1 .. 7; + WPVSRC at 0 range 8 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype USART_US_VERSION_VERSION_Field is HAL.UInt12; + subtype USART_US_VERSION_MFN_Field is HAL.UInt3; + + -- Version Register + type USART_US_VERSION_Register is record + -- Read-only. Hardware Module Version + VERSION : USART_US_VERSION_VERSION_Field; + -- unspecified + Reserved_12_15 : HAL.UInt4; + -- Read-only. Metal Fix Number + MFN : USART_US_VERSION_MFN_Field; + -- unspecified + Reserved_19_31 : HAL.UInt13; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for USART_US_VERSION_Register use record + VERSION at 0 range 0 .. 11; + Reserved_12_15 at 0 range 12 .. 15; + MFN at 0 range 16 .. 18; + Reserved_19_31 at 0 range 19 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- Universal Synchronous Asynchronous Receiver Transmitter + type USART_Peripheral is record + -- Control Register + US_CR : aliased USART_US_CR_Register; + -- Mode Register + US_MR : aliased USART_US_MR_Register; + -- Interrupt Enable Register + US_IER : aliased USART_US_IER_Register; + -- Interrupt Disable Register + US_IDR : aliased USART_US_IDR_Register; + -- Interrupt Mask Register + US_IMR : aliased USART_US_IMR_Register; + -- Channel Status Register + US_CSR : aliased USART_US_CSR_Register; + -- Receive Holding Register + US_RHR : aliased USART_US_RHR_Register; + -- Transmit Holding Register + US_THR : aliased USART_US_THR_Register; + -- Baud Rate Generator Register + US_BRGR : aliased USART_US_BRGR_Register; + -- Receiver Timeout Register + US_RTOR : aliased USART_US_RTOR_Register; + -- Transmitter Timeguard Register + US_TTGR : aliased USART_US_TTGR_Register; + -- FI DI Ratio Register + US_FIDI : aliased USART_US_FIDI_Register; + -- Number of Errors Register + US_NER : aliased USART_US_NER_Register; + -- IrDA Filter Register + US_IF : aliased USART_US_IF_Register; + -- Manchester Configuration Register + US_MAN : aliased USART_US_MAN_Register; + -- LIN Mode Register + US_LINMR : aliased USART_US_LINMR_Register; + -- LIN Identifier Register + US_LINIR : aliased USART_US_LINIR_Register; + -- LIN Baud Rate Register + US_LINBRR : aliased USART_US_LINBRR_Register; + -- LON Mode Register + US_LONMR : aliased USART_US_LONMR_Register; + -- LON Preamble Register + US_LONPR : aliased USART_US_LONPR_Register; + -- LON Data Length Register + US_LONDL : aliased USART_US_LONDL_Register; + -- LON L2HDR Register + US_LONL2HDR : aliased USART_US_LONL2HDR_Register; + -- LON Backlog Register + US_LONBL : aliased USART_US_LONBL_Register; + -- LON Beta1 Tx Register + US_LONB1TX : aliased USART_US_LONB1TX_Register; + -- LON Beta1 Rx Register + US_LONB1RX : aliased USART_US_LONB1RX_Register; + -- LON Priority Register + US_LONPRIO : aliased USART_US_LONPRIO_Register; + -- LON IDT Tx Register + US_IDTTX : aliased USART_US_IDTTX_Register; + -- LON IDT Rx Register + US_IDTRX : aliased USART_US_IDTRX_Register; + -- IC DIFF Register + US_ICDIFF : aliased USART_US_ICDIFF_Register; + -- Write Protection Mode Register + US_WPMR : aliased USART_US_WPMR_Register; + -- Write Protection Status Register + US_WPSR : aliased USART_US_WPSR_Register; + -- Version Register + US_VERSION : aliased USART_US_VERSION_Register; + end record + with Volatile; + + for USART_Peripheral use record + US_CR at 16#0# range 0 .. 31; + US_MR at 16#4# range 0 .. 31; + US_IER at 16#8# range 0 .. 31; + US_IDR at 16#C# range 0 .. 31; + US_IMR at 16#10# range 0 .. 31; + US_CSR at 16#14# range 0 .. 31; + US_RHR at 16#18# range 0 .. 31; + US_THR at 16#1C# range 0 .. 31; + US_BRGR at 16#20# range 0 .. 31; + US_RTOR at 16#24# range 0 .. 31; + US_TTGR at 16#28# range 0 .. 31; + US_FIDI at 16#40# range 0 .. 31; + US_NER at 16#44# range 0 .. 31; + US_IF at 16#4C# range 0 .. 31; + US_MAN at 16#50# range 0 .. 31; + US_LINMR at 16#54# range 0 .. 31; + US_LINIR at 16#58# range 0 .. 31; + US_LINBRR at 16#5C# range 0 .. 31; + US_LONMR at 16#60# range 0 .. 31; + US_LONPR at 16#64# range 0 .. 31; + US_LONDL at 16#68# range 0 .. 31; + US_LONL2HDR at 16#6C# range 0 .. 31; + US_LONBL at 16#70# range 0 .. 31; + US_LONB1TX at 16#74# range 0 .. 31; + US_LONB1RX at 16#78# range 0 .. 31; + US_LONPRIO at 16#7C# range 0 .. 31; + US_IDTTX at 16#80# range 0 .. 31; + US_IDTRX at 16#84# range 0 .. 31; + US_ICDIFF at 16#88# range 0 .. 31; + US_WPMR at 16#E4# range 0 .. 31; + US_WPSR at 16#E8# range 0 .. 31; + US_VERSION at 16#FC# range 0 .. 31; + end record; + + -- Universal Synchronous Asynchronous Receiver Transmitter + USART0_Periph : aliased USART_Peripheral + with Import, Address => System'To_Address (16#40024000#); + + -- Universal Synchronous Asynchronous Receiver Transmitter + USART1_Periph : aliased USART_Peripheral + with Import, Address => System'To_Address (16#40028000#); + + -- Universal Synchronous Asynchronous Receiver Transmitter + USART2_Periph : aliased USART_Peripheral + with Import, Address => System'To_Address (16#4002C000#); + +end SAM_SVD.USART; diff --git a/arch/ARM/SAM/svd/atsamv71/sam_svd-usbhs.ads b/arch/ARM/SAM/svd/atsamv71/sam_svd-usbhs.ads new file mode 100644 index 000000000..49f8bd54b --- /dev/null +++ b/arch/ARM/SAM/svd/atsamv71/sam_svd-usbhs.ads @@ -0,0 +1,3133 @@ +-- This spec has been automatically generated from ATSAMV71Q21.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package SAM_SVD.USBHS is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + subtype USBHS_USBHS_DEVCTRL_UADD_Field is HAL.UInt7; + + -- Mode Configuration + type USBHS_DEVCTRL_SPDCONF_Field is + ( + -- The peripheral starts in Full-speed mode and performs a high-speed + -- reset to switch to High-speed mode if the host is high-speed-capable. + Normal, + -- For a better consumption, if high speed is not needed. + Low_Power, + -- Forced high speed. + High_Speed, + -- The peripheral remains in Full-speed mode whatever the host speed + -- capability. + Forced_Fs) + with Size => 2; + for USBHS_DEVCTRL_SPDCONF_Field use + (Normal => 0, + Low_Power => 1, + High_Speed => 2, + Forced_Fs => 3); + + -- Device General Control Register + type USBHS_USBHS_DEVCTRL_Register is record + -- USB Address + UADD : USBHS_USBHS_DEVCTRL_UADD_Field := 16#0#; + -- Address Enable + ADDEN : Boolean := False; + -- Detach + DETACH : Boolean := False; + -- Remote Wake-Up + RMWKUP : Boolean := False; + -- Mode Configuration + SPDCONF : USBHS_DEVCTRL_SPDCONF_Field := SAM_SVD.USBHS.Normal; + -- Low-Speed Mode Force + LS : Boolean := False; + -- Test mode J + TSTJ : Boolean := False; + -- Test mode K + TSTK : Boolean := False; + -- Test packet mode + TSTPCKT : Boolean := False; + -- Specific Operational mode + OPMODE2 : Boolean := False; + -- unspecified + Reserved_17_31 : HAL.UInt15 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for USBHS_USBHS_DEVCTRL_Register use record + UADD at 0 range 0 .. 6; + ADDEN at 0 range 7 .. 7; + DETACH at 0 range 8 .. 8; + RMWKUP at 0 range 9 .. 9; + SPDCONF at 0 range 10 .. 11; + LS at 0 range 12 .. 12; + TSTJ at 0 range 13 .. 13; + TSTK at 0 range 14 .. 14; + TSTPCKT at 0 range 15 .. 15; + OPMODE2 at 0 range 16 .. 16; + Reserved_17_31 at 0 range 17 .. 31; + end record; + + -- Device Global Interrupt Status Register + type USBHS_USBHS_DEVISR_Register is record + -- Read-only. Suspend Interrupt + SUSP : Boolean; + -- Read-only. Micro Start of Frame Interrupt + MSOF : Boolean; + -- Read-only. Start of Frame Interrupt + SOF : Boolean; + -- Read-only. End of Reset Interrupt + EORST : Boolean; + -- Read-only. Wake-Up Interrupt + WAKEUP : Boolean; + -- Read-only. End of Resume Interrupt + EORSM : Boolean; + -- Read-only. Upstream Resume Interrupt + UPRSM : Boolean; + -- unspecified + Reserved_7_11 : HAL.UInt5; + -- Read-only. Endpoint 0 Interrupt + PEP_0 : Boolean; + -- Read-only. Endpoint 1 Interrupt + PEP_1 : Boolean; + -- Read-only. Endpoint 2 Interrupt + PEP_2 : Boolean; + -- Read-only. Endpoint 3 Interrupt + PEP_3 : Boolean; + -- Read-only. Endpoint 4 Interrupt + PEP_4 : Boolean; + -- Read-only. Endpoint 5 Interrupt + PEP_5 : Boolean; + -- Read-only. Endpoint 6 Interrupt + PEP_6 : Boolean; + -- Read-only. Endpoint 7 Interrupt + PEP_7 : Boolean; + -- Read-only. Endpoint 8 Interrupt + PEP_8 : Boolean; + -- Read-only. Endpoint 9 Interrupt + PEP_9 : Boolean; + -- unspecified + Reserved_22_24 : HAL.UInt3; + -- Read-only. DMA Channel 1 Interrupt + DMA_1 : Boolean; + -- Read-only. DMA Channel 2 Interrupt + DMA_2 : Boolean; + -- Read-only. DMA Channel 3 Interrupt + DMA_3 : Boolean; + -- Read-only. DMA Channel 4 Interrupt + DMA_4 : Boolean; + -- Read-only. DMA Channel 5 Interrupt + DMA_5 : Boolean; + -- Read-only. DMA Channel 6 Interrupt + DMA_6 : Boolean; + -- Read-only. DMA Channel 7 Interrupt + DMA_7 : Boolean; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for USBHS_USBHS_DEVISR_Register use record + SUSP at 0 range 0 .. 0; + MSOF at 0 range 1 .. 1; + SOF at 0 range 2 .. 2; + EORST at 0 range 3 .. 3; + WAKEUP at 0 range 4 .. 4; + EORSM at 0 range 5 .. 5; + UPRSM at 0 range 6 .. 6; + Reserved_7_11 at 0 range 7 .. 11; + PEP_0 at 0 range 12 .. 12; + PEP_1 at 0 range 13 .. 13; + PEP_2 at 0 range 14 .. 14; + PEP_3 at 0 range 15 .. 15; + PEP_4 at 0 range 16 .. 16; + PEP_5 at 0 range 17 .. 17; + PEP_6 at 0 range 18 .. 18; + PEP_7 at 0 range 19 .. 19; + PEP_8 at 0 range 20 .. 20; + PEP_9 at 0 range 21 .. 21; + Reserved_22_24 at 0 range 22 .. 24; + DMA_1 at 0 range 25 .. 25; + DMA_2 at 0 range 26 .. 26; + DMA_3 at 0 range 27 .. 27; + DMA_4 at 0 range 28 .. 28; + DMA_5 at 0 range 29 .. 29; + DMA_6 at 0 range 30 .. 30; + DMA_7 at 0 range 31 .. 31; + end record; + + -- Device Global Interrupt Clear Register + type USBHS_USBHS_DEVICR_Register is record + -- Write-only. Suspend Interrupt Clear + SUSPC : Boolean := False; + -- Write-only. Micro Start of Frame Interrupt Clear + MSOFC : Boolean := False; + -- Write-only. Start of Frame Interrupt Clear + SOFC : Boolean := False; + -- Write-only. End of Reset Interrupt Clear + EORSTC : Boolean := False; + -- Write-only. Wake-Up Interrupt Clear + WAKEUPC : Boolean := False; + -- Write-only. End of Resume Interrupt Clear + EORSMC : Boolean := False; + -- Write-only. Upstream Resume Interrupt Clear + UPRSMC : Boolean := False; + -- unspecified + Reserved_7_31 : HAL.UInt25 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for USBHS_USBHS_DEVICR_Register use record + SUSPC at 0 range 0 .. 0; + MSOFC at 0 range 1 .. 1; + SOFC at 0 range 2 .. 2; + EORSTC at 0 range 3 .. 3; + WAKEUPC at 0 range 4 .. 4; + EORSMC at 0 range 5 .. 5; + UPRSMC at 0 range 6 .. 6; + Reserved_7_31 at 0 range 7 .. 31; + end record; + + -- Device Global Interrupt Set Register + type USBHS_USBHS_DEVIFR_Register is record + -- Write-only. Suspend Interrupt Set + SUSPS : Boolean := False; + -- Write-only. Micro Start of Frame Interrupt Set + MSOFS : Boolean := False; + -- Write-only. Start of Frame Interrupt Set + SOFS : Boolean := False; + -- Write-only. End of Reset Interrupt Set + EORSTS : Boolean := False; + -- Write-only. Wake-Up Interrupt Set + WAKEUPS : Boolean := False; + -- Write-only. End of Resume Interrupt Set + EORSMS : Boolean := False; + -- Write-only. Upstream Resume Interrupt Set + UPRSMS : Boolean := False; + -- unspecified + Reserved_7_24 : HAL.UInt18 := 16#0#; + -- Write-only. DMA Channel 1 Interrupt Set + DMA_1 : Boolean := False; + -- Write-only. DMA Channel 2 Interrupt Set + DMA_2 : Boolean := False; + -- Write-only. DMA Channel 3 Interrupt Set + DMA_3 : Boolean := False; + -- Write-only. DMA Channel 4 Interrupt Set + DMA_4 : Boolean := False; + -- Write-only. DMA Channel 5 Interrupt Set + DMA_5 : Boolean := False; + -- Write-only. DMA Channel 6 Interrupt Set + DMA_6 : Boolean := False; + -- Write-only. DMA Channel 7 Interrupt Set + DMA_7 : Boolean := False; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for USBHS_USBHS_DEVIFR_Register use record + SUSPS at 0 range 0 .. 0; + MSOFS at 0 range 1 .. 1; + SOFS at 0 range 2 .. 2; + EORSTS at 0 range 3 .. 3; + WAKEUPS at 0 range 4 .. 4; + EORSMS at 0 range 5 .. 5; + UPRSMS at 0 range 6 .. 6; + Reserved_7_24 at 0 range 7 .. 24; + DMA_1 at 0 range 25 .. 25; + DMA_2 at 0 range 26 .. 26; + DMA_3 at 0 range 27 .. 27; + DMA_4 at 0 range 28 .. 28; + DMA_5 at 0 range 29 .. 29; + DMA_6 at 0 range 30 .. 30; + DMA_7 at 0 range 31 .. 31; + end record; + + -- Device Global Interrupt Mask Register + type USBHS_USBHS_DEVIMR_Register is record + -- Read-only. Suspend Interrupt Mask + SUSPE : Boolean; + -- Read-only. Micro Start of Frame Interrupt Mask + MSOFE : Boolean; + -- Read-only. Start of Frame Interrupt Mask + SOFE : Boolean; + -- Read-only. End of Reset Interrupt Mask + EORSTE : Boolean; + -- Read-only. Wake-Up Interrupt Mask + WAKEUPE : Boolean; + -- Read-only. End of Resume Interrupt Mask + EORSME : Boolean; + -- Read-only. Upstream Resume Interrupt Mask + UPRSME : Boolean; + -- unspecified + Reserved_7_11 : HAL.UInt5; + -- Read-only. Endpoint 0 Interrupt Mask + PEP_0 : Boolean; + -- Read-only. Endpoint 1 Interrupt Mask + PEP_1 : Boolean; + -- Read-only. Endpoint 2 Interrupt Mask + PEP_2 : Boolean; + -- Read-only. Endpoint 3 Interrupt Mask + PEP_3 : Boolean; + -- Read-only. Endpoint 4 Interrupt Mask + PEP_4 : Boolean; + -- Read-only. Endpoint 5 Interrupt Mask + PEP_5 : Boolean; + -- Read-only. Endpoint 6 Interrupt Mask + PEP_6 : Boolean; + -- Read-only. Endpoint 7 Interrupt Mask + PEP_7 : Boolean; + -- Read-only. Endpoint 8 Interrupt Mask + PEP_8 : Boolean; + -- Read-only. Endpoint 9 Interrupt Mask + PEP_9 : Boolean; + -- unspecified + Reserved_22_24 : HAL.UInt3; + -- Read-only. DMA Channel 1 Interrupt Mask + DMA_1 : Boolean; + -- Read-only. DMA Channel 2 Interrupt Mask + DMA_2 : Boolean; + -- Read-only. DMA Channel 3 Interrupt Mask + DMA_3 : Boolean; + -- Read-only. DMA Channel 4 Interrupt Mask + DMA_4 : Boolean; + -- Read-only. DMA Channel 5 Interrupt Mask + DMA_5 : Boolean; + -- Read-only. DMA Channel 6 Interrupt Mask + DMA_6 : Boolean; + -- Read-only. DMA Channel 7 Interrupt Mask + DMA_7 : Boolean; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for USBHS_USBHS_DEVIMR_Register use record + SUSPE at 0 range 0 .. 0; + MSOFE at 0 range 1 .. 1; + SOFE at 0 range 2 .. 2; + EORSTE at 0 range 3 .. 3; + WAKEUPE at 0 range 4 .. 4; + EORSME at 0 range 5 .. 5; + UPRSME at 0 range 6 .. 6; + Reserved_7_11 at 0 range 7 .. 11; + PEP_0 at 0 range 12 .. 12; + PEP_1 at 0 range 13 .. 13; + PEP_2 at 0 range 14 .. 14; + PEP_3 at 0 range 15 .. 15; + PEP_4 at 0 range 16 .. 16; + PEP_5 at 0 range 17 .. 17; + PEP_6 at 0 range 18 .. 18; + PEP_7 at 0 range 19 .. 19; + PEP_8 at 0 range 20 .. 20; + PEP_9 at 0 range 21 .. 21; + Reserved_22_24 at 0 range 22 .. 24; + DMA_1 at 0 range 25 .. 25; + DMA_2 at 0 range 26 .. 26; + DMA_3 at 0 range 27 .. 27; + DMA_4 at 0 range 28 .. 28; + DMA_5 at 0 range 29 .. 29; + DMA_6 at 0 range 30 .. 30; + DMA_7 at 0 range 31 .. 31; + end record; + + -- Device Global Interrupt Disable Register + type USBHS_USBHS_DEVIDR_Register is record + -- Write-only. Suspend Interrupt Disable + SUSPEC : Boolean := False; + -- Write-only. Micro Start of Frame Interrupt Disable + MSOFEC : Boolean := False; + -- Write-only. Start of Frame Interrupt Disable + SOFEC : Boolean := False; + -- Write-only. End of Reset Interrupt Disable + EORSTEC : Boolean := False; + -- Write-only. Wake-Up Interrupt Disable + WAKEUPEC : Boolean := False; + -- Write-only. End of Resume Interrupt Disable + EORSMEC : Boolean := False; + -- Write-only. Upstream Resume Interrupt Disable + UPRSMEC : Boolean := False; + -- unspecified + Reserved_7_11 : HAL.UInt5 := 16#0#; + -- Write-only. Endpoint 0 Interrupt Disable + PEP_0 : Boolean := False; + -- Write-only. Endpoint 1 Interrupt Disable + PEP_1 : Boolean := False; + -- Write-only. Endpoint 2 Interrupt Disable + PEP_2 : Boolean := False; + -- Write-only. Endpoint 3 Interrupt Disable + PEP_3 : Boolean := False; + -- Write-only. Endpoint 4 Interrupt Disable + PEP_4 : Boolean := False; + -- Write-only. Endpoint 5 Interrupt Disable + PEP_5 : Boolean := False; + -- Write-only. Endpoint 6 Interrupt Disable + PEP_6 : Boolean := False; + -- Write-only. Endpoint 7 Interrupt Disable + PEP_7 : Boolean := False; + -- Write-only. Endpoint 8 Interrupt Disable + PEP_8 : Boolean := False; + -- Write-only. Endpoint 9 Interrupt Disable + PEP_9 : Boolean := False; + -- unspecified + Reserved_22_24 : HAL.UInt3 := 16#0#; + -- Write-only. DMA Channel 1 Interrupt Disable + DMA_1 : Boolean := False; + -- Write-only. DMA Channel 2 Interrupt Disable + DMA_2 : Boolean := False; + -- Write-only. DMA Channel 3 Interrupt Disable + DMA_3 : Boolean := False; + -- Write-only. DMA Channel 4 Interrupt Disable + DMA_4 : Boolean := False; + -- Write-only. DMA Channel 5 Interrupt Disable + DMA_5 : Boolean := False; + -- Write-only. DMA Channel 6 Interrupt Disable + DMA_6 : Boolean := False; + -- Write-only. DMA Channel 7 Interrupt Disable + DMA_7 : Boolean := False; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for USBHS_USBHS_DEVIDR_Register use record + SUSPEC at 0 range 0 .. 0; + MSOFEC at 0 range 1 .. 1; + SOFEC at 0 range 2 .. 2; + EORSTEC at 0 range 3 .. 3; + WAKEUPEC at 0 range 4 .. 4; + EORSMEC at 0 range 5 .. 5; + UPRSMEC at 0 range 6 .. 6; + Reserved_7_11 at 0 range 7 .. 11; + PEP_0 at 0 range 12 .. 12; + PEP_1 at 0 range 13 .. 13; + PEP_2 at 0 range 14 .. 14; + PEP_3 at 0 range 15 .. 15; + PEP_4 at 0 range 16 .. 16; + PEP_5 at 0 range 17 .. 17; + PEP_6 at 0 range 18 .. 18; + PEP_7 at 0 range 19 .. 19; + PEP_8 at 0 range 20 .. 20; + PEP_9 at 0 range 21 .. 21; + Reserved_22_24 at 0 range 22 .. 24; + DMA_1 at 0 range 25 .. 25; + DMA_2 at 0 range 26 .. 26; + DMA_3 at 0 range 27 .. 27; + DMA_4 at 0 range 28 .. 28; + DMA_5 at 0 range 29 .. 29; + DMA_6 at 0 range 30 .. 30; + DMA_7 at 0 range 31 .. 31; + end record; + + -- Device Global Interrupt Enable Register + type USBHS_USBHS_DEVIER_Register is record + -- Write-only. Suspend Interrupt Enable + SUSPES : Boolean := False; + -- Write-only. Micro Start of Frame Interrupt Enable + MSOFES : Boolean := False; + -- Write-only. Start of Frame Interrupt Enable + SOFES : Boolean := False; + -- Write-only. End of Reset Interrupt Enable + EORSTES : Boolean := False; + -- Write-only. Wake-Up Interrupt Enable + WAKEUPES : Boolean := False; + -- Write-only. End of Resume Interrupt Enable + EORSMES : Boolean := False; + -- Write-only. Upstream Resume Interrupt Enable + UPRSMES : Boolean := False; + -- unspecified + Reserved_7_11 : HAL.UInt5 := 16#0#; + -- Write-only. Endpoint 0 Interrupt Enable + PEP_0 : Boolean := False; + -- Write-only. Endpoint 1 Interrupt Enable + PEP_1 : Boolean := False; + -- Write-only. Endpoint 2 Interrupt Enable + PEP_2 : Boolean := False; + -- Write-only. Endpoint 3 Interrupt Enable + PEP_3 : Boolean := False; + -- Write-only. Endpoint 4 Interrupt Enable + PEP_4 : Boolean := False; + -- Write-only. Endpoint 5 Interrupt Enable + PEP_5 : Boolean := False; + -- Write-only. Endpoint 6 Interrupt Enable + PEP_6 : Boolean := False; + -- Write-only. Endpoint 7 Interrupt Enable + PEP_7 : Boolean := False; + -- Write-only. Endpoint 8 Interrupt Enable + PEP_8 : Boolean := False; + -- Write-only. Endpoint 9 Interrupt Enable + PEP_9 : Boolean := False; + -- unspecified + Reserved_22_24 : HAL.UInt3 := 16#0#; + -- Write-only. DMA Channel 1 Interrupt Enable + DMA_1 : Boolean := False; + -- Write-only. DMA Channel 2 Interrupt Enable + DMA_2 : Boolean := False; + -- Write-only. DMA Channel 3 Interrupt Enable + DMA_3 : Boolean := False; + -- Write-only. DMA Channel 4 Interrupt Enable + DMA_4 : Boolean := False; + -- Write-only. DMA Channel 5 Interrupt Enable + DMA_5 : Boolean := False; + -- Write-only. DMA Channel 6 Interrupt Enable + DMA_6 : Boolean := False; + -- Write-only. DMA Channel 7 Interrupt Enable + DMA_7 : Boolean := False; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for USBHS_USBHS_DEVIER_Register use record + SUSPES at 0 range 0 .. 0; + MSOFES at 0 range 1 .. 1; + SOFES at 0 range 2 .. 2; + EORSTES at 0 range 3 .. 3; + WAKEUPES at 0 range 4 .. 4; + EORSMES at 0 range 5 .. 5; + UPRSMES at 0 range 6 .. 6; + Reserved_7_11 at 0 range 7 .. 11; + PEP_0 at 0 range 12 .. 12; + PEP_1 at 0 range 13 .. 13; + PEP_2 at 0 range 14 .. 14; + PEP_3 at 0 range 15 .. 15; + PEP_4 at 0 range 16 .. 16; + PEP_5 at 0 range 17 .. 17; + PEP_6 at 0 range 18 .. 18; + PEP_7 at 0 range 19 .. 19; + PEP_8 at 0 range 20 .. 20; + PEP_9 at 0 range 21 .. 21; + Reserved_22_24 at 0 range 22 .. 24; + DMA_1 at 0 range 25 .. 25; + DMA_2 at 0 range 26 .. 26; + DMA_3 at 0 range 27 .. 27; + DMA_4 at 0 range 28 .. 28; + DMA_5 at 0 range 29 .. 29; + DMA_6 at 0 range 30 .. 30; + DMA_7 at 0 range 31 .. 31; + end record; + + -- USBHS_USBHS_DEVEPT_EPEN array + type USBHS_USBHS_DEVEPT_EPEN_Field_Array is array (0 .. 9) of Boolean + with Component_Size => 1, Size => 10; + + -- Type definition for USBHS_USBHS_DEVEPT_EPEN + type USBHS_USBHS_DEVEPT_EPEN_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- EPEN as a value + Val : HAL.UInt10; + when True => + -- EPEN as an array + Arr : USBHS_USBHS_DEVEPT_EPEN_Field_Array; + end case; + end record + with Unchecked_Union, Size => 10; + + for USBHS_USBHS_DEVEPT_EPEN_Field use record + Val at 0 range 0 .. 9; + Arr at 0 range 0 .. 9; + end record; + + -- USBHS_USBHS_DEVEPT_EPRST array + type USBHS_USBHS_DEVEPT_EPRST_Field_Array is array (0 .. 9) of Boolean + with Component_Size => 1, Size => 10; + + -- Type definition for USBHS_USBHS_DEVEPT_EPRST + type USBHS_USBHS_DEVEPT_EPRST_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- EPRST as a value + Val : HAL.UInt10; + when True => + -- EPRST as an array + Arr : USBHS_USBHS_DEVEPT_EPRST_Field_Array; + end case; + end record + with Unchecked_Union, Size => 10; + + for USBHS_USBHS_DEVEPT_EPRST_Field use record + Val at 0 range 0 .. 9; + Arr at 0 range 0 .. 9; + end record; + + -- Device Endpoint Register + type USBHS_USBHS_DEVEPT_Register is record + -- Endpoint 0 Enable + EPEN : USBHS_USBHS_DEVEPT_EPEN_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_10_15 : HAL.UInt6 := 16#0#; + -- Endpoint 0 Reset + EPRST : USBHS_USBHS_DEVEPT_EPRST_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_26_31 : HAL.UInt6 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for USBHS_USBHS_DEVEPT_Register use record + EPEN at 0 range 0 .. 9; + Reserved_10_15 at 0 range 10 .. 15; + EPRST at 0 range 16 .. 25; + Reserved_26_31 at 0 range 26 .. 31; + end record; + + subtype USBHS_USBHS_DEVFNUM_MFNUM_Field is HAL.UInt3; + subtype USBHS_USBHS_DEVFNUM_FNUM_Field is HAL.UInt11; + + -- Device Frame Number Register + type USBHS_USBHS_DEVFNUM_Register is record + -- Read-only. Micro Frame Number + MFNUM : USBHS_USBHS_DEVFNUM_MFNUM_Field; + -- Read-only. Frame Number + FNUM : USBHS_USBHS_DEVFNUM_FNUM_Field; + -- unspecified + Reserved_14_14 : HAL.Bit; + -- Read-only. Frame Number CRC Error + FNCERR : Boolean; + -- unspecified + Reserved_16_31 : HAL.UInt16; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for USBHS_USBHS_DEVFNUM_Register use record + MFNUM at 0 range 0 .. 2; + FNUM at 0 range 3 .. 13; + Reserved_14_14 at 0 range 14 .. 14; + FNCERR at 0 range 15 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + -- Endpoint Banks + type USBHS_DEVEPTCFG_EPBK_Field is + ( + -- Single-bank endpoint + Val_1_Bank, + -- Double-bank endpoint + Val_2_Bank, + -- Triple-bank endpoint + Val_3_Bank) + with Size => 2; + for USBHS_DEVEPTCFG_EPBK_Field use + (Val_1_Bank => 0, + Val_2_Bank => 1, + Val_3_Bank => 2); + + -- Endpoint Size + type USBHS_DEVEPTCFG_EPSIZE_Field is + ( + -- 8 bytes + Val_8_Byte, + -- 16 bytes + Val_16_Byte, + -- 32 bytes + Val_32_Byte, + -- 64 bytes + Val_64_Byte, + -- 128 bytes + Val_128_Byte, + -- 256 bytes + Val_256_Byte, + -- 512 bytes + Val_512_Byte, + -- 1024 bytes + Val_1024_Byte) + with Size => 3; + for USBHS_DEVEPTCFG_EPSIZE_Field use + (Val_8_Byte => 0, + Val_16_Byte => 1, + Val_32_Byte => 2, + Val_64_Byte => 3, + Val_128_Byte => 4, + Val_256_Byte => 5, + Val_512_Byte => 6, + Val_1024_Byte => 7); + + -- Endpoint Direction + type USBHS_DEVEPTCFG_EPDIR_Field is + ( + -- The endpoint direction is OUT. + Out_k, + -- The endpoint direction is IN (nor for control endpoints). + In_k) + with Size => 1; + for USBHS_DEVEPTCFG_EPDIR_Field use + (Out_k => 0, + In_k => 1); + + -- Endpoint Type + type USBHS_DEVEPTCFG_EPTYPE_Field is + ( + -- Control + Ctrl, + -- Isochronous + Iso, + -- Bulk + Blk, + -- Interrupt + Intrpt) + with Size => 2; + for USBHS_DEVEPTCFG_EPTYPE_Field use + (Ctrl => 0, + Iso => 1, + Blk => 2, + Intrpt => 3); + + -- Number of transactions per microframe for isochronous endpoint + type USBHS_DEVEPTCFG_NBTRANS_Field is + ( + -- Reserved to endpoint that does not have the high-bandwidth + -- isochronous capability. + Val_0_Trans, + -- Default value: one transaction per microframe. + Val_1_Trans, + -- Two transactions per microframe. This endpoint should be configured + -- as double-bank. + Val_2_Trans, + -- Three transactions per microframe. This endpoint should be configured + -- as triple-bank. + Val_3_Trans) + with Size => 2; + for USBHS_DEVEPTCFG_NBTRANS_Field use + (Val_0_Trans => 0, + Val_1_Trans => 1, + Val_2_Trans => 2, + Val_3_Trans => 3); + + -- Device Endpoint Configuration Register (n = 0) 0 + type USBHS_USBHS_DEVEPTCFG_Register is record + -- unspecified + Reserved_0_0 : HAL.Bit := 16#0#; + -- Endpoint Memory Allocate + ALLOC : Boolean := False; + -- Endpoint Banks + EPBK : USBHS_DEVEPTCFG_EPBK_Field := SAM_SVD.USBHS.Val_1_Bank; + -- Endpoint Size + EPSIZE : USBHS_DEVEPTCFG_EPSIZE_Field := + SAM_SVD.USBHS.Val_8_Byte; + -- unspecified + Reserved_7_7 : HAL.Bit := 16#0#; + -- Endpoint Direction + EPDIR : USBHS_DEVEPTCFG_EPDIR_Field := SAM_SVD.USBHS.Out_k; + -- Automatic Switch + AUTOSW : Boolean := False; + -- unspecified + Reserved_10_10 : HAL.Bit := 16#0#; + -- Endpoint Type + EPTYPE : USBHS_DEVEPTCFG_EPTYPE_Field := SAM_SVD.USBHS.Ctrl; + -- Number of transactions per microframe for isochronous endpoint + NBTRANS : USBHS_DEVEPTCFG_NBTRANS_Field := + SAM_SVD.USBHS.Val_0_Trans; + -- unspecified + Reserved_15_31 : HAL.UInt17 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for USBHS_USBHS_DEVEPTCFG_Register use record + Reserved_0_0 at 0 range 0 .. 0; + ALLOC at 0 range 1 .. 1; + EPBK at 0 range 2 .. 3; + EPSIZE at 0 range 4 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + EPDIR at 0 range 8 .. 8; + AUTOSW at 0 range 9 .. 9; + Reserved_10_10 at 0 range 10 .. 10; + EPTYPE at 0 range 11 .. 12; + NBTRANS at 0 range 13 .. 14; + Reserved_15_31 at 0 range 15 .. 31; + end record; + + -- Device Endpoint Configuration Register (n = 0) 0 + type USBHS_USBHS_DEVEPTCFG_Registers is array (0 .. 9) + of USBHS_USBHS_DEVEPTCFG_Register + with Volatile; + + -- Data Toggle Sequence + type USBHS_DEVEPTISR_DTSEQ_Field is + ( + -- Data0 toggle sequence + Data0, + -- Data1 toggle sequence + Data1, + -- Reserved for high-bandwidth isochronous endpoint + Data2, + -- Reserved for high-bandwidth isochronous endpoint + Mdata) + with Size => 2; + for USBHS_DEVEPTISR_DTSEQ_Field use + (Data0 => 0, + Data1 => 1, + Data2 => 2, + Mdata => 3); + + -- Number of Busy Banks + type USBHS_DEVEPTISR_NBUSYBK_Field is + ( + -- 0 busy bank (all banks free) + Val_0_Busy, + -- 1 busy bank + Val_1_Busy, + -- 2 busy banks + Val_2_Busy, + -- 3 busy banks + Val_3_Busy) + with Size => 2; + for USBHS_DEVEPTISR_NBUSYBK_Field use + (Val_0_Busy => 0, + Val_1_Busy => 1, + Val_2_Busy => 2, + Val_3_Busy => 3); + + -- Current Bank + type USBHS_DEVEPTISR_CURRBK_Field is + ( + -- Current bank is bank0 + Bank0, + -- Current bank is bank1 + Bank1, + -- Current bank is bank2 + Bank2) + with Size => 2; + for USBHS_DEVEPTISR_CURRBK_Field use + (Bank0 => 0, + Bank1 => 1, + Bank2 => 2); + + subtype USBHS_USBHS_DEVEPTISR_BYCT_Field is HAL.UInt11; + + -- Device Endpoint Status Register (n = 0) 0 + type USBHS_USBHS_DEVEPTISR_Register is record + -- Read-only. Transmitted IN Data Interrupt + TXINI : Boolean; + -- Read-only. Received OUT Data Interrupt + RXOUTI : Boolean; + -- Read-only. Received SETUP Interrupt + RXSTPI : Boolean; + -- Read-only. NAKed OUT Interrupt + NAKOUTI : Boolean; + -- Read-only. NAKed IN Interrupt + NAKINI : Boolean; + -- Read-only. Overflow Interrupt + OVERFI : Boolean; + -- Read-only. STALLed Interrupt + STALLEDI : Boolean; + -- Read-only. Short Packet Interrupt + SHORTPACKET : Boolean; + -- Read-only. Data Toggle Sequence + DTSEQ : USBHS_DEVEPTISR_DTSEQ_Field; + -- unspecified + Reserved_10_11 : HAL.UInt2; + -- Read-only. Number of Busy Banks + NBUSYBK : USBHS_DEVEPTISR_NBUSYBK_Field; + -- Read-only. Current Bank + CURRBK : USBHS_DEVEPTISR_CURRBK_Field; + -- Read-only. Read/Write Allowed + RWALL : Boolean; + -- Read-only. Control Direction + CTRLDIR : Boolean; + -- Read-only. Configuration OK Status + CFGOK : Boolean; + -- unspecified + Reserved_19_19 : HAL.Bit; + -- Read-only. Byte Count + BYCT : USBHS_USBHS_DEVEPTISR_BYCT_Field; + -- unspecified + Reserved_31_31 : HAL.Bit; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for USBHS_USBHS_DEVEPTISR_Register use record + TXINI at 0 range 0 .. 0; + RXOUTI at 0 range 1 .. 1; + RXSTPI at 0 range 2 .. 2; + NAKOUTI at 0 range 3 .. 3; + NAKINI at 0 range 4 .. 4; + OVERFI at 0 range 5 .. 5; + STALLEDI at 0 range 6 .. 6; + SHORTPACKET at 0 range 7 .. 7; + DTSEQ at 0 range 8 .. 9; + Reserved_10_11 at 0 range 10 .. 11; + NBUSYBK at 0 range 12 .. 13; + CURRBK at 0 range 14 .. 15; + RWALL at 0 range 16 .. 16; + CTRLDIR at 0 range 17 .. 17; + CFGOK at 0 range 18 .. 18; + Reserved_19_19 at 0 range 19 .. 19; + BYCT at 0 range 20 .. 30; + Reserved_31_31 at 0 range 31 .. 31; + end record; + + -- Device Endpoint Status Register (n = 0) 0 + type USBHS_USBHS_DEVEPTISR_Registers is array (0 .. 9) + of USBHS_USBHS_DEVEPTISR_Register + with Volatile; + + -- Device Endpoint Clear Register (n = 0) 0 + type USBHS_USBHS_DEVEPTICR_Register is record + -- Write-only. Transmitted IN Data Interrupt Clear + TXINIC : Boolean := False; + -- Write-only. Received OUT Data Interrupt Clear + RXOUTIC : Boolean := False; + -- Write-only. Received SETUP Interrupt Clear + RXSTPIC : Boolean := False; + -- Write-only. NAKed OUT Interrupt Clear + NAKOUTIC : Boolean := False; + -- Write-only. NAKed IN Interrupt Clear + NAKINIC : Boolean := False; + -- Write-only. Overflow Interrupt Clear + OVERFIC : Boolean := False; + -- Write-only. STALLed Interrupt Clear + STALLEDIC : Boolean := False; + -- Write-only. Short Packet Interrupt Clear + SHORTPACKETC : Boolean := False; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for USBHS_USBHS_DEVEPTICR_Register use record + TXINIC at 0 range 0 .. 0; + RXOUTIC at 0 range 1 .. 1; + RXSTPIC at 0 range 2 .. 2; + NAKOUTIC at 0 range 3 .. 3; + NAKINIC at 0 range 4 .. 4; + OVERFIC at 0 range 5 .. 5; + STALLEDIC at 0 range 6 .. 6; + SHORTPACKETC at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- Device Endpoint Clear Register (n = 0) 0 + type USBHS_USBHS_DEVEPTICR_Registers is array (0 .. 9) + of USBHS_USBHS_DEVEPTICR_Register + with Volatile; + + -- Device Endpoint Set Register (n = 0) 0 + type USBHS_USBHS_DEVEPTIFR_Register is record + -- Write-only. Transmitted IN Data Interrupt Set + TXINIS : Boolean := False; + -- Write-only. Received OUT Data Interrupt Set + RXOUTIS : Boolean := False; + -- Write-only. Received SETUP Interrupt Set + RXSTPIS : Boolean := False; + -- Write-only. NAKed OUT Interrupt Set + NAKOUTIS : Boolean := False; + -- Write-only. NAKed IN Interrupt Set + NAKINIS : Boolean := False; + -- Write-only. Overflow Interrupt Set + OVERFIS : Boolean := False; + -- Write-only. STALLed Interrupt Set + STALLEDIS : Boolean := False; + -- Write-only. Short Packet Interrupt Set + SHORTPACKETS : Boolean := False; + -- unspecified + Reserved_8_11 : HAL.UInt4 := 16#0#; + -- Write-only. Number of Busy Banks Interrupt Set + NBUSYBKS : Boolean := False; + -- unspecified + Reserved_13_31 : HAL.UInt19 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for USBHS_USBHS_DEVEPTIFR_Register use record + TXINIS at 0 range 0 .. 0; + RXOUTIS at 0 range 1 .. 1; + RXSTPIS at 0 range 2 .. 2; + NAKOUTIS at 0 range 3 .. 3; + NAKINIS at 0 range 4 .. 4; + OVERFIS at 0 range 5 .. 5; + STALLEDIS at 0 range 6 .. 6; + SHORTPACKETS at 0 range 7 .. 7; + Reserved_8_11 at 0 range 8 .. 11; + NBUSYBKS at 0 range 12 .. 12; + Reserved_13_31 at 0 range 13 .. 31; + end record; + + -- Device Endpoint Set Register (n = 0) 0 + type USBHS_USBHS_DEVEPTIFR_Registers is array (0 .. 9) + of USBHS_USBHS_DEVEPTIFR_Register + with Volatile; + + -- Device Endpoint Mask Register (n = 0) 0 + type USBHS_USBHS_DEVEPTIMR_Register is record + -- Read-only. Transmitted IN Data Interrupt + TXINE : Boolean; + -- Read-only. Received OUT Data Interrupt + RXOUTE : Boolean; + -- Read-only. Received SETUP Interrupt + RXSTPE : Boolean; + -- Read-only. NAKed OUT Interrupt + NAKOUTE : Boolean; + -- Read-only. NAKed IN Interrupt + NAKINE : Boolean; + -- Read-only. Overflow Interrupt + OVERFE : Boolean; + -- Read-only. STALLed Interrupt + STALLEDE : Boolean; + -- Read-only. Short Packet Interrupt + SHORTPACKETE : Boolean; + -- unspecified + Reserved_8_11 : HAL.UInt4; + -- Read-only. Number of Busy Banks Interrupt + NBUSYBKE : Boolean; + -- Read-only. Kill IN Bank + KILLBK : Boolean; + -- Read-only. FIFO Control + FIFOCON : Boolean; + -- unspecified + Reserved_15_15 : HAL.Bit; + -- Read-only. Endpoint Interrupts Disable HDMA Request + EPDISHDMA : Boolean; + -- Read-only. NYET Token Disable + NYETDIS : Boolean; + -- Read-only. Reset Data Toggle + RSTDT : Boolean; + -- Read-only. STALL Request + STALLRQ : Boolean; + -- unspecified + Reserved_20_31 : HAL.UInt12; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for USBHS_USBHS_DEVEPTIMR_Register use record + TXINE at 0 range 0 .. 0; + RXOUTE at 0 range 1 .. 1; + RXSTPE at 0 range 2 .. 2; + NAKOUTE at 0 range 3 .. 3; + NAKINE at 0 range 4 .. 4; + OVERFE at 0 range 5 .. 5; + STALLEDE at 0 range 6 .. 6; + SHORTPACKETE at 0 range 7 .. 7; + Reserved_8_11 at 0 range 8 .. 11; + NBUSYBKE at 0 range 12 .. 12; + KILLBK at 0 range 13 .. 13; + FIFOCON at 0 range 14 .. 14; + Reserved_15_15 at 0 range 15 .. 15; + EPDISHDMA at 0 range 16 .. 16; + NYETDIS at 0 range 17 .. 17; + RSTDT at 0 range 18 .. 18; + STALLRQ at 0 range 19 .. 19; + Reserved_20_31 at 0 range 20 .. 31; + end record; + + -- Device Endpoint Mask Register (n = 0) 0 + type USBHS_USBHS_DEVEPTIMR_Registers is array (0 .. 9) + of USBHS_USBHS_DEVEPTIMR_Register + with Volatile; + + -- Device Endpoint Enable Register (n = 0) 0 + type USBHS_USBHS_DEVEPTIER_Register is record + -- Write-only. Transmitted IN Data Interrupt Enable + TXINES : Boolean := False; + -- Write-only. Received OUT Data Interrupt Enable + RXOUTES : Boolean := False; + -- Write-only. Received SETUP Interrupt Enable + RXSTPES : Boolean := False; + -- Write-only. NAKed OUT Interrupt Enable + NAKOUTES : Boolean := False; + -- Write-only. NAKed IN Interrupt Enable + NAKINES : Boolean := False; + -- Write-only. Overflow Interrupt Enable + OVERFES : Boolean := False; + -- Write-only. STALLed Interrupt Enable + STALLEDES : Boolean := False; + -- Write-only. Short Packet Interrupt Enable + SHORTPACKETES : Boolean := False; + -- unspecified + Reserved_8_11 : HAL.UInt4 := 16#0#; + -- Write-only. Number of Busy Banks Interrupt Enable + NBUSYBKES : Boolean := False; + -- Write-only. Kill IN Bank + KILLBKS : Boolean := False; + -- Write-only. FIFO Control + FIFOCONS : Boolean := False; + -- unspecified + Reserved_15_15 : HAL.Bit := 16#0#; + -- Write-only. Endpoint Interrupts Disable HDMA Request Enable + EPDISHDMAS : Boolean := False; + -- Write-only. NYET Token Disable Enable + NYETDISS : Boolean := False; + -- Write-only. Reset Data Toggle Enable + RSTDTS : Boolean := False; + -- Write-only. STALL Request Enable + STALLRQS : Boolean := False; + -- unspecified + Reserved_20_31 : HAL.UInt12 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for USBHS_USBHS_DEVEPTIER_Register use record + TXINES at 0 range 0 .. 0; + RXOUTES at 0 range 1 .. 1; + RXSTPES at 0 range 2 .. 2; + NAKOUTES at 0 range 3 .. 3; + NAKINES at 0 range 4 .. 4; + OVERFES at 0 range 5 .. 5; + STALLEDES at 0 range 6 .. 6; + SHORTPACKETES at 0 range 7 .. 7; + Reserved_8_11 at 0 range 8 .. 11; + NBUSYBKES at 0 range 12 .. 12; + KILLBKS at 0 range 13 .. 13; + FIFOCONS at 0 range 14 .. 14; + Reserved_15_15 at 0 range 15 .. 15; + EPDISHDMAS at 0 range 16 .. 16; + NYETDISS at 0 range 17 .. 17; + RSTDTS at 0 range 18 .. 18; + STALLRQS at 0 range 19 .. 19; + Reserved_20_31 at 0 range 20 .. 31; + end record; + + -- Device Endpoint Enable Register (n = 0) 0 + type USBHS_USBHS_DEVEPTIER_Registers is array (0 .. 9) + of USBHS_USBHS_DEVEPTIER_Register + with Volatile; + + -- Device Endpoint Disable Register (n = 0) 0 + type USBHS_USBHS_DEVEPTIDR_Register is record + -- Write-only. Transmitted IN Interrupt Clear + TXINEC : Boolean := False; + -- Write-only. Received OUT Data Interrupt Clear + RXOUTEC : Boolean := False; + -- Write-only. Received SETUP Interrupt Clear + RXSTPEC : Boolean := False; + -- Write-only. NAKed OUT Interrupt Clear + NAKOUTEC : Boolean := False; + -- Write-only. NAKed IN Interrupt Clear + NAKINEC : Boolean := False; + -- Write-only. Overflow Interrupt Clear + OVERFEC : Boolean := False; + -- Write-only. STALLed Interrupt Clear + STALLEDEC : Boolean := False; + -- Write-only. Shortpacket Interrupt Clear + SHORTPACKETEC : Boolean := False; + -- unspecified + Reserved_8_11 : HAL.UInt4 := 16#0#; + -- Write-only. Number of Busy Banks Interrupt Clear + NBUSYBKEC : Boolean := False; + -- unspecified + Reserved_13_13 : HAL.Bit := 16#0#; + -- Write-only. FIFO Control Clear + FIFOCONC : Boolean := False; + -- unspecified + Reserved_15_15 : HAL.Bit := 16#0#; + -- Write-only. Endpoint Interrupts Disable HDMA Request Clear + EPDISHDMAC : Boolean := False; + -- Write-only. NYET Token Disable Clear + NYETDISC : Boolean := False; + -- unspecified + Reserved_18_18 : HAL.Bit := 16#0#; + -- Write-only. STALL Request Clear + STALLRQC : Boolean := False; + -- unspecified + Reserved_20_31 : HAL.UInt12 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for USBHS_USBHS_DEVEPTIDR_Register use record + TXINEC at 0 range 0 .. 0; + RXOUTEC at 0 range 1 .. 1; + RXSTPEC at 0 range 2 .. 2; + NAKOUTEC at 0 range 3 .. 3; + NAKINEC at 0 range 4 .. 4; + OVERFEC at 0 range 5 .. 5; + STALLEDEC at 0 range 6 .. 6; + SHORTPACKETEC at 0 range 7 .. 7; + Reserved_8_11 at 0 range 8 .. 11; + NBUSYBKEC at 0 range 12 .. 12; + Reserved_13_13 at 0 range 13 .. 13; + FIFOCONC at 0 range 14 .. 14; + Reserved_15_15 at 0 range 15 .. 15; + EPDISHDMAC at 0 range 16 .. 16; + NYETDISC at 0 range 17 .. 17; + Reserved_18_18 at 0 range 18 .. 18; + STALLRQC at 0 range 19 .. 19; + Reserved_20_31 at 0 range 20 .. 31; + end record; + + -- Device Endpoint Disable Register (n = 0) 0 + type USBHS_USBHS_DEVEPTIDR_Registers is array (0 .. 9) + of USBHS_USBHS_DEVEPTIDR_Register + with Volatile; + + -------------------------------------------- + -- USBHS_USBHS_DEVDMA cluster's Registers -- + -------------------------------------------- + + subtype USBHS_USBHS_DEVDMACONTROL_USBHS_USBHS_DEVDMA_BUFF_LENGTH_Field is + HAL.UInt16; + + -- Device DMA Channel Control Register (n = 1) + type USBHS_USBHS_DEVDMACONTROL_USBHS_USBHS_DEVDMA_Register is record + -- Channel Enable Command + CHANN_ENB : Boolean := False; + -- Load Next Channel Transfer Descriptor Enable Command + LDNXT_DSC : Boolean := False; + -- End of Transfer Enable Control (OUT transfers only) + END_TR_EN : Boolean := False; + -- End of Buffer Enable Control + END_B_EN : Boolean := False; + -- End of Transfer Interrupt Enable + END_TR_IT : Boolean := False; + -- End of Buffer Interrupt Enable + END_BUFFIT : Boolean := False; + -- Descriptor Loaded Interrupt Enable + DESC_LD_IT : Boolean := False; + -- Burst Lock Enable + BURST_LCK : Boolean := False; + -- unspecified + Reserved_8_15 : HAL.UInt8 := 16#0#; + -- Buffer Byte Length (Write-only) + BUFF_LENGTH : USBHS_USBHS_DEVDMACONTROL_USBHS_USBHS_DEVDMA_BUFF_LENGTH_Field := + 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for USBHS_USBHS_DEVDMACONTROL_USBHS_USBHS_DEVDMA_Register use record + CHANN_ENB at 0 range 0 .. 0; + LDNXT_DSC at 0 range 1 .. 1; + END_TR_EN at 0 range 2 .. 2; + END_B_EN at 0 range 3 .. 3; + END_TR_IT at 0 range 4 .. 4; + END_BUFFIT at 0 range 5 .. 5; + DESC_LD_IT at 0 range 6 .. 6; + BURST_LCK at 0 range 7 .. 7; + Reserved_8_15 at 0 range 8 .. 15; + BUFF_LENGTH at 0 range 16 .. 31; + end record; + + subtype USBHS_USBHS_DEVDMASTATUS_USBHS_USBHS_DEVDMA_BUFF_COUNT_Field is + HAL.UInt16; + + -- Device DMA Channel Status Register (n = 1) + type USBHS_USBHS_DEVDMASTATUS_USBHS_USBHS_DEVDMA_Register is record + -- Channel Enable Status + CHANN_ENB : Boolean := False; + -- Channel Active Status + CHANN_ACT : Boolean := False; + -- unspecified + Reserved_2_3 : HAL.UInt2 := 16#0#; + -- End of Channel Transfer Status + END_TR_ST : Boolean := False; + -- End of Channel Buffer Status + END_BF_ST : Boolean := False; + -- Descriptor Loaded Status + DESC_LDST : Boolean := False; + -- unspecified + Reserved_7_15 : HAL.UInt9 := 16#0#; + -- Buffer Byte Count + BUFF_COUNT : USBHS_USBHS_DEVDMASTATUS_USBHS_USBHS_DEVDMA_BUFF_COUNT_Field := + 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for USBHS_USBHS_DEVDMASTATUS_USBHS_USBHS_DEVDMA_Register use record + CHANN_ENB at 0 range 0 .. 0; + CHANN_ACT at 0 range 1 .. 1; + Reserved_2_3 at 0 range 2 .. 3; + END_TR_ST at 0 range 4 .. 4; + END_BF_ST at 0 range 5 .. 5; + DESC_LDST at 0 range 6 .. 6; + Reserved_7_15 at 0 range 7 .. 15; + BUFF_COUNT at 0 range 16 .. 31; + end record; + + -- Device DMA Channel Next Descriptor Address Register (n = 1) + type USBHS_USBHS_DEVDMA_Cluster is record + -- Device DMA Channel Next Descriptor Address Register (n = 1) + USBHS_DEVDMANXTDSC : aliased HAL.UInt32; + -- Device DMA Channel Address Register (n = 1) + USBHS_DEVDMAADDRESS : aliased HAL.UInt32; + -- Device DMA Channel Control Register (n = 1) + USBHS_DEVDMACONTROL : aliased USBHS_USBHS_DEVDMACONTROL_USBHS_USBHS_DEVDMA_Register; + -- Device DMA Channel Status Register (n = 1) + USBHS_DEVDMASTATUS : aliased USBHS_USBHS_DEVDMASTATUS_USBHS_USBHS_DEVDMA_Register; + end record + with Volatile, Size => 128; + + for USBHS_USBHS_DEVDMA_Cluster use record + USBHS_DEVDMANXTDSC at 16#0# range 0 .. 31; + USBHS_DEVDMAADDRESS at 16#4# range 0 .. 31; + USBHS_DEVDMACONTROL at 16#8# range 0 .. 31; + USBHS_DEVDMASTATUS at 16#C# range 0 .. 31; + end record; + + -- Device DMA Channel Next Descriptor Address Register (n = 1) + type USBHS_USBHS_DEVDMA_Clusters is array (0 .. 6) + of USBHS_USBHS_DEVDMA_Cluster; + + -- Mode Configuration + type USBHS_HSTCTRL_SPDCONF_Field is + ( + -- The host starts in Full-speed mode and performs a high-speed reset to + -- switch to High-speed mode if the downstream peripheral is high-speed + -- capable. + Normal, + -- For a better consumption, if high speed is not needed. + Low_Power, + -- Forced high speed. + High_Speed, + -- The host remains in Full-speed mode whatever the peripheral speed + -- capability. + Forced_Fs) + with Size => 2; + for USBHS_HSTCTRL_SPDCONF_Field use + (Normal => 0, + Low_Power => 1, + High_Speed => 2, + Forced_Fs => 3); + + -- Host General Control Register + type USBHS_USBHS_HSTCTRL_Register is record + -- unspecified + Reserved_0_7 : HAL.UInt8 := 16#0#; + -- Start of Frame Generation Enable + SOFE : Boolean := False; + -- Send USB Reset + RESET : Boolean := False; + -- Send USB Resume + RESUME : Boolean := False; + -- unspecified + Reserved_11_11 : HAL.Bit := 16#0#; + -- Mode Configuration + SPDCONF : USBHS_HSTCTRL_SPDCONF_Field := SAM_SVD.USBHS.Normal; + -- unspecified + Reserved_14_31 : HAL.UInt18 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for USBHS_USBHS_HSTCTRL_Register use record + Reserved_0_7 at 0 range 0 .. 7; + SOFE at 0 range 8 .. 8; + RESET at 0 range 9 .. 9; + RESUME at 0 range 10 .. 10; + Reserved_11_11 at 0 range 11 .. 11; + SPDCONF at 0 range 12 .. 13; + Reserved_14_31 at 0 range 14 .. 31; + end record; + + -- Host Global Interrupt Status Register + type USBHS_USBHS_HSTISR_Register is record + -- Read-only. Device Connection Interrupt + DCONNI : Boolean; + -- Read-only. Device Disconnection Interrupt + DDISCI : Boolean; + -- Read-only. USB Reset Sent Interrupt + RSTI : Boolean; + -- Read-only. Downstream Resume Sent Interrupt + RSMEDI : Boolean; + -- Read-only. Upstream Resume Received Interrupt + RXRSMI : Boolean; + -- Read-only. Host Start of Frame Interrupt + HSOFI : Boolean; + -- Read-only. Host Wake-Up Interrupt + HWUPI : Boolean; + -- unspecified + Reserved_7_7 : HAL.Bit; + -- Read-only. Pipe 0 Interrupt + PEP_0 : Boolean; + -- Read-only. Pipe 1 Interrupt + PEP_1 : Boolean; + -- Read-only. Pipe 2 Interrupt + PEP_2 : Boolean; + -- Read-only. Pipe 3 Interrupt + PEP_3 : Boolean; + -- Read-only. Pipe 4 Interrupt + PEP_4 : Boolean; + -- Read-only. Pipe 5 Interrupt + PEP_5 : Boolean; + -- Read-only. Pipe 6 Interrupt + PEP_6 : Boolean; + -- Read-only. Pipe 7 Interrupt + PEP_7 : Boolean; + -- Read-only. Pipe 8 Interrupt + PEP_8 : Boolean; + -- Read-only. Pipe 9 Interrupt + PEP_9 : Boolean; + -- unspecified + Reserved_18_24 : HAL.UInt7; + -- Read-only. DMA Channel 1 Interrupt + DMA_1 : Boolean; + -- Read-only. DMA Channel 2 Interrupt + DMA_2 : Boolean; + -- Read-only. DMA Channel 3 Interrupt + DMA_3 : Boolean; + -- Read-only. DMA Channel 4 Interrupt + DMA_4 : Boolean; + -- Read-only. DMA Channel 5 Interrupt + DMA_5 : Boolean; + -- Read-only. DMA Channel 6 Interrupt + DMA_6 : Boolean; + -- Read-only. DMA Channel 7 Interrupt + DMA_7 : Boolean; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for USBHS_USBHS_HSTISR_Register use record + DCONNI at 0 range 0 .. 0; + DDISCI at 0 range 1 .. 1; + RSTI at 0 range 2 .. 2; + RSMEDI at 0 range 3 .. 3; + RXRSMI at 0 range 4 .. 4; + HSOFI at 0 range 5 .. 5; + HWUPI at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + PEP_0 at 0 range 8 .. 8; + PEP_1 at 0 range 9 .. 9; + PEP_2 at 0 range 10 .. 10; + PEP_3 at 0 range 11 .. 11; + PEP_4 at 0 range 12 .. 12; + PEP_5 at 0 range 13 .. 13; + PEP_6 at 0 range 14 .. 14; + PEP_7 at 0 range 15 .. 15; + PEP_8 at 0 range 16 .. 16; + PEP_9 at 0 range 17 .. 17; + Reserved_18_24 at 0 range 18 .. 24; + DMA_1 at 0 range 25 .. 25; + DMA_2 at 0 range 26 .. 26; + DMA_3 at 0 range 27 .. 27; + DMA_4 at 0 range 28 .. 28; + DMA_5 at 0 range 29 .. 29; + DMA_6 at 0 range 30 .. 30; + DMA_7 at 0 range 31 .. 31; + end record; + + -- Host Global Interrupt Clear Register + type USBHS_USBHS_HSTICR_Register is record + -- Write-only. Device Connection Interrupt Clear + DCONNIC : Boolean := False; + -- Write-only. Device Disconnection Interrupt Clear + DDISCIC : Boolean := False; + -- Write-only. USB Reset Sent Interrupt Clear + RSTIC : Boolean := False; + -- Write-only. Downstream Resume Sent Interrupt Clear + RSMEDIC : Boolean := False; + -- Write-only. Upstream Resume Received Interrupt Clear + RXRSMIC : Boolean := False; + -- Write-only. Host Start of Frame Interrupt Clear + HSOFIC : Boolean := False; + -- Write-only. Host Wake-Up Interrupt Clear + HWUPIC : Boolean := False; + -- unspecified + Reserved_7_31 : HAL.UInt25 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for USBHS_USBHS_HSTICR_Register use record + DCONNIC at 0 range 0 .. 0; + DDISCIC at 0 range 1 .. 1; + RSTIC at 0 range 2 .. 2; + RSMEDIC at 0 range 3 .. 3; + RXRSMIC at 0 range 4 .. 4; + HSOFIC at 0 range 5 .. 5; + HWUPIC at 0 range 6 .. 6; + Reserved_7_31 at 0 range 7 .. 31; + end record; + + -- Host Global Interrupt Set Register + type USBHS_USBHS_HSTIFR_Register is record + -- Write-only. Device Connection Interrupt Set + DCONNIS : Boolean := False; + -- Write-only. Device Disconnection Interrupt Set + DDISCIS : Boolean := False; + -- Write-only. USB Reset Sent Interrupt Set + RSTIS : Boolean := False; + -- Write-only. Downstream Resume Sent Interrupt Set + RSMEDIS : Boolean := False; + -- Write-only. Upstream Resume Received Interrupt Set + RXRSMIS : Boolean := False; + -- Write-only. Host Start of Frame Interrupt Set + HSOFIS : Boolean := False; + -- Write-only. Host Wake-Up Interrupt Set + HWUPIS : Boolean := False; + -- unspecified + Reserved_7_24 : HAL.UInt18 := 16#0#; + -- Write-only. DMA Channel 1 Interrupt Set + DMA_1 : Boolean := False; + -- Write-only. DMA Channel 2 Interrupt Set + DMA_2 : Boolean := False; + -- Write-only. DMA Channel 3 Interrupt Set + DMA_3 : Boolean := False; + -- Write-only. DMA Channel 4 Interrupt Set + DMA_4 : Boolean := False; + -- Write-only. DMA Channel 5 Interrupt Set + DMA_5 : Boolean := False; + -- Write-only. DMA Channel 6 Interrupt Set + DMA_6 : Boolean := False; + -- Write-only. DMA Channel 7 Interrupt Set + DMA_7 : Boolean := False; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for USBHS_USBHS_HSTIFR_Register use record + DCONNIS at 0 range 0 .. 0; + DDISCIS at 0 range 1 .. 1; + RSTIS at 0 range 2 .. 2; + RSMEDIS at 0 range 3 .. 3; + RXRSMIS at 0 range 4 .. 4; + HSOFIS at 0 range 5 .. 5; + HWUPIS at 0 range 6 .. 6; + Reserved_7_24 at 0 range 7 .. 24; + DMA_1 at 0 range 25 .. 25; + DMA_2 at 0 range 26 .. 26; + DMA_3 at 0 range 27 .. 27; + DMA_4 at 0 range 28 .. 28; + DMA_5 at 0 range 29 .. 29; + DMA_6 at 0 range 30 .. 30; + DMA_7 at 0 range 31 .. 31; + end record; + + -- Host Global Interrupt Mask Register + type USBHS_USBHS_HSTIMR_Register is record + -- Read-only. Device Connection Interrupt Enable + DCONNIE : Boolean; + -- Read-only. Device Disconnection Interrupt Enable + DDISCIE : Boolean; + -- Read-only. USB Reset Sent Interrupt Enable + RSTIE : Boolean; + -- Read-only. Downstream Resume Sent Interrupt Enable + RSMEDIE : Boolean; + -- Read-only. Upstream Resume Received Interrupt Enable + RXRSMIE : Boolean; + -- Read-only. Host Start of Frame Interrupt Enable + HSOFIE : Boolean; + -- Read-only. Host Wake-Up Interrupt Enable + HWUPIE : Boolean; + -- unspecified + Reserved_7_7 : HAL.Bit; + -- Read-only. Pipe 0 Interrupt Enable + PEP_0 : Boolean; + -- Read-only. Pipe 1 Interrupt Enable + PEP_1 : Boolean; + -- Read-only. Pipe 2 Interrupt Enable + PEP_2 : Boolean; + -- Read-only. Pipe 3 Interrupt Enable + PEP_3 : Boolean; + -- Read-only. Pipe 4 Interrupt Enable + PEP_4 : Boolean; + -- Read-only. Pipe 5 Interrupt Enable + PEP_5 : Boolean; + -- Read-only. Pipe 6 Interrupt Enable + PEP_6 : Boolean; + -- Read-only. Pipe 7 Interrupt Enable + PEP_7 : Boolean; + -- Read-only. Pipe 8 Interrupt Enable + PEP_8 : Boolean; + -- Read-only. Pipe 9 Interrupt Enable + PEP_9 : Boolean; + -- unspecified + Reserved_18_24 : HAL.UInt7; + -- Read-only. DMA Channel 1 Interrupt Enable + DMA_1 : Boolean; + -- Read-only. DMA Channel 2 Interrupt Enable + DMA_2 : Boolean; + -- Read-only. DMA Channel 3 Interrupt Enable + DMA_3 : Boolean; + -- Read-only. DMA Channel 4 Interrupt Enable + DMA_4 : Boolean; + -- Read-only. DMA Channel 5 Interrupt Enable + DMA_5 : Boolean; + -- Read-only. DMA Channel 6 Interrupt Enable + DMA_6 : Boolean; + -- Read-only. DMA Channel 7 Interrupt Enable + DMA_7 : Boolean; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for USBHS_USBHS_HSTIMR_Register use record + DCONNIE at 0 range 0 .. 0; + DDISCIE at 0 range 1 .. 1; + RSTIE at 0 range 2 .. 2; + RSMEDIE at 0 range 3 .. 3; + RXRSMIE at 0 range 4 .. 4; + HSOFIE at 0 range 5 .. 5; + HWUPIE at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + PEP_0 at 0 range 8 .. 8; + PEP_1 at 0 range 9 .. 9; + PEP_2 at 0 range 10 .. 10; + PEP_3 at 0 range 11 .. 11; + PEP_4 at 0 range 12 .. 12; + PEP_5 at 0 range 13 .. 13; + PEP_6 at 0 range 14 .. 14; + PEP_7 at 0 range 15 .. 15; + PEP_8 at 0 range 16 .. 16; + PEP_9 at 0 range 17 .. 17; + Reserved_18_24 at 0 range 18 .. 24; + DMA_1 at 0 range 25 .. 25; + DMA_2 at 0 range 26 .. 26; + DMA_3 at 0 range 27 .. 27; + DMA_4 at 0 range 28 .. 28; + DMA_5 at 0 range 29 .. 29; + DMA_6 at 0 range 30 .. 30; + DMA_7 at 0 range 31 .. 31; + end record; + + -- Host Global Interrupt Disable Register + type USBHS_USBHS_HSTIDR_Register is record + -- Write-only. Device Connection Interrupt Disable + DCONNIEC : Boolean := False; + -- Write-only. Device Disconnection Interrupt Disable + DDISCIEC : Boolean := False; + -- Write-only. USB Reset Sent Interrupt Disable + RSTIEC : Boolean := False; + -- Write-only. Downstream Resume Sent Interrupt Disable + RSMEDIEC : Boolean := False; + -- Write-only. Upstream Resume Received Interrupt Disable + RXRSMIEC : Boolean := False; + -- Write-only. Host Start of Frame Interrupt Disable + HSOFIEC : Boolean := False; + -- Write-only. Host Wake-Up Interrupt Disable + HWUPIEC : Boolean := False; + -- unspecified + Reserved_7_7 : HAL.Bit := 16#0#; + -- Write-only. Pipe 0 Interrupt Disable + PEP_0 : Boolean := False; + -- Write-only. Pipe 1 Interrupt Disable + PEP_1 : Boolean := False; + -- Write-only. Pipe 2 Interrupt Disable + PEP_2 : Boolean := False; + -- Write-only. Pipe 3 Interrupt Disable + PEP_3 : Boolean := False; + -- Write-only. Pipe 4 Interrupt Disable + PEP_4 : Boolean := False; + -- Write-only. Pipe 5 Interrupt Disable + PEP_5 : Boolean := False; + -- Write-only. Pipe 6 Interrupt Disable + PEP_6 : Boolean := False; + -- Write-only. Pipe 7 Interrupt Disable + PEP_7 : Boolean := False; + -- Write-only. Pipe 8 Interrupt Disable + PEP_8 : Boolean := False; + -- Write-only. Pipe 9 Interrupt Disable + PEP_9 : Boolean := False; + -- unspecified + Reserved_18_24 : HAL.UInt7 := 16#0#; + -- Write-only. DMA Channel 1 Interrupt Disable + DMA_1 : Boolean := False; + -- Write-only. DMA Channel 2 Interrupt Disable + DMA_2 : Boolean := False; + -- Write-only. DMA Channel 3 Interrupt Disable + DMA_3 : Boolean := False; + -- Write-only. DMA Channel 4 Interrupt Disable + DMA_4 : Boolean := False; + -- Write-only. DMA Channel 5 Interrupt Disable + DMA_5 : Boolean := False; + -- Write-only. DMA Channel 6 Interrupt Disable + DMA_6 : Boolean := False; + -- Write-only. DMA Channel 7 Interrupt Disable + DMA_7 : Boolean := False; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for USBHS_USBHS_HSTIDR_Register use record + DCONNIEC at 0 range 0 .. 0; + DDISCIEC at 0 range 1 .. 1; + RSTIEC at 0 range 2 .. 2; + RSMEDIEC at 0 range 3 .. 3; + RXRSMIEC at 0 range 4 .. 4; + HSOFIEC at 0 range 5 .. 5; + HWUPIEC at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + PEP_0 at 0 range 8 .. 8; + PEP_1 at 0 range 9 .. 9; + PEP_2 at 0 range 10 .. 10; + PEP_3 at 0 range 11 .. 11; + PEP_4 at 0 range 12 .. 12; + PEP_5 at 0 range 13 .. 13; + PEP_6 at 0 range 14 .. 14; + PEP_7 at 0 range 15 .. 15; + PEP_8 at 0 range 16 .. 16; + PEP_9 at 0 range 17 .. 17; + Reserved_18_24 at 0 range 18 .. 24; + DMA_1 at 0 range 25 .. 25; + DMA_2 at 0 range 26 .. 26; + DMA_3 at 0 range 27 .. 27; + DMA_4 at 0 range 28 .. 28; + DMA_5 at 0 range 29 .. 29; + DMA_6 at 0 range 30 .. 30; + DMA_7 at 0 range 31 .. 31; + end record; + + -- Host Global Interrupt Enable Register + type USBHS_USBHS_HSTIER_Register is record + -- Write-only. Device Connection Interrupt Enable + DCONNIES : Boolean := False; + -- Write-only. Device Disconnection Interrupt Enable + DDISCIES : Boolean := False; + -- Write-only. USB Reset Sent Interrupt Enable + RSTIES : Boolean := False; + -- Write-only. Downstream Resume Sent Interrupt Enable + RSMEDIES : Boolean := False; + -- Write-only. Upstream Resume Received Interrupt Enable + RXRSMIES : Boolean := False; + -- Write-only. Host Start of Frame Interrupt Enable + HSOFIES : Boolean := False; + -- Write-only. Host Wake-Up Interrupt Enable + HWUPIES : Boolean := False; + -- unspecified + Reserved_7_7 : HAL.Bit := 16#0#; + -- Write-only. Pipe 0 Interrupt Enable + PEP_0 : Boolean := False; + -- Write-only. Pipe 1 Interrupt Enable + PEP_1 : Boolean := False; + -- Write-only. Pipe 2 Interrupt Enable + PEP_2 : Boolean := False; + -- Write-only. Pipe 3 Interrupt Enable + PEP_3 : Boolean := False; + -- Write-only. Pipe 4 Interrupt Enable + PEP_4 : Boolean := False; + -- Write-only. Pipe 5 Interrupt Enable + PEP_5 : Boolean := False; + -- Write-only. Pipe 6 Interrupt Enable + PEP_6 : Boolean := False; + -- Write-only. Pipe 7 Interrupt Enable + PEP_7 : Boolean := False; + -- Write-only. Pipe 8 Interrupt Enable + PEP_8 : Boolean := False; + -- Write-only. Pipe 9 Interrupt Enable + PEP_9 : Boolean := False; + -- unspecified + Reserved_18_24 : HAL.UInt7 := 16#0#; + -- Write-only. DMA Channel 1 Interrupt Enable + DMA_1 : Boolean := False; + -- Write-only. DMA Channel 2 Interrupt Enable + DMA_2 : Boolean := False; + -- Write-only. DMA Channel 3 Interrupt Enable + DMA_3 : Boolean := False; + -- Write-only. DMA Channel 4 Interrupt Enable + DMA_4 : Boolean := False; + -- Write-only. DMA Channel 5 Interrupt Enable + DMA_5 : Boolean := False; + -- Write-only. DMA Channel 6 Interrupt Enable + DMA_6 : Boolean := False; + -- Write-only. DMA Channel 7 Interrupt Enable + DMA_7 : Boolean := False; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for USBHS_USBHS_HSTIER_Register use record + DCONNIES at 0 range 0 .. 0; + DDISCIES at 0 range 1 .. 1; + RSTIES at 0 range 2 .. 2; + RSMEDIES at 0 range 3 .. 3; + RXRSMIES at 0 range 4 .. 4; + HSOFIES at 0 range 5 .. 5; + HWUPIES at 0 range 6 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + PEP_0 at 0 range 8 .. 8; + PEP_1 at 0 range 9 .. 9; + PEP_2 at 0 range 10 .. 10; + PEP_3 at 0 range 11 .. 11; + PEP_4 at 0 range 12 .. 12; + PEP_5 at 0 range 13 .. 13; + PEP_6 at 0 range 14 .. 14; + PEP_7 at 0 range 15 .. 15; + PEP_8 at 0 range 16 .. 16; + PEP_9 at 0 range 17 .. 17; + Reserved_18_24 at 0 range 18 .. 24; + DMA_1 at 0 range 25 .. 25; + DMA_2 at 0 range 26 .. 26; + DMA_3 at 0 range 27 .. 27; + DMA_4 at 0 range 28 .. 28; + DMA_5 at 0 range 29 .. 29; + DMA_6 at 0 range 30 .. 30; + DMA_7 at 0 range 31 .. 31; + end record; + + -- USBHS_USBHS_HSTPIP_PEN array + type USBHS_USBHS_HSTPIP_PEN_Field_Array is array (0 .. 8) of Boolean + with Component_Size => 1, Size => 9; + + -- Type definition for USBHS_USBHS_HSTPIP_PEN + type USBHS_USBHS_HSTPIP_PEN_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- PEN as a value + Val : HAL.UInt9; + when True => + -- PEN as an array + Arr : USBHS_USBHS_HSTPIP_PEN_Field_Array; + end case; + end record + with Unchecked_Union, Size => 9; + + for USBHS_USBHS_HSTPIP_PEN_Field use record + Val at 0 range 0 .. 8; + Arr at 0 range 0 .. 8; + end record; + + -- USBHS_USBHS_HSTPIP_PRST array + type USBHS_USBHS_HSTPIP_PRST_Field_Array is array (0 .. 8) of Boolean + with Component_Size => 1, Size => 9; + + -- Type definition for USBHS_USBHS_HSTPIP_PRST + type USBHS_USBHS_HSTPIP_PRST_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- PRST as a value + Val : HAL.UInt9; + when True => + -- PRST as an array + Arr : USBHS_USBHS_HSTPIP_PRST_Field_Array; + end case; + end record + with Unchecked_Union, Size => 9; + + for USBHS_USBHS_HSTPIP_PRST_Field use record + Val at 0 range 0 .. 8; + Arr at 0 range 0 .. 8; + end record; + + -- Host Pipe Register + type USBHS_USBHS_HSTPIP_Register is record + -- Pipe 0 Enable + PEN : USBHS_USBHS_HSTPIP_PEN_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_9_15 : HAL.UInt7 := 16#0#; + -- Pipe 0 Reset + PRST : USBHS_USBHS_HSTPIP_PRST_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_25_31 : HAL.UInt7 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for USBHS_USBHS_HSTPIP_Register use record + PEN at 0 range 0 .. 8; + Reserved_9_15 at 0 range 9 .. 15; + PRST at 0 range 16 .. 24; + Reserved_25_31 at 0 range 25 .. 31; + end record; + + subtype USBHS_USBHS_HSTFNUM_MFNUM_Field is HAL.UInt3; + subtype USBHS_USBHS_HSTFNUM_FNUM_Field is HAL.UInt11; + subtype USBHS_USBHS_HSTFNUM_FLENHIGH_Field is HAL.UInt8; + + -- Host Frame Number Register + type USBHS_USBHS_HSTFNUM_Register is record + -- Micro Frame Number + MFNUM : USBHS_USBHS_HSTFNUM_MFNUM_Field := 16#0#; + -- Frame Number + FNUM : USBHS_USBHS_HSTFNUM_FNUM_Field := 16#0#; + -- unspecified + Reserved_14_15 : HAL.UInt2 := 16#0#; + -- Frame Length + FLENHIGH : USBHS_USBHS_HSTFNUM_FLENHIGH_Field := 16#0#; + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for USBHS_USBHS_HSTFNUM_Register use record + MFNUM at 0 range 0 .. 2; + FNUM at 0 range 3 .. 13; + Reserved_14_15 at 0 range 14 .. 15; + FLENHIGH at 0 range 16 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype USBHS_USBHS_HSTADDR1_HSTADDRP0_Field is HAL.UInt7; + subtype USBHS_USBHS_HSTADDR1_HSTADDRP1_Field is HAL.UInt7; + subtype USBHS_USBHS_HSTADDR1_HSTADDRP2_Field is HAL.UInt7; + subtype USBHS_USBHS_HSTADDR1_HSTADDRP3_Field is HAL.UInt7; + + -- Host Address 1 Register + type USBHS_USBHS_HSTADDR1_Register is record + -- USB Host Address + HSTADDRP0 : USBHS_USBHS_HSTADDR1_HSTADDRP0_Field := 16#0#; + -- unspecified + Reserved_7_7 : HAL.Bit := 16#0#; + -- USB Host Address + HSTADDRP1 : USBHS_USBHS_HSTADDR1_HSTADDRP1_Field := 16#0#; + -- unspecified + Reserved_15_15 : HAL.Bit := 16#0#; + -- USB Host Address + HSTADDRP2 : USBHS_USBHS_HSTADDR1_HSTADDRP2_Field := 16#0#; + -- unspecified + Reserved_23_23 : HAL.Bit := 16#0#; + -- USB Host Address + HSTADDRP3 : USBHS_USBHS_HSTADDR1_HSTADDRP3_Field := 16#0#; + -- unspecified + Reserved_31_31 : HAL.Bit := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for USBHS_USBHS_HSTADDR1_Register use record + HSTADDRP0 at 0 range 0 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + HSTADDRP1 at 0 range 8 .. 14; + Reserved_15_15 at 0 range 15 .. 15; + HSTADDRP2 at 0 range 16 .. 22; + Reserved_23_23 at 0 range 23 .. 23; + HSTADDRP3 at 0 range 24 .. 30; + Reserved_31_31 at 0 range 31 .. 31; + end record; + + subtype USBHS_USBHS_HSTADDR2_HSTADDRP4_Field is HAL.UInt7; + subtype USBHS_USBHS_HSTADDR2_HSTADDRP5_Field is HAL.UInt7; + subtype USBHS_USBHS_HSTADDR2_HSTADDRP6_Field is HAL.UInt7; + subtype USBHS_USBHS_HSTADDR2_HSTADDRP7_Field is HAL.UInt7; + + -- Host Address 2 Register + type USBHS_USBHS_HSTADDR2_Register is record + -- USB Host Address + HSTADDRP4 : USBHS_USBHS_HSTADDR2_HSTADDRP4_Field := 16#0#; + -- unspecified + Reserved_7_7 : HAL.Bit := 16#0#; + -- USB Host Address + HSTADDRP5 : USBHS_USBHS_HSTADDR2_HSTADDRP5_Field := 16#0#; + -- unspecified + Reserved_15_15 : HAL.Bit := 16#0#; + -- USB Host Address + HSTADDRP6 : USBHS_USBHS_HSTADDR2_HSTADDRP6_Field := 16#0#; + -- unspecified + Reserved_23_23 : HAL.Bit := 16#0#; + -- USB Host Address + HSTADDRP7 : USBHS_USBHS_HSTADDR2_HSTADDRP7_Field := 16#0#; + -- unspecified + Reserved_31_31 : HAL.Bit := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for USBHS_USBHS_HSTADDR2_Register use record + HSTADDRP4 at 0 range 0 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + HSTADDRP5 at 0 range 8 .. 14; + Reserved_15_15 at 0 range 15 .. 15; + HSTADDRP6 at 0 range 16 .. 22; + Reserved_23_23 at 0 range 23 .. 23; + HSTADDRP7 at 0 range 24 .. 30; + Reserved_31_31 at 0 range 31 .. 31; + end record; + + subtype USBHS_USBHS_HSTADDR3_HSTADDRP8_Field is HAL.UInt7; + subtype USBHS_USBHS_HSTADDR3_HSTADDRP9_Field is HAL.UInt7; + + -- Host Address 3 Register + type USBHS_USBHS_HSTADDR3_Register is record + -- USB Host Address + HSTADDRP8 : USBHS_USBHS_HSTADDR3_HSTADDRP8_Field := 16#0#; + -- unspecified + Reserved_7_7 : HAL.Bit := 16#0#; + -- USB Host Address + HSTADDRP9 : USBHS_USBHS_HSTADDR3_HSTADDRP9_Field := 16#0#; + -- unspecified + Reserved_15_31 : HAL.UInt17 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for USBHS_USBHS_HSTADDR3_Register use record + HSTADDRP8 at 0 range 0 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + HSTADDRP9 at 0 range 8 .. 14; + Reserved_15_31 at 0 range 15 .. 31; + end record; + + -- Pipe Banks + type USBHS_HSTPIPCFG_PBK_Field is + ( + -- Single-bank pipe + Val_1_Bank, + -- Double-bank pipe + Val_2_Bank, + -- Triple-bank pipe + Val_3_Bank) + with Size => 2; + for USBHS_HSTPIPCFG_PBK_Field use + (Val_1_Bank => 0, + Val_2_Bank => 1, + Val_3_Bank => 2); + + -- Pipe Size + type USBHS_HSTPIPCFG_PSIZE_Field is + ( + -- 8 bytes + Val_8_Byte, + -- 16 bytes + Val_16_Byte, + -- 32 bytes + Val_32_Byte, + -- 64 bytes + Val_64_Byte, + -- 128 bytes + Val_128_Byte, + -- 256 bytes + Val_256_Byte, + -- 512 bytes + Val_512_Byte, + -- 1024 bytes + Val_1024_Byte) + with Size => 3; + for USBHS_HSTPIPCFG_PSIZE_Field use + (Val_8_Byte => 0, + Val_16_Byte => 1, + Val_32_Byte => 2, + Val_64_Byte => 3, + Val_128_Byte => 4, + Val_256_Byte => 5, + Val_512_Byte => 6, + Val_1024_Byte => 7); + + -- Pipe Token + type USBHS_HSTPIPCFG_PTOKEN_Field is + ( + -- SETUP + Setup, + -- IN + In_k, + -- OUT + Out_k) + with Size => 2; + for USBHS_HSTPIPCFG_PTOKEN_Field use + (Setup => 0, + In_k => 1, + Out_k => 2); + + -- Pipe Type + type USBHS_HSTPIPCFG_PTYPE_Field is + ( + -- Control + Ctrl, + -- Isochronous + Iso, + -- Bulk + Blk, + -- Interrupt + Intrpt) + with Size => 2; + for USBHS_HSTPIPCFG_PTYPE_Field use + (Ctrl => 0, + Iso => 1, + Blk => 2, + Intrpt => 3); + + subtype USBHS_USBHS_HSTPIPCFG_PEPNUM_Field is HAL.UInt4; + subtype USBHS_USBHS_HSTPIPCFG_INTFRQ_Field is HAL.UInt8; + + -- Host Pipe Configuration Register (n = 0) 0 + type USBHS_USBHS_HSTPIPCFG_Register is record + -- unspecified + Reserved_0_0 : HAL.Bit := 16#0#; + -- Pipe Memory Allocate + ALLOC : Boolean := False; + -- Pipe Banks + PBK : USBHS_HSTPIPCFG_PBK_Field := SAM_SVD.USBHS.Val_1_Bank; + -- Pipe Size + PSIZE : USBHS_HSTPIPCFG_PSIZE_Field := + SAM_SVD.USBHS.Val_8_Byte; + -- unspecified + Reserved_7_7 : HAL.Bit := 16#0#; + -- Pipe Token + PTOKEN : USBHS_HSTPIPCFG_PTOKEN_Field := SAM_SVD.USBHS.Setup; + -- Automatic Switch + AUTOSW : Boolean := False; + -- unspecified + Reserved_11_11 : HAL.Bit := 16#0#; + -- Pipe Type + PTYPE : USBHS_HSTPIPCFG_PTYPE_Field := SAM_SVD.USBHS.Ctrl; + -- unspecified + Reserved_14_15 : HAL.UInt2 := 16#0#; + -- Pipe Endpoint Number + PEPNUM : USBHS_USBHS_HSTPIPCFG_PEPNUM_Field := 16#0#; + -- unspecified + Reserved_20_23 : HAL.UInt4 := 16#0#; + -- Pipe Interrupt Request Frequency + INTFRQ : USBHS_USBHS_HSTPIPCFG_INTFRQ_Field := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for USBHS_USBHS_HSTPIPCFG_Register use record + Reserved_0_0 at 0 range 0 .. 0; + ALLOC at 0 range 1 .. 1; + PBK at 0 range 2 .. 3; + PSIZE at 0 range 4 .. 6; + Reserved_7_7 at 0 range 7 .. 7; + PTOKEN at 0 range 8 .. 9; + AUTOSW at 0 range 10 .. 10; + Reserved_11_11 at 0 range 11 .. 11; + PTYPE at 0 range 12 .. 13; + Reserved_14_15 at 0 range 14 .. 15; + PEPNUM at 0 range 16 .. 19; + Reserved_20_23 at 0 range 20 .. 23; + INTFRQ at 0 range 24 .. 31; + end record; + + -- Host Pipe Configuration Register (n = 0) 0 + type USBHS_USBHS_HSTPIPCFG_Registers is array (0 .. 9) + of USBHS_USBHS_HSTPIPCFG_Register + with Volatile; + + -- Data Toggle Sequence + type USBHS_HSTPIPISR_DTSEQ_Field is + ( + -- Data0 toggle sequence + Data0, + -- Data1 toggle sequence + Data1) + with Size => 2; + for USBHS_HSTPIPISR_DTSEQ_Field use + (Data0 => 0, + Data1 => 1); + + -- Number of Busy Banks + type USBHS_HSTPIPISR_NBUSYBK_Field is + ( + -- 0 busy bank (all banks free) + Val_0_Busy, + -- 1 busy bank + Val_1_Busy, + -- 2 busy banks + Val_2_Busy, + -- 3 busy banks + Val_3_Busy) + with Size => 2; + for USBHS_HSTPIPISR_NBUSYBK_Field use + (Val_0_Busy => 0, + Val_1_Busy => 1, + Val_2_Busy => 2, + Val_3_Busy => 3); + + -- Current Bank + type USBHS_HSTPIPISR_CURRBK_Field is + ( + -- Current bank is bank0 + Bank0, + -- Current bank is bank1 + Bank1, + -- Current bank is bank2 + Bank2) + with Size => 2; + for USBHS_HSTPIPISR_CURRBK_Field use + (Bank0 => 0, + Bank1 => 1, + Bank2 => 2); + + subtype USBHS_USBHS_HSTPIPISR_PBYCT_Field is HAL.UInt11; + + -- Host Pipe Status Register (n = 0) 0 + type USBHS_USBHS_HSTPIPISR_Register is record + -- Read-only. Received IN Data Interrupt + RXINI : Boolean; + -- Read-only. Transmitted OUT Data Interrupt + TXOUTI : Boolean; + -- Read-only. Transmitted SETUP Interrupt + TXSTPI : Boolean; + -- Read-only. Pipe Error Interrupt + PERRI : Boolean; + -- Read-only. NAKed Interrupt + NAKEDI : Boolean; + -- Read-only. Overflow Interrupt + OVERFI : Boolean; + -- Read-only. Received STALLed Interrupt + RXSTALLDI : Boolean; + -- Read-only. Short Packet Interrupt + SHORTPACKETI : Boolean; + -- Read-only. Data Toggle Sequence + DTSEQ : USBHS_HSTPIPISR_DTSEQ_Field; + -- unspecified + Reserved_10_11 : HAL.UInt2; + -- Read-only. Number of Busy Banks + NBUSYBK : USBHS_HSTPIPISR_NBUSYBK_Field; + -- Read-only. Current Bank + CURRBK : USBHS_HSTPIPISR_CURRBK_Field; + -- Read-only. Read/Write Allowed + RWALL : Boolean; + -- unspecified + Reserved_17_17 : HAL.Bit; + -- Read-only. Configuration OK Status + CFGOK : Boolean; + -- unspecified + Reserved_19_19 : HAL.Bit; + -- Read-only. Pipe Byte Count + PBYCT : USBHS_USBHS_HSTPIPISR_PBYCT_Field; + -- unspecified + Reserved_31_31 : HAL.Bit; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for USBHS_USBHS_HSTPIPISR_Register use record + RXINI at 0 range 0 .. 0; + TXOUTI at 0 range 1 .. 1; + TXSTPI at 0 range 2 .. 2; + PERRI at 0 range 3 .. 3; + NAKEDI at 0 range 4 .. 4; + OVERFI at 0 range 5 .. 5; + RXSTALLDI at 0 range 6 .. 6; + SHORTPACKETI at 0 range 7 .. 7; + DTSEQ at 0 range 8 .. 9; + Reserved_10_11 at 0 range 10 .. 11; + NBUSYBK at 0 range 12 .. 13; + CURRBK at 0 range 14 .. 15; + RWALL at 0 range 16 .. 16; + Reserved_17_17 at 0 range 17 .. 17; + CFGOK at 0 range 18 .. 18; + Reserved_19_19 at 0 range 19 .. 19; + PBYCT at 0 range 20 .. 30; + Reserved_31_31 at 0 range 31 .. 31; + end record; + + -- Host Pipe Status Register (n = 0) 0 + type USBHS_USBHS_HSTPIPISR_Registers is array (0 .. 9) + of USBHS_USBHS_HSTPIPISR_Register + with Volatile; + + -- Host Pipe Clear Register (n = 0) 0 + type USBHS_USBHS_HSTPIPICR_Register is record + -- Write-only. Received IN Data Interrupt Clear + RXINIC : Boolean := False; + -- Write-only. Transmitted OUT Data Interrupt Clear + TXOUTIC : Boolean := False; + -- Write-only. Transmitted SETUP Interrupt Clear + TXSTPIC : Boolean := False; + -- unspecified + Reserved_3_3 : HAL.Bit := 16#0#; + -- Write-only. NAKed Interrupt Clear + NAKEDIC : Boolean := False; + -- Write-only. Overflow Interrupt Clear + OVERFIC : Boolean := False; + -- Write-only. Received STALLed Interrupt Clear + RXSTALLDIC : Boolean := False; + -- Write-only. Short Packet Interrupt Clear + SHORTPACKETIC : Boolean := False; + -- unspecified + Reserved_8_31 : HAL.UInt24 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for USBHS_USBHS_HSTPIPICR_Register use record + RXINIC at 0 range 0 .. 0; + TXOUTIC at 0 range 1 .. 1; + TXSTPIC at 0 range 2 .. 2; + Reserved_3_3 at 0 range 3 .. 3; + NAKEDIC at 0 range 4 .. 4; + OVERFIC at 0 range 5 .. 5; + RXSTALLDIC at 0 range 6 .. 6; + SHORTPACKETIC at 0 range 7 .. 7; + Reserved_8_31 at 0 range 8 .. 31; + end record; + + -- Host Pipe Clear Register (n = 0) 0 + type USBHS_USBHS_HSTPIPICR_Registers is array (0 .. 9) + of USBHS_USBHS_HSTPIPICR_Register + with Volatile; + + -- Host Pipe Set Register (n = 0) 0 + type USBHS_USBHS_HSTPIPIFR_Register is record + -- Write-only. Received IN Data Interrupt Set + RXINIS : Boolean := False; + -- Write-only. Transmitted OUT Data Interrupt Set + TXOUTIS : Boolean := False; + -- Write-only. Transmitted SETUP Interrupt Set + TXSTPIS : Boolean := False; + -- Write-only. Pipe Error Interrupt Set + PERRIS : Boolean := False; + -- Write-only. NAKed Interrupt Set + NAKEDIS : Boolean := False; + -- Write-only. Overflow Interrupt Set + OVERFIS : Boolean := False; + -- Write-only. Received STALLed Interrupt Set + RXSTALLDIS : Boolean := False; + -- Write-only. Short Packet Interrupt Set + SHORTPACKETIS : Boolean := False; + -- unspecified + Reserved_8_11 : HAL.UInt4 := 16#0#; + -- Write-only. Number of Busy Banks Set + NBUSYBKS : Boolean := False; + -- unspecified + Reserved_13_31 : HAL.UInt19 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for USBHS_USBHS_HSTPIPIFR_Register use record + RXINIS at 0 range 0 .. 0; + TXOUTIS at 0 range 1 .. 1; + TXSTPIS at 0 range 2 .. 2; + PERRIS at 0 range 3 .. 3; + NAKEDIS at 0 range 4 .. 4; + OVERFIS at 0 range 5 .. 5; + RXSTALLDIS at 0 range 6 .. 6; + SHORTPACKETIS at 0 range 7 .. 7; + Reserved_8_11 at 0 range 8 .. 11; + NBUSYBKS at 0 range 12 .. 12; + Reserved_13_31 at 0 range 13 .. 31; + end record; + + -- Host Pipe Set Register (n = 0) 0 + type USBHS_USBHS_HSTPIPIFR_Registers is array (0 .. 9) + of USBHS_USBHS_HSTPIPIFR_Register + with Volatile; + + -- Host Pipe Mask Register (n = 0) 0 + type USBHS_USBHS_HSTPIPIMR_Register is record + -- Read-only. Received IN Data Interrupt Enable + RXINE : Boolean; + -- Read-only. Transmitted OUT Data Interrupt Enable + TXOUTE : Boolean; + -- Read-only. Transmitted SETUP Interrupt Enable + TXSTPE : Boolean; + -- Read-only. Pipe Error Interrupt Enable + PERRE : Boolean; + -- Read-only. NAKed Interrupt Enable + NAKEDE : Boolean; + -- Read-only. Overflow Interrupt Enable + OVERFIE : Boolean; + -- Read-only. Received STALLed Interrupt Enable + RXSTALLDE : Boolean; + -- Read-only. Short Packet Interrupt Enable + SHORTPACKETIE : Boolean; + -- unspecified + Reserved_8_11 : HAL.UInt4; + -- Read-only. Number of Busy Banks Interrupt Enable + NBUSYBKE : Boolean; + -- unspecified + Reserved_13_13 : HAL.Bit; + -- Read-only. FIFO Control + FIFOCON : Boolean; + -- unspecified + Reserved_15_15 : HAL.Bit; + -- Read-only. Pipe Interrupts Disable HDMA Request Enable + PDISHDMA : Boolean; + -- Read-only. Pipe Freeze + PFREEZE : Boolean; + -- Read-only. Reset Data Toggle + RSTDT : Boolean; + -- unspecified + Reserved_19_31 : HAL.UInt13; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for USBHS_USBHS_HSTPIPIMR_Register use record + RXINE at 0 range 0 .. 0; + TXOUTE at 0 range 1 .. 1; + TXSTPE at 0 range 2 .. 2; + PERRE at 0 range 3 .. 3; + NAKEDE at 0 range 4 .. 4; + OVERFIE at 0 range 5 .. 5; + RXSTALLDE at 0 range 6 .. 6; + SHORTPACKETIE at 0 range 7 .. 7; + Reserved_8_11 at 0 range 8 .. 11; + NBUSYBKE at 0 range 12 .. 12; + Reserved_13_13 at 0 range 13 .. 13; + FIFOCON at 0 range 14 .. 14; + Reserved_15_15 at 0 range 15 .. 15; + PDISHDMA at 0 range 16 .. 16; + PFREEZE at 0 range 17 .. 17; + RSTDT at 0 range 18 .. 18; + Reserved_19_31 at 0 range 19 .. 31; + end record; + + -- Host Pipe Mask Register (n = 0) 0 + type USBHS_USBHS_HSTPIPIMR_Registers is array (0 .. 9) + of USBHS_USBHS_HSTPIPIMR_Register + with Volatile; + + -- Host Pipe Enable Register (n = 0) 0 + type USBHS_USBHS_HSTPIPIER_Register is record + -- Write-only. Received IN Data Interrupt Enable + RXINES : Boolean := False; + -- Write-only. Transmitted OUT Data Interrupt Enable + TXOUTES : Boolean := False; + -- Write-only. Transmitted SETUP Interrupt Enable + TXSTPES : Boolean := False; + -- Write-only. Pipe Error Interrupt Enable + PERRES : Boolean := False; + -- Write-only. NAKed Interrupt Enable + NAKEDES : Boolean := False; + -- Write-only. Overflow Interrupt Enable + OVERFIES : Boolean := False; + -- Write-only. Received STALLed Interrupt Enable + RXSTALLDES : Boolean := False; + -- Write-only. Short Packet Interrupt Enable + SHORTPACKETIES : Boolean := False; + -- unspecified + Reserved_8_11 : HAL.UInt4 := 16#0#; + -- Write-only. Number of Busy Banks Enable + NBUSYBKES : Boolean := False; + -- unspecified + Reserved_13_15 : HAL.UInt3 := 16#0#; + -- Write-only. Pipe Interrupts Disable HDMA Request Enable + PDISHDMAS : Boolean := False; + -- Write-only. Pipe Freeze Enable + PFREEZES : Boolean := False; + -- Write-only. Reset Data Toggle Enable + RSTDTS : Boolean := False; + -- unspecified + Reserved_19_31 : HAL.UInt13 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for USBHS_USBHS_HSTPIPIER_Register use record + RXINES at 0 range 0 .. 0; + TXOUTES at 0 range 1 .. 1; + TXSTPES at 0 range 2 .. 2; + PERRES at 0 range 3 .. 3; + NAKEDES at 0 range 4 .. 4; + OVERFIES at 0 range 5 .. 5; + RXSTALLDES at 0 range 6 .. 6; + SHORTPACKETIES at 0 range 7 .. 7; + Reserved_8_11 at 0 range 8 .. 11; + NBUSYBKES at 0 range 12 .. 12; + Reserved_13_15 at 0 range 13 .. 15; + PDISHDMAS at 0 range 16 .. 16; + PFREEZES at 0 range 17 .. 17; + RSTDTS at 0 range 18 .. 18; + Reserved_19_31 at 0 range 19 .. 31; + end record; + + -- Host Pipe Enable Register (n = 0) 0 + type USBHS_USBHS_HSTPIPIER_Registers is array (0 .. 9) + of USBHS_USBHS_HSTPIPIER_Register + with Volatile; + + -- Host Pipe Disable Register (n = 0) 0 + type USBHS_USBHS_HSTPIPIDR_Register is record + -- Write-only. Received IN Data Interrupt Disable + RXINEC : Boolean := False; + -- Write-only. Transmitted OUT Data Interrupt Disable + TXOUTEC : Boolean := False; + -- Write-only. Transmitted SETUP Interrupt Disable + TXSTPEC : Boolean := False; + -- Write-only. Pipe Error Interrupt Disable + PERREC : Boolean := False; + -- Write-only. NAKed Interrupt Disable + NAKEDEC : Boolean := False; + -- Write-only. Overflow Interrupt Disable + OVERFIEC : Boolean := False; + -- Write-only. Received STALLed Interrupt Disable + RXSTALLDEC : Boolean := False; + -- Write-only. Short Packet Interrupt Disable + SHORTPACKETIEC : Boolean := False; + -- unspecified + Reserved_8_11 : HAL.UInt4 := 16#0#; + -- Write-only. Number of Busy Banks Disable + NBUSYBKEC : Boolean := False; + -- unspecified + Reserved_13_13 : HAL.Bit := 16#0#; + -- Write-only. FIFO Control Disable + FIFOCONC : Boolean := False; + -- unspecified + Reserved_15_15 : HAL.Bit := 16#0#; + -- Write-only. Pipe Interrupts Disable HDMA Request Disable + PDISHDMAC : Boolean := False; + -- Write-only. Pipe Freeze Disable + PFREEZEC : Boolean := False; + -- unspecified + Reserved_18_31 : HAL.UInt14 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for USBHS_USBHS_HSTPIPIDR_Register use record + RXINEC at 0 range 0 .. 0; + TXOUTEC at 0 range 1 .. 1; + TXSTPEC at 0 range 2 .. 2; + PERREC at 0 range 3 .. 3; + NAKEDEC at 0 range 4 .. 4; + OVERFIEC at 0 range 5 .. 5; + RXSTALLDEC at 0 range 6 .. 6; + SHORTPACKETIEC at 0 range 7 .. 7; + Reserved_8_11 at 0 range 8 .. 11; + NBUSYBKEC at 0 range 12 .. 12; + Reserved_13_13 at 0 range 13 .. 13; + FIFOCONC at 0 range 14 .. 14; + Reserved_15_15 at 0 range 15 .. 15; + PDISHDMAC at 0 range 16 .. 16; + PFREEZEC at 0 range 17 .. 17; + Reserved_18_31 at 0 range 18 .. 31; + end record; + + -- Host Pipe Disable Register (n = 0) 0 + type USBHS_USBHS_HSTPIPIDR_Registers is array (0 .. 9) + of USBHS_USBHS_HSTPIPIDR_Register + with Volatile; + + subtype USBHS_USBHS_HSTPIPINRQ_INRQ_Field is HAL.UInt8; + + -- Host Pipe IN Request Register (n = 0) 0 + type USBHS_USBHS_HSTPIPINRQ_Register is record + -- IN Request Number before Freeze + INRQ : USBHS_USBHS_HSTPIPINRQ_INRQ_Field := 16#0#; + -- IN Request Mode + INMODE : Boolean := False; + -- unspecified + Reserved_9_31 : HAL.UInt23 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for USBHS_USBHS_HSTPIPINRQ_Register use record + INRQ at 0 range 0 .. 7; + INMODE at 0 range 8 .. 8; + Reserved_9_31 at 0 range 9 .. 31; + end record; + + -- Host Pipe IN Request Register (n = 0) 0 + type USBHS_USBHS_HSTPIPINRQ_Registers is array (0 .. 9) + of USBHS_USBHS_HSTPIPINRQ_Register + with Volatile; + + subtype USBHS_USBHS_HSTPIPERR_COUNTER_Field is HAL.UInt2; + + -- Host Pipe Error Register (n = 0) 0 + type USBHS_USBHS_HSTPIPERR_Register is record + -- Data Toggle Error + DATATGL : Boolean := False; + -- Data PID Error + DATAPID : Boolean := False; + -- Data PID Error + PID : Boolean := False; + -- Time-Out Error + TIMEOUT : Boolean := False; + -- CRC16 Error + CRC16 : Boolean := False; + -- Error Counter + COUNTER : USBHS_USBHS_HSTPIPERR_COUNTER_Field := 16#0#; + -- unspecified + Reserved_7_31 : HAL.UInt25 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for USBHS_USBHS_HSTPIPERR_Register use record + DATATGL at 0 range 0 .. 0; + DATAPID at 0 range 1 .. 1; + PID at 0 range 2 .. 2; + TIMEOUT at 0 range 3 .. 3; + CRC16 at 0 range 4 .. 4; + COUNTER at 0 range 5 .. 6; + Reserved_7_31 at 0 range 7 .. 31; + end record; + + -- Host Pipe Error Register (n = 0) 0 + type USBHS_USBHS_HSTPIPERR_Registers is array (0 .. 9) + of USBHS_USBHS_HSTPIPERR_Register + with Volatile; + + -------------------------------------------- + -- USBHS_USBHS_HSTDMA cluster's Registers -- + -------------------------------------------- + + subtype USBHS_USBHS_HSTDMACONTROL_USBHS_USBHS_HSTDMA_BUFF_LENGTH_Field is + HAL.UInt16; + + -- Host DMA Channel Control Register (n = 1) + type USBHS_USBHS_HSTDMACONTROL_USBHS_USBHS_HSTDMA_Register is record + -- Channel Enable Command + CHANN_ENB : Boolean := False; + -- Load Next Channel Transfer Descriptor Enable Command + LDNXT_DSC : Boolean := False; + -- End of Transfer Enable Control (OUT transfers only) + END_TR_EN : Boolean := False; + -- End of Buffer Enable Control + END_B_EN : Boolean := False; + -- End of Transfer Interrupt Enable + END_TR_IT : Boolean := False; + -- End of Buffer Interrupt Enable + END_BUFFIT : Boolean := False; + -- Descriptor Loaded Interrupt Enable + DESC_LD_IT : Boolean := False; + -- Burst Lock Enable + BURST_LCK : Boolean := False; + -- unspecified + Reserved_8_15 : HAL.UInt8 := 16#0#; + -- Buffer Byte Length (Write-only) + BUFF_LENGTH : USBHS_USBHS_HSTDMACONTROL_USBHS_USBHS_HSTDMA_BUFF_LENGTH_Field := + 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for USBHS_USBHS_HSTDMACONTROL_USBHS_USBHS_HSTDMA_Register use record + CHANN_ENB at 0 range 0 .. 0; + LDNXT_DSC at 0 range 1 .. 1; + END_TR_EN at 0 range 2 .. 2; + END_B_EN at 0 range 3 .. 3; + END_TR_IT at 0 range 4 .. 4; + END_BUFFIT at 0 range 5 .. 5; + DESC_LD_IT at 0 range 6 .. 6; + BURST_LCK at 0 range 7 .. 7; + Reserved_8_15 at 0 range 8 .. 15; + BUFF_LENGTH at 0 range 16 .. 31; + end record; + + subtype USBHS_USBHS_HSTDMASTATUS_USBHS_USBHS_HSTDMA_BUFF_COUNT_Field is + HAL.UInt16; + + -- Host DMA Channel Status Register (n = 1) + type USBHS_USBHS_HSTDMASTATUS_USBHS_USBHS_HSTDMA_Register is record + -- Channel Enable Status + CHANN_ENB : Boolean := False; + -- Channel Active Status + CHANN_ACT : Boolean := False; + -- unspecified + Reserved_2_3 : HAL.UInt2 := 16#0#; + -- End of Channel Transfer Status + END_TR_ST : Boolean := False; + -- End of Channel Buffer Status + END_BF_ST : Boolean := False; + -- Descriptor Loaded Status + DESC_LDST : Boolean := False; + -- unspecified + Reserved_7_15 : HAL.UInt9 := 16#0#; + -- Buffer Byte Count + BUFF_COUNT : USBHS_USBHS_HSTDMASTATUS_USBHS_USBHS_HSTDMA_BUFF_COUNT_Field := + 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for USBHS_USBHS_HSTDMASTATUS_USBHS_USBHS_HSTDMA_Register use record + CHANN_ENB at 0 range 0 .. 0; + CHANN_ACT at 0 range 1 .. 1; + Reserved_2_3 at 0 range 2 .. 3; + END_TR_ST at 0 range 4 .. 4; + END_BF_ST at 0 range 5 .. 5; + DESC_LDST at 0 range 6 .. 6; + Reserved_7_15 at 0 range 7 .. 15; + BUFF_COUNT at 0 range 16 .. 31; + end record; + + -- Host DMA Channel Next Descriptor Address Register (n = 1) + type USBHS_USBHS_HSTDMA_Cluster is record + -- Host DMA Channel Next Descriptor Address Register (n = 1) + USBHS_HSTDMANXTDSC : aliased HAL.UInt32; + -- Host DMA Channel Address Register (n = 1) + USBHS_HSTDMAADDRESS : aliased HAL.UInt32; + -- Host DMA Channel Control Register (n = 1) + USBHS_HSTDMACONTROL : aliased USBHS_USBHS_HSTDMACONTROL_USBHS_USBHS_HSTDMA_Register; + -- Host DMA Channel Status Register (n = 1) + USBHS_HSTDMASTATUS : aliased USBHS_USBHS_HSTDMASTATUS_USBHS_USBHS_HSTDMA_Register; + end record + with Volatile, Size => 128; + + for USBHS_USBHS_HSTDMA_Cluster use record + USBHS_HSTDMANXTDSC at 16#0# range 0 .. 31; + USBHS_HSTDMAADDRESS at 16#4# range 0 .. 31; + USBHS_HSTDMACONTROL at 16#8# range 0 .. 31; + USBHS_HSTDMASTATUS at 16#C# range 0 .. 31; + end record; + + -- Host DMA Channel Next Descriptor Address Register (n = 1) + type USBHS_USBHS_HSTDMA_Clusters is array (0 .. 6) + of USBHS_USBHS_HSTDMA_Cluster; + + -- USBHS Mode + type USBHS_CTRL_UIMOD_Field is + ( + -- The module is in USB Host mode. + Host, + -- The module is in USB Device mode. + Device) + with Size => 1; + for USBHS_CTRL_UIMOD_Field use + (Host => 0, + Device => 1); + + -- General Control Register + type USBHS_USBHS_CTRL_Register is record + -- unspecified + Reserved_0_3 : HAL.UInt4 := 16#0#; + -- Remote Device Connection Error Interrupt Enable + RDERRE : Boolean := False; + -- unspecified + Reserved_5_7 : HAL.UInt3 := 16#0#; + -- VBUS Hardware Control + VBUSHWC : Boolean := False; + -- unspecified + Reserved_9_13 : HAL.UInt5 := 16#0#; + -- Freeze USB Clock + FRZCLK : Boolean := False; + -- USBHS Enable + USBE : Boolean := False; + -- unspecified + Reserved_16_23 : HAL.UInt8 := 16#0#; + -- UID Pin Enable + UID : Boolean := False; + -- USBHS Mode + UIMOD : USBHS_CTRL_UIMOD_Field := SAM_SVD.USBHS.Host; + -- unspecified + Reserved_26_31 : HAL.UInt6 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for USBHS_USBHS_CTRL_Register use record + Reserved_0_3 at 0 range 0 .. 3; + RDERRE at 0 range 4 .. 4; + Reserved_5_7 at 0 range 5 .. 7; + VBUSHWC at 0 range 8 .. 8; + Reserved_9_13 at 0 range 9 .. 13; + FRZCLK at 0 range 14 .. 14; + USBE at 0 range 15 .. 15; + Reserved_16_23 at 0 range 16 .. 23; + UID at 0 range 24 .. 24; + UIMOD at 0 range 25 .. 25; + Reserved_26_31 at 0 range 26 .. 31; + end record; + + -- Speed Status (Device mode only) + type USBHS_SR_SPEED_Field is + ( + -- Full-Speed mode + Full_Speed, + -- High-Speed mode + High_Speed, + -- Low-Speed mode + Low_Speed) + with Size => 2; + for USBHS_SR_SPEED_Field use + (Full_Speed => 0, + High_Speed => 1, + Low_Speed => 2); + + -- General Status Register + type USBHS_USBHS_SR_Register is record + -- unspecified + Reserved_0_3 : HAL.UInt4; + -- Read-only. Remote Device Connection Error Interrupt (Host mode only) + RDERRI : Boolean; + -- unspecified + Reserved_5_11 : HAL.UInt7; + -- Read-only. Speed Status (Device mode only) + SPEED : USBHS_SR_SPEED_Field; + -- Read-only. UTMI Clock Usable + CLKUSABLE : Boolean; + -- unspecified + Reserved_15_31 : HAL.UInt17; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for USBHS_USBHS_SR_Register use record + Reserved_0_3 at 0 range 0 .. 3; + RDERRI at 0 range 4 .. 4; + Reserved_5_11 at 0 range 5 .. 11; + SPEED at 0 range 12 .. 13; + CLKUSABLE at 0 range 14 .. 14; + Reserved_15_31 at 0 range 15 .. 31; + end record; + + -- General Status Clear Register + type USBHS_USBHS_SCR_Register is record + -- unspecified + Reserved_0_3 : HAL.UInt4 := 16#0#; + -- Write-only. Remote Device Connection Error Interrupt Clear + RDERRIC : Boolean := False; + -- unspecified + Reserved_5_31 : HAL.UInt27 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for USBHS_USBHS_SCR_Register use record + Reserved_0_3 at 0 range 0 .. 3; + RDERRIC at 0 range 4 .. 4; + Reserved_5_31 at 0 range 5 .. 31; + end record; + + -- General Status Set Register + type USBHS_USBHS_SFR_Register is record + -- unspecified + Reserved_0_3 : HAL.UInt4 := 16#0#; + -- Write-only. Remote Device Connection Error Interrupt Set + RDERRIS : Boolean := False; + -- unspecified + Reserved_5_8 : HAL.UInt4 := 16#0#; + -- Write-only. VBUS Request Set + VBUSRQS : Boolean := False; + -- unspecified + Reserved_10_31 : HAL.UInt22 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for USBHS_USBHS_SFR_Register use record + Reserved_0_3 at 0 range 0 .. 3; + RDERRIS at 0 range 4 .. 4; + Reserved_5_8 at 0 range 5 .. 8; + VBUSRQS at 0 range 9 .. 9; + Reserved_10_31 at 0 range 10 .. 31; + end record; + + subtype USBHS_USBHS_TSTA1_CounterA_Field is HAL.UInt15; + subtype USBHS_USBHS_TSTA1_CounterB_Field is HAL.UInt6; + subtype USBHS_USBHS_TSTA1_SOFCntMa1_Field is HAL.UInt7; + + -- General Test A1 Register + type USBHS_USBHS_TSTA1_Register is record + -- Counter A + CounterA : USBHS_USBHS_TSTA1_CounterA_Field := 16#0#; + -- Load CounterA + LoadCntA : Boolean := False; + -- Counter B + CounterB : USBHS_USBHS_TSTA1_CounterB_Field := 16#0#; + -- unspecified + Reserved_22_22 : HAL.Bit := 16#0#; + -- Load CounterB + LoadCntB : Boolean := False; + -- SOF Counter Max + SOFCntMa1 : USBHS_USBHS_TSTA1_SOFCntMa1_Field := 16#0#; + -- Load SOF Counter + LoadSOFCnt : Boolean := False; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for USBHS_USBHS_TSTA1_Register use record + CounterA at 0 range 0 .. 14; + LoadCntA at 0 range 15 .. 15; + CounterB at 0 range 16 .. 21; + Reserved_22_22 at 0 range 22 .. 22; + LoadCntB at 0 range 23 .. 23; + SOFCntMa1 at 0 range 24 .. 30; + LoadSOFCnt at 0 range 31 .. 31; + end record; + + -- General Test A2 Register + type USBHS_USBHS_TSTA2_Register is record + -- Full Detach Enable + FullDetachEn : Boolean := False; + -- HS Serial Mode + HSSerialMode : Boolean := False; + -- Loop-back Mode + LoopBackMode : Boolean := False; + -- Disable Gated Clock + DisableGatedClock : Boolean := False; + -- Force SuspendM to 1 + ForceSuspendMTo1 : Boolean := False; + -- Bypass DPLL + ByPassDpll : Boolean := False; + -- Host HS Disconnect Disable + HostHSDisconnectDisable : Boolean := False; + -- Force HS Reset to 50 ms + ForceHSRst_50ms : Boolean := False; + -- unspecified + Reserved_8_8 : HAL.Bit := 16#0#; + -- Remove Pull-up When TX + RemovePUWhenTX : Boolean := False; + -- unspecified + Reserved_10_31 : HAL.UInt22 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for USBHS_USBHS_TSTA2_Register use record + FullDetachEn at 0 range 0 .. 0; + HSSerialMode at 0 range 1 .. 1; + LoopBackMode at 0 range 2 .. 2; + DisableGatedClock at 0 range 3 .. 3; + ForceSuspendMTo1 at 0 range 4 .. 4; + ByPassDpll at 0 range 5 .. 5; + HostHSDisconnectDisable at 0 range 6 .. 6; + ForceHSRst_50ms at 0 range 7 .. 7; + Reserved_8_8 at 0 range 8 .. 8; + RemovePUWhenTX at 0 range 9 .. 9; + Reserved_10_31 at 0 range 10 .. 31; + end record; + + subtype USBHS_USBHS_VERSION_VERSION_Field is HAL.UInt12; + subtype USBHS_USBHS_VERSION_MFN_Field is HAL.UInt4; + + -- General Version Register + type USBHS_USBHS_VERSION_Register is record + -- Read-only. Version Number + VERSION : USBHS_USBHS_VERSION_VERSION_Field; + -- unspecified + Reserved_12_15 : HAL.UInt4; + -- Read-only. Metal Fix Number + MFN : USBHS_USBHS_VERSION_MFN_Field; + -- unspecified + Reserved_20_31 : HAL.UInt12; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for USBHS_USBHS_VERSION_Register use record + VERSION at 0 range 0 .. 11; + Reserved_12_15 at 0 range 12 .. 15; + MFN at 0 range 16 .. 19; + Reserved_20_31 at 0 range 20 .. 31; + end record; + + -- Dual Role Device State + type USBHS_FSM_DRDSTATE_Field is + ( + -- This is the start state for A-devices (when the ID pin is 0) + A_Idlestate, + -- In this state, the A-device waits for the voltage on VBus to rise + -- above the A-device VBus Valid threshold (4.4 V). + A_Wait_Vrise, + -- In this state, the A-device waits for the B-device to signal a + -- connection. + A_Wait_Bcon, + -- In this state, the A-device that operates in Host mode is + -- operational. + A_Host, + -- The A-device operating as a host is in the Suspend mode. + A_Suspend, + -- The A-device operates as a peripheral. + A_Peripheral, + -- In this state, the A-device waits for the voltage on VBus to drop + -- below the A-device Session Valid threshold (1.4 V). + A_Wait_Vfall, + -- In this state, the A-device waits for recovery of the over-current + -- condition that caused it to enter this state. + A_Vbus_Err, + -- In this state, the A-device waits for the data USB line to discharge + -- (100 us). + A_Wait_Discharge, + -- This is the start state for B-device (when the ID pin is 1). + B_Idle, + -- In this state, the B-device acts as the peripheral. + B_Peripheral, + -- In this state, the B-device is in Suspend mode and waits until 3 ms + -- before initiating the HNP protocol if requested. + B_Wait_Begin_Hnp, + -- In this state, the B-device waits for the data USB line to discharge + -- (100 us)) before becoming Host. + B_Wait_Discharge, + -- In this state, the B-device waits for the A-device to signal a + -- connect before becoming B-Host. + B_Wait_Acon, + -- In this state, the B-device acts as the Host. + B_Host, + -- In this state, the B-device attempts to start a session using the SRP + -- protocol. + B_Srp_Init) + with Size => 4; + for USBHS_FSM_DRDSTATE_Field use + (A_Idlestate => 0, + A_Wait_Vrise => 1, + A_Wait_Bcon => 2, + A_Host => 3, + A_Suspend => 4, + A_Peripheral => 5, + A_Wait_Vfall => 6, + A_Vbus_Err => 7, + A_Wait_Discharge => 8, + B_Idle => 9, + B_Peripheral => 10, + B_Wait_Begin_Hnp => 11, + B_Wait_Discharge => 12, + B_Wait_Acon => 13, + B_Host => 14, + B_Srp_Init => 15); + + -- General Finite State Machine Register + type USBHS_USBHS_FSM_Register is record + -- Read-only. Dual Role Device State + DRDSTATE : USBHS_FSM_DRDSTATE_Field; + -- unspecified + Reserved_4_31 : HAL.UInt28; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for USBHS_USBHS_FSM_Register use record + DRDSTATE at 0 range 0 .. 3; + Reserved_4_31 at 0 range 4 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- USB High-Speed Interface + type USBHS_Peripheral is record + -- Device General Control Register + USBHS_DEVCTRL : aliased USBHS_USBHS_DEVCTRL_Register; + -- Device Global Interrupt Status Register + USBHS_DEVISR : aliased USBHS_USBHS_DEVISR_Register; + -- Device Global Interrupt Clear Register + USBHS_DEVICR : aliased USBHS_USBHS_DEVICR_Register; + -- Device Global Interrupt Set Register + USBHS_DEVIFR : aliased USBHS_USBHS_DEVIFR_Register; + -- Device Global Interrupt Mask Register + USBHS_DEVIMR : aliased USBHS_USBHS_DEVIMR_Register; + -- Device Global Interrupt Disable Register + USBHS_DEVIDR : aliased USBHS_USBHS_DEVIDR_Register; + -- Device Global Interrupt Enable Register + USBHS_DEVIER : aliased USBHS_USBHS_DEVIER_Register; + -- Device Endpoint Register + USBHS_DEVEPT : aliased USBHS_USBHS_DEVEPT_Register; + -- Device Frame Number Register + USBHS_DEVFNUM : aliased USBHS_USBHS_DEVFNUM_Register; + -- Device Endpoint Configuration Register (n = 0) 0 + USBHS_DEVEPTCFG : aliased USBHS_USBHS_DEVEPTCFG_Registers; + -- Device Endpoint Status Register (n = 0) 0 + USBHS_DEVEPTISR : aliased USBHS_USBHS_DEVEPTISR_Registers; + -- Device Endpoint Clear Register (n = 0) 0 + USBHS_DEVEPTICR : aliased USBHS_USBHS_DEVEPTICR_Registers; + -- Device Endpoint Set Register (n = 0) 0 + USBHS_DEVEPTIFR : aliased USBHS_USBHS_DEVEPTIFR_Registers; + -- Device Endpoint Mask Register (n = 0) 0 + USBHS_DEVEPTIMR : aliased USBHS_USBHS_DEVEPTIMR_Registers; + -- Device Endpoint Enable Register (n = 0) 0 + USBHS_DEVEPTIER : aliased USBHS_USBHS_DEVEPTIER_Registers; + -- Device Endpoint Disable Register (n = 0) 0 + USBHS_DEVEPTIDR : aliased USBHS_USBHS_DEVEPTIDR_Registers; + -- Device DMA Channel Next Descriptor Address Register (n = 1) + USBHS_USBHS_DEVDMA : aliased USBHS_USBHS_DEVDMA_Clusters; + -- Host General Control Register + USBHS_HSTCTRL : aliased USBHS_USBHS_HSTCTRL_Register; + -- Host Global Interrupt Status Register + USBHS_HSTISR : aliased USBHS_USBHS_HSTISR_Register; + -- Host Global Interrupt Clear Register + USBHS_HSTICR : aliased USBHS_USBHS_HSTICR_Register; + -- Host Global Interrupt Set Register + USBHS_HSTIFR : aliased USBHS_USBHS_HSTIFR_Register; + -- Host Global Interrupt Mask Register + USBHS_HSTIMR : aliased USBHS_USBHS_HSTIMR_Register; + -- Host Global Interrupt Disable Register + USBHS_HSTIDR : aliased USBHS_USBHS_HSTIDR_Register; + -- Host Global Interrupt Enable Register + USBHS_HSTIER : aliased USBHS_USBHS_HSTIER_Register; + -- Host Pipe Register + USBHS_HSTPIP : aliased USBHS_USBHS_HSTPIP_Register; + -- Host Frame Number Register + USBHS_HSTFNUM : aliased USBHS_USBHS_HSTFNUM_Register; + -- Host Address 1 Register + USBHS_HSTADDR1 : aliased USBHS_USBHS_HSTADDR1_Register; + -- Host Address 2 Register + USBHS_HSTADDR2 : aliased USBHS_USBHS_HSTADDR2_Register; + -- Host Address 3 Register + USBHS_HSTADDR3 : aliased USBHS_USBHS_HSTADDR3_Register; + -- Host Pipe Configuration Register (n = 0) 0 + USBHS_HSTPIPCFG : aliased USBHS_USBHS_HSTPIPCFG_Registers; + -- Host Pipe Status Register (n = 0) 0 + USBHS_HSTPIPISR : aliased USBHS_USBHS_HSTPIPISR_Registers; + -- Host Pipe Clear Register (n = 0) 0 + USBHS_HSTPIPICR : aliased USBHS_USBHS_HSTPIPICR_Registers; + -- Host Pipe Set Register (n = 0) 0 + USBHS_HSTPIPIFR : aliased USBHS_USBHS_HSTPIPIFR_Registers; + -- Host Pipe Mask Register (n = 0) 0 + USBHS_HSTPIPIMR : aliased USBHS_USBHS_HSTPIPIMR_Registers; + -- Host Pipe Enable Register (n = 0) 0 + USBHS_HSTPIPIER : aliased USBHS_USBHS_HSTPIPIER_Registers; + -- Host Pipe Disable Register (n = 0) 0 + USBHS_HSTPIPIDR : aliased USBHS_USBHS_HSTPIPIDR_Registers; + -- Host Pipe IN Request Register (n = 0) 0 + USBHS_HSTPIPINRQ : aliased USBHS_USBHS_HSTPIPINRQ_Registers; + -- Host Pipe Error Register (n = 0) 0 + USBHS_HSTPIPERR : aliased USBHS_USBHS_HSTPIPERR_Registers; + -- Host DMA Channel Next Descriptor Address Register (n = 1) + USBHS_USBHS_HSTDMA : aliased USBHS_USBHS_HSTDMA_Clusters; + -- General Control Register + USBHS_CTRL : aliased USBHS_USBHS_CTRL_Register; + -- General Status Register + USBHS_SR : aliased USBHS_USBHS_SR_Register; + -- General Status Clear Register + USBHS_SCR : aliased USBHS_USBHS_SCR_Register; + -- General Status Set Register + USBHS_SFR : aliased USBHS_USBHS_SFR_Register; + -- General Test A1 Register + USBHS_TSTA1 : aliased USBHS_USBHS_TSTA1_Register; + -- General Test A2 Register + USBHS_TSTA2 : aliased USBHS_USBHS_TSTA2_Register; + -- General Version Register + USBHS_VERSION : aliased USBHS_USBHS_VERSION_Register; + -- General Finite State Machine Register + USBHS_FSM : aliased USBHS_USBHS_FSM_Register; + end record + with Volatile; + + for USBHS_Peripheral use record + USBHS_DEVCTRL at 16#0# range 0 .. 31; + USBHS_DEVISR at 16#4# range 0 .. 31; + USBHS_DEVICR at 16#8# range 0 .. 31; + USBHS_DEVIFR at 16#C# range 0 .. 31; + USBHS_DEVIMR at 16#10# range 0 .. 31; + USBHS_DEVIDR at 16#14# range 0 .. 31; + USBHS_DEVIER at 16#18# range 0 .. 31; + USBHS_DEVEPT at 16#1C# range 0 .. 31; + USBHS_DEVFNUM at 16#20# range 0 .. 31; + USBHS_DEVEPTCFG at 16#100# range 0 .. 319; + USBHS_DEVEPTISR at 16#130# range 0 .. 319; + USBHS_DEVEPTICR at 16#160# range 0 .. 319; + USBHS_DEVEPTIFR at 16#190# range 0 .. 319; + USBHS_DEVEPTIMR at 16#1C0# range 0 .. 319; + USBHS_DEVEPTIER at 16#1F0# range 0 .. 319; + USBHS_DEVEPTIDR at 16#220# range 0 .. 319; + USBHS_USBHS_DEVDMA at 16#310# range 0 .. 895; + USBHS_HSTCTRL at 16#400# range 0 .. 31; + USBHS_HSTISR at 16#404# range 0 .. 31; + USBHS_HSTICR at 16#408# range 0 .. 31; + USBHS_HSTIFR at 16#40C# range 0 .. 31; + USBHS_HSTIMR at 16#410# range 0 .. 31; + USBHS_HSTIDR at 16#414# range 0 .. 31; + USBHS_HSTIER at 16#418# range 0 .. 31; + USBHS_HSTPIP at 16#41C# range 0 .. 31; + USBHS_HSTFNUM at 16#420# range 0 .. 31; + USBHS_HSTADDR1 at 16#424# range 0 .. 31; + USBHS_HSTADDR2 at 16#428# range 0 .. 31; + USBHS_HSTADDR3 at 16#42C# range 0 .. 31; + USBHS_HSTPIPCFG at 16#500# range 0 .. 319; + USBHS_HSTPIPISR at 16#530# range 0 .. 319; + USBHS_HSTPIPICR at 16#560# range 0 .. 319; + USBHS_HSTPIPIFR at 16#590# range 0 .. 319; + USBHS_HSTPIPIMR at 16#5C0# range 0 .. 319; + USBHS_HSTPIPIER at 16#5F0# range 0 .. 319; + USBHS_HSTPIPIDR at 16#620# range 0 .. 319; + USBHS_HSTPIPINRQ at 16#650# range 0 .. 319; + USBHS_HSTPIPERR at 16#680# range 0 .. 319; + USBHS_USBHS_HSTDMA at 16#710# range 0 .. 895; + USBHS_CTRL at 16#800# range 0 .. 31; + USBHS_SR at 16#804# range 0 .. 31; + USBHS_SCR at 16#808# range 0 .. 31; + USBHS_SFR at 16#80C# range 0 .. 31; + USBHS_TSTA1 at 16#810# range 0 .. 31; + USBHS_TSTA2 at 16#814# range 0 .. 31; + USBHS_VERSION at 16#818# range 0 .. 31; + USBHS_FSM at 16#82C# range 0 .. 31; + end record; + + -- USB High-Speed Interface + USBHS_Periph : aliased USBHS_Peripheral + with Import, Address => System'To_Address (16#40038000#); + +end SAM_SVD.USBHS; diff --git a/arch/ARM/SAM/svd/atsamv71/sam_svd-utmi.ads b/arch/ARM/SAM/svd/atsamv71/sam_svd-utmi.ads new file mode 100644 index 000000000..02aee89f4 --- /dev/null +++ b/arch/ARM/SAM/svd/atsamv71/sam_svd-utmi.ads @@ -0,0 +1,96 @@ +-- This spec has been automatically generated from ATSAMV71Q21.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package SAM_SVD.UTMI is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + -- OHCI Interrupt Configuration Register + type UTMI_UTMI_OHCIICR_Register is record + -- USB PORTx Reset + RES0 : Boolean := False; + -- unspecified + Reserved_1_3 : HAL.UInt3 := 16#0#; + -- OHCI Asynchronous Resume Interrupt Enable + ARIE : Boolean := False; + -- Reserved + APPSTART : Boolean := False; + -- unspecified + Reserved_6_22 : HAL.UInt17 := 16#0#; + -- USB Device Pull-up Disable + UDPPUDIS : Boolean := False; + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for UTMI_UTMI_OHCIICR_Register use record + RES0 at 0 range 0 .. 0; + Reserved_1_3 at 0 range 1 .. 3; + ARIE at 0 range 4 .. 4; + APPSTART at 0 range 5 .. 5; + Reserved_6_22 at 0 range 6 .. 22; + UDPPUDIS at 0 range 23 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- UTMI Reference Clock Frequency + type UTMI_CKTRIM_FREQ_Field is + ( + -- 12 MHz reference clock + Xtal12, + -- 16 MHz reference clock + Xtal16) + with Size => 2; + for UTMI_CKTRIM_FREQ_Field use + (Xtal12 => 0, + Xtal16 => 1); + + -- UTMI Clock Trimming Register + type UTMI_UTMI_CKTRIM_Register is record + -- UTMI Reference Clock Frequency + FREQ : UTMI_CKTRIM_FREQ_Field := SAM_SVD.UTMI.Xtal12; + -- unspecified + Reserved_2_31 : HAL.UInt30 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for UTMI_UTMI_CKTRIM_Register use record + FREQ at 0 range 0 .. 1; + Reserved_2_31 at 0 range 2 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- USB Transmitter Interface Macrocell + type UTMI_Peripheral is record + -- OHCI Interrupt Configuration Register + UTMI_OHCIICR : aliased UTMI_UTMI_OHCIICR_Register; + -- UTMI Clock Trimming Register + UTMI_CKTRIM : aliased UTMI_UTMI_CKTRIM_Register; + end record + with Volatile; + + for UTMI_Peripheral use record + UTMI_OHCIICR at 16#10# range 0 .. 31; + UTMI_CKTRIM at 16#30# range 0 .. 31; + end record; + + -- USB Transmitter Interface Macrocell + UTMI_Periph : aliased UTMI_Peripheral + with Import, Address => System'To_Address (16#400E0400#); + +end SAM_SVD.UTMI; diff --git a/arch/ARM/SAM/svd/atsamv71/sam_svd-wdt.ads b/arch/ARM/SAM/svd/atsamv71/sam_svd-wdt.ads new file mode 100644 index 000000000..1bb3df3df --- /dev/null +++ b/arch/ARM/SAM/svd/atsamv71/sam_svd-wdt.ads @@ -0,0 +1,129 @@ +-- This spec has been automatically generated from ATSAMV71Q21.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package SAM_SVD.WDT is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + -- Password + type WDT_CR_KEY_Field is + ( + -- Reset value for the field + Wdt_Cr_Key_Field_Reset, + -- Writing any other value in this field aborts the write operation. + Passwd) + with Size => 8; + for WDT_CR_KEY_Field use + (Wdt_Cr_Key_Field_Reset => 0, + Passwd => 165); + + -- Control Register + type WDT_WDT_CR_Register is record + -- Write-only. Watchdog Restart + WDRSTT : Boolean := False; + -- unspecified + Reserved_1_23 : HAL.UInt23 := 16#0#; + -- Write-only. Password + KEY : WDT_CR_KEY_Field := Wdt_Cr_Key_Field_Reset; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for WDT_WDT_CR_Register use record + WDRSTT at 0 range 0 .. 0; + Reserved_1_23 at 0 range 1 .. 23; + KEY at 0 range 24 .. 31; + end record; + + subtype WDT_WDT_MR_WDV_Field is HAL.UInt12; + subtype WDT_WDT_MR_WDD_Field is HAL.UInt12; + + -- Mode Register + type WDT_WDT_MR_Register is record + -- Watchdog Counter Value + WDV : WDT_WDT_MR_WDV_Field := 16#0#; + -- Watchdog Fault Interrupt Enable + WDFIEN : Boolean := False; + -- Watchdog Reset Enable + WDRSTEN : Boolean := False; + -- unspecified + Reserved_14_14 : HAL.Bit := 16#0#; + -- Watchdog Disable + WDDIS : Boolean := False; + -- Watchdog Delta Value + WDD : WDT_WDT_MR_WDD_Field := 16#0#; + -- Watchdog Debug Halt + WDDBGHLT : Boolean := False; + -- Watchdog Idle Halt + WDIDLEHLT : Boolean := False; + -- unspecified + Reserved_30_31 : HAL.UInt2 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for WDT_WDT_MR_Register use record + WDV at 0 range 0 .. 11; + WDFIEN at 0 range 12 .. 12; + WDRSTEN at 0 range 13 .. 13; + Reserved_14_14 at 0 range 14 .. 14; + WDDIS at 0 range 15 .. 15; + WDD at 0 range 16 .. 27; + WDDBGHLT at 0 range 28 .. 28; + WDIDLEHLT at 0 range 29 .. 29; + Reserved_30_31 at 0 range 30 .. 31; + end record; + + -- Status Register + type WDT_WDT_SR_Register is record + -- Read-only. Watchdog Underflow (cleared on read) + WDUNF : Boolean; + -- Read-only. Watchdog Error (cleared on read) + WDERR : Boolean; + -- unspecified + Reserved_2_31 : HAL.UInt30; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for WDT_WDT_SR_Register use record + WDUNF at 0 range 0 .. 0; + WDERR at 0 range 1 .. 1; + Reserved_2_31 at 0 range 2 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- Watchdog Timer + type WDT_Peripheral is record + -- Control Register + WDT_CR : aliased WDT_WDT_CR_Register; + -- Mode Register + WDT_MR : aliased WDT_WDT_MR_Register; + -- Status Register + WDT_SR : aliased WDT_WDT_SR_Register; + end record + with Volatile; + + for WDT_Peripheral use record + WDT_CR at 16#0# range 0 .. 31; + WDT_MR at 16#4# range 0 .. 31; + WDT_SR at 16#8# range 0 .. 31; + end record; + + -- Watchdog Timer + WDT_Periph : aliased WDT_Peripheral + with Import, Address => System'To_Address (16#400E1850#); + +end SAM_SVD.WDT; diff --git a/arch/ARM/SAM/svd/atsamv71/sam_svd-xdmac.ads b/arch/ARM/SAM/svd/atsamv71/sam_svd-xdmac.ads new file mode 100644 index 000000000..0aebbc977 --- /dev/null +++ b/arch/ARM/SAM/svd/atsamv71/sam_svd-xdmac.ads @@ -0,0 +1,1425 @@ +-- This spec has been automatically generated from ATSAMV71Q21.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with HAL; +with System; + +package SAM_SVD.XDMAC is + pragma Preelaborate; + + --------------- + -- Registers -- + --------------- + + subtype XDMAC_XDMAC_GTYPE_NB_CH_Field is HAL.UInt5; + subtype XDMAC_XDMAC_GTYPE_FIFO_SZ_Field is HAL.UInt11; + subtype XDMAC_XDMAC_GTYPE_NB_REQ_Field is HAL.UInt7; + + -- Global Type Register + type XDMAC_XDMAC_GTYPE_Register is record + -- Read-only. Number of Channels Minus One + NB_CH : XDMAC_XDMAC_GTYPE_NB_CH_Field; + -- Read-only. Number of Bytes + FIFO_SZ : XDMAC_XDMAC_GTYPE_FIFO_SZ_Field; + -- Read-only. Number of Peripheral Requests Minus One + NB_REQ : XDMAC_XDMAC_GTYPE_NB_REQ_Field; + -- unspecified + Reserved_23_31 : HAL.UInt9; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for XDMAC_XDMAC_GTYPE_Register use record + NB_CH at 0 range 0 .. 4; + FIFO_SZ at 0 range 5 .. 15; + NB_REQ at 0 range 16 .. 22; + Reserved_23_31 at 0 range 23 .. 31; + end record; + + -- Global Configuration Register + type XDMAC_XDMAC_GCFG_Register is record + -- Configuration Registers Clock Gating Disable + CGDISREG : Boolean := False; + -- Pipeline Clock Gating Disable + CGDISPIPE : Boolean := False; + -- FIFO Clock Gating Disable + CGDISFIFO : Boolean := False; + -- Bus Interface Clock Gating Disable + CGDISIF : Boolean := False; + -- unspecified + Reserved_4_7 : HAL.UInt4 := 16#0#; + -- Boundary X Kilobyte Enable + BXKBEN : Boolean := False; + -- unspecified + Reserved_9_31 : HAL.UInt23 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for XDMAC_XDMAC_GCFG_Register use record + CGDISREG at 0 range 0 .. 0; + CGDISPIPE at 0 range 1 .. 1; + CGDISFIFO at 0 range 2 .. 2; + CGDISIF at 0 range 3 .. 3; + Reserved_4_7 at 0 range 4 .. 7; + BXKBEN at 0 range 8 .. 8; + Reserved_9_31 at 0 range 9 .. 31; + end record; + + -- XDMAC_XDMAC_GWAC_PW array element + subtype XDMAC_XDMAC_GWAC_PW_Element is HAL.UInt4; + + -- XDMAC_XDMAC_GWAC_PW array + type XDMAC_XDMAC_GWAC_PW_Field_Array is array (0 .. 3) + of XDMAC_XDMAC_GWAC_PW_Element + with Component_Size => 4, Size => 16; + + -- Type definition for XDMAC_XDMAC_GWAC_PW + type XDMAC_XDMAC_GWAC_PW_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- PW as a value + Val : HAL.UInt16; + when True => + -- PW as an array + Arr : XDMAC_XDMAC_GWAC_PW_Field_Array; + end case; + end record + with Unchecked_Union, Size => 16; + + for XDMAC_XDMAC_GWAC_PW_Field use record + Val at 0 range 0 .. 15; + Arr at 0 range 0 .. 15; + end record; + + -- Global Weighted Arbiter Configuration Register + type XDMAC_XDMAC_GWAC_Register is record + -- Pool Weight 0 + PW : XDMAC_XDMAC_GWAC_PW_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_16_31 : HAL.UInt16 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for XDMAC_XDMAC_GWAC_Register use record + PW at 0 range 0 .. 15; + Reserved_16_31 at 0 range 16 .. 31; + end record; + + -- XDMAC_XDMAC_GIE_IE array + type XDMAC_XDMAC_GIE_IE_Field_Array is array (0 .. 23) of Boolean + with Component_Size => 1, Size => 24; + + -- Type definition for XDMAC_XDMAC_GIE_IE + type XDMAC_XDMAC_GIE_IE_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- IE as a value + Val : HAL.UInt24; + when True => + -- IE as an array + Arr : XDMAC_XDMAC_GIE_IE_Field_Array; + end case; + end record + with Unchecked_Union, Size => 24; + + for XDMAC_XDMAC_GIE_IE_Field use record + Val at 0 range 0 .. 23; + Arr at 0 range 0 .. 23; + end record; + + -- Global Interrupt Enable Register + type XDMAC_XDMAC_GIE_Register is record + -- Write-only. XDMAC Channel 0 Interrupt Enable Bit + IE : XDMAC_XDMAC_GIE_IE_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for XDMAC_XDMAC_GIE_Register use record + IE at 0 range 0 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- XDMAC_XDMAC_GID_ID array + type XDMAC_XDMAC_GID_ID_Field_Array is array (0 .. 23) of Boolean + with Component_Size => 1, Size => 24; + + -- Type definition for XDMAC_XDMAC_GID_ID + type XDMAC_XDMAC_GID_ID_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- ID as a value + Val : HAL.UInt24; + when True => + -- ID as an array + Arr : XDMAC_XDMAC_GID_ID_Field_Array; + end case; + end record + with Unchecked_Union, Size => 24; + + for XDMAC_XDMAC_GID_ID_Field use record + Val at 0 range 0 .. 23; + Arr at 0 range 0 .. 23; + end record; + + -- Global Interrupt Disable Register + type XDMAC_XDMAC_GID_Register is record + -- Write-only. XDMAC Channel 0 Interrupt Disable Bit + ID : XDMAC_XDMAC_GID_ID_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for XDMAC_XDMAC_GID_Register use record + ID at 0 range 0 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- XDMAC_XDMAC_GIM_IM array + type XDMAC_XDMAC_GIM_IM_Field_Array is array (0 .. 23) of Boolean + with Component_Size => 1, Size => 24; + + -- Type definition for XDMAC_XDMAC_GIM_IM + type XDMAC_XDMAC_GIM_IM_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- IM as a value + Val : HAL.UInt24; + when True => + -- IM as an array + Arr : XDMAC_XDMAC_GIM_IM_Field_Array; + end case; + end record + with Unchecked_Union, Size => 24; + + for XDMAC_XDMAC_GIM_IM_Field use record + Val at 0 range 0 .. 23; + Arr at 0 range 0 .. 23; + end record; + + -- Global Interrupt Mask Register + type XDMAC_XDMAC_GIM_Register is record + -- Read-only. XDMAC Channel 0 Interrupt Mask Bit + IM : XDMAC_XDMAC_GIM_IM_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for XDMAC_XDMAC_GIM_Register use record + IM at 0 range 0 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- XDMAC_XDMAC_GIS_IS array + type XDMAC_XDMAC_GIS_IS_Field_Array is array (0 .. 23) of Boolean + with Component_Size => 1, Size => 24; + + -- Type definition for XDMAC_XDMAC_GIS_IS + type XDMAC_XDMAC_GIS_IS_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- IS as a value + Val : HAL.UInt24; + when True => + -- IS as an array + Arr : XDMAC_XDMAC_GIS_IS_Field_Array; + end case; + end record + with Unchecked_Union, Size => 24; + + for XDMAC_XDMAC_GIS_IS_Field use record + Val at 0 range 0 .. 23; + Arr at 0 range 0 .. 23; + end record; + + -- Global Interrupt Status Register + type XDMAC_XDMAC_GIS_Register is record + -- Read-only. XDMAC Channel 0 Interrupt Status Bit + IS_k : XDMAC_XDMAC_GIS_IS_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for XDMAC_XDMAC_GIS_Register use record + IS_k at 0 range 0 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- XDMAC_XDMAC_GE_EN array + type XDMAC_XDMAC_GE_EN_Field_Array is array (0 .. 23) of Boolean + with Component_Size => 1, Size => 24; + + -- Type definition for XDMAC_XDMAC_GE_EN + type XDMAC_XDMAC_GE_EN_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- EN as a value + Val : HAL.UInt24; + when True => + -- EN as an array + Arr : XDMAC_XDMAC_GE_EN_Field_Array; + end case; + end record + with Unchecked_Union, Size => 24; + + for XDMAC_XDMAC_GE_EN_Field use record + Val at 0 range 0 .. 23; + Arr at 0 range 0 .. 23; + end record; + + -- Global Channel Enable Register + type XDMAC_XDMAC_GE_Register is record + -- Write-only. XDMAC Channel 0 Enable Bit + EN : XDMAC_XDMAC_GE_EN_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for XDMAC_XDMAC_GE_Register use record + EN at 0 range 0 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- XDMAC_XDMAC_GD_DI array + type XDMAC_XDMAC_GD_DI_Field_Array is array (0 .. 23) of Boolean + with Component_Size => 1, Size => 24; + + -- Type definition for XDMAC_XDMAC_GD_DI + type XDMAC_XDMAC_GD_DI_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- DI as a value + Val : HAL.UInt24; + when True => + -- DI as an array + Arr : XDMAC_XDMAC_GD_DI_Field_Array; + end case; + end record + with Unchecked_Union, Size => 24; + + for XDMAC_XDMAC_GD_DI_Field use record + Val at 0 range 0 .. 23; + Arr at 0 range 0 .. 23; + end record; + + -- Global Channel Disable Register + type XDMAC_XDMAC_GD_Register is record + -- Write-only. XDMAC Channel 0 Disable Bit + DI : XDMAC_XDMAC_GD_DI_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for XDMAC_XDMAC_GD_Register use record + DI at 0 range 0 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- XDMAC_XDMAC_GS_ST array + type XDMAC_XDMAC_GS_ST_Field_Array is array (0 .. 23) of Boolean + with Component_Size => 1, Size => 24; + + -- Type definition for XDMAC_XDMAC_GS_ST + type XDMAC_XDMAC_GS_ST_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- ST as a value + Val : HAL.UInt24; + when True => + -- ST as an array + Arr : XDMAC_XDMAC_GS_ST_Field_Array; + end case; + end record + with Unchecked_Union, Size => 24; + + for XDMAC_XDMAC_GS_ST_Field use record + Val at 0 range 0 .. 23; + Arr at 0 range 0 .. 23; + end record; + + -- Global Channel Status Register + type XDMAC_XDMAC_GS_Register is record + -- Read-only. XDMAC Channel 0 Status Bit + ST : XDMAC_XDMAC_GS_ST_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for XDMAC_XDMAC_GS_Register use record + ST at 0 range 0 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- XDMAC_XDMAC_GRS_RS array + type XDMAC_XDMAC_GRS_RS_Field_Array is array (0 .. 23) of Boolean + with Component_Size => 1, Size => 24; + + -- Type definition for XDMAC_XDMAC_GRS_RS + type XDMAC_XDMAC_GRS_RS_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- RS as a value + Val : HAL.UInt24; + when True => + -- RS as an array + Arr : XDMAC_XDMAC_GRS_RS_Field_Array; + end case; + end record + with Unchecked_Union, Size => 24; + + for XDMAC_XDMAC_GRS_RS_Field use record + Val at 0 range 0 .. 23; + Arr at 0 range 0 .. 23; + end record; + + -- Global Channel Read Suspend Register + type XDMAC_XDMAC_GRS_Register is record + -- XDMAC Channel 0 Read Suspend Bit + RS : XDMAC_XDMAC_GRS_RS_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for XDMAC_XDMAC_GRS_Register use record + RS at 0 range 0 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- XDMAC_XDMAC_GWS_WS array + type XDMAC_XDMAC_GWS_WS_Field_Array is array (0 .. 23) of Boolean + with Component_Size => 1, Size => 24; + + -- Type definition for XDMAC_XDMAC_GWS_WS + type XDMAC_XDMAC_GWS_WS_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- WS as a value + Val : HAL.UInt24; + when True => + -- WS as an array + Arr : XDMAC_XDMAC_GWS_WS_Field_Array; + end case; + end record + with Unchecked_Union, Size => 24; + + for XDMAC_XDMAC_GWS_WS_Field use record + Val at 0 range 0 .. 23; + Arr at 0 range 0 .. 23; + end record; + + -- Global Channel Write Suspend Register + type XDMAC_XDMAC_GWS_Register is record + -- XDMAC Channel 0 Write Suspend Bit + WS : XDMAC_XDMAC_GWS_WS_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for XDMAC_XDMAC_GWS_Register use record + WS at 0 range 0 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- XDMAC_XDMAC_GRWS_RWS array + type XDMAC_XDMAC_GRWS_RWS_Field_Array is array (0 .. 23) of Boolean + with Component_Size => 1, Size => 24; + + -- Type definition for XDMAC_XDMAC_GRWS_RWS + type XDMAC_XDMAC_GRWS_RWS_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- RWS as a value + Val : HAL.UInt24; + when True => + -- RWS as an array + Arr : XDMAC_XDMAC_GRWS_RWS_Field_Array; + end case; + end record + with Unchecked_Union, Size => 24; + + for XDMAC_XDMAC_GRWS_RWS_Field use record + Val at 0 range 0 .. 23; + Arr at 0 range 0 .. 23; + end record; + + -- Global Channel Read Write Suspend Register + type XDMAC_XDMAC_GRWS_Register is record + -- Write-only. XDMAC Channel 0 Read Write Suspend Bit + RWS : XDMAC_XDMAC_GRWS_RWS_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for XDMAC_XDMAC_GRWS_Register use record + RWS at 0 range 0 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- XDMAC_XDMAC_GRWR_RWR array + type XDMAC_XDMAC_GRWR_RWR_Field_Array is array (0 .. 23) of Boolean + with Component_Size => 1, Size => 24; + + -- Type definition for XDMAC_XDMAC_GRWR_RWR + type XDMAC_XDMAC_GRWR_RWR_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- RWR as a value + Val : HAL.UInt24; + when True => + -- RWR as an array + Arr : XDMAC_XDMAC_GRWR_RWR_Field_Array; + end case; + end record + with Unchecked_Union, Size => 24; + + for XDMAC_XDMAC_GRWR_RWR_Field use record + Val at 0 range 0 .. 23; + Arr at 0 range 0 .. 23; + end record; + + -- Global Channel Read Write Resume Register + type XDMAC_XDMAC_GRWR_Register is record + -- Write-only. XDMAC Channel 0 Read Write Resume Bit + RWR : XDMAC_XDMAC_GRWR_RWR_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for XDMAC_XDMAC_GRWR_Register use record + RWR at 0 range 0 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- XDMAC_XDMAC_GSWR_SWREQ array + type XDMAC_XDMAC_GSWR_SWREQ_Field_Array is array (0 .. 23) of Boolean + with Component_Size => 1, Size => 24; + + -- Type definition for XDMAC_XDMAC_GSWR_SWREQ + type XDMAC_XDMAC_GSWR_SWREQ_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- SWREQ as a value + Val : HAL.UInt24; + when True => + -- SWREQ as an array + Arr : XDMAC_XDMAC_GSWR_SWREQ_Field_Array; + end case; + end record + with Unchecked_Union, Size => 24; + + for XDMAC_XDMAC_GSWR_SWREQ_Field use record + Val at 0 range 0 .. 23; + Arr at 0 range 0 .. 23; + end record; + + -- Global Channel Software Request Register + type XDMAC_XDMAC_GSWR_Register is record + -- Write-only. XDMAC Channel 0 Software Request Bit + SWREQ : XDMAC_XDMAC_GSWR_SWREQ_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for XDMAC_XDMAC_GSWR_Register use record + SWREQ at 0 range 0 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- XDMAC_XDMAC_GSWS_SWRS array + type XDMAC_XDMAC_GSWS_SWRS_Field_Array is array (0 .. 23) of Boolean + with Component_Size => 1, Size => 24; + + -- Type definition for XDMAC_XDMAC_GSWS_SWRS + type XDMAC_XDMAC_GSWS_SWRS_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- SWRS as a value + Val : HAL.UInt24; + when True => + -- SWRS as an array + Arr : XDMAC_XDMAC_GSWS_SWRS_Field_Array; + end case; + end record + with Unchecked_Union, Size => 24; + + for XDMAC_XDMAC_GSWS_SWRS_Field use record + Val at 0 range 0 .. 23; + Arr at 0 range 0 .. 23; + end record; + + -- Global Channel Software Request Status Register + type XDMAC_XDMAC_GSWS_Register is record + -- Read-only. XDMAC Channel 0 Software Request Status Bit + SWRS : XDMAC_XDMAC_GSWS_SWRS_Field; + -- unspecified + Reserved_24_31 : HAL.UInt8; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for XDMAC_XDMAC_GSWS_Register use record + SWRS at 0 range 0 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + -- XDMAC_XDMAC_GSWF_SWF array + type XDMAC_XDMAC_GSWF_SWF_Field_Array is array (0 .. 23) of Boolean + with Component_Size => 1, Size => 24; + + -- Type definition for XDMAC_XDMAC_GSWF_SWF + type XDMAC_XDMAC_GSWF_SWF_Field + (As_Array : Boolean := False) + is record + case As_Array is + when False => + -- SWF as a value + Val : HAL.UInt24; + when True => + -- SWF as an array + Arr : XDMAC_XDMAC_GSWF_SWF_Field_Array; + end case; + end record + with Unchecked_Union, Size => 24; + + for XDMAC_XDMAC_GSWF_SWF_Field use record + Val at 0 range 0 .. 23; + Arr at 0 range 0 .. 23; + end record; + + -- Global Channel Software Flush Request Register + type XDMAC_XDMAC_GSWF_Register is record + -- Write-only. XDMAC Channel 0 Software Flush Request Bit + SWF : XDMAC_XDMAC_GSWF_SWF_Field := + (As_Array => False, Val => 16#0#); + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for XDMAC_XDMAC_GSWF_Register use record + SWF at 0 range 0 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + ------------------------------------------ + -- XDMAC_XDMAC_CHID cluster's Registers -- + ------------------------------------------ + + -- Channel Interrupt Enable Register (chid = 0) + type XDMAC_XDMAC_CIE_XDMAC_XDMAC_CHID_Register is record + -- Write-only. End of Block Interrupt Enable Bit + BIE : Boolean := False; + -- Write-only. End of Linked List Interrupt Enable Bit + LIE : Boolean := False; + -- Write-only. End of Disable Interrupt Enable Bit + DIE : Boolean := False; + -- Write-only. End of Flush Interrupt Enable Bit + FIE : Boolean := False; + -- Write-only. Read Bus Error Interrupt Enable Bit + RBIE : Boolean := False; + -- Write-only. Write Bus Error Interrupt Enable Bit + WBIE : Boolean := False; + -- Write-only. Request Overflow Error Interrupt Enable Bit + ROIE : Boolean := False; + -- unspecified + Reserved_7_31 : HAL.UInt25 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for XDMAC_XDMAC_CIE_XDMAC_XDMAC_CHID_Register use record + BIE at 0 range 0 .. 0; + LIE at 0 range 1 .. 1; + DIE at 0 range 2 .. 2; + FIE at 0 range 3 .. 3; + RBIE at 0 range 4 .. 4; + WBIE at 0 range 5 .. 5; + ROIE at 0 range 6 .. 6; + Reserved_7_31 at 0 range 7 .. 31; + end record; + + -- Channel Interrupt Disable Register (chid = 0) + type XDMAC_XDMAC_CID_XDMAC_XDMAC_CHID_Register is record + -- Write-only. End of Block Interrupt Disable Bit + BID : Boolean := False; + -- Write-only. End of Linked List Interrupt Disable Bit + LID : Boolean := False; + -- Write-only. End of Disable Interrupt Disable Bit + DID : Boolean := False; + -- Write-only. End of Flush Interrupt Disable Bit + FID : Boolean := False; + -- Write-only. Read Bus Error Interrupt Disable Bit + RBEID : Boolean := False; + -- Write-only. Write Bus Error Interrupt Disable Bit + WBEID : Boolean := False; + -- Write-only. Request Overflow Error Interrupt Disable Bit + ROID : Boolean := False; + -- unspecified + Reserved_7_31 : HAL.UInt25 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for XDMAC_XDMAC_CID_XDMAC_XDMAC_CHID_Register use record + BID at 0 range 0 .. 0; + LID at 0 range 1 .. 1; + DID at 0 range 2 .. 2; + FID at 0 range 3 .. 3; + RBEID at 0 range 4 .. 4; + WBEID at 0 range 5 .. 5; + ROID at 0 range 6 .. 6; + Reserved_7_31 at 0 range 7 .. 31; + end record; + + -- Channel Interrupt Mask Register (chid = 0) + type XDMAC_XDMAC_CIM_XDMAC_XDMAC_CHID_Register is record + -- Read-only. End of Block Interrupt Mask Bit + BIM : Boolean; + -- Read-only. End of Linked List Interrupt Mask Bit + LIM : Boolean; + -- Read-only. End of Disable Interrupt Mask Bit + DIM : Boolean; + -- Read-only. End of Flush Interrupt Mask Bit + FIM : Boolean; + -- Read-only. Read Bus Error Interrupt Mask Bit + RBEIM : Boolean; + -- Read-only. Write Bus Error Interrupt Mask Bit + WBEIM : Boolean; + -- Read-only. Request Overflow Error Interrupt Mask Bit + ROIM : Boolean; + -- unspecified + Reserved_7_31 : HAL.UInt25; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for XDMAC_XDMAC_CIM_XDMAC_XDMAC_CHID_Register use record + BIM at 0 range 0 .. 0; + LIM at 0 range 1 .. 1; + DIM at 0 range 2 .. 2; + FIM at 0 range 3 .. 3; + RBEIM at 0 range 4 .. 4; + WBEIM at 0 range 5 .. 5; + ROIM at 0 range 6 .. 6; + Reserved_7_31 at 0 range 7 .. 31; + end record; + + -- Channel Interrupt Status Register (chid = 0) + type XDMAC_XDMAC_CIS_XDMAC_XDMAC_CHID_Register is record + -- Read-only. End of Block Interrupt Status Bit + BIS : Boolean; + -- Read-only. End of Linked List Interrupt Status Bit + LIS : Boolean; + -- Read-only. End of Disable Interrupt Status Bit + DIS : Boolean; + -- Read-only. End of Flush Interrupt Status Bit + FIS : Boolean; + -- Read-only. Read Bus Error Interrupt Status Bit + RBEIS : Boolean; + -- Read-only. Write Bus Error Interrupt Status Bit + WBEIS : Boolean; + -- Read-only. Request Overflow Error Interrupt Status Bit + ROIS : Boolean; + -- unspecified + Reserved_7_31 : HAL.UInt25; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for XDMAC_XDMAC_CIS_XDMAC_XDMAC_CHID_Register use record + BIS at 0 range 0 .. 0; + LIS at 0 range 1 .. 1; + DIS at 0 range 2 .. 2; + FIS at 0 range 3 .. 3; + RBEIS at 0 range 4 .. 4; + WBEIS at 0 range 5 .. 5; + ROIS at 0 range 6 .. 6; + Reserved_7_31 at 0 range 7 .. 31; + end record; + + subtype XDMAC_XDMAC_CNDA_XDMAC_XDMAC_CHID_NDA_Field is HAL.UInt30; + + -- Channel Next Descriptor Address Register (chid = 0) + type XDMAC_XDMAC_CNDA_XDMAC_XDMAC_CHID_Register is record + -- Channel x Next Descriptor Interface + NDAIF : Boolean := False; + -- unspecified + Reserved_1_1 : HAL.Bit := 16#0#; + -- Channel x Next Descriptor Address + NDA : XDMAC_XDMAC_CNDA_XDMAC_XDMAC_CHID_NDA_Field := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for XDMAC_XDMAC_CNDA_XDMAC_XDMAC_CHID_Register use record + NDAIF at 0 range 0 .. 0; + Reserved_1_1 at 0 range 1 .. 1; + NDA at 0 range 2 .. 31; + end record; + + -- Channel x Next Descriptor Enable + type XDMAC_CNDC_NDE_Field is + ( + -- Descriptor fetch is disabled. + Dscr_Fetch_Dis, + -- Descriptor fetch is enabled. + Dscr_Fetch_En) + with Size => 1; + for XDMAC_CNDC_NDE_Field use + (Dscr_Fetch_Dis => 0, + Dscr_Fetch_En => 1); + + -- Channel x Next Descriptor Source Update + type XDMAC_CNDC_NDSUP_Field is + ( + -- Source parameters remain unchanged. + Src_Params_Unchanged, + -- Source parameters are updated when the descriptor is retrieved. + Src_Params_Updated) + with Size => 1; + for XDMAC_CNDC_NDSUP_Field use + (Src_Params_Unchanged => 0, + Src_Params_Updated => 1); + + -- Channel x Next Descriptor Destination Update + type XDMAC_CNDC_NDDUP_Field is + ( + -- Destination parameters remain unchanged. + Dst_Params_Unchanged, + -- Destination parameters are updated when the descriptor is retrieved. + Dst_Params_Updated) + with Size => 1; + for XDMAC_CNDC_NDDUP_Field use + (Dst_Params_Unchanged => 0, + Dst_Params_Updated => 1); + + -- Channel x Next Descriptor View + type XDMAC_CNDC_NDVIEW_Field is + ( + -- Next Descriptor View 0 + Ndv0, + -- Next Descriptor View 1 + Ndv1, + -- Next Descriptor View 2 + Ndv2, + -- Next Descriptor View 3 + Ndv3) + with Size => 2; + for XDMAC_CNDC_NDVIEW_Field use + (Ndv0 => 0, + Ndv1 => 1, + Ndv2 => 2, + Ndv3 => 3); + + -- Channel Next Descriptor Control Register (chid = 0) + type XDMAC_XDMAC_CNDC_XDMAC_XDMAC_CHID_Register is record + -- Channel x Next Descriptor Enable + NDE : XDMAC_CNDC_NDE_Field := SAM_SVD.XDMAC.Dscr_Fetch_Dis; + -- Channel x Next Descriptor Source Update + NDSUP : XDMAC_CNDC_NDSUP_Field := + SAM_SVD.XDMAC.Src_Params_Unchanged; + -- Channel x Next Descriptor Destination Update + NDDUP : XDMAC_CNDC_NDDUP_Field := + SAM_SVD.XDMAC.Dst_Params_Unchanged; + -- Channel x Next Descriptor View + NDVIEW : XDMAC_CNDC_NDVIEW_Field := SAM_SVD.XDMAC.Ndv0; + -- unspecified + Reserved_5_31 : HAL.UInt27 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for XDMAC_XDMAC_CNDC_XDMAC_XDMAC_CHID_Register use record + NDE at 0 range 0 .. 0; + NDSUP at 0 range 1 .. 1; + NDDUP at 0 range 2 .. 2; + NDVIEW at 0 range 3 .. 4; + Reserved_5_31 at 0 range 5 .. 31; + end record; + + subtype XDMAC_XDMAC_CUBC_XDMAC_XDMAC_CHID_UBLEN_Field is HAL.UInt24; + + -- Channel Microblock Control Register (chid = 0) + type XDMAC_XDMAC_CUBC_XDMAC_XDMAC_CHID_Register is record + -- Channel x Microblock Length + UBLEN : XDMAC_XDMAC_CUBC_XDMAC_XDMAC_CHID_UBLEN_Field := 16#0#; + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for XDMAC_XDMAC_CUBC_XDMAC_XDMAC_CHID_Register use record + UBLEN at 0 range 0 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype XDMAC_XDMAC_CBC_XDMAC_XDMAC_CHID_BLEN_Field is HAL.UInt12; + + -- Channel Block Control Register (chid = 0) + type XDMAC_XDMAC_CBC_XDMAC_XDMAC_CHID_Register is record + -- Channel x Block Length + BLEN : XDMAC_XDMAC_CBC_XDMAC_XDMAC_CHID_BLEN_Field := 16#0#; + -- unspecified + Reserved_12_31 : HAL.UInt20 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for XDMAC_XDMAC_CBC_XDMAC_XDMAC_CHID_Register use record + BLEN at 0 range 0 .. 11; + Reserved_12_31 at 0 range 12 .. 31; + end record; + + -- Channel x Transfer Type + type XDMAC_CC_TYPE_Field is + ( + -- Self-triggered mode (memory-to-memory transfer). + Mem_Tran, + -- Synchronized mode (peripheral-to-memory or memory-to-peripheral + -- transfer). + Per_Tran) + with Size => 1; + for XDMAC_CC_TYPE_Field use + (Mem_Tran => 0, + Per_Tran => 1); + + -- Channel x Memory Burst Size + type XDMAC_CC_MBSIZE_Field is + ( + -- The memory burst size is set to one. + Single, + -- The memory burst size is set to four. + Four, + -- The memory burst size is set to eight. + Eight, + -- The memory burst size is set to sixteen. + Sixteen) + with Size => 2; + for XDMAC_CC_MBSIZE_Field use + (Single => 0, + Four => 1, + Eight => 2, + Sixteen => 3); + + -- Channel x Synchronization + type XDMAC_CC_DSYNC_Field is + ( + -- Peripheral-to-memory transfer. + Per2Mem, + -- Memory-to-peripheral transfer. + Mem2Per) + with Size => 1; + for XDMAC_CC_DSYNC_Field use + (Per2Mem => 0, + Mem2Per => 1); + + -- Channel x Software Request Trigger + type XDMAC_CC_SWREQ_Field is + ( + -- Hardware request line is connected to the peripheral request line. + Hwr_Connected, + -- Software request is connected to the peripheral request line. + Swr_Connected) + with Size => 1; + for XDMAC_CC_SWREQ_Field use + (Hwr_Connected => 0, + Swr_Connected => 1); + + -- Channel x Fill Block of Memory + type XDMAC_CC_MEMSET_Field is + ( + -- Memset is not activated. + Normal_Mode, + -- Sets the block of memory pointed by DA field to the specified value. + -- This operation is performed on 8-, 16- or 32-bit basis. + Hw_Mode) + with Size => 1; + for XDMAC_CC_MEMSET_Field use + (Normal_Mode => 0, + Hw_Mode => 1); + + -- Channel x Chunk Size + type XDMAC_CC_CSIZE_Field is + ( + -- 1 data transferred + Chk_1, + -- 2 data transferred + Chk_2, + -- 4 data transferred + Chk_4, + -- 8 data transferred + Chk_8, + -- 16 data transferred + Chk_16) + with Size => 3; + for XDMAC_CC_CSIZE_Field use + (Chk_1 => 0, + Chk_2 => 1, + Chk_4 => 2, + Chk_8 => 3, + Chk_16 => 4); + + -- Channel x Data Width + type XDMAC_CC_DWIDTH_Field is + ( + -- The data size is set to 8 bits + Byte, + -- The data size is set to 16 bits + Halfword, + -- The data size is set to 32 bits + Word) + with Size => 2; + for XDMAC_CC_DWIDTH_Field use + (Byte => 0, + Halfword => 1, + Word => 2); + + -- Channel x Source Interface Identifier + type XDMAC_CC_SIF_Field is + ( + -- The data is read through the system bus interface 0. + Ahb_If0, + -- The data is read through the system bus interface 1. + Ahb_If1) + with Size => 1; + for XDMAC_CC_SIF_Field use + (Ahb_If0 => 0, + Ahb_If1 => 1); + + -- Channel x Destination Interface Identifier + type XDMAC_CC_DIF_Field is + ( + -- The data is written through the system bus interface 0. + Ahb_If0, + -- The data is written though the system bus interface 1. + Ahb_If1) + with Size => 1; + for XDMAC_CC_DIF_Field use + (Ahb_If0 => 0, + Ahb_If1 => 1); + + -- Channel x Source Addressing Mode + type XDMAC_CC_SAM_Field is + ( + -- The address remains unchanged. + Fixed_Am, + -- The addressing mode is incremented (the increment size is set to the + -- data size). + Incremented_Am, + -- The microblock stride is added at the microblock boundary. + Ubs_Am, + -- The microblock stride is added at the microblock boundary, the data + -- stride is added at the data boundary. + Ubs_Ds_Am) + with Size => 2; + for XDMAC_CC_SAM_Field use + (Fixed_Am => 0, + Incremented_Am => 1, + Ubs_Am => 2, + Ubs_Ds_Am => 3); + + -- Channel x Destination Addressing Mode + type XDMAC_CC_DAM_Field is + ( + -- The address remains unchanged. + Fixed_Am, + -- The addressing mode is incremented (the increment size is set to the + -- data size). + Incremented_Am, + -- The microblock stride is added at the microblock boundary. + Ubs_Am, + -- The microblock stride is added at the microblock boundary; the data + -- stride is added at the data boundary. + Ubs_Ds_Am) + with Size => 2; + for XDMAC_CC_DAM_Field use + (Fixed_Am => 0, + Incremented_Am => 1, + Ubs_Am => 2, + Ubs_Ds_Am => 3); + + -- Channel Initialization Done (this bit is read-only) + type XDMAC_CC_INITD_Field is + ( + -- Channel initialization is in progress. + In_Progress, + -- Channel initialization is completed. + Terminated) + with Size => 1; + for XDMAC_CC_INITD_Field use + (In_Progress => 0, + Terminated => 1); + + -- Read in Progress (this bit is read-only) + type XDMAC_CC_RDIP_Field is + ( + -- No active read transaction on the bus. + Done, + -- A read transaction is in progress. + In_Progress) + with Size => 1; + for XDMAC_CC_RDIP_Field use + (Done => 0, + In_Progress => 1); + + -- Write in Progress (this bit is read-only) + type XDMAC_CC_WRIP_Field is + ( + -- No active write transaction on the bus. + Done, + -- A write transaction is in progress. + In_Progress) + with Size => 1; + for XDMAC_CC_WRIP_Field use + (Done => 0, + In_Progress => 1); + + subtype XDMAC_XDMAC_CC_XDMAC_XDMAC_CHID_PERID_Field is HAL.UInt7; + + -- Channel Configuration Register (chid = 0) + type XDMAC_XDMAC_CC_XDMAC_XDMAC_CHID_Register is record + -- Channel x Transfer Type + TYPE_k : XDMAC_CC_TYPE_Field := SAM_SVD.XDMAC.Mem_Tran; + -- Channel x Memory Burst Size + MBSIZE : XDMAC_CC_MBSIZE_Field := SAM_SVD.XDMAC.Single; + -- unspecified + Reserved_3_3 : HAL.Bit := 16#0#; + -- Channel x Synchronization + DSYNC : XDMAC_CC_DSYNC_Field := SAM_SVD.XDMAC.Per2Mem; + -- unspecified + Reserved_5_5 : HAL.Bit := 16#0#; + -- Channel x Software Request Trigger + SWREQ : XDMAC_CC_SWREQ_Field := SAM_SVD.XDMAC.Hwr_Connected; + -- Channel x Fill Block of Memory + MEMSET : XDMAC_CC_MEMSET_Field := SAM_SVD.XDMAC.Normal_Mode; + -- Channel x Chunk Size + CSIZE : XDMAC_CC_CSIZE_Field := SAM_SVD.XDMAC.Chk_1; + -- Channel x Data Width + DWIDTH : XDMAC_CC_DWIDTH_Field := SAM_SVD.XDMAC.Byte; + -- Channel x Source Interface Identifier + SIF : XDMAC_CC_SIF_Field := SAM_SVD.XDMAC.Ahb_If0; + -- Channel x Destination Interface Identifier + DIF : XDMAC_CC_DIF_Field := SAM_SVD.XDMAC.Ahb_If0; + -- unspecified + Reserved_15_15 : HAL.Bit := 16#0#; + -- Channel x Source Addressing Mode + SAM : XDMAC_CC_SAM_Field := SAM_SVD.XDMAC.Fixed_Am; + -- Channel x Destination Addressing Mode + DAM : XDMAC_CC_DAM_Field := SAM_SVD.XDMAC.Fixed_Am; + -- unspecified + Reserved_20_20 : HAL.Bit := 16#0#; + -- Channel Initialization Done (this bit is read-only) + INITD : XDMAC_CC_INITD_Field := SAM_SVD.XDMAC.In_Progress; + -- Read in Progress (this bit is read-only) + RDIP : XDMAC_CC_RDIP_Field := SAM_SVD.XDMAC.Done; + -- Write in Progress (this bit is read-only) + WRIP : XDMAC_CC_WRIP_Field := SAM_SVD.XDMAC.Done; + -- Channel x Peripheral Hardware Request Line Identifier + PERID : XDMAC_XDMAC_CC_XDMAC_XDMAC_CHID_PERID_Field := 16#0#; + -- unspecified + Reserved_31_31 : HAL.Bit := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for XDMAC_XDMAC_CC_XDMAC_XDMAC_CHID_Register use record + TYPE_k at 0 range 0 .. 0; + MBSIZE at 0 range 1 .. 2; + Reserved_3_3 at 0 range 3 .. 3; + DSYNC at 0 range 4 .. 4; + Reserved_5_5 at 0 range 5 .. 5; + SWREQ at 0 range 6 .. 6; + MEMSET at 0 range 7 .. 7; + CSIZE at 0 range 8 .. 10; + DWIDTH at 0 range 11 .. 12; + SIF at 0 range 13 .. 13; + DIF at 0 range 14 .. 14; + Reserved_15_15 at 0 range 15 .. 15; + SAM at 0 range 16 .. 17; + DAM at 0 range 18 .. 19; + Reserved_20_20 at 0 range 20 .. 20; + INITD at 0 range 21 .. 21; + RDIP at 0 range 22 .. 22; + WRIP at 0 range 23 .. 23; + PERID at 0 range 24 .. 30; + Reserved_31_31 at 0 range 31 .. 31; + end record; + + subtype XDMAC_XDMAC_CDS_MSP_XDMAC_XDMAC_CHID_SDS_MSP_Field is HAL.UInt16; + subtype XDMAC_XDMAC_CDS_MSP_XDMAC_XDMAC_CHID_DDS_MSP_Field is HAL.UInt16; + + -- Channel Data Stride Memory Set Pattern (chid = 0) + type XDMAC_XDMAC_CDS_MSP_XDMAC_XDMAC_CHID_Register is record + -- Channel x Source Data stride or Memory Set Pattern + SDS_MSP : XDMAC_XDMAC_CDS_MSP_XDMAC_XDMAC_CHID_SDS_MSP_Field := 16#0#; + -- Channel x Destination Data Stride or Memory Set Pattern + DDS_MSP : XDMAC_XDMAC_CDS_MSP_XDMAC_XDMAC_CHID_DDS_MSP_Field := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for XDMAC_XDMAC_CDS_MSP_XDMAC_XDMAC_CHID_Register use record + SDS_MSP at 0 range 0 .. 15; + DDS_MSP at 0 range 16 .. 31; + end record; + + subtype XDMAC_XDMAC_CSUS_XDMAC_XDMAC_CHID_SUBS_Field is HAL.UInt24; + + -- Channel Source Microblock Stride (chid = 0) + type XDMAC_XDMAC_CSUS_XDMAC_XDMAC_CHID_Register is record + -- Channel x Source Microblock Stride + SUBS : XDMAC_XDMAC_CSUS_XDMAC_XDMAC_CHID_SUBS_Field := 16#0#; + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for XDMAC_XDMAC_CSUS_XDMAC_XDMAC_CHID_Register use record + SUBS at 0 range 0 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + subtype XDMAC_XDMAC_CDUS_XDMAC_XDMAC_CHID_DUBS_Field is HAL.UInt24; + + -- Channel Destination Microblock Stride (chid = 0) + type XDMAC_XDMAC_CDUS_XDMAC_XDMAC_CHID_Register is record + -- Channel x Destination Microblock Stride + DUBS : XDMAC_XDMAC_CDUS_XDMAC_XDMAC_CHID_DUBS_Field := 16#0#; + -- unspecified + Reserved_24_31 : HAL.UInt8 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for XDMAC_XDMAC_CDUS_XDMAC_XDMAC_CHID_Register use record + DUBS at 0 range 0 .. 23; + Reserved_24_31 at 0 range 24 .. 31; + end record; + + type XDMAC_RESERVED_Region is array (1 .. 2) of HAL.UInt32; + + -- Channel Interrupt Enable Register (chid = 0) + type XDMAC_XDMAC_CHID_Cluster is record + -- Channel Interrupt Enable Register (chid = 0) + XDMAC_CIE : aliased XDMAC_XDMAC_CIE_XDMAC_XDMAC_CHID_Register; + -- Channel Interrupt Disable Register (chid = 0) + XDMAC_CID : aliased XDMAC_XDMAC_CID_XDMAC_XDMAC_CHID_Register; + -- Channel Interrupt Mask Register (chid = 0) + XDMAC_CIM : aliased XDMAC_XDMAC_CIM_XDMAC_XDMAC_CHID_Register; + -- Channel Interrupt Status Register (chid = 0) + XDMAC_CIS : aliased XDMAC_XDMAC_CIS_XDMAC_XDMAC_CHID_Register; + -- Channel Source Address Register (chid = 0) + XDMAC_CSA : aliased HAL.UInt32; + -- Channel Destination Address Register (chid = 0) + XDMAC_CDA : aliased HAL.UInt32; + -- Channel Next Descriptor Address Register (chid = 0) + XDMAC_CNDA : aliased XDMAC_XDMAC_CNDA_XDMAC_XDMAC_CHID_Register; + -- Channel Next Descriptor Control Register (chid = 0) + XDMAC_CNDC : aliased XDMAC_XDMAC_CNDC_XDMAC_XDMAC_CHID_Register; + -- Channel Microblock Control Register (chid = 0) + XDMAC_CUBC : aliased XDMAC_XDMAC_CUBC_XDMAC_XDMAC_CHID_Register; + -- Channel Block Control Register (chid = 0) + XDMAC_CBC : aliased XDMAC_XDMAC_CBC_XDMAC_XDMAC_CHID_Register; + -- Channel Configuration Register (chid = 0) + XDMAC_CC : aliased XDMAC_XDMAC_CC_XDMAC_XDMAC_CHID_Register; + -- Channel Data Stride Memory Set Pattern (chid = 0) + XDMAC_CDS_MSP : aliased XDMAC_XDMAC_CDS_MSP_XDMAC_XDMAC_CHID_Register; + -- Channel Source Microblock Stride (chid = 0) + XDMAC_CSUS : aliased XDMAC_XDMAC_CSUS_XDMAC_XDMAC_CHID_Register; + -- Channel Destination Microblock Stride (chid = 0) + XDMAC_CDUS : aliased XDMAC_XDMAC_CDUS_XDMAC_XDMAC_CHID_Register; + -- Reserved Region + Reserved_88_8F : aliased XDMAC_RESERVED_Region; + end record + with Volatile, Size => 512; + + for XDMAC_XDMAC_CHID_Cluster use record + XDMAC_CIE at 16#0# range 0 .. 31; + XDMAC_CID at 16#4# range 0 .. 31; + XDMAC_CIM at 16#8# range 0 .. 31; + XDMAC_CIS at 16#C# range 0 .. 31; + XDMAC_CSA at 16#10# range 0 .. 31; + XDMAC_CDA at 16#14# range 0 .. 31; + XDMAC_CNDA at 16#18# range 0 .. 31; + XDMAC_CNDC at 16#1C# range 0 .. 31; + XDMAC_CUBC at 16#20# range 0 .. 31; + XDMAC_CBC at 16#24# range 0 .. 31; + XDMAC_CC at 16#28# range 0 .. 31; + XDMAC_CDS_MSP at 16#2C# range 0 .. 31; + XDMAC_CSUS at 16#30# range 0 .. 31; + XDMAC_CDUS at 16#34# range 0 .. 31; + Reserved_88_8F at 16#38# range 0 .. 63; + end record; + + -- Channel Interrupt Enable Register (chid = 0) + type XDMAC_XDMAC_CHID_Clusters is array (0 .. 23) + of XDMAC_XDMAC_CHID_Cluster; + + subtype XDMAC_XDMAC_VERSION_VERSION_Field is HAL.UInt12; + subtype XDMAC_XDMAC_VERSION_MFN_Field is HAL.UInt3; + + -- XDMAC Version Register + type XDMAC_XDMAC_VERSION_Register is record + -- Version of the Hardware Module + VERSION : XDMAC_XDMAC_VERSION_VERSION_Field := 16#0#; + -- unspecified + Reserved_12_15 : HAL.UInt4 := 16#0#; + -- Metal Fix Number + MFN : XDMAC_XDMAC_VERSION_MFN_Field := 16#0#; + -- unspecified + Reserved_19_31 : HAL.UInt13 := 16#0#; + end record + with Volatile_Full_Access, Size => 32, + Bit_Order => System.Low_Order_First; + + for XDMAC_XDMAC_VERSION_Register use record + VERSION at 0 range 0 .. 11; + Reserved_12_15 at 0 range 12 .. 15; + MFN at 0 range 16 .. 18; + Reserved_19_31 at 0 range 19 .. 31; + end record; + + ----------------- + -- Peripherals -- + ----------------- + + -- Extensible DMA Controller + type XDMAC_Peripheral is record + -- Global Type Register + XDMAC_GTYPE : aliased XDMAC_XDMAC_GTYPE_Register; + -- Global Configuration Register + XDMAC_GCFG : aliased XDMAC_XDMAC_GCFG_Register; + -- Global Weighted Arbiter Configuration Register + XDMAC_GWAC : aliased XDMAC_XDMAC_GWAC_Register; + -- Global Interrupt Enable Register + XDMAC_GIE : aliased XDMAC_XDMAC_GIE_Register; + -- Global Interrupt Disable Register + XDMAC_GID : aliased XDMAC_XDMAC_GID_Register; + -- Global Interrupt Mask Register + XDMAC_GIM : aliased XDMAC_XDMAC_GIM_Register; + -- Global Interrupt Status Register + XDMAC_GIS : aliased XDMAC_XDMAC_GIS_Register; + -- Global Channel Enable Register + XDMAC_GE : aliased XDMAC_XDMAC_GE_Register; + -- Global Channel Disable Register + XDMAC_GD : aliased XDMAC_XDMAC_GD_Register; + -- Global Channel Status Register + XDMAC_GS : aliased XDMAC_XDMAC_GS_Register; + -- Global Channel Read Suspend Register + XDMAC_GRS : aliased XDMAC_XDMAC_GRS_Register; + -- Global Channel Write Suspend Register + XDMAC_GWS : aliased XDMAC_XDMAC_GWS_Register; + -- Global Channel Read Write Suspend Register + XDMAC_GRWS : aliased XDMAC_XDMAC_GRWS_Register; + -- Global Channel Read Write Resume Register + XDMAC_GRWR : aliased XDMAC_XDMAC_GRWR_Register; + -- Global Channel Software Request Register + XDMAC_GSWR : aliased XDMAC_XDMAC_GSWR_Register; + -- Global Channel Software Request Status Register + XDMAC_GSWS : aliased XDMAC_XDMAC_GSWS_Register; + -- Global Channel Software Flush Request Register + XDMAC_GSWF : aliased XDMAC_XDMAC_GSWF_Register; + -- Channel Interrupt Enable Register (chid = 0) + XDMAC_XDMAC_CHID : aliased XDMAC_XDMAC_CHID_Clusters; + -- XDMAC Version Register + XDMAC_VERSION : aliased XDMAC_XDMAC_VERSION_Register; + end record + with Volatile; + + for XDMAC_Peripheral use record + XDMAC_GTYPE at 16#0# range 0 .. 31; + XDMAC_GCFG at 16#4# range 0 .. 31; + XDMAC_GWAC at 16#8# range 0 .. 31; + XDMAC_GIE at 16#C# range 0 .. 31; + XDMAC_GID at 16#10# range 0 .. 31; + XDMAC_GIM at 16#14# range 0 .. 31; + XDMAC_GIS at 16#18# range 0 .. 31; + XDMAC_GE at 16#1C# range 0 .. 31; + XDMAC_GD at 16#20# range 0 .. 31; + XDMAC_GS at 16#24# range 0 .. 31; + XDMAC_GRS at 16#28# range 0 .. 31; + XDMAC_GWS at 16#2C# range 0 .. 31; + XDMAC_GRWS at 16#30# range 0 .. 31; + XDMAC_GRWR at 16#34# range 0 .. 31; + XDMAC_GSWR at 16#38# range 0 .. 31; + XDMAC_GSWS at 16#3C# range 0 .. 31; + XDMAC_GSWF at 16#40# range 0 .. 31; + XDMAC_XDMAC_CHID at 16#50# range 0 .. 12287; + XDMAC_VERSION at 16#FFC# range 0 .. 31; + end record; + + -- Extensible DMA Controller + XDMAC_Periph : aliased XDMAC_Peripheral + with Import, Address => System'To_Address (16#40078000#); + +end SAM_SVD.XDMAC; diff --git a/arch/ARM/SAM/svd/atsamv71/sam_svd.ads b/arch/ARM/SAM/svd/atsamv71/sam_svd.ads new file mode 100644 index 000000000..660907f84 --- /dev/null +++ b/arch/ARM/SAM/svd/atsamv71/sam_svd.ads @@ -0,0 +1,140 @@ +-- This spec has been automatically generated from ATSAMV71Q21.svd + +pragma Restrictions (No_Elaboration_Code); +pragma Ada_2012; +pragma Style_Checks (Off); + +with System; + +-- Microchip ATSAMV71Q21 Microcontroller +package SAM_SVD is + pragma Preelaborate; + + -------------------- + -- Base addresses -- + -------------------- + + ACC_Base : constant System.Address := + System'To_Address (16#40044000#); + AES_Base : constant System.Address := + System'To_Address (16#4006C000#); + AFEC0_Base : constant System.Address := + System'To_Address (16#4003C000#); + AFEC1_Base : constant System.Address := + System'To_Address (16#40064000#); + CHIPID_Base : constant System.Address := + System'To_Address (16#400E0940#); + DACC_Base : constant System.Address := + System'To_Address (16#40040000#); + EFC_Base : constant System.Address := + System'To_Address (16#400E0C00#); + GMAC_Base : constant System.Address := + System'To_Address (16#40050000#); + GPBR_Base : constant System.Address := + System'To_Address (16#400E1890#); + HSMCI_Base : constant System.Address := + System'To_Address (16#40000000#); + ICM_Base : constant System.Address := + System'To_Address (16#40048000#); + ISI_Base : constant System.Address := + System'To_Address (16#4004C000#); + MATRIX_Base : constant System.Address := + System'To_Address (16#40088000#); + MCAN0_Base : constant System.Address := + System'To_Address (16#40030000#); + MCAN1_Base : constant System.Address := + System'To_Address (16#40034000#); + MLB_Base : constant System.Address := + System'To_Address (16#40068000#); + PIOA_Base : constant System.Address := + System'To_Address (16#400E0E00#); + PIOB_Base : constant System.Address := + System'To_Address (16#400E1000#); + PIOC_Base : constant System.Address := + System'To_Address (16#400E1200#); + PIOD_Base : constant System.Address := + System'To_Address (16#400E1400#); + PIOE_Base : constant System.Address := + System'To_Address (16#400E1600#); + PMC_Base : constant System.Address := + System'To_Address (16#400E0600#); + PWM0_Base : constant System.Address := + System'To_Address (16#40020000#); + PWM1_Base : constant System.Address := + System'To_Address (16#4005C000#); + QSPI_Base : constant System.Address := + System'To_Address (16#4007C000#); + RSTC_Base : constant System.Address := + System'To_Address (16#400E1800#); + RSWDT_Base : constant System.Address := + System'To_Address (16#400E1900#); + RTC_Base : constant System.Address := + System'To_Address (16#400E1860#); + RTT_Base : constant System.Address := + System'To_Address (16#400E1830#); + SDRAMC_Base : constant System.Address := + System'To_Address (16#40084000#); + SMC_Base : constant System.Address := + System'To_Address (16#40080000#); + SPI0_Base : constant System.Address := + System'To_Address (16#40008000#); + SPI1_Base : constant System.Address := + System'To_Address (16#40058000#); + SSC_Base : constant System.Address := + System'To_Address (16#40004000#); + SUPC_Base : constant System.Address := + System'To_Address (16#400E1810#); + TC0_Base : constant System.Address := + System'To_Address (16#4000C000#); + TC1_Base : constant System.Address := + System'To_Address (16#40010000#); + TC2_Base : constant System.Address := + System'To_Address (16#40014000#); + TC3_Base : constant System.Address := + System'To_Address (16#40054000#); + TRNG_Base : constant System.Address := + System'To_Address (16#40070000#); + TWIHS0_Base : constant System.Address := + System'To_Address (16#40018000#); + TWIHS1_Base : constant System.Address := + System'To_Address (16#4001C000#); + TWIHS2_Base : constant System.Address := + System'To_Address (16#40060000#); + UART0_Base : constant System.Address := + System'To_Address (16#400E0800#); + UART1_Base : constant System.Address := + System'To_Address (16#400E0A00#); + UART2_Base : constant System.Address := + System'To_Address (16#400E1A00#); + UART3_Base : constant System.Address := + System'To_Address (16#400E1C00#); + UART4_Base : constant System.Address := + System'To_Address (16#400E1E00#); + USART0_Base : constant System.Address := + System'To_Address (16#40024000#); + USART1_Base : constant System.Address := + System'To_Address (16#40028000#); + USART2_Base : constant System.Address := + System'To_Address (16#4002C000#); + USBHS_Base : constant System.Address := + System'To_Address (16#40038000#); + UTMI_Base : constant System.Address := + System'To_Address (16#400E0400#); + WDT_Base : constant System.Address := + System'To_Address (16#400E1850#); + XDMAC_Base : constant System.Address := + System'To_Address (16#40078000#); + LOCKBIT_Base : constant System.Address := + System'To_Address (16#0#); + SystemControl_Base : constant System.Address := + System'To_Address (16#E000E000#); + SysTick_Base : constant System.Address := + System'To_Address (16#E000E010#); + NVIC_Base : constant System.Address := + System'To_Address (16#E000E100#); + MPU_Base : constant System.Address := + System'To_Address (16#E000ED90#); + FPU_Base : constant System.Address := + System'To_Address (16#E000EF34#); + +end SAM_SVD; diff --git a/arch/svd.mk b/arch/svd.mk index c84487e01..f9b2abf77 100644 --- a/arch/svd.mk +++ b/arch/svd.mk @@ -3,6 +3,7 @@ CORTEX_DIR=$(PWD)/ARM/cortex_m/src STM_DIR=$(PWD)/ARM/STM32/svd NORDIC_DIR=$(PWD)/ARM/Nordic/svd SIFIVE_DIR=$(PWD)/RISC-V/SiFive/svd +SAM_DIR=$(PWD)/ARM/SAM/svd all: svd @@ -25,3 +26,6 @@ svd: rm -rf $(SIFIVE_DIR)/FE* $(SVD2ADA_DIR)/svd2ada $(SVD2ADA_DIR)/CMSIS-SVD/SiFive/FE310.svd --boolean -o $(SIFIVE_DIR)/FE310 -p FE310_SVD --base-types-package HAL --gen-uint-always + + rm -rf $(SAM_DIR)/atsam* + $(SVD2ADA_DIR)/svd2ada $(SVD2ADA_DIR)/CMSIS-SVD/ATMEL/ATSAMV71Q21.svd --boolean -o $(SAM_DIR)/atsamv71 -p SAM_SVD --base-types-package HAL --gen-uint-always diff --git a/boards/board_projects_generator.py b/boards/board_projects_generator.py index be2adc2fc..1dbb1e324 100755 --- a/boards/board_projects_generator.py +++ b/boards/board_projects_generator.py @@ -14,6 +14,7 @@ 'STM32F469_Discovery': { 'rts_profiles': ['ravenscar-sfp', 'ravenscar-full']}, 'STM32F746_Discovery': { 'rts_profiles': ['ravenscar-sfp', 'ravenscar-full']}, 'STM32F769_Discovery': { 'rts_profiles': ['ravenscar-sfp', 'ravenscar-full']}, + 'SAMV71_XPLAINED' : { 'rts_profiles': ['ravenscar-sfp', 'ravenscar-full']}, } @@ -26,7 +27,8 @@ 'STM32F429_Discovery': 'stm32f429_discovery', 'STM32F469_Discovery': 'stm32f469_discovery', 'STM32F746_Discovery': 'stm32f746_discovery', - 'STM32F769_Discovery': 'stm32f769_discovery'} + 'STM32F769_Discovery': 'stm32f769_discovery', + 'SAMV71_XPLAINED': 'samv71_xplained'} def gen_project(board_name, rts): diff --git a/boards/samv71_xplained/samv71_xplained_full.gpr b/boards/samv71_xplained/samv71_xplained_full.gpr new file mode 100644 index 000000000..19476f1d1 --- /dev/null +++ b/boards/samv71_xplained/samv71_xplained_full.gpr @@ -0,0 +1,82 @@ +-- This project file was generated by the Ada_Drivers_Library project wizard script +library project SAMV71_XPLAINED_Full is + + type BUILD_TYPE is ("Debug", "Production"); + Build : BUILD_Type := external ("ADL_BUILD", "Debug"); + + -- Target architecture + Target := Project'Target; + + -- Callgraph info is not available on all architectures + Callgraph_Switch := (); + case Target is + when "riscv32-unknown-elf" => + null; + when others => + Callgraph_Switch := ("-fcallgraph-info=su"); + end case; + + package Compiler is + case Build is + when "Production" => + for Default_Switches ("Ada") use + ("-g", "-O3", "-gnatp", "-gnatn"); + when "Debug" => + for Default_Switches ("Ada") use + ("-g", "-O0", "-gnata") & Callgraph_Switch; + end case; + for Default_Switches ("ada") use Compiler'Default_Switches ("Ada") & + ("-gnatwa", "-gnatwe", "-gnatQ", "-gnatw.X", "-gnaty", "-gnatyO", + "-gnatyM120", "-ffunction-sections", "-fdata-sections"); + end Compiler; + + for Languages use ("Ada"); + for Create_Missing_Dirs use "True"; + for Object_Dir use "obj_" & Build; + for Library_Dir use "obj_lib_" & Build; + for Library_Kind use "static"; + for Library_Name use "ada_drivers_library"; + for Target use "arm-eabi"; + for Runtime ("Ada") use "ravenscar-full-samv71"; + + Vendor := "Atmel"; -- From board definition + Max_Mount_Points := "2"; -- From user input + Max_Mount_Name_Length := "128"; -- From user input + Runtime_Profile := "ravenscar-full"; -- From user input + Device_Name := "ATSAMV71x"; -- From board definition + Device_Family := "SAM"; -- From board definition + Runtime_Name := "ravenscar-full-samv71"; -- From user input + Has_Ravenscar_Full_Runtime := "True"; -- From board definition + CPU_Core := "ARM Cortex-M7F"; -- From mcu definition + Board := "SAMV71_XPLAINED"; -- From user input + Has_ZFP_Runtime := "True"; -- From board definition + Has_Ravenscar_SFP_Runtime := "True"; -- From board definition + Max_Path_Length := "1024"; -- From user input + Runtime_Name_Suffix := "samv71"; -- From board definition + Architecture := "ARM"; -- From board definition + + -- Project source directories + Src_Dirs_Root := "../.."; + for Source_Dirs use ( + Src_Dirs_Root & "/hal/src/", -- From HAL config + Src_Dirs_Root & "/boards/samv71_xplained/src/", -- From board definition + Src_Dirs_Root & "/arch/ARM/cortex_m/src", -- From arch definition + Src_Dirs_Root & "/arch/ARM/cortex_m/src/cm7", -- From arch definition + Src_Dirs_Root & "/arch/ARM/cortex_m/src/fpu", -- From arch definition + Src_Dirs_Root & "/arch/ARM/cortex_m/src/cache", -- From arch definition + Src_Dirs_Root & "/arch/ARM/cortex_m/src/nvic_cm4_cm7", -- From arch definition + Src_Dirs_Root & "/arch/ARM/SAM/devices/", -- From MCU definition + Src_Dirs_Root & "/arch/ARM/SAM/drivers/", -- From MCU definition + Src_Dirs_Root & "/arch/ARM/SAM/svd/atsamv71/", -- From MCU definition + Src_Dirs_Root & "/middleware/src/filesystem", -- From middleware config + Src_Dirs_Root & "/middleware/src/BLE", -- From middleware config + Src_Dirs_Root & "/middleware/src/utils", -- From middleware config + Src_Dirs_Root & "/middleware/src/audio", -- From middleware config + Src_Dirs_Root & "/middleware/src/monitor", -- From middleware config + Src_Dirs_Root & "/middleware/src/bitmap", -- From middleware config + Src_Dirs_Root & "/middleware/src/command_line", -- From middleware config + Src_Dirs_Root & "/middleware/src/sdmmc", -- From middleware config + Src_Dirs_Root & "/middleware/src/ravenscar-common", -- From middleware config + Src_Dirs_Root & "/components/src/**", -- From components config + "src/full"); +end SAMV71_XPLAINED_Full; diff --git a/boards/samv71_xplained/samv71_xplained_sfp.gpr b/boards/samv71_xplained/samv71_xplained_sfp.gpr new file mode 100644 index 000000000..1a8b759a1 --- /dev/null +++ b/boards/samv71_xplained/samv71_xplained_sfp.gpr @@ -0,0 +1,82 @@ +-- This project file was generated by the Ada_Drivers_Library project wizard script +library project SAMV71_XPLAINED_Sfp is + + type BUILD_TYPE is ("Debug", "Production"); + Build : BUILD_Type := external ("ADL_BUILD", "Debug"); + + -- Target architecture + Target := Project'Target; + + -- Callgraph info is not available on all architectures + Callgraph_Switch := (); + case Target is + when "riscv32-unknown-elf" => + null; + when others => + Callgraph_Switch := ("-fcallgraph-info=su"); + end case; + + package Compiler is + case Build is + when "Production" => + for Default_Switches ("Ada") use + ("-g", "-O3", "-gnatp", "-gnatn"); + when "Debug" => + for Default_Switches ("Ada") use + ("-g", "-O0", "-gnata") & Callgraph_Switch; + end case; + for Default_Switches ("ada") use Compiler'Default_Switches ("Ada") & + ("-gnatwa", "-gnatwe", "-gnatQ", "-gnatw.X", "-gnaty", "-gnatyO", + "-gnatyM120", "-ffunction-sections", "-fdata-sections"); + end Compiler; + + for Languages use ("Ada"); + for Create_Missing_Dirs use "True"; + for Object_Dir use "obj_" & Build; + for Library_Dir use "obj_lib_" & Build; + for Library_Kind use "static"; + for Library_Name use "ada_drivers_library"; + for Target use "arm-eabi"; + for Runtime ("Ada") use "ravenscar-sfp-samv71"; + + Vendor := "Atmel"; -- From board definition + Max_Mount_Points := "2"; -- From user input + Max_Mount_Name_Length := "128"; -- From user input + Runtime_Profile := "ravenscar-sfp"; -- From user input + Device_Name := "ATSAMV71x"; -- From board definition + Device_Family := "SAM"; -- From board definition + Runtime_Name := "ravenscar-sfp-samv71"; -- From user input + Has_Ravenscar_Full_Runtime := "True"; -- From board definition + CPU_Core := "ARM Cortex-M7F"; -- From mcu definition + Board := "SAMV71_XPLAINED"; -- From user input + Has_ZFP_Runtime := "True"; -- From board definition + Has_Ravenscar_SFP_Runtime := "True"; -- From board definition + Max_Path_Length := "1024"; -- From user input + Runtime_Name_Suffix := "samv71"; -- From board definition + Architecture := "ARM"; -- From board definition + + -- Project source directories + Src_Dirs_Root := "../.."; + for Source_Dirs use ( + Src_Dirs_Root & "/hal/src/", -- From HAL config + Src_Dirs_Root & "/boards/samv71_xplained/src/", -- From board definition + Src_Dirs_Root & "/arch/ARM/cortex_m/src", -- From arch definition + Src_Dirs_Root & "/arch/ARM/cortex_m/src/cm7", -- From arch definition + Src_Dirs_Root & "/arch/ARM/cortex_m/src/fpu", -- From arch definition + Src_Dirs_Root & "/arch/ARM/cortex_m/src/cache", -- From arch definition + Src_Dirs_Root & "/arch/ARM/cortex_m/src/nvic_cm4_cm7", -- From arch definition + Src_Dirs_Root & "/arch/ARM/SAM/devices/", -- From MCU definition + Src_Dirs_Root & "/arch/ARM/SAM/drivers/", -- From MCU definition + Src_Dirs_Root & "/arch/ARM/SAM/svd/atsamv71q21/", -- From MCU definition + Src_Dirs_Root & "/middleware/src/filesystem", -- From middleware config + Src_Dirs_Root & "/middleware/src/BLE", -- From middleware config + Src_Dirs_Root & "/middleware/src/utils", -- From middleware config + Src_Dirs_Root & "/middleware/src/audio", -- From middleware config + Src_Dirs_Root & "/middleware/src/monitor", -- From middleware config + Src_Dirs_Root & "/middleware/src/bitmap", -- From middleware config + Src_Dirs_Root & "/middleware/src/command_line", -- From middleware config + Src_Dirs_Root & "/middleware/src/sdmmc", -- From middleware config + Src_Dirs_Root & "/middleware/src/ravenscar-common", -- From middleware config + Src_Dirs_Root & "/components/src/**", -- From components config + "src/sfp/"); +end SAM_V71_XPLAINED_Sfp; diff --git a/boards/samv71_xplained/src/full/adl_config.ads b/boards/samv71_xplained/src/full/adl_config.ads new file mode 100644 index 000000000..ca27d8975 --- /dev/null +++ b/boards/samv71_xplained/src/full/adl_config.ads @@ -0,0 +1,18 @@ +-- This package was generated by the Ada_Drivers_Library project wizard script +package ADL_Config is + Vendor : constant String := "Atmel"; -- From board definition + Max_Mount_Points : constant := 2; -- From user input + Max_Mount_Name_Length : constant := 128; -- From user input + Runtime_Profile : constant String := "ravenscar-full"; -- From user input + Device_Name : constant String := "ATSAMV71x"; -- From board definition + Device_Family : constant String := "SAM"; -- From board definition + Runtime_Name : constant String := "ravenscar-full-samv71"; -- From user input + Has_Ravenscar_Full_Runtime : constant String := "True"; -- From board definition + CPU_Core : constant String := "ARM Cortex-M7F"; -- From mcu definition + Board : constant String := "SAMV71_XPLAINED"; -- From user input + Has_ZFP_Runtime : constant String := "True"; -- From board definition + Has_Ravenscar_SFP_Runtime : constant String := "True"; -- From board definition + Max_Path_Length : constant := 1024; -- From user input + Runtime_Name_Suffix : constant String := "samv71"; -- From board definition + Architecture : constant String := "ARM"; -- From board definition +end ADL_Config; diff --git a/boards/samv71_xplained/src/sfp/adl_config.ads b/boards/samv71_xplained/src/sfp/adl_config.ads new file mode 100644 index 000000000..79e7e3ab9 --- /dev/null +++ b/boards/samv71_xplained/src/sfp/adl_config.ads @@ -0,0 +1,18 @@ +-- This package was generated by the Ada_Drivers_Library project wizard script +package ADL_Config is + Vendor : constant String := "Atmel"; -- From board definition + Max_Mount_Points : constant := 2; -- From user input + Max_Mount_Name_Length : constant := 128; -- From user input + Runtime_Profile : constant String := "ravenscar-sfp"; -- From user input + Device_Name : constant String := "ATSAMV71x"; -- From board definition + Device_Family : constant String := "SAM"; -- From board definition + Runtime_Name : constant String := "ravenscar-sfp-samv71"; -- From user input + Has_Ravenscar_Full_Runtime : constant String := "True"; -- From board definition + CPU_Core : constant String := "ARM Cortex-M7F"; -- From mcu definition + Board : constant String := "SAMV71_XPLAINED"; -- From user input + Has_ZFP_Runtime : constant String := "True"; -- From board definition + Has_Ravenscar_SFP_Runtime : constant String := "True"; -- From board definition + Max_Path_Length : constant := 1024; -- From user input + Runtime_Name_Suffix : constant String := "samv71"; -- From board definition + Architecture : constant String := "ARM"; -- From board definition +end ADL_Config; diff --git a/components/src/screen/FT801/ft801-coproc.adb b/components/src/screen/FT801/ft801-coproc.adb new file mode 100644 index 000000000..6fd463069 --- /dev/null +++ b/components/src/screen/FT801/ft801-coproc.adb @@ -0,0 +1,96 @@ +with FT801.Registers; use FT801.Registers; + +package body FT801.Coproc is + + procedure Send_Coproc_Cmds (This : in out FT801_Device; + Cmds : Coproc_List) + is + Freespace : Fifo_Pointer_Type; + Cmds_Arr : UInt8_Array (1 .. Cmds'Size / 8) + with Address => Cmds'Address; + begin + loop + Freespace := Compute_Free_Space (This => This); + exit when Freespace >= Cmds'Size / 8; + end loop; + + Host_Memory_Write (This => This, + Address => UInt22 (RAM_CMD_Address) + UInt22 (This.Fifo_Ptr), + Payload => Cmds_Arr); + This.Fifo_Ptr := This.Fifo_Ptr + Cmds_Arr'Length; + + Write_Register (This => This, + Reg => REG_CMD_WRITE, + Val => UInt32 (This.Fifo_Ptr)); + +-- for I in Cmds'Range loop +-- declare +-- Payload : UInt8_Array (1 .. 4) +-- with Address => Cmds (I)'Address; +-- begin +-- +-- Host_Memory_Write (This => This, +-- Address => UInt22 (RAM_CMD_Address) + UInt22 (This.Fifo_Ptr), +-- Payload => Payload); +-- This.Fifo_Ptr := This.Fifo_Ptr + Payload'Length; +-- +-- Write_Register (This => This, +-- Reg => REG_CMD_WRITE, +-- Val => UInt32 (This.Fifo_Ptr)); +-- end; +-- end loop; + + end Send_Coproc_Cmds; + + function Compute_Free_Space (This : FT801_Device) return Fifo_Pointer_Type + is + Fullness : Fifo_Pointer_Type; + Cmd_Write : UInt32; + Cmd_Read : UInt32; + begin + Read_Register (This => This, + Reg => REG_CMD_WRITE, + Val => Cmd_Write); + + Read_Register (This => This, + Reg => REG_CMD_READ, + Val => Cmd_Read); + + Fullness := Fifo_Pointer_Type (Cmd_Write - Cmd_Read); + + return (4092 - Fullness); + end Compute_Free_Space; + + function Fault_Occured (This : FT801_Device) return Boolean + is + Cmd_Read : UInt32; + begin + Read_Register (This => This, + Reg => REG_CMD_READ, + Val => Cmd_Read); + + if Cmd_Read = 16#FFF# then + return True; + end if; + + return False; + end Fault_Occured; + + procedure Recover_Fault (This : FT801_Device) + is + begin + Write_Register (This => This, + Reg => REG_CPURESET, + Val => 1); + Write_Register (This => This, + Reg => REG_CMD_READ, + Val => 0); + Write_Register (This => This, + Reg => REG_CMD_WRITE, + Val => 0); + Write_Register (This => This, + Reg => REG_CPURESET, + Val => 0); + end Recover_Fault; + +end FT801.Coproc; diff --git a/components/src/screen/FT801/ft801-coproc.ads b/components/src/screen/FT801/ft801-coproc.ads new file mode 100644 index 000000000..b4256f177 --- /dev/null +++ b/components/src/screen/FT801/ft801-coproc.ads @@ -0,0 +1,118 @@ +package FT801.Coproc is + + OPT_3D : constant := 0; + OPT_RGB565 : constant := 0; + OPT_MONO : constant := 1; + OPT_NODL : constant := 2; + OPT_FLAT : constant := 256; + OPT_SIGNED : constant := 256; + OPT_CENTERX : constant := 512; + OPT_CENTERY : constant := 1024; + OPT_CENTER : constant := 1536; + OPT_RIGHTX : constant := 2048; + OPT_NOBACK : constant := 4096; + OPT_NOTICKS : constant := 8192; + OPT_NOHM : constant := 16384; + OPT_NOPOINTER : constant := 16384; + OPT_NOSECS : constant := 32768; + OPT_NOHANDS : constant := 49152; + + type Coproc_List is array (Natural range <>) of UInt32; + + procedure Send_Coproc_Cmds (This : in out FT801_Device; + Cmds : Coproc_List); + + CMD_DLSTART : constant UInt32 := 16#FFFF_FF00#; + CMD_DLSWAP : constant UInt32 := 16#FFFF_FF01#; + CMD_COLDSTART : constant UInt32 := 16#FFFF_FF32#; + CMD_LOGO : constant UInt32 := 16#FFFF_FF31#; + + type CMD_INTERRUPT (As_Array : Boolean := False) is record + case As_Array is + when False => + Cmd : UInt32 := 16#FFFF_FF02#; + MS : UInt32; + when True => + Arr : Coproc_List (1 .. 2); + end case; + end record + with Unchecked_Union, Size => 64; + + for CMD_INTERRUPT use record + Cmd at 0 range 0 .. 31; + MS at 0 range 32 .. 63; + Arr at 0 range 0 .. 63; + end record; + + type CMD_MEMCPY (As_Array : Boolean := False) is record + case As_Array is + when False => + Cmd : UInt32 := 16#FFFF_FF1D#; + Dst : UInt32; + Src : UInt32; + Num : UInt32; + when True => + Arr : Coproc_List (1 .. 4); + end case; + end record + with Unchecked_Union, Size => 128; + + for CMD_MEMCPY use record + Cmd at 0 range 0 .. 31; + Dst at 4 range 0 .. 31; + Src at 8 range 0 .. 31; + Num at 12 range 0 .. 31; + Arr at 0 range 0 .. 127; + end record; + + type CMD_MEMZERO (As_Array : Boolean := False) is record + case As_Array is + when False => + Cmd : UInt32 := 16#FFFF_FF1C#; + Ptr : UInt32; + Num : UInt32; when True => + Arr : Coproc_List (1 .. 3); + end case; + end record + with Unchecked_Union, Size => 96; + + for CMD_MEMZERO use record + Cmd at 0 range 0 .. 31; + Ptr at 4 range 0 .. 31; + Num at 8 range 0 .. 31; + Arr at 0 range 0 .. 95; + end record; + + type CMD_MEMSET (As_Array : Boolean := False) is record + case As_Array is + when False => + Cmd : UInt32 := 16#FFFF_FF1B#; + Ptr : UInt32; + Value : UInt32; + Num : UInt32; + when True => + Arr : Coproc_List (1 .. 4); + end case; + end record + with Unchecked_Union, Size => 128; + + for CMD_MEMSET use record + Cmd at 0 range 0 .. 31; + Ptr at 4 range 0 .. 31; + Value at 8 range 0 .. 31; + Num at 12 range 0 .. 31; + Arr at 0 range 0 .. 127; + end record; + + function Fault_Occured (This : FT801_Device) return Boolean; + + procedure Recover_Fault (This : FT801_Device); + + +private + + function Compute_Free_Space (This : FT801_Device) return Fifo_Pointer_Type; + + + +end FT801.Coproc; diff --git a/components/src/screen/FT801/ft801-display_list.adb b/components/src/screen/FT801/ft801-display_list.adb new file mode 100644 index 000000000..cc36f31cf --- /dev/null +++ b/components/src/screen/FT801/ft801-display_list.adb @@ -0,0 +1,38 @@ +with FT801.Registers; use FT801.Registers; + +package body FT801.Display_List is + + procedure Poll_For_Ready (This : FT801_Device) + is + Dlswap : REG_DLSWAP_Reg; + begin + loop + Read_Register (This => This, + Reg => REG_DLSWAP, + Val => Dlswap.Val); + + exit when Dlswap.Val = 0; + end loop; + + end Poll_For_Ready; + + + ------------------- + -- Send_Cmd_List -- + ------------------- + + procedure Send_Cmd_List (This : in out FT801_Device; + Cmds : Cmd_List) + is + Cmd_Arr : UInt8_Array (1 .. Cmds'Size / 8) + with Address => Cmds'Address; + begin + Host_Memory_Write (This => This, + Address => RAM_DL_Address + UInt22 (This.Dl_Ptr), + Payload => Cmd_Arr); + + Poll_For_Ready (This => This); + + end Send_Cmd_List; + +end FT801.Display_List; diff --git a/components/src/screen/FT801/ft801-display_list.ads b/components/src/screen/FT801/ft801-display_list.ads new file mode 100644 index 000000000..ba4dea2c7 --- /dev/null +++ b/components/src/screen/FT801/ft801-display_list.ads @@ -0,0 +1,332 @@ +package FT801.Display_List is + + type Cmd_List is array (Natural range <>) of UInt32; + + procedure Send_Cmd_List (This : in out FT801_Device; + Cmds : Cmd_List) + with Pre => Cmds'Length <= Dl_Pointer_Type'Last / 4; + + type Graphics_Primitives is + (BITMAPS, + POINTS, + LINES, + LINE_STRIP, + EDGE_STRIP_R, + EDGE_STRIP_L, + EDGE_STRIP_A, + EDGE_STRIP_B, + RECTS) + with Size => 4; + + for Graphics_Primitives use + (BITMAPS => 1, + POINTS => 2, + LINES => 3, + LINE_STRIP => 4, + EDGE_STRIP_R => 5, + EDGE_STRIP_L => 6, + EDGE_STRIP_A => 7, + EDGE_STRIP_B => 8, + RECTS => 9); + + type Cmd_Begin (As_Val : Boolean := False) is record + case As_Val is + when False => + Cmd : UInt8 := 16#1F#; + RSVD : UInt16 := 0; + Prim : Graphics_Primitives; + when True => + Val : UInt32; + end case; + end record + with Unchecked_Union, Size => 32; + + for Cmd_Begin use record + Cmd at 0 range 24 .. 31; + RSVD at 0 range 4 .. 23; + Prim at 0 range 0 .. 3; + Val at 0 range 0 .. 31; + end record; + + type Bitmap_Layout (As_Val : Boolean := False) is record + case As_Val is + when False => + Cmd : UInt8 := 16#07#; + Format : Graphics_Bitmap_Format; + Linestride : UInt10; + Height : UInt9; + when True => + Val : UInt32; + end case; + end record + with Unchecked_Union, Size => 32; + + for Bitmap_Layout use record + Cmd at 0 range 24 .. 31; + Format at 0 range 19 .. 23; + Linestride at 0 range 9 .. 18; + Height at 0 range 0 .. 8; + Val at 0 range 0 .. 31; + end record; + + type Bitmap_Size_Filter_Field is + (NEAREST, BILINEAR) + with Size => 1; + + for Bitmap_Size_Filter_Field use + (NEAREST => 0, + BILINEAR => 1); + + type Bitmap_Size_Wrap_Field is + (BORDER, REPEAT) + with Size => 1; + + for Bitmap_Size_Wrap_Field use + (BORDER => 0, + REPEAT => 1); + + type Bitmap_Size (As_Val : Boolean := False) is record + case As_Val is + when False => + Cmd : UInt8 := 16#08#; + RSVD : UInt3 := 0; + Filter : Bitmap_Size_Filter_Field; + Wrapx : Bitmap_Size_Wrap_Field; + WrapY : Bitmap_Size_Wrap_Field; + Width : UInt9; + Height : UInt9; + when True => + Val : UInt32; + end case; + end record + with Unchecked_Union, Size => 32; + + for Bitmap_Size use record + Cmd at 0 range 24 .. 31; + RSVD at 0 range 21 .. 23; + Filter at 0 range 20 .. 20; + Wrapx at 0 range 19 .. 19; + Wrapy at 0 range 18 .. 18; + Width at 0 range 9 .. 17; + Height at 0 range 0 .. 8; + Val at 0 range 0 .. 31; + end record; + + type Bitmap_Source (As_Val : Boolean := False) is record + case As_Val is + when False => + Cmd : UInt8 := 16#01#; + RSVD : UInt4 := 0; + Addr : UInt20; + when True => + Val : UInt32; + end case; + end record + with Unchecked_Union, Size => 32; + + for Bitmap_Source use record + Cmd at 0 range 24 .. 31; + RSVD at 0 range 20 .. 23; + Addr at 0 range 0 .. 19; + Val at 0 range 0 .. 31; + end record; + + type Clear (As_Val : Boolean := False) is record + case As_Val is + when False => + Cmd : UInt8 := 16#26#; + RSVD : UInt21 := 0; + Color : Boolean; + Stencil : Boolean; + Tag : Boolean; + when True => + Val : UInt32; + end case; + end record + with Unchecked_Union, Size => 32; + + for Clear use record + Cmd at 0 range 24 .. 31; + RSVD at 0 range 3 .. 23; + Color at 0 range 2 .. 2; + Stencil at 0 range 1 .. 1; + Tag at 0 range 0 .. 0; + Val at 0 range 0 .. 31; + end record; + + type ClearRGB (As_Val : Boolean := False) is record + case As_Val is + when False => + Cmd : UInt8 := 16#02#; + Red : UInt8; + Blue : UInt8; + Green : UInt8; + when True => + Val : UInt32; + end case; + end record + with Unchecked_Union, Size => 32; + + for ClearRGB use record + Cmd at 0 range 24 .. 31; + Red at 0 range 16 .. 23; + Blue at 0 range 8 .. 15; + Green at 0 range 0 .. 7; + Val at 0 range 0 .. 31; + end record; + + type Display (As_Val : Boolean := False) is record + case As_Val is + when False => + Cmd : UInt8 := 0; + RSVD : UInt24 := 0; + when True => + Val : UInt32; + end case; + end record + with Unchecked_Union, Size => 32; + + for Display use record + Cmd at 0 range 24 .. 31; + RSVD at 0 range 0 .. 23; + Val at 0 range 0 .. 31; + end record; + + type Cmd_End (As_Val : Boolean := False) is record + case As_Val is + when False => + Cmd : UInt8 := 16#21#; + RSVD : UInt24 := 0; + when True => + Val : UInt32; + end case; + end record + with Unchecked_Union, Size => 32; + + for Cmd_End use record + Cmd at 0 range 24 .. 31; + RSVD at 0 range 0 .. 23; + Val at 0 range 0 .. 31; + end record; + + type Vertex2ii (As_Val : Boolean := False) is record + case As_Val is + when False => + Cmd : UInt2 := 2#10#; + X : UInt9; + Y : UInt9; + Handle : UInt5; + Cell : UInt7; + when True => + Val : UInt32; + end case; + end record + with Unchecked_Union, Size => 32; + + for Vertex2ii use record + Cmd at 0 range 30 .. 31; + X at 0 range 21 .. 29; + Y at 0 range 12 .. 20; + Handle at 0 range 7 .. 11; + Cell at 0 range 0 .. 6; + Val at 0 range 0 .. 31; + end record; + + type Vertex2f (As_Val : Boolean := False) is record + case As_Val is + when False => + Cmd : UInt2 := 2#01#; + X : UInt15; + Y : UInt15; + when True => + Val : UInt32; + end case; + end record + with Unchecked_Union, Size => 32; + + for Vertex2f use record + Cmd at 0 range 30 .. 31; + X at 0 range 15 .. 29; + Y at 0 range 0 .. 14; + Val at 0 range 0 .. 31; + end record; + + type ColorRGB (As_Val : Boolean := False) is record + case As_Val is + when False => + Cmd : UInt8 := 16#04#; + Red : UInt8; + Blue : UInt8; + Green : UInt8; + when True => + Val : UInt32; + end case; + end record + with Unchecked_Union, Size => 32; + + for ColorRGB use record + Cmd at 0 range 24 .. 31; + Red at 0 range 16 .. 23; + Blue at 0 range 8 .. 15; + Green at 0 range 0 .. 7; + Val at 0 range 0 .. 31; + end record; + + type Point_Size (As_Val : Boolean := False) is record + case As_Val is + when False => + Cmd : UInt8 := 16#0D#; + RSVD : UInt7 := 0; + Size : UInt17; + when True => + Val : UInt32; + end case; + end record + with Unchecked_Union, Size => 32; + + for Point_Size use record + Cmd at 0 range 24 .. 31; + RSVD at 0 range 17 .. 23; + Size at 0 range 0 .. 16; + Val at 0 range 0 .. 31; + end record; + + type Save_Context (As_Val : Boolean := False) is record + case As_Val is + when False => + Cmd : UInt8 := 16#22#; + RSVD : UInt24 := 16#00#; + when True => + Val : UInt32; + end case; + end record + with Unchecked_Union, Size => 32; + + for Save_Context use record + Cmd at 0 range 24 .. 31; + RSVD at 0 range 0 .. 23; + Val at 0 range 0 .. 31; + end record; + + type Restore_Context (As_Val : Boolean := False) is record + case As_Val is + when False => + Cmd : UInt8 := 16#23#; + RSVD : UInt24 := 16#00#; + when True => + Val : UInt32; + end case; + end record + with Unchecked_Union, Size => 32; + + for Restore_Context use record + Cmd at 0 range 24 .. 31; + RSVD at 0 range 0 .. 23; + Val at 0 range 0 .. 31; + end record; + +private + + procedure Poll_For_Ready (This : FT801_Device); + +end FT801.Display_List; diff --git a/components/src/screen/FT801/ft801-registers.adb b/components/src/screen/FT801/ft801-registers.adb new file mode 100644 index 000000000..a2a25fc2a --- /dev/null +++ b/components/src/screen/FT801/ft801-registers.adb @@ -0,0 +1,36 @@ + +package body FT801.Registers is + + -------------------- + -- Write_Register -- + -------------------- + + procedure Write_Register (This : FT801_Device; + Reg : Register; + Val : UInt32) + is + Arr : UInt8_Array (1 .. 4) + with Address => Val'Address; + begin + Host_Memory_Write (This => This, + Address => Register'Enum_Rep (Reg), + Payload => Arr); + end Write_Register; + + ------------------- + -- Read_Register -- + ------------------- + + procedure Read_Register (This : FT801_Device; + Reg : Register; + Val : out UInt32) + is + Arr : UInt8_Array (1 .. 4) + with Address => Val'Address; + begin + Host_Memory_Read (This => This, + Address => Register'Enum_Rep (Reg), + Payload => Arr); + end Read_Register; + +end FT801.Registers; diff --git a/components/src/screen/FT801/ft801-registers.ads b/components/src/screen/FT801/ft801-registers.ads new file mode 100644 index 000000000..5ae66054f --- /dev/null +++ b/components/src/screen/FT801/ft801-registers.ads @@ -0,0 +1,605 @@ +package FT801.Registers is + + type Register is + (REG_ID, + REG_FRAMES, + REG_CLOCK, + REG_FREQUENCY, + REG_SCREENSHOT_EN, + REG_SCREENSHOT_Y, + REG_SCREENSHOT_START, + REG_CPURESET, + REG_TAP_CRC, + REG_TAP_MASK, + REG_HCYCLE, + REG_HOFFSET, + REG_HSIZE, + REG_HSYNC0, + REG_HSYNC1, + REG_VCYCLE, + REG_VOFFSET, + REG_VSIZE, + REG_VSYNC0, + REG_VSYNC1, + REG_DLSWAP, + REG_ROTATE, + REG_OUTBITS, + REG_DITHER, + REG_SWIZZLE, + REG_CSPREAD, + REG_PCLK_POL, + REG_PCLK, + REG_TAG_X, + REG_TAG_Y, + REG_TAG, + REG_VOL_PB, + REG_VOL_SOUND, + REG_SOUND, + REG_PLAY, + REG_GPIO_DIR, + REG_GPIO, + REG_INT_FLAGS, + REG_INT_EN, + REG_INT_MASK, + REG_PLAYBACK_START, + REG_PLAYBACK_LENGTH, + REG_PLAYBACK_READPT, + REG_PLAYBACK_FREQ, + REG_PLAYBACK_FORMAT, + REG_PLAYBACK_LOOP, + REG_PLAYBACK_PLAY, + REG_PWM_HZ, + REG_PWM_DUTY, + REG_MACRO0, + REG_MACRO1, + REG_SCREENSHOT_BUS_Y, + REG_CMD_READ, + REG_CMD_WRITE, + REG_CMD_DL, + REG_TOUCH_MODE, + REG_CTOUCH_EXTENDED, + REG_CTOUCH_REG, + REG_CTOUCH_TOUCH1_XY, + REG_CTOUCH_TOUCH4_Y, + REG_CTOUCH_TOUCH0_XY, + REG_TOUCH_TAG_XY, + REG_TOUCH_TAG, + REG_CTOUCH_TRANSFORM_A, + REG_COUTCH_TRANSFORM_B, + REG_CTOUCH_TRANSFORM_C, + REG_CTOUCH_TRANSFORM_D, + REG_CTOUCH_TRANSFORM_E, + REG_CTOUCH_TRANSFORM_F, + REG_CTOUCH_TOUCH4_X, + REG_SCREENSHOT_READ, + REG_TRIM, + REG_CTOUCH_TOUCH2_XY, + REG_CTOUCH_TOUCH3_XY, + REG_TRACKER) + with Size => 22; + + for Register use + (REG_ID => 16#102400#, + REG_FRAMES => 16#102404#, + REG_CLOCK => 16#102408#, + REG_FREQUENCY => 16#10240C#, + REG_SCREENSHOT_EN => 16#102410#, + REG_SCREENSHOT_Y => 16#102414#, + REG_SCREENSHOT_START => 16#102418#, + REG_CPURESET => 16#10241C#, + REG_TAP_CRC => 16#102420#, + REG_TAP_MASK => 16#102424#, + REG_HCYCLE => 16#102428#, + REG_HOFFSET => 16#10242C#, + REG_HSIZE => 16#102430#, + REG_HSYNC0 => 16#102434#, + REG_HSYNC1 => 16#102438#, + REG_VCYCLE => 16#10243C#, + REG_VOFFSET => 16#102440#, + REG_VSIZE => 16#102444#, + REG_VSYNC0 => 16#102448#, + REG_VSYNC1 => 16#10244C#, + REG_DLSWAP => 16#102450#, + REG_ROTATE => 16#102454#, + REG_OUTBITS => 16#102458#, + REG_DITHER => 16#10245C#, + REG_SWIZZLE => 16#102460#, + REG_CSPREAD => 16#102464#, + REG_PCLK_POL => 16#102468#, + REG_PCLK => 16#10246C#, + REG_TAG_X => 16#102470#, + REG_TAG_Y => 16#102474#, + REG_TAG => 16#102478#, + REG_VOL_PB => 16#10247C#, + REG_VOL_SOUND => 16#102480#, + REG_SOUND => 16#102484#, + REG_PLAY => 16#102488#, + REG_GPIO_DIR => 16#10248C#, + REG_GPIO => 16#102490#, + REG_INT_FLAGS => 16#102498#, + REG_INT_EN => 16#10249C#, + REG_INT_MASK => 16#1024A0#, + REG_PLAYBACK_START => 16#1024A4#, + REG_PLAYBACK_LENGTH => 16#1024A8#, + REG_PLAYBACK_READPT => 16#1024AC#, + REG_PLAYBACK_FREQ => 16#1024B0#, + REG_PLAYBACK_FORMAT => 16#1024B4#, + REG_PLAYBACK_LOOP => 16#1024B8#, + REG_PLAYBACK_PLAY => 16#1024BC#, + REG_PWM_HZ => 16#1024C0#, + REG_PWM_DUTY => 16#1024C4#, + REG_MACRO0 => 16#1024C8#, + REG_MACRO1 => 16#1024CC#, + REG_SCREENSHOT_BUS_Y => 16#1024D8#, + REG_CMD_READ => 16#1024E4#, + REG_CMD_WRITE => 16#1024E8#, + REG_CMD_DL => 16#1024EC#, + REG_TOUCH_MODE => 16#1024F0#, + REG_CTOUCH_EXTENDED => 16#1024F4#, + REG_CTOUCH_REG => 16#1024F8#, + REG_CTOUCH_TOUCH1_XY => 16#102508#, + REG_CTOUCH_TOUCH4_Y => 16#10250C#, + REG_CTOUCH_TOUCH0_XY => 16#102510#, + REG_TOUCH_TAG_XY => 16#102514#, + REG_TOUCH_TAG => 16#102518#, + REG_CTOUCH_TRANSFORM_A => 16#10251C#, + REG_COUTCH_TRANSFORM_B => 16#102520#, + REG_CTOUCH_TRANSFORM_C => 16#102524#, + REG_CTOUCH_TRANSFORM_D => 16#102528#, + REG_CTOUCH_TRANSFORM_E => 16#10252C#, + REG_CTOUCH_TRANSFORM_F => 16#102530#, + REG_CTOUCH_TOUCH4_X => 16#102538#, + REG_SCREENSHOT_READ => 16#102554#, + REG_TRIM => 16#10256C#, + REG_CTOUCH_TOUCH2_XY => 16#102574#, + REG_CTOUCH_TOUCH3_XY => 16#102578#, + REG_TRACKER => 16#109000#); + + procedure Write_Register (This : FT801_Device; + Reg : Register; + Val : UInt32); + + procedure Read_Register (This : FT801_Device; + Reg : Register; + Val : out UInt32); + + type REG_PCLK_Reg (As_Val : Boolean := False) is record + case As_Val is + when False => + RSVD : UInt24 := 0; + Div : UInt8; + when True => + Val : UInt32; + end case; + end record + with Unchecked_Union, Size => 32; + + for REG_PCLK_Reg use record + RSVD at 0 range 8 .. 31; + Div at 0 range 0 .. 7; + Val at 0 range 0 .. 31; + end record; + + type REG_PCLK_POL_Reg (As_Val : Boolean := False) is record + case As_Val is + when False => + RSVD : UInt31 := 0; + Falling_Edge : Boolean := False; + when True => + Val : UInt32; + end case; + end record + with Unchecked_Union, Size => 32; + + for REG_PCLK_POL_Reg use record + RSVD at 0 range 1 .. 31; + Falling_Edge at 0 range 0 .. 0; + Val at 0 range 0 .. 31; + end record; + + type REG_CSPREAD_Reg (As_Val : Boolean := False) is record + case As_Val is + when False => + RSVD : UInt31 := 0; + Early : Boolean := True; + when True => + Val : UInt32; + end case; + end record + with Unchecked_Union, Size => 32; + + for REG_CSPREAD_Reg use record + RSVD at 0 range 1 .. 31; + Early at 0 range 0 .. 0; + Val at 0 range 0 .. 31; + end record; + + type REG_SWIZZLE_Reg (As_Val : Boolean := False) is record + case As_Val is + when False => + RSVD : UInt28 := 0; + Pin_Cfg : UInt4 := 0; + when True => + Val : UInt32; + end case; + end record + with Unchecked_Union, Size => 32; + + for REG_SWIZZLE_Reg use record + RSVD at 0 range 4 .. 31; + Pin_Cfg at 0 range 0 .. 3; + Val at 0 range 0 .. 31; + end record; + + type REG_DITHER_Reg (As_Val : Boolean := False) is record + case As_Val is + when False => + RSVD : UInt31 := 16#1B6#; + Enable : Boolean := False; + when True => + Val : UInt32; + end case; + end record + with Unchecked_Union, Size => 32; + + for REG_DITHER_Reg use record + RSVD at 0 range 1 .. 31; + Enable at 0 range 0 .. 0; + Val at 0 range 0 .. 31; + end record; + + type REG_OUTBITS_Reg (As_Val : Boolean := False) is record + case As_Val is + when False => + RSVD : UInt23 := 0; + B : UInt3 := 6; + G : UInt3 := 6; + R : UInt3 := 6; + when True => + Val : UInt32; + end case; + end record + with Unchecked_Union, Size => 32; + + for REG_OUTBITS_Reg use record + RSVD at 0 range 9 .. 31; + B at 0 range 0 .. 2; + G at 0 range 3 .. 5; + R at 0 range 6 .. 8; + Val at 0 range 0 .. 31; + end record; + + type REG_ROTATE_Reg (As_Val : Boolean := False) is record + case As_Val is + when False => + RSVD : UInt31 := 0; + Enable : Boolean := False; + when True => + Val : UInt32; + end case; + end record + with Unchecked_Union, Size => 32; + + for REG_ROTATE_Reg use record + RSVD at 0 range 1 .. 31; + Enable at 0 range 0 .. 0; + Val at 0 range 0 .. 31; + end record; + + type REG_VSYNC1_Reg (As_Val : Boolean := False) is record + case As_Val is + when False => + RSVD : UInt22 := 0; + Lines : UInt10 := 16#0A#; + when True => + Val : UInt32; + end case; + end record + with Unchecked_Union, Size => 32; + + for REG_VSYNC1_Reg use record + RSVD at 0 range 10 .. 31; + Lines at 0 range 0 .. 9; + Val at 0 range 0 .. 31; + end record; + + type REG_VSYNC0_Reg (As_Val : Boolean := False) is record + case As_Val is + when False => + RSVD : UInt22 := 0; + Lines : UInt10 := 0; + when True => + Val : UInt32; + end case; + end record + with Unchecked_Union, Size => 32; + + for REG_VSYNC0_Reg use record + RSVD at 0 range 10 .. 31; + Lines at 0 range 0 .. 9; + Val at 0 range 0 .. 31; + end record; + + type REG_VSIZE_Reg (As_Val : Boolean := False) is record + case As_Val is + when False => + RSVD : UInt22 := 0; + Lines : UInt10 := 16#110#; + when True => + Val : UInt32; + end case; + end record + with Unchecked_Union, Size => 32; + + for REG_VSIZE_Reg use record + RSVD at 0 range 10 .. 31; + Lines at 0 range 0 .. 9; + Val at 0 range 0 .. 31; + end record; + + type REG_VOFFSET_Reg (As_Val : Boolean := False) is record + case As_Val is + when False => + RSVD : UInt22 := 0; + Lines : UInt10 := 16#00C#; + when True => + Val : UInt32; + end case; + end record + with Unchecked_Union, Size => 32; + + for REG_VOFFSET_Reg use record + RSVD at 0 range 10 .. 31; + Lines at 0 range 0 .. 9; + Val at 0 range 0 .. 31; + end record; + + type REG_VCYCLE_Reg (As_Val : Boolean := False) is record + case As_Val is + when False => + RSVD : UInt22 := 0; + Lines : UInt10 := 16#124#; + when True => + Val : UInt32; + end case; + end record + with Unchecked_Union, Size => 32; + + for REG_VCYCLE_Reg use record + RSVD at 0 range 10 .. 31; + Lines at 0 range 0 .. 9; + Val at 0 range 0 .. 31; + end record; + + type REG_HSYNC1_Reg (As_Val : Boolean := False) is record + case As_Val is + when False => + RSVD : UInt22 := 0; + Cycles : UInt10 := 16#029#; + when True => + Val : UInt32; + end case; + end record + with Unchecked_Union, Size => 32; + + for REG_HSYNC1_Reg use record + RSVD at 0 range 10 .. 31; + Cycles at 0 range 0 .. 9; + Val at 0 range 0 .. 31; + end record; + + type REG_HSYNC0_Reg (As_Val : Boolean := False) is record + case As_Val is + when False => + RSVD : UInt22 := 0; + Cycles : UInt10 := 0; + when True => + Val : UInt32; + end case; + end record + with Unchecked_Union, Size => 32; + + for REG_HSYNC0_Reg use record + RSVD at 0 range 10 .. 31; + Cycles at 0 range 0 .. 9; + Val at 0 range 0 .. 31; + end record; + + type REG_HSIZE_Reg (As_Val : Boolean := False) is record + case As_Val is + when False => + RSVD : UInt22 := 0; + Cycles : UInt10 := 16#1E0#; + when True => + Val : UInt32; + end case; + end record + with Unchecked_Union, Size => 32; + + for REG_HSIZE_Reg use record + RSVD at 0 range 10 .. 31; + Cycles at 0 range 0 .. 9; + Val at 0 range 0 .. 31; + end record; + + type REG_HOFFSET_Reg (As_Val : Boolean := False) is record + case As_Val is + when False => + RSVD : UInt22 := 0; + Cycles : UInt10 := 16#2B#; + when True => + Val : UInt32; + end case; + end record + with Unchecked_Union, Size => 32; + + for REG_HOFFSET_Reg use record + RSVD at 0 range 10 .. 31; + Cycles at 0 range 0 .. 9; + Val at 0 range 0 .. 31; + end record; + + type REG_HCYCLE_Reg (As_Val : Boolean := False) is record + case As_Val is + when False => + RSVD : UInt22 := 0; + Cycles : UInt10 := 16#224#; + when True => + Val : UInt32; + end case; + end record + with Unchecked_Union, Size => 32; + + for REG_HCYCLE_Reg use record + RSVD at 0 range 10 .. 31; + Cycles at 0 range 0 .. 9; + Val at 0 range 0 .. 31; + end record; + + type GPIO_Direction is + (Input, Output) + with Size => 1; + + for GPIO_Direction use + (Input => 0, + Output => 1); + + type REG_GPIO_DIR_Reg (As_Val : Boolean := False) is record + case As_Val is + when False => + RSVD : UInt24 := 0; + GPIO0_Dir : GPIO_Direction := Input; + GPIO1_Dir : GPIO_Direction := Input; + GPIO2_Dir : GPIO_Direction := Input; + GPIO3_Dir : GPIO_Direction := Input; + GPIO4_Dir : GPIO_Direction := Input; + GPIO5_Dir : GPIO_Direction := Input; + GPIO6_Dir : GPIO_Direction := Input; + GPIO7_Dir : GPIO_Direction := Output; + when True => + Val : UInt32; + end case; + end record + with Unchecked_Union, Size => 32; + + for REG_GPIO_DIR_Reg use record + RSVD at 0 range 8 .. 31; + GPIO0_Dir at 0 range 0 .. 0; + GPIO1_Dir at 0 range 1 .. 1; + GPIO2_Dir at 0 range 2 .. 2; + GPIO3_Dir at 0 range 3 .. 3; + GPIO4_Dir at 0 range 4 .. 4; + GPIO5_Dir at 0 range 5 .. 5; + GPIO6_Dir at 0 range 6 .. 6; + GPIO7_Dir at 0 range 7 .. 7; + Val at 0 range 0 .. 31; + end record; + + type REG_GPIO_Reg (As_Val : Boolean := False) is record + case As_Val is + when False => + RSVD : UInt24 := 0; + GPIO0 : Boolean := False; + GPIO1 : Boolean := False; + GPIO2 : Boolean := False; + GPIO3 : Boolean := False; + GPIO4 : Boolean := False; + GPIO5 : Boolean := False; + GPIO6 : Boolean := False; + GPIO7 : Boolean := False; + when True => + Val : UInt32; + end case; + end record + with Unchecked_Union, Size => 32; + + for REG_GPIO_Reg use record + RSVD at 0 range 8 .. 31; + GPIO0 at 0 range 0 .. 0; + GPIO1 at 0 range 1 .. 1; + GPIO2 at 0 range 2 .. 2; + GPIO3 at 0 range 3 .. 3; + GPIO4 at 0 range 4 .. 4; + GPIO5 at 0 range 5 .. 5; + GPIO6 at 0 range 6 .. 6; + GPIO7 at 0 range 7 .. 7; + Val at 0 range 0 .. 31; + end record; + + type REG_INT_MASK_Reg (As_Val : Boolean := False) is record + case As_Val is + when False => + RSVD : UInt24 := 0; + Mask : Interrupts := (others => True); + when True => + Val : UInt32; + end case; + end record + with Unchecked_Union, Size => 32; + + for REG_INT_MASK_Reg use record + RSVD at 0 range 8 .. 31; + Mask at 0 range 0 .. 7; + Val at 0 range 0 .. 31; + end record; + + type REG_INT_EN_Reg (As_Val : Boolean := False) is record + case As_Val is + when False => + RSVD : UInt31 := 0; + Enable : Boolean := False; + when True => + Val : UInt32; + end case; + end record + with Unchecked_Union, Size => 32; + + for REG_INT_EN_Reg use record + RSVD at 0 range 1 .. 31; + Enable at 0 range 0 .. 0; + Val at 0 range 0 .. 31; + end record; + + type REG_INT_FLAGS_Reg (As_Val : Boolean := False) is record + case As_Val is + when False => + RSVD : UInt24 := 0; + Mask : Interrupts := (others => False); + when True => + Val : UInt32; + end case; + end record + with Unchecked_Union, Size => 32; + + for REG_INT_FLAGS_Reg use record + RSVD at 0 range 8 .. 31; + Mask at 0 range 0 .. 7; + Val at 0 range 0 .. 31; + end record; + + type Swap_Type is + (Immediate, After_Scan_Out) + with Size => 2; + + for Swap_Type use + (Immediate => 1, + After_Scan_Out => 2); + + type REG_DLSWAP_Reg (As_Val : Boolean := False) is record + case As_Val is + when False => + RSVD : UInt30 := 0; + Swap : Swap_Type := After_Scan_Out; + when True => + Val : UInt32; + end case; + end record + with Unchecked_Union, Size => 32; + + for REG_DLSWAP_Reg use record + RSVD at 0 range 2 .. 31; + Swap at 0 range 0 .. 1; + Val at 0 range 0 .. 31; + end record; + +end FT801.Registers; diff --git a/components/src/screen/FT801/ft801.adb b/components/src/screen/FT801/ft801.adb new file mode 100644 index 000000000..d85d9633a --- /dev/null +++ b/components/src/screen/FT801/ft801.adb @@ -0,0 +1,489 @@ +with Ada.Real_Time; use Ada.Real_Time; + +with FT801.Registers; use FT801.Registers; +with FT801.Display_List; +with FT801.Coproc; + +package body FT801 is + + procedure Wait (Period : Time_Span) + is + begin + delay until (Period + Clock); + end Wait; + + procedure Host_Memory_Write (This : FT801_Device; + Address : UInt22; + Payload : UInt8_Array) + is + Status : SPI_Status; + Packet : constant UInt8_Array := Create_Header (Address => Address, + Direction => Write) & Payload; + begin + + This.Port.Transmit (Data => SPI_Data_8b (Packet), + Status => Status); + if Status /= Ok then + raise Program_Error; + end if; + end Host_Memory_Write; + + procedure Host_Memory_Read (This : FT801_Device; + Address : UInt22; + Payload : out UInt8_Array) + is + Status : SPI_Status; + Tx_Header : constant UInt8_Array := Create_Header (Address => Address, + Direction => Read) & 0; + Tx_Payload : constant UInt8_Array (Payload'Range) := (others => 0); + Tx_Packet : constant UInt8_Array := Tx_Header & Tx_Payload; + Rx_Packet : UInt8_Array (Tx_Packet'Range); + begin + This.Port.Transfer (Tx_Data => SPI_Data_8b (Tx_Packet), + Rx_Data => SPI_Data_8b (Rx_Packet), + Status => Status); + + if Status /= Ok then + raise Program_Error; + end if; + + Payload := Rx_Packet (Tx_Header'First + Tx_Header'Length .. Rx_Packet'Last); + end Host_Memory_Read; + + function Create_Header (Address : UInt22; + Direction : Read_Or_Write) return Header + is + Cast_Address : UInt24 := UInt24 (Address); + Mapped_Address : UInt8_Array (1 .. 3) + with Address => Cast_Address'Address; + Ret : Header; + begin + Ret (1) := 2#0011_1111# and Mapped_Address (3); + case Direction is + when Read => + null; + when Write => + Ret (1) := 2#1000_0000# or Ret (1); + end case; + + Ret (2) := Mapped_Address (2); + Ret (3) := Mapped_Address (1); + + return Ret; + end Create_Header; + + procedure Send_Host_Command (This : in out FT801_Device; + Cmd : Command_Table) + is + Arr : constant SPI_Data_8b := (Command_Table'Enum_Rep (Cmd), 0, 0); + Status : SPI_Status; + begin + This.Port.Transmit (Data => Arr, + Status => Status); + if Status /= Ok then + raise Program_Error; + end if; + Wait (Period => Milliseconds (20)); + end Send_Host_Command; + + + procedure Initialize (This : in out FT801_Device; + Settings : Display_Settings) + is + GPIO_Dir_Reg : REG_GPIO_DIR_Reg; + GPIO_Reg : REG_GPIO_Reg; + Chipid : UInt32; + begin + This.Settings := Settings; + + This.Fifo_Ptr := 0; + + -- set PD high + -- Set (This => This.PD.all); + + -- bootup graphics controller + Reset (This => This); + + Read_Register (This => This, + Reg => REG_ID, + Val => Chipid); + + if Chipid /= 16#7C# then + raise Program_Error; + end if; + + -- Configure display registers + Write_Register (This => This, + Reg => REG_VSYNC0, + Val => REG_VSYNC0_Reg'(Lines => This.Settings.Vsync0, + others => <>).Val); + Write_Register (This => This, + Reg => REG_VSYNC1, + Val => REG_VSYNC1_Reg'(Lines => This.Settings.Vsync1, + others => <>).Val); + Write_Register (This => This, + Reg => REG_VOFFSET, + Val => REG_VOFFSET_Reg'(Lines => This.Settings.Voffset, + others => <>).Val); + Write_Register (This => This, + Reg => REG_VCYCLE, + Val => REG_VCYCLE_Reg'(Lines => This.Settings.VCycle, + others => <>).Val); + Write_Register (This => This, + Reg => REG_HSYNC0, + Val => REG_HSYNC0_Reg'(Cycles => This.Settings.Hsync0, + others => <>).Val); + Write_Register (This => This, + Reg => REG_HSYNC1, + Val => REG_HSYNC1_Reg'(Cycles => This.Settings.Hsync1, + others => <>).Val); + + Write_Register (This => This, + Reg => REG_HOFFSET, + Val => REG_HOFFSET_Reg'(Cycles => This.Settings.Hoffset, + others => <>).Val); + Write_Register (This => This, + Reg => REG_HCYCLE, + Val => REG_HCYCLE_Reg'(Cycles => This.Settings.HCycle, + others => <>).Val); + Write_Register (This => This, + Reg => REG_HSIZE, + Val => REG_HSIZE_Reg'(Cycles => This.Settings.Width, + others => <>).Val); + Write_Register (This => This, + Reg => REG_VSIZE, + Val => REG_VSIZE_Reg'(Lines => This.Settings.Height, + others => <>).Val); + Write_Register (This => This, + Reg => REG_PCLK_POL, + Val => REG_PCLK_POL_Reg'(Falling_Edge => This.Settings.Polarity, + others => <>).Val); + Write_Register (This => This, + Reg => REG_SWIZZLE, + Val => REG_SWIZZLE_Reg'(Pin_Cfg => This.Settings.Swizzle, + others => <>).Val); + Write_Register (This => This, + Reg => REG_CSPREAD, + Val => REG_CSPREAD_Reg'(Early => True, + others => <>).Val); + + Write_Register (This => This, + Reg => REG_PCLK, + Val => REG_PCLK_Reg'(Div => This.Settings.PClk, + others => <>).Val); + + if This.Settings.Ext_Clock then + Send_Host_Command (This => This, + Cmd => CLKEXT); + else + Send_Host_Command (This => This, + Cmd => CLKINT); + end if; + + Read_Register (This => This, + Reg => REG_GPIO_DIR, + Val => GPIO_Dir_Reg.Val); + + GPIO_Dir_Reg.GPIO7_Dir := Output; + + Write_Register (This => This, + Reg => REG_GPIO_DIR, + Val => GPIO_Dir_Reg.Val); + + Read_Register (This => This, + Reg => REG_GPIO, + Val => GPIO_Reg.Val); + + GPIO_Reg.GPIO7 := True; + + Write_Register (This => This, + Reg => REG_GPIO, + Val => GPIO_Reg.Val); + + -- Set SPI Freq back up to 30MHz + + end Initialize; + + procedure Cycle_PD (This : in out FT801_Device) + is + begin + Set (This => This.PD.all); + Wait (Period => Milliseconds (20)); + Clear (This => This.PD.all); + Wait (Period => Milliseconds (20)); + Set (This => This.PD.all); + Wait (Period => Milliseconds (20)); + end Cycle_PD; + + procedure Internal_Clock (This : in out FT801_Device) + is + Bootup : constant UInt8_Array := (0, 0, 0, 2, + 7, 0, 0, 38, + 0, 0, 0, 0); + Dummy_Read : UInt8_Array (1 .. 1); + pragma Unreferenced (Dummy_Read); + begin + -- Send_Host_Command (This => This, + -- Cmd => ACTIVE); + -- Send ACTIVE, Dummy read from Address 0 generates ACTIVE command + Host_Memory_Read (This => This, + Address => 0, + Payload => Dummy_Read); + + Wait (Period => Milliseconds (20)); + + Host_Memory_Write (This => This, + Address => RAM_DL_Address, + Payload => Bootup); + Write_Register (This => This, + Reg => REG_DLSWAP, + Val => REG_DLSWAP_Reg'(others => <>).Val); + This.Fifo_Ptr := 0; + + end Internal_Clock; + + procedure Reset (This : in out FT801_Device) + is + begin + Cycle_PD (This => This); + Internal_Clock (This => This); + end Reset; + + + procedure Display_On (This : in out FT801_Device) + is + Reg : REG_GPIO_Reg; + begin + Read_Register (This => This, + Reg => REG_GPIO, + Val => Reg.Val); + Reg.GPIO7 := True; + + Write_Register (This => This, + Reg => REG_GPIO, + Val => Reg.Val); + end Display_On; + + procedure Display_Off (This : in out FT801_Device) + is + Reg : REG_GPIO_Reg; + begin + Read_Register (This => This, + Reg => REG_GPIO, + Val => Reg.Val); + Reg.GPIO7 := False; + + Write_Register (This => This, + Reg => REG_GPIO, + Val => Reg.Val); + end Display_Off; + + procedure Enable_Interrupts (This : FT801_Device; + Mask : Interrupts) + is + + begin + Write_Register (This => This, + Reg => REG_INT_EN, + Val => REG_INT_EN_Reg'(Enable => True, + others => <>).Val); + Write_Register (This => This, + Reg => REG_INT_MASK, + Val => REG_INT_MASK_Reg'(Mask => Mask, + others => <>).Val); + end Enable_Interrupts; + + procedure Disable_Interrupts (This : FT801_Device) + is + begin + Write_Register (This => This, + Reg => REG_INT_EN, + Val => REG_INT_EN_Reg'(Enable => False, + others => <>).Val); + end Disable_Interrupts; + + function Read_Interrupts (This : FT801_Device) return Interrupts + is + Reg : REG_INT_FLAGS_Reg; + begin + Read_Register (This => This, + Reg => REG_INT_FLAGS, + Val => Reg.Val); + return Reg.Mask; + end Read_Interrupts; + + procedure Draw_Bitmap (This : in out FT801_Device; + Format : Graphics_Bitmap_Format; + Width : UInt9; + Height : UInt9; + X : UInt9; + Y : UInt9; + Img : UInt8_Array) + is + begin + Fill_G_Ram (This => This, + Start => 0, + Buffer => Img); + + Publish_G_Ram_Bitmap (This => This, + Width => Width, + Height => Height, + X => X, + Y => Y, + Format => Format); + + end Draw_Bitmap; + + procedure Fill_G_Ram (This : in out FT801_Device; + Start : UInt22; + Buffer : UInt8_Array) + is + begin + Host_Memory_Write (This => This, + Address => RAM_G_Address + Start, + Payload => Buffer); + end Fill_G_Ram; + + + procedure Publish_G_Ram_Bitmap (This : in out FT801_Device; + Width : UInt9; + Height : UInt9; + X : UInt9; + Y : UInt9; + Format : Graphics_Bitmap_Format) + is + + begin + Coproc.Send_Coproc_Cmds (This => This, + Cmds => (Coproc.CMD_DLSTART, + Display_List.Clear'(Color => True, + Stencil => True, + Tag => True, + others => <>).Val, + Display_List.Bitmap_Source'(Addr => RAM_G_Address, + others => <>).Val, + Display_List.Bitmap_Layout'(Format => Format, + Linestride => UInt10 (Width * 2), + Height => Height, + others => <>).Val, + Display_List.Bitmap_Size'(Filter => Display_List.NEAREST, + Wrapx => Display_List.BORDER, + WrapY => Display_List.BORDER, + Width => Width, + Height => Height, + others => <>).Val, + Display_List.Cmd_Begin'(Prim => Display_List.BITMAPS, + others => <>).Val, + Display_List.ColorRGB'(Red => 255, + Blue => 255, + Green => 255, + others => <>).Val, + Display_List.Vertex2ii'(X => X, + Y => Y, + Handle => 0, + Cell => 0, + others => <>).Val, + Display_List.Cmd_End'(others => <>).Val, + Display_List.Display'(others => <>).Val, + Coproc.CMD_DLSWAP)); + + end Publish_G_Ram_Bitmap; + + procedure Clear_Screen (This : in out FT801_Device) + is + begin + Coproc.Send_Coproc_Cmds (This => This, + Cmds => (1 => Display_List.Clear'(Color => True, + Stencil => True, + Tag => True, + others => <>).Val)); + + end Clear_Screen; + + procedure Wait_For_Coproc_Sync (This : FT801_Device) + is + Read : UInt32 := 0; + Write : UInt32 := 1; + begin + while Read /= Write loop + Read_Register (This => This, + Reg => REG_CMD_READ, + Val => Read); + Read_Register (This => This, + Reg => REG_CMD_WRITE, + Val => Write); + end loop; + + end Wait_For_Coproc_Sync; + + + procedure Draw_Logo (This : in out FT801_Device) + is + begin + Coproc.Send_Coproc_Cmds (This => This, + Cmds => (Coproc.CMD_DLSTART, + Display_List.Clear'(Color => True, + Stencil => True, + Tag => True, + others => <>).Val, + Display_List.Cmd_Begin'(Prim => Display_List.BITMAPS, + others => <>).Val, + Display_List.Vertex2ii'(X => 220, + Y => 110, + Handle => 31, + Cell => Character'Pos ('F'), + others => <>).Val, + Display_List.Vertex2ii'(X => 244, + Y => 110, + Handle => 31, + Cell => Character'Pos ('T'), + others => <>).Val, + Display_List.Vertex2ii'(X => 270, + Y => 110, + Handle => 31, + Cell => Character'Pos ('D'), + others => <>).Val, + Display_List.Vertex2ii'(X => 299, + Y => 110, + Handle => 31, + Cell => Character'Pos ('I'), + others => <>).Val, + Display_List.Cmd_End'(others => <>).Val, + Display_List.ColorRGB'(Red => 160, + Blue => 22, + Green => 22, + others => <>).Val, + Display_List.Point_Size'(Size => 320, + others => <>).Val, + Display_List.Cmd_Begin'(Prim => Display_List.POINTS, + others => <>).Val, + Display_List.Vertex2ii'(X => 192, + Y => 133, + Handle => 0, + Cell => 0, + others => <>).Val, + Display_List.Cmd_End'(others => <>).Val, + Display_List.Display'(others => <>).Val, + Coproc.CMD_DLSWAP)); + end Draw_Logo; + + procedure Play_Logo (This : in out FT801_Device) + is + Cmd_Read, Cmd_Write : UInt32 := 1; + begin + Coproc.Send_Coproc_Cmds (This => This, + Cmds => (1 => CMD_LOGO)); + Wait (Period => Milliseconds (2600)); + + while Cmd_Read /= 0 and Cmd_Write /= 0 loop + Read_Register (This => This, + Reg => REG_CMD_READ, + Val => Cmd_Read); + Read_Register (This => This, + Reg => REG_CMD_WRITE, + Val => Cmd_Write); + end loop; + end Play_Logo; + + +end FT801; diff --git a/components/src/screen/FT801/ft801.ads b/components/src/screen/FT801/ft801.ads new file mode 100644 index 000000000..4e20ff0ab --- /dev/null +++ b/components/src/screen/FT801/ft801.ads @@ -0,0 +1,349 @@ +with HAL; use HAL; +with HAL.SPI; use HAL.SPI; +with HAL.GPIO; use HAL.GPIO; + +private with Ada.Real_Time; + +package FT801 is + + type Display_Settings is record + Width : UInt10; + Height : UInt10; + Swizzle : UInt4 := 0; + Polarity : Boolean := True; + PClk : UInt8 := 5; + HCycle : UInt10 := 548; + Hoffset : UInt10 := 43; + Hsync0 : UInt10 := 0; + Hsync1 : UInt10 := 41; + VCycle : UInt10 := 292; + Voffset : UInt10 := 12; + Vsync0 : UInt10 := 0; + Vsync1 : UInt10 := 10; + Ext_Clock : Boolean := True; + end record; + + WQVGA_480x272 : constant Display_Settings := + Display_Settings'(Width => 480, + Height => 272, + Swizzle => 0, + Polarity => True, + PClk => 5, + HCycle => 548, + Hoffset => 43, + Hsync0 => 0, + Hsync1 => 41, + VCycle => 292, + Voffset => 12, + Vsync0 => 0, + Vsync1 => 10, + Ext_Clock => True); + + QVGA_320x240 : constant Display_Settings := + Display_Settings'(Width => 320, + Height => 240, + Swizzle => 2, + Polarity => False, + PClk => 8, + HCycle => 408, + Hoffset => 70, + Hsync0 => 0, + Hsync1 => 10, + VCycle => 263, + Voffset => 13, + Vsync0 => 0, + Vsync1 => 2, + Ext_Clock => True); + + type FT801_Device (Port : not null Any_SPI_Port; + PD : not null Any_GPIO_Point) is private; + + procedure Initialize (This : in out FT801_Device; + Settings : Display_Settings); + + procedure Display_On (This : in out FT801_Device); + procedure Display_Off (This : in out FT801_Device); + + procedure Reset (This : in out FT801_Device); + + type Interrupts is record + Swap : Boolean; + Rsv : Boolean; + Tag : Boolean; + Sound : Boolean; + Playback : Boolean; + CmdEmpty : Boolean; + CmdFlag : Boolean; + ConvComplete : Boolean; + end record + with Size => 8; + + for Interrupts use record + Swap at 0 range 0 .. 0; + Rsv at 0 range 1 .. 1; + Tag at 0 range 2 .. 2; + Sound at 0 range 3 .. 3; + Playback at 0 range 4 .. 4; + CmdEmpty at 0 range 5 .. 5; + CmdFlag at 0 range 6 .. 6; + ConvComplete at 0 range 7 .. 7; + end record; + + + function Read_Interrupts (This : FT801_Device) return Interrupts; + + type Graphics_Bitmap_Format is + (ARGB1555, + L1, + L4, + L8, + RGB332, + ARGB2, + ARGB4, + RGB565, + PALETTED, + TEXT8x8, + TEXTVGA, + BARGRAPH) + with Size => 5; + + for Graphics_Bitmap_Format use + (ARGB1555 => 0, + L1 => 1, + L4 => 2, + L8 => 3, + RGB332 => 4, + ARGB2 => 5, + ARGB4 => 6, + RGB565 => 7, + PALETTED => 8, + TEXT8x8 => 9, + TEXTVGA => 10, + BARGRAPH => 11); + + type Screen_Coordinate is record + X, Y : Integer; + end record; + + procedure Draw_Bitmap (This : in out FT801_Device; + Format : Graphics_Bitmap_Format; + Width : UInt9; + Height : UInt9; + X : UInt9; + Y : UInt9; + Img : UInt8_Array); + +-- procedure Draw_Rectangle (This : FT801_Device; +-- Lower_Left : Screen_Coordinate; +-- Upper_Right : Screen_Coordinate; +-- Fill : Boolean); +-- +-- procedure Draw_Button (This : FT801_Device; +-- Lower_Left : Screen_Coordinate; +-- Upper_Right : Screen_Coordinate; +-- Text : String); + + procedure Draw_Logo (This : in out FT801_Device); + + procedure Play_Logo (This : in out FT801_Device); + + procedure Clear_Screen (This : in out FT801_Device); + + procedure Fill_G_Ram (This : in out FT801_Device; + Start : UInt22; + Buffer : UInt8_Array); + + procedure Publish_G_Ram_Bitmap (This : in out FT801_Device; + Width : UInt9; + Height : UInt9; + X : UInt9; + Y : UInt9; + Format : Graphics_Bitmap_Format); + + procedure Wait_For_Coproc_Sync (This : FT801_Device); + + type Dl_Pointer_Type is range 0 .. 8191; + type Fifo_Pointer_Type is mod 4096 + with Size => 12; + + RAM_G_Address : constant := 16#0000_0000#; + + ROM_CHIPID_Address : constant := 16#0C_0000#; + + ROM_FONT_Address : constant := 16#B0_B23C#; + + ROM_FONT_ADDR_Address : constant := 16#0F_FFFC#; + + RAM_DL_Address : constant := 16#10_0000#; + + RAM_PAL_Address : constant := 16#10_2000#; + + REG_Address : constant := 16#10_2400#; + + RAM_CMD_Address : constant := 16#10_8000#; + + RAM_SCREENSHOT_Address : constant := 16#1C_2000#; + +private + + type FT801_Device (Port : not null Any_SPI_Port; + PD : not null Any_GPIO_Point) + is record + Settings : Display_Settings; + Dl_Ptr : Dl_Pointer_Type := 0; + Fifo_Ptr : Fifo_Pointer_Type := 0; + end record; + + type Command_Table is + ( + ACTIVE, + -- Switch from Standby/Sleep modes to + -- active mode. Dummy read from address + -- 0 generates ACTIVE command. + STANDBY, + -- Put FT801 core to standby mode. Clock + -- gate off, PLL and Oscillator remain on + -- (default). + SLEEP, + -- Put FT801 core to sleep mode. Clock + -- gate off, PLL and Oscillator off. + CLKEXT, + -- Select PLL input from Crystal oscillator + -- or external input clock. + CLKINT, + -- Select PLL input from Internal relaxation + -- oscillator (default). + PWRDOWN, + -- Switch off 1.2V internal regulator. Clock, + -- PLL and Oscillator off. + CLK36M, + -- Switch PLL output clock to 36MHz. + CLK48M, + -- Switch PLL output clock to 48MHz + -- (default). + -- Send reset pulse to FT801 core. All + -- registers and state machines will be + -- reset. + CORERST) with Size => 8; + + for Command_Table use + (ACTIVE => 16#00#, + STANDBY => 16#41#, + SLEEP => 16#42#, + CLKEXT => 16#44#, + CLKINT => 16#48#, + PWRDOWN => 16#50#, + CLK36M => 16#61#, + CLK48M => 16#62#, + + CORERST => 16#68#); + + procedure Send_Host_Command (This : in out FT801_Device; + Cmd : Command_Table); + + procedure Host_Memory_Write (This : FT801_Device; + Address : UInt22; + Payload : UInt8_Array) + with Pre => Payload'Length > 0; + + procedure Host_Memory_Read (This : FT801_Device; + Address : UInt22; + Payload : out UInt8_Array) + with Pre => Payload'Length > 0; + + subtype Header is UInt8_Array (1 .. 3); + + type Read_Or_Write is (Read, Write); + + function Create_Header (Address : UInt22; + Direction : Read_Or_Write) return Header; + + + type Read_Write is + (READ, WRITE); + + for Read_Write use + (READ => 0, + WRITE => 1); + + type Bitmap_Header is record + Format : UInt8; + Width : UInt16; + Height : UInt16; + Stride : UInt16; + Offset : UInt32; + end record; + + + + -- Coprocessor related commands + CMD_APPEND : constant := 16#FFFF_FF1E#; + CMD_BGCOLOR : constant := 16#FFFF_FF09#; + CMD_BITMAP_TRANSFORM : constant := 16#FFFF_FF21#; + CMD_BUTTON : constant := 16#FFFF_FF0D#; + CMD_CALIBRATE : constant := 16#FFFF_FF15#; + CMD_CLOCK : constant := 16#FFFF_FF14#; + CMD_COLDSTART : constant := 16#FFFF_FF32#; + CMD_CRC : constant := 16#FFFF_FF03#; + CMD_DIAL : constant := 16#FFFF_FF2D#; + CMD_DLSTART : constant := 16#FFFF_FF00#; + CMD_EXECUTE : constant := 16#FFFF_FF07#; + CMD_FGCOLOR : constant := 16#FFFF_FF0A#; + CMD_GAUGE : constant := 16#FFFF_FF13#; + CMD_GETMATRIX : constant := 16#FFFF_FF33#; + CMD_GETPOINT : constant := 16#FFFF_FF08#; + CMD_GETPROPS : constant := 16#FFFF_FF25#; + CMD_GETPTR : constant := 16#FFFF_FF23#; + CMD_GRADCOLOR : constant := 16#FFFF_FF34#; + CMD_GRADIENT : constant := 16#FFFF_FF0B#; + CMD_HAMMERAUX : constant := 16#FFFF_FF04#; + CMD_IDCT : constant := 16#FFFF_FF06#; + CMD_INFLATE : constant := 16#FFFF_FF22#; + CMD_INTERRUPT : constant := 16#FFFF_FF02#; + CMD_KEYS : constant := 16#FFFF_FF0E#; + CMD_LOADIDENTITY : constant := 16#FFFF_FF26#; + CMD_LOADIMAGE : constant := 16#FFFF_FF24#; + CMD_LOGO : constant := 16#FFFF_FF31#; + CMD_MARCH : constant := 16#FFFF_FF05#; + CMD_MEMCPY : constant := 16#FFFF_FF1D#; + CMD_MEMCRC : constant := 16#FFFF_FF18#; + CMD_MEMSET : constant := 16#FFFF_FF1B#; + CMD_MEMWRITE : constant := 16#FFFF_FF1A#; + CMD_MEMZERO : constant := 16#FFFF_FF1C#; + CMD_NUMBER : constant := 16#FFFF_FF2E#; + CMD_PROGRESS : constant := 16#FFFF_FF0F#; + CMD_REGREAD : constant := 16#FFFF_FF19#; + CMD_ROTATE : constant := 16#FFFF_FF29#; + CMD_SCALE : constant := 16#FFFF_FF28#; + CMD_SCREENSAVER : constant := 16#FFFF_FF2F#; + CMD_SCROLLBAR : constant := 16#FFFF_FF11#; + CMD_SETFONT : constant := 16#FFFF_FF2B#; + CMD_SETMATRIX : constant := 16#FFFF_FF2A#; + CMD_SKETCH : constant := 16#FFFF_FF30#; + CMD_SLIDER : constant := 16#FFFF_FF10#; + CMD_SNAPSHOT : constant := 16#FFFF_FF1F#; + CMD_SPINNER : constant := 16#FFFF_FF16#; + CMD_STOP : constant := 16#FFFF_FF17#; + CMD_SWAP : constant := 16#FFFF_FF01#; + CMD_TEXT : constant := 16#FFFF_FF0C#; + CMD_TOGGLE : constant := 16#FFFF_FF12#; + CMD_TOUCH_TRANSFORM : constant := 16#FFFF_FF20#; + CMD_TRACK : constant := 16#FFFF_FF2C#; + CMD_TRANSLATE : constant := 16#FFFF_FF27#; + + procedure Wait (Period : Ada.Real_Time.Time_Span); + +-- procedure Set_Display_Enable (This : in out FT801_Device; +-- Enable : Boolean); + + + procedure Cycle_PD (This : in out FT801_Device); + procedure Internal_Clock (This : in out FT801_Device); + + procedure Enable_Interrupts (This : FT801_Device; + Mask : Interrupts); + procedure Disable_Interrupts (This : FT801_Device); + + + +end FT801; diff --git a/components/src/screen/ili9488/ili9488.adb b/components/src/screen/ili9488/ili9488.adb new file mode 100644 index 000000000..60995b9aa --- /dev/null +++ b/components/src/screen/ili9488/ili9488.adb @@ -0,0 +1,390 @@ +------------------------------------------------------------------------------ +-- -- +-- Copyright (C) 2020, AdaCore -- +-- -- +-- Redistribution and use in source and binary forms, with or without -- +-- modification, are permitted provided that the following conditions are -- +-- met: -- +-- 1. Redistributions of source code must retain the above copyright -- +-- notice, this list of conditions and the following disclaimer. -- +-- 2. Redistributions in binary form must reproduce the above copyright -- +-- notice, this list of conditions and the following disclaimer in -- +-- the documentation and/or other materials provided with the -- +-- distribution. -- +-- 3. Neither the name of STMicroelectronics nor the names of its -- +-- contributors may be used to endorse or promote products derived -- +-- from this software without specific prior written permission. -- +-- -- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- +-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- +-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -- +-- A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -- +-- HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -- +-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -- +-- LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -- +-- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -- +-- THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- +-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -- +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- +-- -- +------------------------------------------------------------------------------ + +with Ada.Unchecked_Conversion; + +with ILI9488_Regs; use ILI9488_Regs; + +package body ILI9488 is + + function As_UInt16 is new Ada.Unchecked_Conversion + (Source => Colors, Target => UInt16); + + ------------------- + -- Current_Width -- + ------------------- + + function Current_Width (This : ILI9488_Device) return Natural is + (This.Selected_Width); + + -------------------- + -- Current_Height -- + -------------------- + + function Current_Height (This : ILI9488_Device) return Natural is + (This.Selected_Height); + + ------------------------- + -- Current_Orientation -- + ------------------------- + + function Current_Orientation (This : ILI9488_Device) return Orientations is + (This.Selected_Orientation); + + ---------------- + -- Initialize -- + ---------------- + + procedure Initialize + (This : in out ILI9488_Device; + Mode : ILI9488_Mode) + is + begin + if This.Initialized then + return; + end if; + + This.Chip_Select_High; + + This.Init_LCD (Mode); + + This.Selected_Width := Device_Width; + This.Selected_Height := Device_Height; + This.Selected_Orientation := Portrait_2; + + This.Initialized := True; + end Initialize; + + --------------- + -- Set_Pixel -- + --------------- + + procedure Set_Pixel + (This : in out ILI9488_Device; + X : Width; + Y : Height; + Color : Colors) + is + Color_High_UInt8 : constant UInt8 := + UInt8 (Shift_Right (As_UInt16 (Color), 8)); + Color_Low_UInt8 : constant UInt8 := + UInt8 (As_UInt16 (Color) and 16#FF#); + begin + This.Set_Cursor_Position (X, Y, X, Y); + This.Send_Command (ILI9488_GRAM); + This.Send_Data (Color_High_UInt8); + This.Send_Data (Color_Low_UInt8); + end Set_Pixel; + + ---------- + -- Fill -- + ---------- + + procedure Fill (This : in out ILI9488_Device; Color : Colors) is + Color_High_UInt8 : constant UInt8 := + UInt8 (Shift_Right (As_UInt16 (Color), 8)); + Color_Low_UInt8 : constant UInt8 := + UInt8 (As_UInt16 (Color) and 16#FF#); + begin + This.Set_Cursor_Position (X1 => 0, + Y1 => 0, + X2 => This.Selected_Width - 1, + Y2 => This.Selected_Height - 1); + + This.Send_Command (ILI9488_GRAM); + for N in 1 .. (Device_Width * Device_Height) loop + This.Send_Data (Color_High_UInt8); + This.Send_Data (Color_Low_UInt8); + end loop; + end Fill; + + --------------------- + -- Set_Orientation -- + --------------------- + + procedure Set_Orientation (This : in out ILI9488_Device; + To : Orientations) + is + begin + This.Send_Command (ILI9488_MAC); + case To is + when Portrait_1 => This.Send_Data (16#58#); + when Portrait_2 => This.Send_Data (16#88#); + when Landscape_1 => This.Send_Data (16#28#); + when Landscape_2 => This.Send_Data (16#E8#); + end case; + + case To is + when Portrait_1 | Portrait_2 => + This.Selected_Width := Device_Width; + This.Selected_Height := Device_Height; + when Landscape_1 | Landscape_2 => + This.Selected_Width := Device_Height; + This.Selected_Height := Device_Width; + end case; + + This.Selected_Orientation := To; + end Set_Orientation; + + -------------------- + -- Enable_Display -- + -------------------- + + procedure Enable_Display (This : in out ILI9488_Device) is + begin + This.Send_Command (ILI9488_DISPLAY_ON); + end Enable_Display; + + --------------------- + -- Disable_Display -- + --------------------- + + procedure Disable_Display (This : in out ILI9488_Device) is + begin + This.Send_Command (ILI9488_DISPLAY_OFF); + end Disable_Display; + + ------------------------- + -- Set_Cursor_Position -- + ------------------------- + + procedure Set_Cursor_Position + (This : in out ILI9488_Device; + X1 : Width; + Y1 : Height; + X2 : Width; + Y2 : Height) + is + X1_High : constant UInt8 := UInt8 (Shift_Right (UInt16 (X1), 8)); + X1_Low : constant UInt8 := UInt8 (UInt16 (X1) and 16#FF#); + X2_High : constant UInt8 := UInt8 (Shift_Right (UInt16 (X2), 8)); + X2_Low : constant UInt8 := UInt8 (UInt16 (X2) and 16#FF#); + + Y1_High : constant UInt8 := UInt8 (Shift_Right (UInt16 (Y1), 8)); + Y1_Low : constant UInt8 := UInt8 (UInt16 (Y1) and 16#FF#); + Y2_High : constant UInt8 := UInt8 (Shift_Right (UInt16 (Y2), 8)); + Y2_Low : constant UInt8 := UInt8 (UInt16 (Y2) and 16#FF#); + begin + This.Send_Command (ILI9488_COLUMN_ADDR); + This.Send_Data (X1_High); + This.Send_Data (X1_Low); + This.Send_Data (X2_High); + This.Send_Data (X2_Low); + + This.Send_Command (ILI9488_PAGE_ADDR); + This.Send_Data (Y1_High); + This.Send_Data (Y1_Low); + This.Send_Data (Y2_High); + This.Send_Data (Y2_Low); + end Set_Cursor_Position; + + ---------------------- + -- Chip_Select_High -- + ---------------------- + + procedure Chip_Select_High (This : in out ILI9488_Device) is + begin + This.Chip_Select.Set; + end Chip_Select_High; + + --------------------- + -- Chip_Select_Low -- + --------------------- + + procedure Chip_Select_Low (This : in out ILI9488_Device) is + begin + This.Chip_Select.Clear; + end Chip_Select_Low; + + --------------- + -- Send_Data -- + --------------- + + procedure Send_Data (This : in out ILI9488_Device; Data : UInt8) is + Status : SPI_Status; + begin + This.WRX.Set; + This.Chip_Select_Low; + This.Port.Transmit (SPI_Data_8b'(1 => Data), Status); + if Status /= Ok then + raise Program_Error; + end if; + This.Chip_Select_High; + end Send_Data; + + ------------------ + -- Send_Command -- + ------------------ + + procedure Send_Command (This : in out ILI9488_Device; Cmd : UInt8) is + Status : SPI_Status; + begin + This.WRX.Clear; + This.Chip_Select_Low; + This.Port.Transmit (SPI_Data_8b'(1 => Cmd), Status); + if Status /= Ok then + raise Program_Error; + end if; + This.Chip_Select_High; + end Send_Command; + + -------------- + -- Init_LCD -- + -------------- + + procedure Init_LCD (This : in out ILI9488_Device; + Mode : ILI9488_Mode) is + begin + This.Reset.Set; + This.Send_Command (ILI9488_RESET); + This.Time.Delay_Milliseconds (5); + + This.Send_Command (ILI9488_POWERA); + This.Send_Data (16#39#); + This.Send_Data (16#2C#); + This.Send_Data (16#00#); + This.Send_Data (16#34#); + This.Send_Data (16#02#); + This.Send_Command (ILI9488_POWERB); + This.Send_Data (16#00#); + This.Send_Data (16#C1#); + This.Send_Data (16#30#); + This.Send_Command (ILI9488_DTCA); + This.Send_Data (16#85#); + This.Send_Data (16#00#); + This.Send_Data (16#78#); + This.Send_Command (ILI9488_DTCB); + This.Send_Data (16#00#); + This.Send_Data (16#00#); + This.Send_Command (ILI9488_POWER_SEQ); + This.Send_Data (16#64#); + This.Send_Data (16#03#); + This.Send_Data (16#12#); + This.Send_Data (16#81#); + This.Send_Command (ILI9488_PRC); + This.Send_Data (16#20#); + This.Send_Command (ILI9488_POWER1); + This.Send_Data (16#23#); + This.Send_Command (ILI9488_POWER2); + This.Send_Data (16#10#); + This.Send_Command (ILI9488_VCOM1); + This.Send_Data (16#3E#); + This.Send_Data (16#28#); + This.Send_Command (ILI9488_VCOM2); + This.Send_Data (16#86#); + This.Send_Command (ILI9488_MAC); + This.Send_Data (16#C8#); + This.Send_Command (ILI9488_FRC); + This.Send_Data (16#00#); + This.Send_Data (16#18#); + case Mode is + when RGB_Mode => + This.Send_Command (ILI9488_RGB_INTERFACE); + This.Send_Data (16#C2#); + This.Send_Command (ILI9488_INTERFACE); + This.Send_Data (16#01#); + This.Send_Data (16#00#); + This.Send_Data (16#06#); + This.Send_Command (ILI9488_DFC); + This.Send_Data (16#0A#); + This.Send_Data (16#A7#); + This.Send_Data (16#27#); + This.Send_Data (16#04#); + when SPI_Mode => + This.Send_Command (ILI9488_PIXEL_FORMAT); + This.Send_Data (16#55#); + This.Send_Command (ILI9488_DFC); + This.Send_Data (16#08#); + This.Send_Data (16#82#); + This.Send_Data (16#27#); + end case; + This.Send_Command (ILI9488_3GAMMA_EN); + This.Send_Data (16#00#); + This.Send_Command (ILI9488_COLUMN_ADDR); + This.Send_Data (16#00#); + This.Send_Data (16#00#); + This.Send_Data (16#00#); + This.Send_Data (16#EF#); + This.Send_Command (ILI9488_PAGE_ADDR); + This.Send_Data (16#00#); + This.Send_Data (16#00#); + This.Send_Data (16#01#); + This.Send_Data (16#3F#); + This.Send_Command (ILI9488_GAMMA); + This.Send_Data (16#01#); + This.Send_Command (ILI9488_PGAMMA); + This.Send_Data (16#0F#); + This.Send_Data (16#31#); + This.Send_Data (16#2B#); + This.Send_Data (16#0C#); + This.Send_Data (16#0E#); + This.Send_Data (16#08#); + This.Send_Data (16#4E#); + This.Send_Data (16#F1#); + This.Send_Data (16#37#); + This.Send_Data (16#07#); + This.Send_Data (16#10#); + This.Send_Data (16#03#); + This.Send_Data (16#0E#); + This.Send_Data (16#09#); + This.Send_Data (16#00#); + This.Send_Command (ILI9488_NGAMMA); + This.Send_Data (16#00#); + This.Send_Data (16#0E#); + This.Send_Data (16#14#); + This.Send_Data (16#03#); + This.Send_Data (16#11#); + This.Send_Data (16#07#); + This.Send_Data (16#31#); + This.Send_Data (16#C1#); + This.Send_Data (16#48#); + This.Send_Data (16#08#); + This.Send_Data (16#0F#); + This.Send_Data (16#0C#); + This.Send_Data (16#31#); + This.Send_Data (16#36#); + This.Send_Data (16#0F#); + This.Send_Command (ILI9488_SLEEP_OUT); + + case Mode is + when RGB_Mode => + This.Time.Delay_Milliseconds (150); + when SPI_Mode => + This.Time.Delay_Milliseconds (20); + end case; + -- document ILI9488_DS_V1.02, section 11.2, pg 205 says we need + -- either 120ms or 5ms, depending on the mode, but seems incorrect. + + This.Send_Command (ILI9488_DISPLAY_ON); + This.Send_Command (ILI9488_GRAM); + end Init_LCD; + +end ILI9488; diff --git a/components/src/screen/ili9488/ili9488.ads b/components/src/screen/ili9488/ili9488.ads new file mode 100644 index 000000000..a7a515f51 --- /dev/null +++ b/components/src/screen/ili9488/ili9488.ads @@ -0,0 +1,184 @@ +------------------------------------------------------------------------------ +-- -- +-- Copyright (C) 2015, AdaCore -- +-- -- +-- Redistribution and use in source and binary forms, with or without -- +-- modification, are permitted provided that the following conditions are -- +-- met: -- +-- 1. Redistributions of source code must retain the above copyright -- +-- notice, this list of conditions and the following disclaimer. -- +-- 2. Redistributions in binary form must reproduce the above copyright -- +-- notice, this list of conditions and the following disclaimer in -- +-- the documentation and/or other materials provided with the -- +-- distribution. -- +-- 3. Neither the name of STMicroelectronics nor the names of its -- +-- contributors may be used to endorse or promote products derived -- +-- from this software without specific prior written permission. -- +-- -- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- +-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- +-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -- +-- A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -- +-- HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -- +-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -- +-- LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -- +-- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -- +-- THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- +-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -- +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- +-- -- +-- This file is based on: -- +-- -- +-- @file ili9341.h -- +-- @author MCD Application Team -- +-- @version V1.0.2 -- +-- @date 02-December-2014 -- +-- @brief This file includes the LCD driver for ILI9341 LCD. -- +-- -- +-- COPYRIGHT(c) 2014 STMicroelectronics -- +------------------------------------------------------------------------------ + +-- This file provides the component driver for the ILI9341 LCD on the +-- STM32F429 Discovery boards, among others. Support does not include the +-- TFT hardware. + +-- See the "a-Si TFT LCD Single Chip Driver" specification by ILITEK, file +-- name "ILI9341_DS_V1.02" for details. + +with HAL; use HAL; +with HAL.SPI; use HAL.SPI; +with HAL.GPIO; use HAL.GPIO; +with HAL.Time; + +package ILI9341 is + + type ILI9341_Device + (Port : not null access SPI_Port'Class; + Chip_Select : not null Any_GPIO_Point; + WRX : not null Any_GPIO_Point; + Reset : not null Any_GPIO_Point; + Time : not null HAL.Time.Any_Delays) + is tagged limited private; + + type ILI9341_Mode is + (RGB_Mode, + SPI_Mode); + + procedure Initialize + (This : in out ILI9341_Device; + Mode : ILI9341_Mode); + -- Initializes the device. Afterward, the device is also enabled so there + -- is no immediate need to call Enable_Display. + + procedure Send_Command (This : in out ILI9341_Device; Cmd : UInt8); + + procedure Send_Data (This : in out ILI9341_Device; Data : UInt8); + + Device_Width : constant := 240; + Device_Height : constant := 320; + + -- The operational upper bounds for width and height depend on the selected + -- orientation so these subtypes cannot specify an upper bound using the + -- device max height/width. In particular, if the orientation is rotated, + -- the width becomes the height, and vice versa. Hence these are mainly for + -- readability. + subtype Width is Natural; + subtype Height is Natural; + + type Colors is + (Black, + Blue, + Light_Blue, + Green, + Cyan, + Gray, + Magenta, + Light_Green, + Brown, + Red, + Orange, + Yellow, + White); + + for Colors use + (Black => 16#0000#, + Blue => 16#001F#, + Light_Blue => 16#051D#, + Green => 16#07E0#, + Cyan => 16#07FF#, + Gray => 16#7BEF#, + Magenta => 16#A254#, + Light_Green => 16#B723#, + Brown => 16#BBCA#, + Red => 16#F800#, + Orange => 16#FBE4#, + Yellow => 16#FFE0#, + White => 16#FFFF#); + + procedure Set_Pixel + (This : in out ILI9341_Device; + X : Width; + Y : Height; + Color : Colors) with Inline; + + procedure Fill (This : in out ILI9341_Device; Color : Colors); + + -- Descriptions assume the USB power/debug connector at the top + type Orientations is + (Portrait_1, -- origin at lower right, text going right to left + Portrait_2, -- origin at upper left, text going left to right + Landscape_1, -- origin at lower left, text going up + Landscape_2); -- origin at upper right, text going down + + procedure Set_Orientation + (This : in out ILI9341_Device; + To : Orientations); + + procedure Enable_Display (This : in out ILI9341_Device); + + procedure Disable_Display (This : in out ILI9341_Device); + + -- These values reflect the currently selected orientation + + function Current_Width (This : ILI9341_Device) return Natural + with Inline; + + function Current_Height (This : ILI9341_Device) return Natural + with Inline; + + function Current_Orientation (This : ILI9341_Device) return Orientations; + +private + + type ILI9341_Device + (Port : not null access SPI_Port'Class; + Chip_Select : not null Any_GPIO_Point; + WRX : not null Any_GPIO_Point; + Reset : not null Any_GPIO_Point; + Time : not null HAL.Time.Any_Delays) + is tagged limited record + Selected_Orientation : Orientations; + + -- The following objects' upper bounds vary with the selected + -- orientation. + Selected_Width : Natural; + Selected_Height : Natural; + + Initialized : Boolean := False; + end record; + + procedure Set_Cursor_Position + (This : in out ILI9341_Device; + X1 : Width; + Y1 : Height; + X2 : Width; + Y2 : Height) + with Inline; + + procedure Chip_Select_High (This : in out ILI9341_Device) with Inline; + procedure Chip_Select_Low (This : in out ILI9341_Device) with Inline; + + procedure Init_LCD (This : in out ILI9341_Device; + Mode : ILI9341_Mode); + +end ILI9341; diff --git a/components/src/screen/ili9488/ili9488_regs.ads b/components/src/screen/ili9488/ili9488_regs.ads new file mode 100644 index 000000000..c28524ae5 --- /dev/null +++ b/components/src/screen/ili9488/ili9488_regs.ads @@ -0,0 +1,65 @@ +------------------------------------------------------------------------------ +-- -- +-- Copyright (C) 2015-2016, AdaCore -- +-- -- +-- Redistribution and use in source and binary forms, with or without -- +-- modification, are permitted provided that the following conditions are -- +-- met: -- +-- 1. Redistributions of source code must retain the above copyright -- +-- notice, this list of conditions and the following disclaimer. -- +-- 2. Redistributions in binary form must reproduce the above copyright -- +-- notice, this list of conditions and the following disclaimer in -- +-- the documentation and/or other materials provided with the -- +-- distribution. -- +-- 3. Neither the name of the copyright holder nor the names of its -- +-- contributors may be used to endorse or promote products derived -- +-- from this software without specific prior written permission. -- +-- -- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- +-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- +-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -- +-- A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -- +-- HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -- +-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -- +-- LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -- +-- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -- +-- THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- +-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -- +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- +-- -- +------------------------------------------------------------------------------ + +package ILI9341_Regs is + + ILI9341_RESET : constant := 16#01#; + ILI9341_SLEEP_OUT : constant := 16#11#; + ILI9341_GAMMA : constant := 16#26#; + ILI9341_DISPLAY_OFF : constant := 16#28#; + ILI9341_DISPLAY_ON : constant := 16#29#; + ILI9341_COLUMN_ADDR : constant := 16#2A#; + ILI9341_PAGE_ADDR : constant := 16#2B#; + ILI9341_GRAM : constant := 16#2C#; + ILI9341_MAC : constant := 16#36#; + ILI9341_PIXEL_FORMAT : constant := 16#3A#; + ILI9341_WDB : constant := 16#51#; + ILI9341_WCD : constant := 16#53#; + ILI9341_RGB_INTERFACE : constant := 16#B0#; + ILI9341_FRC : constant := 16#B1#; + ILI9341_BPC : constant := 16#B5#; + ILI9341_DFC : constant := 16#B6#; + ILI9341_POWER1 : constant := 16#C0#; + ILI9341_POWER2 : constant := 16#C1#; + ILI9341_VCOM1 : constant := 16#C5#; + ILI9341_VCOM2 : constant := 16#C7#; + ILI9341_POWERA : constant := 16#CB#; + ILI9341_POWERB : constant := 16#CF#; + ILI9341_PGAMMA : constant := 16#E0#; + ILI9341_NGAMMA : constant := 16#E1#; + ILI9341_DTCA : constant := 16#E8#; + ILI9341_DTCB : constant := 16#EA#; + ILI9341_POWER_SEQ : constant := 16#ED#; + ILI9341_3GAMMA_EN : constant := 16#F2#; + ILI9341_INTERFACE : constant := 16#F6#; + ILI9341_PRC : constant := 16#F7#; + +end ILI9341_Regs; diff --git a/hal/src/hal-spi.ads b/hal/src/hal-spi.ads index 3769657de..dc58671c4 100644 --- a/hal/src/hal-spi.ads +++ b/hal/src/hal-spi.ads @@ -83,4 +83,14 @@ package HAL.SPI is with Pre'Class => Data_Size (This) = Data_Size_16b; + procedure Transfer + (This : in out SPI_Port; + Tx_Data : SPI_Data_8b; + Rx_Data : out SPI_Data_8b; + Status : out SPI_Status; + Timeout : Natural := 1000) is abstract + with + Pre'Class => Data_Size (This) = Data_Size_8b and + Tx_Data'Length = Rx_Data'Length; + end HAL.SPI; diff --git a/scripts/config/boards.py b/scripts/config/boards.py index d6434f828..8356f025f 100644 --- a/scripts/config/boards.py +++ b/scripts/config/boards.py @@ -12,6 +12,7 @@ def list_of_boards(): 'OpenMV2', "MicroBit", "HiFive1", + 'SAMV71_XPLAINED', 'Native'] @@ -146,6 +147,18 @@ def load_board_config(config): config.add_memory('rom', 'board_flash', '0x20400000', '512M') config.add_source_dir('boards/HiFive1/src/', origin) + elif board == "SAMV71_XPLAINED": + config.pre_define('Architecture', 'ARM', origin) + config.pre_define('Vendor', 'Atmel', origin) + config.pre_define('Device_Family', 'SAM', origin) + config.pre_define('Device_Name', 'ATSAMV71x', origin) + config.pre_define('Has_ZFP_Runtime', 'True', origin) + config.pre_define('Has_Ravenscar_SFP_Runtime', 'True', origin) + config.pre_define('Has_Ravenscar_Full_Runtime', 'True', origin) + config.pre_define('Runtime_Name_Suffix', 'samv71', origin) + config.add_source_dir('boards/samv71_xplained/src/', origin) + + elif board == "Native": config.pre_define('Architecture', 'Native', origin) config.add_source_dir('boards/native/src/', origin) diff --git a/scripts/config/devices.py b/scripts/config/devices.py index a7b9b0b4d..e58a0e2f1 100644 --- a/scripts/config/devices.py +++ b/scripts/config/devices.py @@ -18,6 +18,8 @@ def list_of_devices(config): return ['nRF51822xxAA'] elif family == "FE3": return ['FE310'] + elif family == "SAM": + return ['ATSAMV71x'] else: print "fatal error, unknown family '%s'" % family sys.exit(1) @@ -26,7 +28,7 @@ def list_of_devices(config): def list_of_vendors(config): arch = config.get_config("Architecture") if arch == "ARM": - return ["STMicro", "Nordic"] + return ["STMicro", "Nordic", "Atmel"] elif arch == "RISC-V": return ["SiFive"] elif arch == "Native": @@ -44,6 +46,8 @@ def list_of_families(config): return ["nRF51"] elif vendor == "SiFive": return ['FE3'] + elif vendor == "Atmel": + return ["SAM"] else: print "fatal error, unknown vendor '%s'" % vendor sys.exit(1) @@ -157,6 +161,11 @@ def load_device_config(config): 'arch/RISC-V/SiFive/devices/FE310/', 'arch/RISC-V/SiFive/drivers/'] + elif mcu == 'ATSAMV71x': + src += ['arch/ARM/SAM/devices/', + 'arch/ARM/SAM/drivers/', + 'arch/ARM/SAM/svd/atsamv71q21/'] + else: print "Unknown MCU device %s." % mcu diff --git a/scripts/project_wizard.py b/scripts/project_wizard.py index 11d69e26c..c88f3916f 100755 --- a/scripts/project_wizard.py +++ b/scripts/project_wizard.py @@ -49,6 +49,8 @@ def mcu_config(config): core = "ARM Cortex-M0" elif device.startswith("FE3"): core = "RISC-V32" + elif device.startswith("ATSAMV7"): + core = "ARM Cortex-M7F" config.set_config_string_key("CPU_Core", core, "mcu definition")