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Add button dejitter
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Dejitter/ButtonDejitter.v

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`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer: James Swineson
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//
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// Create Date: 14:47:27 12/30/2017
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// Design Name: ButtonDejitter
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// Module Name: ButtonDejitter.v
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// Project Name: ButtonDejitter
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// Target Devices: XC6LX16
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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// Generated by the following python code:
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// for i in range(1, 32): print("(x <= {})?{}:\\".format(2**i, i))
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// we end at 4294967295 since default int is 32 bit.
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// use WIDTH'dxxxx if larger int is needed.
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// the last -1 is used to indicater no LUT value error.
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`define CLOG2(x) \
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(x <= 2)?1:\
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(x <= 4)?2:\
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(x <= 8)?3:\
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(x <= 16)?4:\
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(x <= 32)?5:\
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(x <= 64)?6:\
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(x <= 128)?7:\
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(x <= 256)?8:\
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(x <= 512)?9:\
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(x <= 1024)?10:\
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(x <= 2048)?11:\
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(x <= 4096)?12:\
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(x <= 8192)?13:\
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(x <= 16384)?14:\
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(x <= 32768)?15:\
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(x <= 65536)?16:\
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(x <= 131072)?17:\
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(x <= 262144)?18:\
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(x <= 524288)?19:\
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(x <= 1048576)?20:\
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(x <= 2097152)?21:\
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(x <= 4194304)?22:\
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(x <= 8388608)?23:\
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(x <= 16777216)?24:\
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(x <= 33554432)?25:\
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(x <= 67108864)?26:\
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(x <= 134217728)?27:\
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(x <= 268435456)?28:\
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(x <= 536870912)?29:\
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(x <= 1073741824)?30:\
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(x <= 2147483648)?31:\
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(x <= 4294967295)?32:\
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-1
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module ButtonDejitter #(
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parameter COUNT_TO = 5000000,
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parameter DATA_WIDTH = `CLOG2(COUNT_TO) + 1
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)(
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input BTN_IN,
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input CLK,
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output BTN_OUT
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);
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reg DEJITTERED = 0;
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reg [DATA_WIDTH:0] count = 0;
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assign BTN_OUT = DEJITTERED;
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always @(posedge CLK) begin
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if (BTN_IN != DEJITTERED) count = count + 1;
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else count = 0;
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if (count == COUNT_TO) begin
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DEJITTERED = BTN_IN;
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count = 0;
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end
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end
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endmodule

Dejitter/ButtonDejitterTest.v

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`timescale 1ns / 1ns
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////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer: James Swineson
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//
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// Create Date: 14:57:18 12/30/2017
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// Design Name: ButtonDejitter
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// Module Name: ButtonDejitterTest.v
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// Project Name: ButtonDejitter
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// Target Device: XC6LX16
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// Tool versions:
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// Description:
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//
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// Verilog Test Fixture created by ISE for module: ButtonDejitter
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//
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// Dependencies: ButtonDejitter.v
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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// The following test runs for ~0.04s.
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//
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////////////////////////////////////////////////////////////////////////////////
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module ButtonDejitterTest;
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// Inputs
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reg BTN_IN = 0;
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reg CLK = 0;
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// Outputs
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wire BTN_OUT;
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// Instantiate the Unit Under Test (UUT)
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ButtonDejitter #(
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.COUNT_TO(250000)
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)uut (
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.BTN_IN(BTN_IN),
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.CLK(CLK),
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.BTN_OUT(BTN_OUT)
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);
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// 100 MHz Clock
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always @* CLK <= #10 ~CLK;
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initial begin
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// Initialize Inputs
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BTN_IN = 0;
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// Wait 100 ns for global reset to finish
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#100;
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// Add stimulus here
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// Note: delay = cycles * time per cycle (#10)
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// should trigger
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BTN_IN = 1;
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#6000000;
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BTN_IN = 0;
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#6000000;
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// should not trigger
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BTN_IN = 1;
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#4000000;
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BTN_IN = 0;
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#1000000;
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BTN_IN = 1;
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#3000000;
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BTN_IN = 0;
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// should trigger
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BTN_IN = 1;
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#6000000;
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// should not trigger
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BTN_IN = 0;
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#4000000;
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BTN_IN = 1;
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#1000000;
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BTN_IN = 0;
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#3000000;
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BTN_IN = 1;
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end
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endmodule
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Dejitter/RTL.png

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README.md

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* 寄存器
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* 移位寄存器
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* 按键消抖
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## 版权
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