diff --git a/.gitignore b/.gitignore index 32ea314..a507599 100644 --- a/.gitignore +++ b/.gitignore @@ -1,8 +1,22 @@ +*.* +* +!*/ +!Makefile +!*.mk +!*.scala +!*.[cSh] +!*.v +!*.cpp +!*.cc +!.gitignore +!.scalafmt.conf +!build.sc +!README.md +build/ + # mill out/ .bsp/ .idea/ .idea_modules/ test_run_dir/ - -build/ diff --git a/Makefile b/Makefile index fa6b95c..8a92776 100644 --- a/Makefile +++ b/Makefile @@ -1,10 +1,15 @@ BUILD_DIR = ./build +export PATH := $(PATH):$(abspath ./utils) + +$(BUILD_DIR): + mkdir -p $@ + test: mill -i __.test -verilog: - mkdir -p $(BUILD_DIR) +verilog: $(BUILD_DIR) + $(call git_commit, "generate verilog") mill -i __.test.runMain Elaborate -td $(BUILD_DIR) help: @@ -26,3 +31,9 @@ clean: -rm -rf $(BUILD_DIR) .PHONY: test verilog help compile bsp reformat checkformat clean + +sim: + $(call git_commit, "sim RTL") # DO NOT REMOVE THIS LINE!!! + @echo "Write this Makefile by yourself." + +-include ../Makefile diff --git a/README.md b/README.md index 0a27c83..906c4e2 100644 --- a/README.md +++ b/README.md @@ -29,3 +29,9 @@ To generate Verilog: ```bash make verilog ``` + +## Change FIRRTL Compiler + +You can change the FIRRTL compiler between SFC (Scala-based FIRRTL compiler) and +MFC (MLIR-based FIRRTL compiler) by modifying the `useMFC` variable in `playground/src/Elaborate.scala`. +The latter one requires `firtool`, which is included under `utils/`. diff --git a/build.sc b/build.sc index 7ef4e51..11a432b 100644 --- a/build.sc +++ b/build.sc @@ -7,24 +7,33 @@ import mill.scalalib.TestModule.Utest import mill.bsp._ object playground extends ScalaModule with ScalafmtModule { m => - override def scalaVersion = "2.13.8" + val useChisel5 = true + override def scalaVersion = "2.13.10" override def scalacOptions = Seq( "-language:reflectiveCalls", "-deprecation", "-feature", - "-Xcheckinit", - "-P:chiselplugin:genBundleElements" + "-Xcheckinit" ) override def ivyDeps = Agg( - ivy"edu.berkeley.cs::chisel3:3.5.4", + if (useChisel5) ivy"org.chipsalliance::chisel:5.0.0" else + ivy"edu.berkeley.cs::chisel3:3.6.0", ) override def scalacPluginIvyDeps = Agg( - ivy"edu.berkeley.cs:::chisel3-plugin:3.5.4", + if (useChisel5) ivy"org.chipsalliance:::chisel-plugin:5.0.0" else + ivy"edu.berkeley.cs:::chisel3-plugin:3.6.0", ) - object test extends Tests with Utest { + object test extends Tests with Utest with ScalafmtModule { override def ivyDeps = m.ivyDeps() ++ Agg( - ivy"com.lihaoyi::utest:0.7.10", - ivy"edu.berkeley.cs::chiseltest:0.5.4", + ivy"com.lihaoyi::utest:0.8.1", + if (useChisel5) ivy"edu.berkeley.cs::chiseltest:5.0-SNAPSHOT" else + ivy"edu.berkeley.cs::chiseltest:0.6.0", ) } + def repositoriesTask = T.task { Seq( + coursier.MavenRepository("https://maven.aliyun.com/repository/central"), + coursier.MavenRepository("https://repo.scala-sbt.org/scalasbt/maven-releases"), + coursier.MavenRepository("https://oss.sonatype.org/content/repositories/releases"), + coursier.MavenRepository("https://oss.sonatype.org/content/repositories/snapshots"), + ) ++ super.repositoriesTask() } } diff --git a/playground/src/Elaborate.scala b/playground/src/Elaborate.scala index 67345a1..6a95895 100644 --- a/playground/src/Elaborate.scala +++ b/playground/src/Elaborate.scala @@ -1,3 +1,7 @@ +import circt.stage._ + object Elaborate extends App { - (new chisel3.stage.ChiselStage).execute(args, Seq(chisel3.stage.ChiselGeneratorAnnotation(() => new GCD()))) + def top = new GCD() + val generator = Seq(chisel3.stage.ChiselGeneratorAnnotation(() => top)) + (new ChiselStage).execute(args, generator :+ CIRCTTargetAnnotation(CIRCTTarget.Verilog)) } diff --git a/utils/firtool b/utils/firtool new file mode 100755 index 0000000..1ece37d --- /dev/null +++ b/utils/firtool @@ -0,0 +1,2 @@ +#!/usr/bin/env bash +firtool.elf.strip --lowering-options=disallowLocalVariables,disallowPackedArrays,locationInfoStyle=wrapInAtSquareBracket $@ diff --git a/utils/firtool.elf.strip b/utils/firtool.elf.strip new file mode 100755 index 0000000..749b297 Binary files /dev/null and b/utils/firtool.elf.strip differ