FlyDSL Development Roadmap (v0.2)

Modeled on the SGLang AMD roadmap (sgl-project/sglang#23494). Milestone: v0.2 · due 2026-05-15 · ✓ released.

Contributions and feedback are welcome.

FlyDSL (Flexible LaYout DSL) is the Python front-end of the project. Legend: ✓ done · ▶ in progress · ○ planned.

Focus

• Layout algebra core: A complete, composable layout algebra as the foundation for all codegen.
• Codegen on layout algebra: GEMM and MHA built directly on the algebra.
• Multi-vendor runtime: A clean runtime and Python registration build layout.

Feature and Performance Improvements (v0.2 delivered)

• Layout algebra & ast_writer
  PoC: @coderfeli @sjfeng1999
  Goal: Full layout algebra plus a better AST writer.

  • ✓ Full layout algebra
  • ✓ Better ast_writer — lower dynamic control flow in external helper functions AST rewriter does not lower dynamic control flow in external helper functions #452

• GEMM & MHA
  PoC: @coderfeli
  Goal: GEMM and attention on top of the layout algebra.

  • ✓ GEMM based on layout algebra
  • ✓ MHA support

• Runtime & packaging
  PoC: @coderfeli
  Goal: Multi-vendor runtime, clean symbol isolation, working install.

  • ✓ Multi-vendor runtime & Python registration build layout (RFC [Feature]: RFC : Multi-vendor runtime and Python registration build layout #320)
  • ✓ Hide LLVM/MLIR symbols to co-exist with other MLIR libs [Issue]: symbols may conflict, need to hide llvm and mlir related to co work with other mlir lib #104
  • ✓ CentOS install fix [Issue]: centos install failed #396 · quickstart vecAdd segfault [Issue]: "A Minimal Vector Add Kernel" from docs/quickstart.rst segfaults #286

Next: v0.3 roadmap. All milestones: https://github.com/ROCm/FlyDSL/milestones