diff --git a/grammars/verilog.cson b/grammars/verilog.cson
index f716211..984e2be 100644
--- a/grammars/verilog.cson
+++ b/grammars/verilog.cson
@@ -57,10 +57,6 @@
         'match': '\\b[0-9]+\'[bBoOdDhH][a-fA-F0-9_xXzZ]+\\b'
         'name': 'constant.numeric.sized_integer.verilog'
       }
-      {
-        'match': '\\s\'[bBoOdDhH][a-fA-F0-9_xXzZ]+\\b'
-        'name': 'constant.numeric.unsized_integer.verilog'
-      }
       {
         'captures':
           '1':
@@ -95,7 +91,7 @@
         'include': '#keywords'
       }
       {
-        'begin': '^\\s*([a-zA-Z][a-zA-Z0-9_]*)\\s+([a-zA-Z][a-zA-Z0-9_]*)(?<!begin|if)\\s*(?=\\(|$)'
+        'begin': '^\\s*([a-zA-Z][a-zA-Z0-9_]*)\\s+([a-zA-Z][a-zA-Z0-9_]*)(?<!begin|if|case)\\s*(?=\\(|$)'
         'beginCaptures':
           '1':
             'name': 'entity.name.tag.module.reference.verilog'
@@ -142,7 +138,7 @@
   'keywords':
     'patterns': [
       {
-        'match': '\\b(alias|always|always_comb|always_ff|always_latch|and|assert|assign|assume|attribute|automatic|begin|before|bind|bins|binsof|bit|break|buf|bufif0|bufif1|byte|case(xz)?|cell|chandle|class|clocking|cmos|config|const|constraint|context|continue|cover|covergroup|coverpoint|cross|dist|do|deassign|default|defparam|design|disable|edge|else|end(attribute|case|class|clocking|config|function|generate|group|interface|module|package|primitive|program|property|sequence|specify|table|task)?|enum|event|expect|export|extends|extern|final|first_match|for|foreach|force|forever|fork|forkjoin|function|generate|genvar|incdir|include|instance|highz(01)|if(none|f)?|ignore_bins|import|initial|inout|input|inside|integer|int|interface|interact|join|join_any|join_none|large|liblist|library|local|logic|localparam|longing|matches|medium|module|modport|macromodule|nand|negedge|new|nmos|nor|noshowcancelled|not|notif(01)|null|or|output|package|packed|parameter|pmos|posedge|primitive|priority|program|property|protected|pull0|pull1|pulldown|pullup|pulsestyle_onevent|pulsestyle_ondetect|pure|rand|randc|randcase|randsequence|rcmos|real|realtime|ref|reg|release|repeat|return|rnmos|rpmos|rtran|rtranif(01)|scalared|sequence|semaphore|shortint|shortreal|showcancelled|signed|small|solve|specify|specparam|static|strength|string|strong0|strong1|struct|super|supply0|supply1|table|tagged|task|this|throughout|time|timeprecision|timeunit|type|typedef|ran|tranif(01)|tri(01)?|tri(and|or|reg)|union|unique|unsigned|use|uwire|var|vectored|virtual|void|wait|wait_order|wand|weak(01)|wildcard|while|with|within|wire|wor|xnor|xor)\\b'
+        'match': '\\b(alias|always|always_comb|always_ff|always_latch|and|assert|assign|assume|attribute|automatic|begin|before|bind|bins|binsof|bit|break|buf|bufif0|bufif1|byte|case(xz)?|cell|chandle|class|clocking|cmos|config|const|constraint|context|continue|cover|covergroup|coverpoint|cross|dist|do|deassign|default|defparam|design|disable|edge|else|end(attribute|case|class|clocking|config|function|generate|group|interface|module|package|primitive|program|property|sequence|specify|table|task)?|enum|event|expect|export|extends|extern|final|first_match|for|foreach|force|forever|fork|forkjoin|function|generate|genvar|incdir|include|instance|highz(01)|if(none|f)?|ignore_bins|import|initial|inout|input|inside|integer|int|interface|interact|join|join_any|join_none|large|liblist|library|local|logic|localparam|longint|matches|medium|module|modport|macromodule|nand|negedge|new|nmos|nor|noshowcancelled|not|notif(01)|null|or|output|package|packed|parameter|pmos|posedge|primitive|priority|program|property|protected|pull0|pull1|pulldown|pullup|pulsestyle_onevent|pulsestyle_ondetect|pure|rand|randc|randcase|randsequence|rcmos|real|realtime|ref|reg|release|repeat|return|rnmos|rpmos|rtran|rtranif(01)|scalared|sequence|shortint|shortreal|showcancelled|signed|small|solve|specify|specparam|static|strength|string|strong0|strong1|struct|super|supply0|supply1|table|tagged|task|this|throughout|time|timeprecision|timeunit|type|typedef|ran|tranif(01)|tri(01)?|tri(and|or|reg)|union|unique|unsigned|use|uwire|var|vectored|virtual|void|wait|wait_order|wand|weak(01)|wildcard|while|with|within|wire|wor|xnor|xor)\\b'
         'name': 'keyword.other.verilog'
       }
       {