fix broken msg passing in wishbone master for (fix #692)#693
fix broken msg passing in wishbone master for (fix #692)#693eine merged 2 commits intoVUnit:masterfrom
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Fails on modelsim, but working properly on ghdl.
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| def gen_wb_tests(obj, *args): | ||
| for dat_width, num_cycles, strobe_prob, ack_prob, stall_prob in product(*args): | ||
| for dat_width, num_cycles, strobe_prob, ack_prob, stall_prob, slave_inst in product(*args): |
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I would use slave_comb instead of slave_inst, since my understanding is that the difference between the two cases is whether the slave is combinatorial or registered.
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The idea is to have possibility to skip wb slave VC instantiation and drive wishbone slave signals directly. It makes possible to test various corner cases - like here when specific set of acknowledge logic lead to crash on modelsim, but not ghdl. I thinks it's not feasible to add this corner cases reproducers to wishbone slave as it will obfuscate code. This is all about wb master VC bug.
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| for test in TB_WISHBONE_MASTER.get_tests(): | ||
| gen_wb_tests(test, [8, 32], [1, 64], [0.3, 1.0], [0.3, 1.0], [0.4, 0.0]) | ||
| if test.name == "slave comb ack": |
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I'm not sure to understand this. Why is the combinatorial version tested with one set of params but the other one is tested with two?
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slave comb ack test case doesn't need/cannot have random stimulus
| stall => stall, | ||
| ack => ack | ||
| ); | ||
| slave_gen : if tb_cfg.slave_inst generate |
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Would it make sense for comb to be an option (generic) of the wishbone slave, instead of using a generate in the testbench?
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as described in first comment IMHO: no, it would not
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