Systematically initialize registers to zero (and not only in BENCH mode)

BrunoLevy · BrunoLevy · commit 408c2441e390 · 2023-01-08T22:49:46.000+01:00
diff --git a/FemtoRV/TUTORIALS/FROM_BLINKER_TO_RISCV/step7_with_disasm.v b/FemtoRV/TUTORIALS/FROM_BLINKER_TO_RISCV/step7_with_disasm.v
@@ -93,14 +93,12 @@ module SOC (
    wire [31:0] writeBackData; // data to be written to rd
    wire        writeBackEn;   // asserted if data should be written to rd
 
-`ifdef BENCH   
-   integer     i;
+   integer i;
    initial begin
       for(i=0; i<32; ++i) begin
 	 RegisterBank[i] = 0;
       end
    end
-`endif   
 
    // The ALU
    wire [31:0] aluIn1 = rs1;
