|
83 | 83 | reg = <0x0 0x0>;
|
84 | 84 | enable-method = "psci";
|
85 | 85 | next-level-cache = <&l2>;
|
| 86 | + clocks = <&scpi_dvfs 0>; |
86 | 87 | };
|
87 | 88 |
|
88 | 89 | cpu1: cpu@1 {
|
|
91 | 92 | reg = <0x0 0x1>;
|
92 | 93 | enable-method = "psci";
|
93 | 94 | next-level-cache = <&l2>;
|
| 95 | + clocks = <&scpi_dvfs 0>; |
94 | 96 | };
|
95 | 97 |
|
96 | 98 | cpu2: cpu@2 {
|
|
99 | 101 | reg = <0x0 0x2>;
|
100 | 102 | enable-method = "psci";
|
101 | 103 | next-level-cache = <&l2>;
|
| 104 | + clocks = <&scpi_dvfs 0>; |
102 | 105 | };
|
103 | 106 |
|
104 | 107 | cpu3: cpu@3 {
|
|
107 | 110 | reg = <0x0 0x3>;
|
108 | 111 | enable-method = "psci";
|
109 | 112 | next-level-cache = <&l2>;
|
| 113 | + clocks = <&scpi_dvfs 0>; |
110 | 114 | };
|
111 | 115 |
|
112 | 116 | l2: l2-cache0 {
|
|
171 | 175 | };
|
172 | 176 | };
|
173 | 177 |
|
| 178 | + scpi { |
| 179 | + compatible = "amlogic,meson-gxbb-scpi", "arm,scpi-pre-1.0"; |
| 180 | + mboxes = <&mailbox 1 &mailbox 2>; |
| 181 | + shmem = <&cpu_scp_lpri &cpu_scp_hpri>; |
| 182 | + |
| 183 | + scpi_clocks: clocks { |
| 184 | + compatible = "arm,scpi-clocks"; |
| 185 | + |
| 186 | + scpi_dvfs: scpi_clocks@0 { |
| 187 | + compatible = "arm,scpi-dvfs-clocks"; |
| 188 | + #clock-cells = <1>; |
| 189 | + clock-indices = <0>; |
| 190 | + clock-output-names = "vcpu"; |
| 191 | + }; |
| 192 | + }; |
| 193 | + |
| 194 | + scpi_sensors: sensors { |
| 195 | + compatible = "arm,scpi-sensors"; |
| 196 | + #thermal-sensor-cells = <1>; |
| 197 | + }; |
| 198 | + }; |
| 199 | + |
174 | 200 | soc {
|
175 | 201 | compatible = "simple-bus";
|
176 | 202 | #address-cells = <2>;
|
|
229 | 255 | status = "disabled";
|
230 | 256 | };
|
231 | 257 |
|
| 258 | + saradc: adc@8680 { |
| 259 | + compatible = "amlogic,meson-saradc"; |
| 260 | + reg = <0x0 0x8680 0x0 0x34>; |
| 261 | + #io-channel-cells = <1>; |
| 262 | + interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>; |
| 263 | + status = "disabled"; |
| 264 | + }; |
| 265 | + |
232 | 266 | pwm_ef: pwm@86c0 {
|
233 | 267 | compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
|
234 | 268 | reg = <0x0 0x086c0 0x0 0x10>;
|
|
282 | 316 | #address-cells = <0>;
|
283 | 317 | };
|
284 | 318 |
|
| 319 | + sram: sram@c8000000 { |
| 320 | + compatible = "amlogic,meson-gxbb-sram", "mmio-sram"; |
| 321 | + reg = <0x0 0xc8000000 0x0 0x14000>; |
| 322 | + |
| 323 | + #address-cells = <1>; |
| 324 | + #size-cells = <1>; |
| 325 | + ranges = <0 0x0 0xc8000000 0x14000>; |
| 326 | + |
| 327 | + cpu_scp_lpri: scp-shmem@0 { |
| 328 | + compatible = "amlogic,meson-gxbb-scp-shmem"; |
| 329 | + reg = <0x13000 0x400>; |
| 330 | + }; |
| 331 | + |
| 332 | + cpu_scp_hpri: scp-shmem@200 { |
| 333 | + compatible = "amlogic,meson-gxbb-scp-shmem"; |
| 334 | + reg = <0x13400 0x400>; |
| 335 | + }; |
| 336 | + }; |
| 337 | + |
285 | 338 | aobus: aobus@c8100000 {
|
286 | 339 | compatible = "simple-bus";
|
287 | 340 | reg = <0x0 0xc8100000 0x0 0x100000>;
|
|
297 | 350 | status = "disabled";
|
298 | 351 | };
|
299 | 352 |
|
| 353 | + uart_AO_B: serial@4e0 { |
| 354 | + compatible = "amlogic,meson-uart"; |
| 355 | + reg = <0x0 0x004e0 0x0 0x14>; |
| 356 | + interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; |
| 357 | + clocks = <&xtal>; |
| 358 | + status = "disabled"; |
| 359 | + }; |
| 360 | + |
| 361 | + pwm_AO_ab: pwm@550 { |
| 362 | + compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm"; |
| 363 | + reg = <0x0 0x00550 0x0 0x10>; |
| 364 | + #pwm-cells = <3>; |
| 365 | + status = "disabled"; |
| 366 | + }; |
| 367 | + |
300 | 368 | ir: ir@580 {
|
301 | 369 | compatible = "amlogic,meson-gxbb-ir";
|
302 | 370 | reg = <0x0 0x00580 0x0 0x40>;
|
|
0 commit comments