33
33
LPI2C_Type * mcu_i2c_banks [] = { LPI2C1 , LPI2C2 , LPI2C3 , LPI2C4 };
34
34
35
35
const mcu_periph_obj_t mcu_i2c_sda_list [8 ] = {
36
- PERIPH_PIN (1 , 0 , kIOMUXC_LPI2C1_SDA_SELECT_INPUT , 0 , & pin_GPIO_AD_B1_15 ),
37
- PERIPH_PIN (1 , 6 , kIOMUXC_LPI2C1_SDA_SELECT_INPUT , 1 , & pin_GPIO_EMC_03 ),
36
+ PERIPH_PIN (1 , 6 , kIOMUXC_LPI2C1_SDA_SELECT_INPUT , 0 , & pin_GPIO_EMC_03 ),
37
+ PERIPH_PIN (1 , 0 , kIOMUXC_LPI2C1_SDA_SELECT_INPUT , 1 , & pin_GPIO_AD_B1_15 ),
38
38
39
39
PERIPH_PIN (2 , 0 , kIOMUXC_LPI2C2_SDA_SELECT_INPUT , 0 , & pin_GPIO_AD_B1_09 ),
40
40
PERIPH_PIN (2 , 2 , kIOMUXC_LPI2C2_SDA_SELECT_INPUT , 1 , & pin_GPIO_EMC_18 ),
41
41
42
- PERIPH_PIN (3 , 1 , kIOMUXC_LPI2C3_SDA_SELECT_INPUT , 0 , & pin_GPIO_AD_B0_09 ),
43
- PERIPH_PIN (3 , 4 , kIOMUXC_LPI2C3_SDA_SELECT_INPUT , 1 , & pin_GPIO_SD_B0_01 ),
42
+ PERIPH_PIN (3 , 4 , kIOMUXC_LPI2C3_SDA_SELECT_INPUT , 0 , & pin_GPIO_SD_B0_01 ),
43
+ PERIPH_PIN (3 , 1 , kIOMUXC_LPI2C3_SDA_SELECT_INPUT , 1 , & pin_GPIO_AD_B0_09 ),
44
44
45
45
PERIPH_PIN (4 , 2 , kIOMUXC_LPI2C4_SDA_SELECT_INPUT , 0 , & pin_GPIO_EMC_10 ),
46
46
PERIPH_PIN (4 , 3 , kIOMUXC_LPI2C4_SDA_SELECT_INPUT , 1 , & pin_GPIO_SD_B1_03 ),
47
47
};
48
48
49
49
const mcu_periph_obj_t mcu_i2c_scl_list [8 ] = {
50
- PERIPH_PIN (1 , 0 , kIOMUXC_LPI2C1_SCL_SELECT_INPUT , 0 , & pin_GPIO_AD_B1_14 ),
51
- PERIPH_PIN (1 , 6 , kIOMUXC_LPI2C1_SCL_SELECT_INPUT , 1 , & pin_GPIO_EMC_02 ),
50
+ PERIPH_PIN (1 , 6 , kIOMUXC_LPI2C1_SCL_SELECT_INPUT , 0 , & pin_GPIO_EMC_02 ),
51
+ PERIPH_PIN (1 , 0 , kIOMUXC_LPI2C1_SCL_SELECT_INPUT , 1 , & pin_GPIO_AD_B1_14 ),
52
52
53
53
PERIPH_PIN (2 , 0 , kIOMUXC_LPI2C2_SCL_SELECT_INPUT , 0 , & pin_GPIO_AD_B1_08 ),
54
54
PERIPH_PIN (2 , 2 , kIOMUXC_LPI2C2_SCL_SELECT_INPUT , 1 , & pin_GPIO_EMC_19 ),
55
55
56
- PERIPH_PIN (3 , 1 , kIOMUXC_LPI2C3_SCL_SELECT_INPUT , 0 , & pin_GPIO_AD_B0_08 ),
57
- PERIPH_PIN (3 , 4 , kIOMUXC_LPI2C3_SCL_SELECT_INPUT , 1 , & pin_GPIO_SD_B0_00 ),
56
+ PERIPH_PIN (3 , 4 , kIOMUXC_LPI2C3_SCL_SELECT_INPUT , 0 , & pin_GPIO_SD_B0_00 ),
57
+ PERIPH_PIN (3 , 1 , kIOMUXC_LPI2C3_SCL_SELECT_INPUT , 1 , & pin_GPIO_AD_B0_08 ),
58
58
59
59
PERIPH_PIN (4 , 2 , kIOMUXC_LPI2C4_SCL_SELECT_INPUT , 0 , & pin_GPIO_EMC_11 ),
60
60
PERIPH_PIN (4 , 3 , kIOMUXC_LPI2C4_SCL_SELECT_INPUT , 1 , & pin_GPIO_SD_B1_02 ),
@@ -63,8 +63,8 @@ const mcu_periph_obj_t mcu_i2c_scl_list[8] = {
63
63
LPSPI_Type * mcu_spi_banks [] = { LPSPI1 , LPSPI2 , LPSPI3 , LPSPI4 };
64
64
65
65
const mcu_periph_obj_t mcu_spi_sck_list [8 ] = {
66
- PERIPH_PIN (1 , 1 , kIOMUXC_LPSPI1_SCK_SELECT_INPUT , 0 , & pin_GPIO_AD_B0_10 ),
67
- PERIPH_PIN (1 , 4 , kIOMUXC_LPSPI1_SCK_SELECT_INPUT , 1 , & pin_GPIO_SD_B0_02 ),
66
+ PERIPH_PIN (1 , 4 , kIOMUXC_LPSPI1_SCK_SELECT_INPUT , 0 , & pin_GPIO_SD_B0_02 ),
67
+ PERIPH_PIN (1 , 1 , kIOMUXC_LPSPI1_SCK_SELECT_INPUT , 1 , & pin_GPIO_AD_B0_10 ),
68
68
69
69
PERIPH_PIN (2 , 4 , kIOMUXC_LPSPI2_SCK_SELECT_INPUT , 0 , & pin_GPIO_EMC_00 ),
70
70
PERIPH_PIN (2 , 4 , kIOMUXC_LPSPI2_SCK_SELECT_INPUT , 1 , & pin_GPIO_EMC_10 ),
@@ -77,31 +77,31 @@ const mcu_periph_obj_t mcu_spi_sck_list[8] = {
77
77
};
78
78
79
79
const mcu_periph_obj_t mcu_spi_mosi_list [8 ] = {
80
- PERIPH_PIN (1 , 1 , kIOMUXC_LPSPI1_SDO_SELECT_INPUT , 0 , & pin_GPIO_AD_B0_13 ),
81
- PERIPH_PIN (1 , 4 , kIOMUXC_LPSPI1_SDO_SELECT_INPUT , 1 , & pin_GPIO_SD_B0_05 ),
80
+ PERIPH_PIN (1 , 4 , kIOMUXC_LPSPI1_SDO_SELECT_INPUT , 0 , & pin_GPIO_SD_B0_04 ),
81
+ PERIPH_PIN (1 , 1 , kIOMUXC_LPSPI1_SDO_SELECT_INPUT , 1 , & pin_GPIO_AD_B0_12 ),
82
82
83
- PERIPH_PIN (2 , 4 , kIOMUXC_LPSPI2_SDO_SELECT_INPUT , 0 , & pin_GPIO_EMC_03 ),
84
- PERIPH_PIN (2 , 4 , kIOMUXC_LPSPI2_SDO_SELECT_INPUT , 1 , & pin_GPIO_EMC_13 ),
85
- PERIPH_PIN (2 , 4 , kIOMUXC_LPSPI2_SDO_SELECT_INPUT , 2 , & pin_GPIO_SD_B1_09 ),
83
+ PERIPH_PIN (2 , 4 , kIOMUXC_LPSPI2_SDO_SELECT_INPUT , 0 , & pin_GPIO_EMC_02 ),
84
+ PERIPH_PIN (2 , 4 , kIOMUXC_LPSPI2_SDO_SELECT_INPUT , 1 , & pin_GPIO_EMC_12 ),
85
+ PERIPH_PIN (2 , 4 , kIOMUXC_LPSPI2_SDO_SELECT_INPUT , 2 , & pin_GPIO_SD_B1_08 ),
86
86
87
- PERIPH_PIN (3 , 2 , kIOMUXC_LPSPI2_SDO_SELECT_INPUT , 0 , & pin_GPIO_AD_B1_15 ),
87
+ PERIPH_PIN (3 , 2 , kIOMUXC_LPSPI2_SDO_SELECT_INPUT , 0 , & pin_GPIO_AD_B1_14 ),
88
88
89
- PERIPH_PIN (4 , 2 , kIOMUXC_LPSPI2_SDO_SELECT_INPUT , 0 , & pin_GPIO_AD_B1_05 ),
90
- PERIPH_PIN (4 , 4 , kIOMUXC_LPSPI2_SDO_SELECT_INPUT , 1 , & pin_GPIO_EMC_35 ),
89
+ PERIPH_PIN (4 , 2 , kIOMUXC_LPSPI2_SDO_SELECT_INPUT , 0 , & pin_GPIO_AD_B1_04 ),
90
+ PERIPH_PIN (4 , 4 , kIOMUXC_LPSPI2_SDO_SELECT_INPUT , 1 , & pin_GPIO_EMC_34 ),
91
91
};
92
92
93
93
const mcu_periph_obj_t mcu_spi_miso_list [8 ] = {
94
- PERIPH_PIN (1 , 1 , kIOMUXC_LPSPI1_SDI_SELECT_INPUT , 0 , & pin_GPIO_AD_B0_12 ),
95
- PERIPH_PIN (1 , 4 , kIOMUXC_LPSPI1_SDI_SELECT_INPUT , 1 , & pin_GPIO_SD_B0_04 ),
94
+ PERIPH_PIN (1 , 4 , kIOMUXC_LPSPI1_SDI_SELECT_INPUT , 0 , & pin_GPIO_SD_B0_05 ),
95
+ PERIPH_PIN (1 , 1 , kIOMUXC_LPSPI1_SDI_SELECT_INPUT , 1 , & pin_GPIO_AD_B0_13 ),
96
96
97
- PERIPH_PIN (2 , 4 , kIOMUXC_LPSPI2_SDI_SELECT_INPUT , 0 , & pin_GPIO_EMC_02 ),
98
- PERIPH_PIN (2 , 4 , kIOMUXC_LPSPI2_SDI_SELECT_INPUT , 1 , & pin_GPIO_EMC_12 ),
99
- PERIPH_PIN (2 , 4 , kIOMUXC_LPSPI2_SDI_SELECT_INPUT , 2 , & pin_GPIO_SD_B1_08 ),
97
+ PERIPH_PIN (2 , 4 , kIOMUXC_LPSPI2_SDI_SELECT_INPUT , 0 , & pin_GPIO_EMC_03 ),
98
+ PERIPH_PIN (2 , 4 , kIOMUXC_LPSPI2_SDI_SELECT_INPUT , 1 , & pin_GPIO_EMC_13 ),
99
+ PERIPH_PIN (2 , 4 , kIOMUXC_LPSPI2_SDI_SELECT_INPUT , 2 , & pin_GPIO_SD_B1_09 ),
100
100
101
- PERIPH_PIN (3 , 2 , kIOMUXC_LPSPI2_SDI_SELECT_INPUT , 0 , & pin_GPIO_AD_B1_14 ),
101
+ PERIPH_PIN (3 , 2 , kIOMUXC_LPSPI2_SDI_SELECT_INPUT , 0 , & pin_GPIO_AD_B1_15 ),
102
102
103
- PERIPH_PIN (4 , 2 , kIOMUXC_LPSPI2_SDI_SELECT_INPUT , 0 , & pin_GPIO_AD_B1_04 ),
104
- PERIPH_PIN (4 , 4 , kIOMUXC_LPSPI2_SDI_SELECT_INPUT , 1 , & pin_GPIO_EMC_34 ),
103
+ PERIPH_PIN (4 , 2 , kIOMUXC_LPSPI2_SDI_SELECT_INPUT , 0 , & pin_GPIO_AD_B1_05 ),
104
+ PERIPH_PIN (4 , 4 , kIOMUXC_LPSPI2_SDI_SELECT_INPUT , 1 , & pin_GPIO_EMC_35 ),
105
105
};
106
106
107
107
LPUART_Type * mcu_uart_banks [] = { LPUART1 , LPUART2 , LPUART3 , LPUART4 , LPUART5 , LPUART6 , LPUART7 , LPUART8 };
0 commit comments