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Add Register Spill to GC for all target processor architectures #10311

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eightycc opened this issue May 5, 2025 · 2 comments
Open

Add Register Spill to GC for all target processor architectures #10311

eightycc opened this issue May 5, 2025 · 2 comments
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bug esp32-c2 esp32-c3 esp32-c6 esp32-h2 esp32-p4
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10.0.0

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@eightycc
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eightycc commented May 5, 2025

It is possible, as demonstrated by #10298, for a live memory pointer to exist only in a register when gc_collect is called. ports/espressif/mphalport.c:cpu_get_regs_and_sp() implements register spill for Xtensa processors. Similar spilling needs to be implemented, in a processor-dependent fashion, for other target processor architectures.
@tannewt
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tannewt commented May 5, 2025

I don't think RISC-V needs spilling because it doesn't have register windows. Instead, we'll want to copy out of the RISC-V registers.

@tannewt tannewt added this to the 10.0.0 milestone May 5, 2025
@eightycc
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eightycc commented May 5, 2025

I don't think RISC-V needs spilling because it doesn't have register windows. Instead, we'll want to copy out of the RISC-V registers.

I think we mean the same thing. I was using the term spill in its more general sense, meaning to move register contents to RAM.

@eightycc eightycc mentioned this issue May 6, 2025
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