Thanks to visit codestin.com
Credit goes to github.com

Skip to content

Commit dc9e841

Browse files
Guoniu.zhouDong Aisheng
Guoniu.zhou
authored and
Dong Aisheng
committed
LF-1909-1: arm64: dts: imx8mp.dtsi: add device node for isi and csi of iMX8MP
Add device node for isi and csi of iMX8MP Signed-off-by: Guoniu.zhou <[email protected]> Reviewed-by: Robby.Cai <[email protected]>
1 parent 6fb9804 commit dc9e841

File tree

1 file changed

+120
-0
lines changed

1 file changed

+120
-0
lines changed

‎arch/arm64/boot/dts/freescale/imx8mp.dtsi‎

Lines changed: 120 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -39,6 +39,10 @@
3939
serial2 = &uart3;
4040
serial3 = &uart4;
4141
spi0 = &flexspi;
42+
isi0 = &isi_0;
43+
isi1 = &isi_1;
44+
csi0 = &mipi_csi_0;
45+
csi1 = &mipi_csi_1;
4246
};
4347

4448
cpus {
@@ -1369,6 +1373,122 @@
13691373
#phy-cells = <0>;
13701374
};
13711375
};
1376+
1377+
mediamix_gpr: media_gpr@32ec0008 {
1378+
compatible = "fsl,imx8mp-iomuxc-gpr", "syscon";
1379+
reg = <0x32ec0008 0x4>;
1380+
};
1381+
1382+
mediamix_gasket0: gasket@32ec0060 {
1383+
compatible = "fsl,imx8mp-iomuxc-gpr", "syscon";
1384+
reg = <0x32ec0060 0x28>;
1385+
};
1386+
1387+
mediamix_gasket1: gasket@32ec0090 {
1388+
compatible = "fsl,imx8mp-iomuxc-gpr", "syscon";
1389+
reg = <0x32ec0090 0x28>;
1390+
};
1391+
1392+
cameradev: camera {
1393+
compatible = "fsl,mxc-md", "simple-bus";
1394+
#address-cells = <1>;
1395+
#size-cells = <1>;
1396+
ranges;
1397+
status = "disabled";
1398+
1399+
isi_0: isi@32e00000 {
1400+
compatible = "fsl,imx8mp-isi", "fsl,imx8mn-isi";
1401+
reg = <0x32e00000 0x2000>;
1402+
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1403+
interface = <2 0 2>;
1404+
clocks = <&clk IMX8MP_CLK_MEDIA_AXI>,
1405+
<&clk IMX8MP_CLK_MEDIA_APB>,
1406+
<&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
1407+
<&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
1408+
clock-names = "disp_axi", "disp_apb", "disp_axi_root", "disp_apb_root";
1409+
assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
1410+
<&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
1411+
assigned-clock-rates = <500000000>, <200000000>;
1412+
no-reset-control;
1413+
power-domains = <&mediamix_pd>;
1414+
status = "disabled";
1415+
1416+
cap_device {
1417+
compatible = "imx-isi-capture";
1418+
status = "disabled";
1419+
};
1420+
1421+
m2m_device{
1422+
compatible = "imx-isi-m2m";
1423+
status = "disabled";
1424+
};
1425+
};
1426+
1427+
isi_1: isi@32e02000 {
1428+
compatible = "fsl,imx8mp-isi", "fsl,imx8mn-isi";
1429+
reg = <0x32e02000 0x2000>;
1430+
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
1431+
interface = <3 0 2>;
1432+
clocks = <&clk IMX8MP_CLK_MEDIA_AXI>,
1433+
<&clk IMX8MP_CLK_MEDIA_APB>,
1434+
<&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
1435+
<&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
1436+
clock-names = "disp_axi", "disp_apb", "disp_axi_root", "disp_apb_root";
1437+
assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
1438+
<&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
1439+
assigned-clock-rates = <500000000>, <200000000>;
1440+
no-reset-control;
1441+
power-domains = <&mediamix_pd>;
1442+
status = "disabled";
1443+
1444+
cap_device {
1445+
compatible = "imx-isi-capture";
1446+
status = "disabled";
1447+
};
1448+
};
1449+
1450+
mipi_csi_0: csi@32e40000 {
1451+
compatible = "fsl,imx8mp-mipi-csi", "fsl,imx8mn-mipi-csi";
1452+
reg = <0x32e40000 0x10000>;
1453+
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1454+
clock-frequency = <500000000>;
1455+
clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>,
1456+
<&clk IMX8MP_CLK_MEDIA_AXI>,
1457+
<&clk IMX8MP_CLK_MEDIA_APB>;
1458+
clock-names = "mipi_clk", "disp_axi", "disp_apb";
1459+
assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>;
1460+
assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>;
1461+
assigned-clock-rates = <500000000>;
1462+
bus-width = <4>;
1463+
csi-gpr = <&mediamix_gasket0>;
1464+
csi-gpr2 = <&mediamix_gpr>;
1465+
gpr = <&media_blk_ctrl>;
1466+
no-reset-control;
1467+
power-domains = <&mipi_phy1_pd>;
1468+
status = "disabled";
1469+
};
1470+
1471+
mipi_csi_1: csi@32e50000 {
1472+
compatible = "fsl,imx8mp-mipi-csi", "fsl,imx8mn-mipi-csi";
1473+
reg = <0x32e50000 0x10000>;
1474+
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
1475+
clock-frequency = <266000000>;
1476+
clocks = <&clk IMX8MP_CLK_MEDIA_CAM2_PIX>,
1477+
<&clk IMX8MP_CLK_MEDIA_AXI>,
1478+
<&clk IMX8MP_CLK_MEDIA_APB>;
1479+
clock-names = "mipi_clk", "disp_axi", "disp_apb";
1480+
assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM2_PIX>;
1481+
assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>;
1482+
assigned-clock-rates = <266000000>;
1483+
bus-width = <4>;
1484+
csi-gpr = <&mediamix_gasket1>;
1485+
csi-gpr2 = <&mediamix_gpr>;
1486+
gpr = <&media_blk_ctrl>;
1487+
no-reset-control;
1488+
power-domains = <&mipi_phy2_pd>;
1489+
status = "disabled";
1490+
};
1491+
};
13721492
};
13731493

13741494
aips5: bus@30c00000 {

0 commit comments

Comments
 (0)