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Merge branch 'fix/spi_test_memory_layout' into 'master'
test: fix the unit test fail issue under single_core config See merge request idf/esp-idf!3596
2 parents dba29ee + 4132834 commit a4357ae

3 files changed

Lines changed: 10 additions & 2 deletions

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components/soc/esp32/include/soc/soc.h

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@@ -286,6 +286,10 @@
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#define SOC_DROM_HIGH 0x3F800000
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#define SOC_IROM_LOW 0x400D0000
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#define SOC_IROM_HIGH 0x40400000
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#define SOC_CACHE_PRO_LOW 0x40070000
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#define SOC_CACHE_PRO_HIGH 0x40078000
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#define SOC_CACHE_APP_LOW 0x40078000
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#define SOC_CACHE_APP_HIGH 0x40080000
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#define SOC_IRAM_LOW 0x40080000
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#define SOC_IRAM_HIGH 0x400A0000
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#define SOC_RTC_IRAM_LOW 0x400C0000

components/soc/esp32/soc_memory_layout.c

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@@ -130,9 +130,9 @@ const size_t soc_memory_region_count = sizeof(soc_memory_regions)/sizeof(soc_mem
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These are removed from the soc_memory_regions array when heaps are created.
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*/
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SOC_RESERVE_MEMORY_REGION(0x40070000, 0x40078000, cpu0_cache);
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SOC_RESERVE_MEMORY_REGION(SOC_CACHE_PRO_LOW, SOC_CACHE_PRO_HIGH, cpu0_cache);
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#ifndef CONFIG_FREERTOS_UNICORE
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SOC_RESERVE_MEMORY_REGION(0x40078000, 0x40080000, cpu1_cache);
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SOC_RESERVE_MEMORY_REGION(SOC_CACHE_APP_LOW, SOC_CACHE_APP_HIGH, cpu1_cache);
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#endif
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/* Warning: The ROM stack is located in the 0x3ffe0000 area. We do not specifically disable that area here because

components/soc/include/soc/soc_memory_layout.h

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@@ -175,7 +175,11 @@ inline static bool IRAM_ATTR esp_ptr_external_ram(const void *p) {
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}
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inline static bool IRAM_ATTR esp_ptr_in_iram(const void *p) {
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#ifndef CONFIG_FREERTOS_UNICORE
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return ((intptr_t)p >= SOC_IRAM_LOW && (intptr_t)p < SOC_IRAM_HIGH);
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#else
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return ((intptr_t)p >= SOC_CACHE_APP_LOW && (intptr_t)p < SOC_IRAM_HIGH);
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#endif
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}
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inline static bool IRAM_ATTR esp_ptr_in_drom(const void *p) {

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