diff --git a/.github/workflows/rust_all.yml b/.github/workflows/rust_all.yml index b019d29..b1e2e22 100644 --- a/.github/workflows/rust_all.yml +++ b/.github/workflows/rust_all.yml @@ -75,3 +75,10 @@ jobs: cargo make ci_debug cargo make ci_release cargo doc + + - name: Minimal Async Basic + working-directory: ${{github.workspace}}/minimal_async_basic + run: | + cargo make ci_debug + cargo make ci_release + cargo doc diff --git a/README.md b/README.md index ae99f14..c875527 100644 --- a/README.md +++ b/README.md @@ -2,7 +2,7 @@ Rust on microcontrollers -# Projects +# Base Projects - Minimal blinky - Barebones blinky example i.e linker script to main @@ -25,15 +25,104 @@ Rust on microcontrollers - Added **heapless** library to `l2` - Added USART buffered traits to `l3` +# Async Rust + +- Minimal Async Basic + - Forked from `Minimal Interrupt` + - Configure Interrupts and main loop with rust cooperative async/await + - No executor/waker implementation. Just basic polling functionality + # Roadmap -## Libraries +## Supported Architecture + +- [x] ARM Cortex M4 + +> TODO, Add more eventually + +## Supported Chips + +- [x] STM32L475xx +- [ ] LPC4078xx + +## Supported Development platforms -- [Bitflags](https://crates.io/crates/bitflags): Rust macros to generate bitflags -- [Heapless](https://crates.io/crates/heapless): Stack allocated data structures +**See CI/CD** + +- [x] Windows +- [x] Linux +- [x] Mac + +## Async Rust + +- [x] Basic Async Rust + - Polling support +- [ ] Efficient Async Rust + - Waker support + - Interrupt support ## RTOS +### C based + +- [ ] FreeRTOS +- [ ] Zephyr RTOS + +### Rust based + +- [ ] RTIC + ## Debugging -## Tooling +- [x] OpenOCD +- [ ] Semihosting + +## Mocking + +- [ ] Mockall + +## Buildsystem + +- [x] Cargo +- [x] Cargo Make +- [ ] Cargo features + - Conditional compiling for additional platforms + +## Code coverage + +- [ ] Grcov + - Rust based code coverage +- [ ] Lcov + - Stable code coverage tool +- [ ] Codecov + - Web based code coverage +- [ ] Coveralls + - Web based code coverage + +## FFI compat with C + +- [x] Bindgen + - Use C in Rust +- [ ] CBindgen + - Use Rust in C + +## Crates.io Libraries + +- [x] [Bitflags](https://crates.io/crates/bitflags) + - Rust macros to generate bitflags +- [x] [Heapless](https://crates.io/crates/heapless) + - Stack allocated data structures + +## Rust integrated tooling + +- [x] Unit testing +- [ ] Clippy + - Linting +- [x] Cargofmt + - Integrated in VSCode +- [ ] Documentation + +## External tooling + +- [x] Continuous Integration + - [x] Github Actions diff --git a/minimal_async_basic/.cargo/config.toml b/minimal_async_basic/.cargo/config.toml new file mode 100644 index 0000000..7d682db --- /dev/null +++ b/minimal_async_basic/.cargo/config.toml @@ -0,0 +1,43 @@ +[target.thumbv7em-none-eabihf] +# uncomment this to make `cargo run` execute programs on QEMU +# runner = "qemu-system-arm -cpu cortex-m3 -machine lm3s6965evb -nographic -semihosting-config enable=on,target=native -kernel" + +[target.'cfg(all(target_arch = "arm", target_os = "none"))'] +# uncomment ONE of these three option to make `cargo run` start a GDB session +# which option to pick depends on your system +# runner = "arm-none-eabi-gdb -q -x openocd.gdb" +# runner = "gdb-multiarch -q -x openocd.gdb" +# runner = "gdb -q -x openocd.gdb" +rustflags = [ + # This is needed if your flash or ram addresses are not aligned to 0x10000 in memory.x + # See https://github.com/rust-embedded/cortex-m-quickstart/pull/95 + # "-C", "link-arg=--nmagic", + + # LLD (shipped with the Rust toolchain) is used as the default linker + # "-C", "link-arg=-Tgcc_arm.ld", + + # Generate a .map file + # "-C", "link-args=-Map=application.map", + + # if you run into problems with LLD switch to the GNU linker by commenting out + # this line + "-C", "linker=arm-none-eabi-ld", + + # if you need to link to pre-compiled C libraries provided by a C toolchain + # use GCC as the linker by commenting out both lines above and then + # uncommenting the three lines below + "-C", "linker=arm-none-eabi-gcc", + "-C", "link-arg=-Wl,-Tgcc_arm.ld", + "-C", "link-arg=-Wl,-Map,application.map", + "-C", "link-arg=-nostartfiles", +] + +[build] +# Pick ONE of these compilation targets +# target = "thumbv6m-none-eabi" # Cortex-M0 and Cortex-M0+ +# target = "thumbv7m-none-eabi" # Cortex-M3 +# target = "thumbv7em-none-eabi" # Cortex-M4 and Cortex-M7 (no FPU) +target = "thumbv7em-none-eabihf" # Cortex-M4F and Cortex-M7F (with FPU) +# target = "thumbv8m.base-none-eabi" # Cortex-M23 +# target = "thumbv8m.main-none-eabi" # Cortex-M33 (no FPU) +# target = "thumbv8m.main-none-eabihf" # Cortex-M33 (with FPU) diff --git a/minimal_async_basic/.gitignore b/minimal_async_basic/.gitignore new file mode 100644 index 0000000..4145ba0 --- /dev/null +++ b/minimal_async_basic/.gitignore @@ -0,0 +1,6 @@ +# Files +*.map +.vscode/.cortex-debug.* + +# Folders +target diff --git a/minimal_async_basic/.vscode/launch.json b/minimal_async_basic/.vscode/launch.json new file mode 100644 index 0000000..6f4d0f8 --- /dev/null +++ b/minimal_async_basic/.vscode/launch.json @@ -0,0 +1,36 @@ +{ + "configurations": [ + { + "cwd": "${workspaceFolder}", + "executable": "target/thumbv7em-none-eabihf/debug/application", + "configFiles": [ + "stm32l4discovery.cfg" + ], + "postLaunchCommands": [ + "load", + "monitor arm semihosting enable", + ], + "name": "Rust Debug", + "request": "launch", + "type": "cortex-debug", + "servertype": "openocd", + "svdFile": "l0/svd/STM32L4x5.svd", + "svdPath": "l0/svd/STM32L4x5.svd" + }, + { + "cwd": "${workspaceFolder}", + "executable": "target/thumbv7em-none-eabihf/release/application", + "configFiles": [ + "stm32l4discovery.cfg" + ], + "postLaunchCommands": [ + "load", + "monitor arm semihosting enable", + ], + "name": "Rust Release", + "request": "launch", + "type": "cortex-debug", + "servertype": "openocd" + } + ] +} diff --git a/minimal_async_basic/.vscode/settings.json b/minimal_async_basic/.vscode/settings.json new file mode 100644 index 0000000..713dd6a --- /dev/null +++ b/minimal_async_basic/.vscode/settings.json @@ -0,0 +1,12 @@ +{ + "rust-analyzer.cargo.target": "thumbv7em-none-eabihf", + "rust-analyzer.check.allTargets": false, + "rust-analyzer.imports.prefer.no.std": true, + "rust-analyzer.cargo.unsetTest": [ + "core", + "l0", + "l3", + "l5", + "application", + ], +} diff --git a/minimal_async_basic/Cargo.toml b/minimal_async_basic/Cargo.toml new file mode 100644 index 0000000..a1cff08 --- /dev/null +++ b/minimal_async_basic/Cargo.toml @@ -0,0 +1,7 @@ +[workspace] +members = [ + "l0", + "l3", + "l4", + "l5" +] diff --git a/minimal_async_basic/Makefile.toml b/minimal_async_basic/Makefile.toml new file mode 100644 index 0000000..4e5c0ba --- /dev/null +++ b/minimal_async_basic/Makefile.toml @@ -0,0 +1,94 @@ +[config] +default_to_workspace = false + +# Duckscript is used here to convert \ to / for binary output path +[tasks.build_debug] +script_runner = "@duckscript" +script = ''' +output = set ${CARGO_MAKE_CRATE_CUSTOM_TRIPLE_TARGET_DIRECTORY}/debug/application +echo OUTPUT: ${output} +output = replace ${output} \\ / +set_env OUTPUT ${output} +exec cargo build +''' + +# Duckscript is used here to convert \ to / for binary output path +[tasks.build_release] +script_runner = "@duckscript" +script = ''' +output = set ${CARGO_MAKE_CRATE_CUSTOM_TRIPLE_TARGET_DIRECTORY}/release/application +output = replace ${output} \\ / +set_env OUTPUT ${output} +exec cargo build --release +''' + +[tasks.test] +command = "cargo" +args = ["test", "--target", "${CARGO_MAKE_RUST_TARGET_TRIPLE}"] + +[tasks.flash_debug] +script_runner = "@shell" +script = ''' +openocd -f board/stm32l4discovery.cfg -c "program ${OUTPUT} verify reset exit" +''' +dependencies = ["build_debug"] + +[tasks.flash_release] +script_runner = "@shell" +script = ''' +openocd -f board/stm32l4discovery.cfg -c "program ${OUTPUT} verify reset exit" +''' +dependencies = ["build_release"] + +[tasks.ci_debug] +dependencies = [ + "build_debug", + "test", + "objcopy_to_binary", + "objcopy_to_hex", + "objdump", + "size", +] + +[tasks.ci_release] +dependencies = [ + "build_release", + "test", + "objcopy_to_binary", + "objcopy_to_hex", + "objdump", + "size", +] + +# Private Tasks + +# Requires +# arm-none-eabi-size executable (ARM GCC toolchain) +# OUTPUT env variable (Set by build_*) +[tasks.size] +private = true +command = "arm-none-eabi-size" +args = ["${OUTPUT}"] + +# arm-none-eabi-objcopy executable (ARM GCC toolchain) +# OUTPUT env variable (Set by build_*) +[tasks.objcopy_to_binary] +private = true +command = "arm-none-eabi-objcopy" +args = ["-O", "binary", "${OUTPUT}", "${OUTPUT}.bin"] + +# arm-none-eabi-objcopy executable (ARM GCC toolchain) +# OUTPUT env variable (Set by build_*) +[tasks.objcopy_to_hex] +private = true +command = "arm-none-eabi-objcopy" +args = ["-O", "ihex", "${OUTPUT}", "${OUTPUT}.hex"] + +# arm-none-eabi-objdump executable (ARM GCC toolchain) +# OUTPUT env variable (Set by build_*) +[tasks.objdump] +private = true +script_runner = "@shell" +script = ''' +arm-none-eabi-objdump --source --all-headers --demangle --line-numbers --wide ${OUTPUT} > ${OUTPUT}.lst +''' diff --git a/minimal_async_basic/README.md b/minimal_async_basic/README.md new file mode 100644 index 0000000..93b1cb8 --- /dev/null +++ b/minimal_async_basic/README.md @@ -0,0 +1,122 @@ +- [Minimal Interrupt](#minimal-interrupt) + - [Links](#links) + - [Microcontrollers layers](#microcontrollers-layers) + - [Pre-requisites](#pre-requisites) +- [Changelog](#changelog) + - [L0 - Entry](#l0---entry) + - [L0 - Utility](#l0---utility) + - [L0 - Chip](#l0---chip) + - [L0 - Architecture](#l0---architecture) + - [L2 - Utility](#l2---utility) + - [L3 Improvements](#l3-improvements) + - [Hardware](#hardware) + - [Software](#software) + - [L3 - Interface](#l3---interface) + - [L3 - Driver](#l3---driver) + - [L5 - Application](#l5---application) + +# Minimal Interrupt + +This code has been tested on + +- B-L475-IOT01A board (STM32L475VGT6 ARM Cortex M4 CPU with FPU) + +## Links + +- [Cargo binutils](https://github.com/rust-embedded/cargo-binutils) +- [Embedded Rust book](https://doc.rust-lang.org/stable/embedded-book/) +- [Lowlevel Embedded Rust book](https://docs.rust-embedded.org/embedonomicon/) + +## Microcontrollers layers + +- L0 Lowlevel + - Chip Interrupts +- L1 RTOS +- L2 Utility + - Heapless library +- L3 Driver + - Interrupt support for GPIO and USART +- L4 Sensor +- L5 Application + - Interrupt usage + +--- + +## Pre-requisites + +- Pre-requisites from `minimal_driver` + +# Changelog + +## L0 - Entry + +- Updated linker script to remove PROVIDE attributes +- Updated entry point with a better EXCEPTIONS usage + +## L0 - Utility + +- Added `write_assign_register` macro + +## L0 - Chip + +- Updated `controller_init` with `SCB->VTOR = FLASH_BASE` +- Added `attach_interrupt_handler` for STM32L475xx chip + +## L0 - Architecture + +- Added `nvic` module with `enable_irq` function + - NOTE, This has only been added since bindgen cannot parse `static inline` C functions + + +## L2 - Utility + +- Added [heapless](https://crates.io/crates/heapless) library for stack based datastructures + +## L3 Improvements + +### Hardware + +```mermaid +graph BT; + subgraph Port + USART1-3 + subgraph Peripheral + USART + subgraph Register + CR1 + CR2 + RDR + TDR + end + end + end +``` + +### Software + +```mermaid +graph BT; + subgraph Port + USART1-3 + subgraph Peripheral + PolledUSART + BufferedUSART + end + end +``` + +## L3 - Interface + +- Removed `PeripheralConfiguration` trait +- Added `UsartBufferedIn` and `UsartBufferedInOut` trait + +## L3 - Driver + +- Added `USARTBufferedFunction` functionality +- Renamed to `USARTPolledFunction` +- Renamed to `GPIOFunction` + +## L5 - Application + +- Updated example with GPIO Input using interrupt and Atomics +- Updated example with USART Buffered RX and TX using interrupts and static stack allocated lock free queues diff --git a/minimal_async_basic/gcc_arm.ld b/minimal_async_basic/gcc_arm.ld new file mode 100644 index 0000000..5460960 --- /dev/null +++ b/minimal_async_basic/gcc_arm.ld @@ -0,0 +1,423 @@ +/****************************************************************************** + * @file gcc_arm.ld + * @brief GNU Linker Script for Cortex-M based device + * @version V2.0.0 + * @date 21. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + *-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- + */ + +/*---------------------- Flash Configuration ---------------------------------- + Flash Configuration + Flash Base Address <0x0-0xFFFFFFFF:8> + Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> + + -----------------------------------------------------------------------------*/ +__ROM_BASE = 0x08000000; +__ROM_SIZE = 0x00100000; + +/*--------------------- Embedded RAM Configuration ---------------------------- + RAM Configuration + RAM Base Address <0x0-0xFFFFFFFF:8> + RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> + + -----------------------------------------------------------------------------*/ +__RAM_BASE = 0x20000000; +__RAM_SIZE = 0x00018000; + +/*--------------------- Stack / Heap Configuration ---------------------------- + Stack / Heap Configuration + Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> + Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> + + -----------------------------------------------------------------------------*/ +/** +See Diagram below + +FreeRTOS Heap 4 allocated on BSS +FreeRTOS allocation on BSS: 40K +STACK SIZE to 20K +HEAP SIZE to 10K +Remaining unallocated memory = 96 - 40 - 20 - 10 = 26K +DATA and other BSS can consume 26K +**/ +__STACK_SIZE = 20K; +__HEAP_SIZE = 10K; + +/************************************************* + * + 64K RAM +-----Stack Top +-----+ 32K RAM * + | || | | * + | \/ | | * + | | | | * + | | | | * + | /\ heap | /\ * + | || overflow | || * + .-----. +-----Heap Start * + |bbbbb| 0x2000000 * + |bbbbb| *bss * + .-----. * + |ddddd| * + |ddddd| *data * + .-----. * + 0x1000000 * + * +************************************************** +*/ + +/* + *-------------------- <<< end of configuration section >>> ------------------- + */ + +MEMORY +{ + FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE + RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.vector_table.exceptions)) + KEEP(*(.vector_table.interrupts)) + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + /* + * SG veneers: + * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address + * must be set, either with the command line option �--section-start� or in a linker script, + * to indicate where to place these veneers in memory. + */ +/* + .gnu.sgstubs : + { + . = ALIGN(32); + } > FLASH +*/ + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + LONG (__etext) + LONG (__data_start__) + LONG ((__data_end__ - __data_start__) / 4) + /* Add each additional data section here */ +/* + LONG (__etext2) + LONG (__data2_start__) + LONG (__data2_end__ - __data2_start__) +*/ + __copy_table_end__ = .; + } > FLASH + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG ((__bss_end__ - __bss_start__) / 4) + /* Add each additional bss section here */ +/* + LONG (__bss2_start__) + LONG (__bss2_end__ - __bss2_start__) +*/ + __zero_table_end__ = .; + } > FLASH + + /** + * Location counter can end up 2byte aligned with narrow Thumb code but + * __etext is assumed by startup code to be the LMA of a section in RAM + * which must be 4byte aligned + */ + __etext = ALIGN (4); + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data) + *(.data.*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + /* + * Secondary data section, optional + * + * Remember to add each additional data section + * to the .copy.table above to asure proper + * initialization during startup. + */ +/* + __etext2 = ALIGN (4); + + .data2 : AT (__etext2) + { + . = ALIGN(4); + __data2_start__ = .; + *(.data2) + *(.data2.*) + . = ALIGN(4); + __data2_end__ = .; + + } > RAM2 +*/ + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM AT > RAM + + /* + * Secondary bss section, optional + * + * Remember to add each additional bss section + * to the .zero.table above to asure proper + * initialization during startup. + */ +/* + .bss2 : + { + . = ALIGN(4); + __bss2_start__ = .; + *(.bss2) + *(.bss2.*) + . = ALIGN(4); + __bss2_end__ = .; + } > RAM2 AT > RAM2 +*/ + + .heap (COPY) : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + . = . + __HEAP_SIZE; + . = ALIGN(8); + __HeapLimit = .; + } > RAM + + .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE) (COPY) : + { + . = ALIGN(8); + __StackLimit = .; + . = . + __STACK_SIZE; + . = ALIGN(8); + __StackTop = .; + } > RAM + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} + +/* Exceptions */ +PROVIDE(NMI = DefaultExceptionHandler); +PROVIDE(HardFault = DefaultExceptionHandler); +PROVIDE(MemManage = DefaultExceptionHandler); +PROVIDE(BusFault = DefaultExceptionHandler); +PROVIDE(UsageFault = DefaultExceptionHandler); +PROVIDE(SVCall = DefaultExceptionHandler); +PROVIDE(PendSV = DefaultExceptionHandler); +PROVIDE(SysTick = DefaultExceptionHandler); + +/* Interrupts */ +PROVIDE(WWDG_Interrupt_Handler = DefaultExceptionHandler); +PROVIDE(PVD_PVM_Interrupt_Handler = DefaultExceptionHandler); +PROVIDE(RTC_TAMP_STAMP_Interrupt_Handler = DefaultExceptionHandler); +PROVIDE(RTC_WKUP_Interrupt_Handler = DefaultExceptionHandler); +PROVIDE(FLASH_Interrupt_Handler = DefaultExceptionHandler); +PROVIDE(RCC_Interrupt_Handler = DefaultExceptionHandler); +PROVIDE(EXTI0_Interrupt_Handler = DefaultExceptionHandler); +PROVIDE(EXTI1_Interrupt_Handler = DefaultExceptionHandler); +PROVIDE(EXTI2_Interrupt_Handler = DefaultExceptionHandler); +PROVIDE(EXTI3_Interrupt_Handler = DefaultExceptionHandler); +PROVIDE(EXTI4_Interrupt_Handler = DefaultExceptionHandler); +PROVIDE(DMA1_CH1_Interrupt_Handler = DefaultExceptionHandler); +PROVIDE(DMA1_CH2_Interrupt_Handler = DefaultExceptionHandler); +PROVIDE(DMA1_CH3_Interrupt_Handler = DefaultExceptionHandler); +PROVIDE(DMA1_CH4_Interrupt_Handler = DefaultExceptionHandler); +PROVIDE(DMA1_CH5_Interrupt_Handler = DefaultExceptionHandler); +PROVIDE(DMA1_CH6_Interrupt_Handler = DefaultExceptionHandler); +PROVIDE(DMA1_CH7_Interrupt_Handler = DefaultExceptionHandler); +PROVIDE(ADC1_2_Interrupt_Handler = DefaultExceptionHandler); +PROVIDE(CAN1_TX_Interrupt_Handler = DefaultExceptionHandler); +PROVIDE(CAN1_RX0_Interrupt_Handler = DefaultExceptionHandler); +PROVIDE(CAN1_RX1_Interrupt_Handler = DefaultExceptionHandler); +PROVIDE(CAN1_SCE_Interrupt_Handler = DefaultExceptionHandler); +PROVIDE(EXTI9_5_Interrupt_Handler = DefaultExceptionHandler); +PROVIDE(TIM1_BRK_Interrupt_Handler = DefaultExceptionHandler); +PROVIDE(TIM1_UP_Interrupt_Handler = DefaultExceptionHandler); +PROVIDE(TIM1_TRG_COM_Interrupt_Handler = DefaultExceptionHandler); +PROVIDE(TIM1_CC_Interrupt_Handler = DefaultExceptionHandler); +PROVIDE(TIM2_Interrupt_Handler = DefaultExceptionHandler); +PROVIDE(TIM3_Interrupt_Handler = DefaultExceptionHandler); +PROVIDE(TIM4_Interrupt_Handler = DefaultExceptionHandler); +PROVIDE(I2C1_EV_Interrupt_Handler = DefaultExceptionHandler); +PROVIDE(I2C1_ER_Interrupt_Handler = DefaultExceptionHandler); +PROVIDE(I2C2_EV_Interrupt_Handler = DefaultExceptionHandler); +PROVIDE(I2C2_ER_Interrupt_Handler = DefaultExceptionHandler); +PROVIDE(SPI1_Interrupt_Handler = DefaultExceptionHandler); +PROVIDE(SPI2_Interrupt_Handler = DefaultExceptionHandler); +PROVIDE(USART1_Interrupt_Handler = DefaultExceptionHandler); +PROVIDE(USART2_Interrupt_Handler = DefaultExceptionHandler); +PROVIDE(USART3_Interrupt_Handler = DefaultExceptionHandler); +PROVIDE(EXTI15_10_Interrupt_Handler = DefaultExceptionHandler); +PROVIDE(RTC_ALARM_Interrupt_Handler = DefaultExceptionHandler); +PROVIDE(DFSDM1_FLT3_Interrupt_Handler = DefaultExceptionHandler); +PROVIDE(TIM8_BRK_Interrupt_Handler = DefaultExceptionHandler); +PROVIDE(TIM8_UP_Interrupt_Handler = DefaultExceptionHandler); +PROVIDE(TIM8_TRG_COM_Interrupt_Handler = DefaultExceptionHandler); +PROVIDE(TIM8_CC_Interrupt_Handler = DefaultExceptionHandler); +PROVIDE(ADC3_Interrupt_Handler = DefaultExceptionHandler); +PROVIDE(FMC_Interrupt_Handler = DefaultExceptionHandler); +PROVIDE(SDMMC1_Interrupt_Handler = DefaultExceptionHandler); +PROVIDE(TIM5_Interrupt_Handler = DefaultExceptionHandler); +PROVIDE(SPI3_Interrupt_Handler = DefaultExceptionHandler); +PROVIDE(UART4_Interrupt_Handler = DefaultExceptionHandler); +PROVIDE(UART5_Interrupt_Handler = DefaultExceptionHandler); +PROVIDE(TIM6_DAC_Interrupt_Handler = DefaultExceptionHandler); +PROVIDE(TIM7_Interrupt_Handler = DefaultExceptionHandler); +PROVIDE(DMA2_CH1_Interrupt_Handler = DefaultExceptionHandler); +PROVIDE(DMA2_CH2_Interrupt_Handler = DefaultExceptionHandler); +PROVIDE(DMA2_CH3_Interrupt_Handler = DefaultExceptionHandler); +PROVIDE(DMA2_CH4_Interrupt_Handler = DefaultExceptionHandler); +PROVIDE(DMA2_CH5_Interrupt_Handler = DefaultExceptionHandler); +PROVIDE(DFSDM1_FLT0_Interrupt_Handler = DefaultExceptionHandler); +PROVIDE(DFSDM1_FLT1_Interrupt_Handler = DefaultExceptionHandler); +PROVIDE(DFSDM1_FLT2_Interrupt_Handler = DefaultExceptionHandler); +PROVIDE(COMP_Interrupt_Handler = DefaultExceptionHandler); +PROVIDE(LPTIM1_Interrupt_Handler = DefaultExceptionHandler); +PROVIDE(LPTIM2_Interrupt_Handler = DefaultExceptionHandler); +PROVIDE(OTG_FS_Interrupt_Handler = DefaultExceptionHandler); +PROVIDE(DMA2_CH6_Interrupt_Handler = DefaultExceptionHandler); +PROVIDE(DMA2_CH7_Interrupt_Handler = DefaultExceptionHandler); +PROVIDE(LPUART1_Interrupt_Handler = DefaultExceptionHandler); +PROVIDE(QUADSPI_Interrupt_Handler = DefaultExceptionHandler); +PROVIDE(I2C3_EV_Interrupt_Handler = DefaultExceptionHandler); +PROVIDE(I2C3_ER_Interrupt_Handler = DefaultExceptionHandler); +PROVIDE(SAI1_Interrupt_Handler = DefaultExceptionHandler); +PROVIDE(SAI2_Interrupt_Handler = DefaultExceptionHandler); +PROVIDE(SWPMI1_Interrupt_Handler = DefaultExceptionHandler); +PROVIDE(TSC_Interrupt_Handler = DefaultExceptionHandler); +PROVIDE(LCD_Interrupt_Handler = DefaultExceptionHandler); +PROVIDE(AES_Interrupt_Handler = DefaultExceptionHandler); +PROVIDE(RNG_Interrupt_Handler = DefaultExceptionHandler); +PROVIDE(FPU_Interrupt_Handler = DefaultExceptionHandler); diff --git a/minimal_async_basic/l0/.gitignore b/minimal_async_basic/l0/.gitignore new file mode 100644 index 0000000..e133420 --- /dev/null +++ b/minimal_async_basic/l0/.gitignore @@ -0,0 +1,2 @@ +# This file is generated by build.rs +src/stm32l475xx/controller.rs diff --git a/minimal_async_basic/l0/Cargo.toml b/minimal_async_basic/l0/Cargo.toml new file mode 100644 index 0000000..bd0bdf2 --- /dev/null +++ b/minimal_async_basic/l0/Cargo.toml @@ -0,0 +1,13 @@ +[package] +name = "l0" +version = "0.1.0" +authors = ["Niket Naidu "] +edition = "2021" +readme = "README.md" + +# See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html + +[dependencies] + +[build-dependencies] +bindgen = "0.63.0" diff --git a/minimal_async_basic/l0/build.rs b/minimal_async_basic/l0/build.rs new file mode 100644 index 0000000..155fd78 --- /dev/null +++ b/minimal_async_basic/l0/build.rs @@ -0,0 +1,48 @@ +use std::{env, path::PathBuf}; + +fn parse_header(input_filename: &str, output_path: &PathBuf) { + let target = env::var_os("TARGET").expect("Expects environment variable TARGET"); + println!("Target: {:?}", target); + + // Convert c header to rust using bindgen + let bindings = bindgen::Builder::default() + .header(input_filename) + .clang_arg("-Idevice") + .clang_arg("-Idevice/cmsis") + .clang_arg("-Idevice/controller") + .clang_arg(format!("--target={}", target.to_str().unwrap())) + .layout_tests(false) + .use_core() + .wrap_unsafe_ops(true) + .translate_enum_integer_types(true) + .explicit_padding(false) + .generate_block(true) + .default_enum_style(bindgen::EnumVariation::ModuleConsts) + .parse_callbacks(Box::new(bindgen::CargoCallbacks)) + .generate() + .expect("Unable to generate bindings"); + + // Write to output + bindings + .write_to_file(output_path) + .expect("Couldn't write bindings!"); +} + +fn main() { + // Parse headers only for valid on-target microcontrollers + let target = env::var_os("TARGET").expect("Expects environment variable TARGET"); + let should_parse = match target.to_str().unwrap() { + "thumbv7em-none-eabihf" => true, + _ => false, + }; + + // TODO, Make this user configurable to support multiple microcontroller formats + // NOTE, This controller.rs contains both + // - Architecture considerations (ARM specific peripherals) + // - Microcontroller considerations (STM32 specific peripherals) + const PARSE_INPUT_FILE: &str = "device/controller/stm32l475xx.h"; + const OUTPUT_FILE: &str = "src/stm32l475xx/controller.rs"; + if should_parse { + parse_header(PARSE_INPUT_FILE, &PathBuf::from(OUTPUT_FILE)); + } +} diff --git a/minimal_async_basic/l0/device/cmsis/cmsis_compiler.h b/minimal_async_basic/l0/device/cmsis/cmsis_compiler.h new file mode 100644 index 0000000..94212eb --- /dev/null +++ b/minimal_async_basic/l0/device/cmsis/cmsis_compiler.h @@ -0,0 +1,266 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/minimal_async_basic/l0/device/cmsis/cmsis_gcc.h b/minimal_async_basic/l0/device/cmsis/cmsis_gcc.h new file mode 100644 index 0000000..2e14533 --- /dev/null +++ b/minimal_async_basic/l0/device/cmsis/cmsis_gcc.h @@ -0,0 +1,2311 @@ +/**************************************************************************/ /** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.0.4 + * @date 09. April 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin +#define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM +#define __ASM __asm +#endif +#ifndef __INLINE +#define __INLINE inline +#endif +#ifndef __STATIC_INLINE +#define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE +#define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN +#define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED +#define __USED __attribute__((used)) +#endif +#ifndef __WEAK +#define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED +#define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT +#define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION +#define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpacked" +#pragma GCC diagnostic ignored "-Wattributes" +struct __attribute__((packed)) T_UINT32 +{ + uint32_t v; +}; +#pragma GCC diagnostic pop +#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpacked" +#pragma GCC diagnostic ignored "-Wattributes" +__PACKED_STRUCT T_UINT16_WRITE +{ + uint16_t v; +}; +#pragma GCC diagnostic pop +#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpacked" +#pragma GCC diagnostic ignored "-Wattributes" +__PACKED_STRUCT T_UINT16_READ +{ + uint16_t v; +}; +#pragma GCC diagnostic pop +#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpacked" +#pragma GCC diagnostic ignored "-Wattributes" +__PACKED_STRUCT T_UINT32_WRITE +{ + uint32_t v; +}; +#pragma GCC diagnostic pop +#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpacked" +#pragma GCC diagnostic ignored "-Wattributes" +__PACKED_STRUCT T_UINT32_READ +{ + uint32_t v; +}; +#pragma GCC diagnostic pop +#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED +#define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT +#define __RESTRICT __restrict +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile("cpsie i" + : + : + : "memory"); +} + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile("cpsid i" + : + : + : "memory"); +} + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile("MRS %0, control" + : "=r"(result)); + return (result); +} + +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile("MRS %0, control_ns" + : "=r"(result)); + return (result); +} +#endif + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile("MSR control, %0" + : + : "r"(control) + : "memory"); +} + +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile("MSR control_ns, %0" + : + : "r"(control) + : "memory"); +} +#endif + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile("MRS %0, ipsr" + : "=r"(result)); + return (result); +} + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile("MRS %0, apsr" + : "=r"(result)); + return (result); +} + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile("MRS %0, xpsr" + : "=r"(result)); + return (result); +} + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile("MRS %0, psp" + : "=r"(result)); + return (result); +} + +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile("MRS %0, psp_ns" + : "=r"(result)); + return (result); +} +#endif + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile("MSR psp, %0" + : + : "r"(topOfProcStack) + :); +} + +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile("MSR psp_ns, %0" + : + : "r"(topOfProcStack) + :); +} +#endif + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile("MRS %0, msp" + : "=r"(result)); + return (result); +} + +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile("MRS %0, msp_ns" + : "=r"(result)); + return (result); +} +#endif + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile("MSR msp, %0" + : + : "r"(topOfMainStack) + :); +} + +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile("MSR msp_ns, %0" + : + : "r"(topOfMainStack) + :); +} +#endif + +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile("MRS %0, sp_ns" + : "=r"(result)); + return (result); +} + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile("MSR sp_ns, %0" + : + : "r"(topOfStack) + :); +} +#endif + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile("MRS %0, primask" + : "=r"(result)::"memory"); + return (result); +} + +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile("MRS %0, primask_ns" + : "=r"(result)::"memory"); + return (result); +} +#endif + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile("MSR primask, %0" + : + : "r"(priMask) + : "memory"); +} + +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile("MSR primask_ns, %0" + : + : "r"(priMask) + : "memory"); +} +#endif + +#if ((defined(__ARM_ARCH_7M__) && (__ARM_ARCH_7M__ == 1)) || \ + (defined(__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile("cpsie f" + : + : + : "memory"); +} + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile("cpsid f" + : + : + : "memory"); +} + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile("MRS %0, basepri" + : "=r"(result)); + return (result); +} + +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile("MRS %0, basepri_ns" + : "=r"(result)); + return (result); +} +#endif + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile("MSR basepri, %0" + : + : "r"(basePri) + : "memory"); +} + +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile("MSR basepri_ns, %0" + : + : "r"(basePri) + : "memory"); +} +#endif + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile("MSR basepri_max, %0" + : + : "r"(basePri) + : "memory"); +} + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile("MRS %0, faultmask" + : "=r"(result)); + return (result); +} + +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile("MRS %0, faultmask_ns" + : "=r"(result)); + return (result); +} +#endif + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile("MSR faultmask, %0" + : + : "r"(faultMask) + : "memory"); +} + +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile("MSR faultmask_ns, %0" + : + : "r"(faultMask) + : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +#if ((defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ == 1))) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined(__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile("MRS %0, psplim" + : "=r"(result)); + return result; +#endif +} + +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile("MRS %0, psplim_ns" + : "=r"(result)); + return result; +#endif +} +#endif + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined(__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile("MSR psplim, %0" + : + : "r"(ProcStackPtrLimit)); +#endif +} + +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile("MSR psplim_ns, %0\n" + : + : "r"(ProcStackPtrLimit)); +#endif +} +#endif + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined(__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile("MRS %0, msplim" + : "=r"(result)); + return result; +#endif +} + +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile("MRS %0, msplim_ns" + : "=r"(result)); + return result; +#endif +} +#endif + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined(__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile("MSR msplim, %0" + : + : "r"(MainStackPtrLimit)); +#endif +} + +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile("MSR msplim_ns, %0" + : + : "r"(MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined(__FPU_USED) && (__FPU_USED == 1U))) +#if __has_builtin(__builtin_arm_get_fpscr) + // Re-enable using built-in when GCC has been fixed + // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile("VMRS %0, fpscr" + : "=r"(result)); + return (result); +#endif +#else + return (0U); +#endif +} + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined(__FPU_USED) && (__FPU_USED == 1U))) +#if __has_builtin(__builtin_arm_set_fpscr) + // Re-enable using built-in when GCC has been fixed + // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile("VMSR fpscr, %0" + : + : "r"(fpscr) + : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + +/*@} end of CMSIS_Core_RegAccFunctions */ + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined(__thumb__) && !defined(__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l"(r) +#define __CMSIS_GCC_RW_REG(r) "+l"(r) +#define __CMSIS_GCC_USE_REG(r) "l"(r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r"(r) +#define __CMSIS_GCC_RW_REG(r) "+r"(r) +#define __CMSIS_GCC_USE_REG(r) "r"(r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile("wfi") + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile("wfe") + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile("sev") + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile("isb 0xF" :: + : "memory"); +} + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile("dsb 0xF" :: + : "memory"); +} + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile("dmb 0xF" :: + : "memory"); +} + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile("rev %0, %1" + : __CMSIS_GCC_OUT_REG(result) + : __CMSIS_GCC_USE_REG(value)); + return result; +#endif +} + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile("rev16 %0, %1" + : __CMSIS_GCC_OUT_REG(result) + : __CMSIS_GCC_USE_REG(value)); + return result; +} + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM volatile("revsh %0, %1" + : __CMSIS_GCC_OUT_REG(result) + : __CMSIS_GCC_USE_REG(value)); + return result; +#endif +} + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile("bkpt " #value) + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined(__ARM_ARCH_7M__) && (__ARM_ARCH_7M__ == 1)) || \ + (defined(__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))) + __ASM volatile("rbit %0, %1" + : "=r"(result) + : "r"(value)); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ (uint8_t) __builtin_clz + +#if ((defined(__ARM_ARCH_7M__) && (__ARM_ARCH_7M__ == 1)) || \ + (defined(__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ == 1))) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile("ldrexb %0, %1" + : "=r"(result) + : "Q"(*addr)); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile("ldrexb %0, [%1]" + : "=r"(result) + : "r"(addr) + : "memory"); +#endif + return ((uint8_t)result); /* Add explicit type cast here */ +} + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile("ldrexh %0, %1" + : "=r"(result) + : "Q"(*addr)); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile("ldrexh %0, [%1]" + : "=r"(result) + : "r"(addr) + : "memory"); +#endif + return ((uint16_t)result); /* Add explicit type cast here */ +} + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile("ldrex %0, %1" + : "=r"(result) + : "Q"(*addr)); + return (result); +} + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile("strexb %0, %2, %1" + : "=&r"(result), "=Q"(*addr) + : "r"((uint32_t)value)); + return (result); +} + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile("strexh %0, %2, %1" + : "=&r"(result), "=Q"(*addr) + : "r"((uint32_t)value)); + return (result); +} + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile("strex %0, %2, %1" + : "=&r"(result), "=Q"(*addr) + : "r"(value)); + return (result); +} + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile("clrex" :: + : "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +#if ((defined(__ARM_ARCH_7M__) && (__ARM_ARCH_7M__ == 1)) || \ + (defined(__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1))) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1, ARG2) \ + __extension__({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM("ssat %0, %1, %2" \ + : "=r"(__RES) \ + : "I"(ARG2), "r"(__ARG1)); \ + __RES; \ + }) + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1, ARG2) \ + __extension__({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM("usat %0, %1, %2" \ + : "=r"(__RES) \ + : "I"(ARG2), "r"(__ARG1)); \ + __RES; \ + }) + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile("rrx %0, %1" + : __CMSIS_GCC_OUT_REG(result) + : __CMSIS_GCC_USE_REG(value)); + return (result); +} + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile("ldrbt %0, %1" + : "=r"(result) + : "Q"(*ptr)); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile("ldrbt %0, [%1]" + : "=r"(result) + : "r"(ptr) + : "memory"); +#endif + return ((uint8_t)result); /* Add explicit type cast here */ +} + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile("ldrht %0, %1" + : "=r"(result) + : "Q"(*ptr)); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile("ldrht %0, [%1]" + : "=r"(result) + : "r"(ptr) + : "memory"); +#endif + return ((uint16_t)result); /* Add explicit type cast here */ +} + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile("ldrt %0, %1" + : "=r"(result) + : "Q"(*ptr)); + return (result); +} + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile("strbt %1, %0" + : "=Q"(*ptr) + : "r"((uint32_t)value)); +} + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile("strht %1, %0" + : "=Q"(*ptr) + : "r"((uint32_t)value)); +} + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile("strt %1, %0" + : "=Q"(*ptr) + : "r"(value)); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +#if ((defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ == 1))) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile("ldab %0, %1" + : "=r"(result) + : "Q"(*ptr)); + return ((uint8_t)result); +} + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile("ldah %0, %1" + : "=r"(result) + : "Q"(*ptr)); + return ((uint16_t)result); +} + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile("lda %0, %1" + : "=r"(result) + : "Q"(*ptr)); + return (result); +} + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile("stlb %1, %0" + : "=Q"(*ptr) + : "r"((uint32_t)value)); +} + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile("stlh %1, %0" + : "=Q"(*ptr) + : "r"((uint32_t)value)); +} + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile("stl %1, %0" + : "=Q"(*ptr) + : "r"((uint32_t)value)); +} + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile("ldaexb %0, %1" + : "=r"(result) + : "Q"(*ptr)); + return ((uint8_t)result); +} + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile("ldaexh %0, %1" + : "=r"(result) + : "Q"(*ptr)); + return ((uint16_t)result); +} + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile("ldaex %0, %1" + : "=r"(result) + : "Q"(*ptr)); + return (result); +} + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile("stlexb %0, %2, %1" + : "=&r"(result), "=Q"(*ptr) + : "r"((uint32_t)value)); + return (result); +} + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile("stlexh %0, %2, %1" + : "=&r"(result), "=Q"(*ptr) + : "r"((uint32_t)value)); + return (result); +} + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile("stlex %0, %2, %1" + : "=&r"(result), "=Q"(*ptr) + : "r"((uint32_t)value)); + return (result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined(__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("sadd8 %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("qadd8 %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("shadd8 %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uadd8 %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uqadd8 %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uhadd8 %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("ssub8 %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("qsub8 %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("shsub8 %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("usub8 %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uqsub8 %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uhsub8 %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("sadd16 %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("qadd16 %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("shadd16 %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uadd16 %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uqadd16 %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uhadd16 %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("ssub16 %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("qsub16 %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("shsub16 %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("usub16 %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uqsub16 %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uhsub16 %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("sasx %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("qasx %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("shasx %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uasx %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uqasx %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uhasx %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("ssax %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("qsax %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("shsax %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("usax %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uqsax %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uhsax %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("usad8 %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile("usada8 %0, %1, %2, %3" + : "=r"(result) + : "r"(op1), "r"(op2), "r"(op3)); + return (result); +} + +#define __SSAT16(ARG1, ARG2) \ + ({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM("ssat16 %0, %1, %2" \ + : "=r"(__RES) \ + : "I"(ARG2), "r"(__ARG1)); \ + __RES; \ + }) + +#define __USAT16(ARG1, ARG2) \ + ({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM("usat16 %0, %1, %2" \ + : "=r"(__RES) \ + : "I"(ARG2), "r"(__ARG1)); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile("uxtb16 %0, %1" + : "=r"(result) + : "r"(op1)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uxtab16 %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile("sxtb16 %0, %1" + : "=r"(result) + : "r"(op1)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("sxtab16 %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("smuad %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("smuadx %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile("smlad %0, %1, %2, %3" + : "=r"(result) + : "r"(op1), "r"(op2), "r"(op3)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile("smladx %0, %1, %2, %3" + : "=r"(result) + : "r"(op1), "r"(op2), "r"(op3)); + return (result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD(uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u + { + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile("smlald %0, %1, %2, %3" + : "=r"(llr.w32[0]), "=r"(llr.w32[1]) + : "r"(op1), "r"(op2), "0"(llr.w32[0]), "1"(llr.w32[1])); +#else /* Big endian */ + __ASM volatile("smlald %0, %1, %2, %3" + : "=r"(llr.w32[1]), "=r"(llr.w32[0]) + : "r"(op1), "r"(op2), "0"(llr.w32[1]), "1"(llr.w32[0])); +#endif + + return (llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX(uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u + { + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile("smlaldx %0, %1, %2, %3" + : "=r"(llr.w32[0]), "=r"(llr.w32[1]) + : "r"(op1), "r"(op2), "0"(llr.w32[0]), "1"(llr.w32[1])); +#else /* Big endian */ + __ASM volatile("smlaldx %0, %1, %2, %3" + : "=r"(llr.w32[1]), "=r"(llr.w32[0]) + : "r"(op1), "r"(op2), "0"(llr.w32[1]), "1"(llr.w32[0])); +#endif + + return (llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("smusd %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("smusdx %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile("smlsd %0, %1, %2, %3" + : "=r"(result) + : "r"(op1), "r"(op2), "r"(op3)); + return (result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile("smlsdx %0, %1, %2, %3" + : "=r"(result) + : "r"(op1), "r"(op2), "r"(op3)); + return (result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD(uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u + { + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile("smlsld %0, %1, %2, %3" + : "=r"(llr.w32[0]), "=r"(llr.w32[1]) + : "r"(op1), "r"(op2), "0"(llr.w32[0]), "1"(llr.w32[1])); +#else /* Big endian */ + __ASM volatile("smlsld %0, %1, %2, %3" + : "=r"(llr.w32[1]), "=r"(llr.w32[0]) + : "r"(op1), "r"(op2), "0"(llr.w32[1]), "1"(llr.w32[0])); +#endif + + return (llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX(uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u + { + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile("smlsldx %0, %1, %2, %3" + : "=r"(llr.w32[0]), "=r"(llr.w32[1]) + : "r"(op1), "r"(op2), "0"(llr.w32[0]), "1"(llr.w32[1])); +#else /* Big endian */ + __ASM volatile("smlsldx %0, %1, %2, %3" + : "=r"(llr.w32[1]), "=r"(llr.w32[0]) + : "r"(op1), "r"(op2), "0"(llr.w32[1]), "1"(llr.w32[0])); +#endif + + return (llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("sel %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE int32_t __QADD(int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile("qadd %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); +} + +__STATIC_FORCEINLINE int32_t __QSUB(int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile("qsub %0, %1, %2" + : "=r"(result) + : "r"(op1), "r"(op2)); + return (result); +} + +#if 0 +#define __PKHBT(ARG1, ARG2, ARG3) \ + ({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM("pkhbt %0, %1, %2, lsl %3" \ + : "=r"(__RES) \ + : "r"(__ARG1), "r"(__ARG2), "I"(ARG3)); \ + __RES; \ + }) + +#define __PKHTB(ARG1, ARG2, ARG3) \ + ({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM("pkhtb %0, %1, %2" \ + : "=r"(__RES) \ + : "r"(__ARG1), "r"(__ARG2)); \ + else \ + __ASM("pkhtb %0, %1, %2, asr %3" \ + : "=r"(__RES) \ + : "r"(__ARG1), "r"(__ARG2), "I"(ARG3)); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1, ARG2, ARG3) (((((uint32_t)(ARG1))) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)) + +#define __PKHTB(ARG1, ARG2, ARG3) (((((uint32_t)(ARG1))) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)) + +__STATIC_FORCEINLINE int32_t __SMMLA(int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile("smmla %0, %1, %2, %3" + : "=r"(result) + : "r"(op1), "r"(op2), "r"(op3)); + return (result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/minimal_async_basic/l0/device/cmsis/cmsis_version.h b/minimal_async_basic/l0/device/cmsis/cmsis_version.h new file mode 100644 index 0000000..660f612 --- /dev/null +++ b/minimal_async_basic/l0/device/cmsis/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.2 + * @date 19. April 2017 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/minimal_async_basic/l0/device/cmsis/core_cm4.h b/minimal_async_basic/l0/device/cmsis/core_cm4.h new file mode 100644 index 0000000..7d56873 --- /dev/null +++ b/minimal_async_basic/l0/device/cmsis/core_cm4.h @@ -0,0 +1,2129 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 04. June 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (4U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000U + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/minimal_async_basic/l0/device/cmsis/mpu_armv7.h b/minimal_async_basic/l0/device/cmsis/mpu_armv7.h new file mode 100644 index 0000000..0142203 --- /dev/null +++ b/minimal_async_basic/l0/device/cmsis/mpu_armv7.h @@ -0,0 +1,270 @@ +/****************************************************************************** + * @file mpu_armv7.h + * @brief CMSIS MPU API for Armv7-M MPU + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes + +#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access +#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only +#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only +#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access +#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only +#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Memory Access Attributes +* +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +*/ +#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ + ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ + ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) + +/** +* MPU Memory Access Attribute for strongly ordered memory. +* - TEX: 000b +* - Shareable +* - Non-cacheable +* - Non-bufferable +*/ +#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) + +/** +* MPU Memory Access Attribute for device memory. +* - TEX: 000b (if non-shareable) or 010b (if shareable) +* - Shareable or non-shareable +* - Non-cacheable +* - Bufferable (if shareable) or non-bufferable (if non-shareable) +* +* \param IsShareable Configures the device memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) + +/** +* MPU Memory Access Attribute for normal memory. +* - TEX: 1BBb (reflecting outer cacheability rules) +* - Shareable or non-shareable +* - Cacheable or non-cacheable (reflecting inner cacheability rules) +* - Bufferable or non-bufferable (reflecting inner cacheability rules) +* +* \param OuterCp Configures the outer cache policy. +* \param InnerCp Configures the inner cache policy. +* \param IsShareable Configures the memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U)) + +/** +* MPU Memory Access Attribute non-cacheable policy. +*/ +#define ARM_MPU_CACHEP_NOCACHE 0U + +/** +* MPU Memory Access Attribute write-back, write and read allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_WRA 1U + +/** +* MPU Memory Access Attribute write-through, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WT_NWA 2U + +/** +* MPU Memory Access Attribute write-back, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_NWA 3U + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DSB(); + __ISB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DSB(); + __ISB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif diff --git a/minimal_async_basic/l0/device/controller/stm32l475xx.h b/minimal_async_basic/l0/device/controller/stm32l475xx.h new file mode 100644 index 0000000..ae97097 --- /dev/null +++ b/minimal_async_basic/l0/device/controller/stm32l475xx.h @@ -0,0 +1,22688 @@ +/** + ****************************************************************************** + * @file stm32l475xx.h + * @author MCD Application Team + * @brief CMSIS STM32L475xx Device Peripheral Access Layer Header File. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral�s registers hardware + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32l475xx + * @{ + */ + +#ifndef __STM32L475xx_H +#define __STM32L475xx_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ +#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */ +#define __MPU_PRESENT 1 /*!< STM32L4XX provides an MPU */ +#define __NVIC_PRIO_BITS \ + 4 /*!< STM32L4XX uses 4 Bits for the Priority Levels \ + */ +#define __Vendor_SysTickConfig \ + 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present */ + +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32L4XX Interrupt Number Definition, according to the selected + * device in @ref Library_configuration_section + */ +typedef enum { + /****** Cortex-M4 Processor Exceptions Numbers + ****************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ + /****** STM32 specific Interrupt Numbers + **********************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_PVM_IRQn = + 1, /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection Interrupts */ + TAMP_STAMP_IRQn = + 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ + DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ + DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ + DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ + DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ + DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ + DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ + ADC1_2_IRQn = 18, /*!< ADC1, ADC2 SAR global Interrupts */ + CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ + CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM15_IRQn = + 24, /*!< TIM1 Break interrupt and TIM15 global interrupt */ + TIM1_UP_TIM16_IRQn = + 25, /*!< TIM1 Update Interrupt and TIM16 global interrupt */ + TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and + TIM17 global interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ + DFSDM1_FLT3_IRQn = 42, /*!< DFSDM1 Filter 3 global Interrupt */ + TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */ + TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */ + TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + ADC3_IRQn = 47, /*!< ADC3 global Interrupt */ + FMC_IRQn = 48, /*!< FMC global Interrupt */ + SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ + TIM7_IRQn = 55, /*!< TIM7 global interrupt */ + DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */ + DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */ + DFSDM1_FLT0_IRQn = 61, /*!< DFSDM1 Filter 0 global Interrupt */ + DFSDM1_FLT1_IRQn = 62, /*!< DFSDM1 Filter 1 global Interrupt */ + DFSDM1_FLT2_IRQn = 63, /*!< DFSDM1 Filter 2 global Interrupt */ + COMP_IRQn = 64, /*!< COMP1 and COMP2 Interrupts */ + LPTIM1_IRQn = 65, /*!< LP TIM1 interrupt */ + LPTIM2_IRQn = 66, /*!< LP TIM2 interrupt */ + OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ + DMA2_Channel6_IRQn = 68, /*!< DMA2 Channel 6 global interrupt */ + DMA2_Channel7_IRQn = 69, /*!< DMA2 Channel 7 global interrupt */ + LPUART1_IRQn = 70, /*!< LP UART1 interrupt */ + QUADSPI_IRQn = 71, /*!< Quad SPI global interrupt */ + I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ + SAI1_IRQn = 74, /*!< Serial Audio Interface 1 global interrupt */ + SAI2_IRQn = 75, /*!< Serial Audio Interface 2 global interrupt */ + SWPMI1_IRQn = 76, /*!< Serial Wire Interface 1 global interrupt */ + TSC_IRQn = 77, /*!< Touch Sense Controller global interrupt */ + RNG_IRQn = 80, /*!< RNG global interrupt */ + FPU_IRQn = 81 /*!< FPU global interrupt */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct { + __IO uint32_t ISR; /*!< ADC interrupt and status register, Address + offset: 0x00 */ + __IO uint32_t IER; /*!< ADC interrupt enable register, Address + offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address + offset: 0x08 */ + __IO uint32_t CFGR; /*!< ADC configuration register 1, Address offset: 0x0C */ + __IO uint32_t + CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ + __IO uint32_t + SMPR1; /*!< ADC sampling time register 1, Address offset: 0x14 */ + __IO uint32_t + SMPR2; /*!< ADC sampling time register 2, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved, 0x1C */ + __IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address + offset: 0x20 */ + __IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address + offset: 0x24 */ + __IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address + offset: 0x28 */ + uint32_t RESERVED2; /*!< Reserved, 0x2C */ + __IO uint32_t SQR1; /*!< ADC group regular sequencer register 1, Address + offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC group regular sequencer register 2, Address + offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC group regular sequencer register 3, Address + offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC group regular sequencer register 4, Address + offset: 0x3C */ + __IO uint32_t DR; /*!< ADC group regular data register, Address + offset: 0x40 */ + uint32_t RESERVED3; /*!< Reserved, 0x44 */ + uint32_t RESERVED4; /*!< Reserved, 0x48 */ + __IO uint32_t JSQR; /*!< ADC group injected sequencer register, Address + offset: 0x4C */ + uint32_t RESERVED5[4]; /*!< Reserved, 0x50 - 0x5C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ + uint32_t RESERVED6[4]; /*!< Reserved, 0x70 - 0x7C */ + __IO uint32_t JDR1; /*!< ADC group injected rank 1 data register, Address + offset: 0x80 */ + __IO uint32_t JDR2; /*!< ADC group injected rank 2 data register, Address + offset: 0x84 */ + __IO uint32_t JDR3; /*!< ADC group injected rank 3 data register, Address + offset: 0x88 */ + __IO uint32_t JDR4; /*!< ADC group injected rank 4 data register, Address + offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC analog watchdog 1 configuration register, + Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 Configuration Register, + Address offset: 0xA4 */ + uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ + uint32_t RESERVED9; /*!< Reserved, 0x0AC */ + __IO uint32_t DIFSEL; /*!< ADC differential mode selection register, Address + offset: 0xB0 */ + __IO uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0xB4 */ + +} ADC_TypeDef; + +typedef struct { + __IO uint32_t CSR; /*!< ADC common status register, Address + offset: ADC1 base address + 0x300 */ + uint32_t RESERVED; /*!< Reserved, Address + offset: ADC1 base address + 0x304 */ + __IO uint32_t CCR; /*!< ADC common configuration register, Address + offset: ADC1 base address + 0x308 */ + __IO uint32_t CDR; /*!< ADC common group regular data register Address + offset: ADC1 base address + 0x30C */ +} ADC_Common_TypeDef; + +/** + * @brief Controller Area Network TxMailBox + */ + +typedef struct { + __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ + __IO uint32_t + TDTR; /*!< CAN mailbox data length control and time stamp register */ + __IO uint32_t TDLR; /*!< CAN mailbox data low register */ + __IO uint32_t TDHR; /*!< CAN mailbox data high register */ +} CAN_TxMailBox_TypeDef; + +/** + * @brief Controller Area Network FIFOMailBox + */ + +typedef struct { + __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ + __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time + stamp register */ + __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ + __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ +} CAN_FIFOMailBox_TypeDef; + +/** + * @brief Controller Area Network FilterRegister + */ + +typedef struct { + __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ + __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ +} CAN_FilterRegister_TypeDef; + +/** + * @brief Controller Area Network + */ + +typedef struct { + __IO uint32_t + MCR; /*!< CAN master control register, Address offset: 0x00 */ + __IO uint32_t + MSR; /*!< CAN master status register, Address offset: 0x04 */ + __IO uint32_t + TSR; /*!< CAN transmit status register, Address offset: 0x08 */ + __IO uint32_t + RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ + __IO uint32_t + RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ + __IO uint32_t + IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ + __IO uint32_t + ESR; /*!< CAN error status register, Address offset: 0x18 */ + __IO uint32_t + BTR; /*!< CAN bit timing register, Address offset: 0x1C */ + uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ + CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: + 0x180 - 0x1AC */ + CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address + offset: 0x1B0 - 0x1CC */ + uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ + __IO uint32_t + FMR; /*!< CAN filter master register, Address offset: 0x200 */ + __IO uint32_t + FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ + uint32_t RESERVED2; /*!< Reserved, 0x208 */ + __IO uint32_t + FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ + uint32_t RESERVED3; /*!< Reserved, 0x210 */ + __IO uint32_t + FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ + uint32_t RESERVED4; /*!< Reserved, 0x218 */ + __IO uint32_t + FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ + uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ + CAN_FilterRegister_TypeDef + sFilterRegister[28]; /*!< CAN Filter Register, Address + offset: 0x240-0x31C */ +} CAN_TypeDef; + +/** + * @brief Comparator + */ + +typedef struct { + __IO uint32_t + CSR; /*!< COMP control and status register, Address offset: 0x00 */ +} COMP_TypeDef; + +typedef struct { + __IO uint32_t CSR; /*!< COMP control and status register, used for bits common + to several COMP instances, Address offset: 0x00 */ +} COMP_Common_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct { + __IO uint32_t DR; /*!< CRC Data register, Address + offset: 0x00 */ + __IO uint8_t IDR; /*!< CRC Independent data register, Address + offset: 0x04 */ + uint8_t RESERVED0; /*!< Reserved, 0x05 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint32_t CR; /*!< CRC Control register, Address + offset: 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address + offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address + offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Digital to Analog Converter + */ + +typedef struct { + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t + SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding + register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding + register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding + register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding + register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding + register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding + register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding + register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding + register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, + Address offset: 0x28 */ + __IO uint32_t + DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t + DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 + */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address + offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address + offset: 0x44 */ + __IO uint32_t + SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address + offset: 0x4C */ +} DAC_TypeDef; + +/** + * @brief DFSDM module registers + */ +typedef struct { + __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */ + __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */ + __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address + offset: 0x108 */ + __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address + offset: 0x10C */ + __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, + Address offset: 0x110 */ + __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: + 0x114 */ + __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address + offset: 0x118 */ + __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address + offset: 0x11C */ + __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, + Address offset: 0x120 */ + __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, + Address offset: 0x124 */ + __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address + offset: 0x128 */ + __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address + offset: 0x12C */ + __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address + offset: 0x130 */ + __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address + offset: 0x134 */ + __IO uint32_t + FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */ +} DFSDM_Filter_TypeDef; + +/** + * @brief DFSDM channel configuration registers + */ +typedef struct { + __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address + offset: 0x00 */ + __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address + offset: 0x04 */ + __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and + short circuit detector register, Address offset: + 0x08 */ + __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, + Address offset: 0x0C */ + __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address + offset: 0x10 */ +} DFSDM_Channel_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct { + __IO uint32_t + IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t + CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t + APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ + __IO uint32_t + APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ + __IO uint32_t + APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ +} DBGMCU_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct { + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CMAR; /*!< DMA channel x memory address register */ +} DMA_Channel_TypeDef; + +typedef struct { + __IO uint32_t ISR; /*!< DMA interrupt status register, Address + offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: + 0x04 */ +} DMA_TypeDef; + +typedef struct { + __IO uint32_t CSELR; /*!< DMA channel selection register */ +} DMA_Request_TypeDef; + +/* Legacy define */ +#define DMA_request_TypeDef DMA_Request_TypeDef + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct { + __IO uint32_t IMR1; /*!< EXTI Interrupt mask register 1, Address + offset: 0x00 */ + __IO uint32_t EMR1; /*!< EXTI Event mask register 1, Address + offset: 0x04 */ + __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register 1, Address + offset: 0x08 */ + __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register 1, Address + offset: 0x0C */ + __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register 1, Address + offset: 0x10 */ + __IO uint32_t PR1; /*!< EXTI Pending register 1, Address + offset: 0x14 */ + uint32_t RESERVED1; /*!< Reserved, 0x18 */ + uint32_t RESERVED2; /*!< Reserved, 0x1C */ + __IO uint32_t IMR2; /*!< EXTI Interrupt mask register 2, Address + offset: 0x20 */ + __IO uint32_t EMR2; /*!< EXTI Event mask register 2, Address + offset: 0x24 */ + __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register 2, Address + offset: 0x28 */ + __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register 2, Address + offset: 0x2C */ + __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register 2, Address + offset: 0x30 */ + __IO uint32_t PR2; /*!< EXTI Pending register 2, Address + offset: 0x34 */ +} EXTI_TypeDef; + +/** + * @brief Firewall + */ + +typedef struct { + __IO uint32_t CSSA; /*!< Code Segment Start Address register, Address offset: + 0x00 */ + __IO uint32_t CSL; /*!< Code Segment Length register, Address offset: 0x04 */ + __IO uint32_t NVDSSA; /*!< NON volatile data Segment Start Address register, + Address offset: 0x08 */ + __IO uint32_t NVDSL; /*!< NON volatile data Segment Length register, Address + offset: 0x0C */ + __IO uint32_t VDSSA; /*!< Volatile data Segment Start Address register, + Address offset: 0x10 */ + __IO uint32_t VDSL; /*!< Volatile data Segment Length register, Address + offset: 0x14 */ + uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */ + __IO uint32_t CR; /*!< Configuration register, Address offset: 0x20 */ +} FIREWALL_TypeDef; + +/** + * @brief FLASH Registers + */ + +typedef struct { + __IO uint32_t ACR; /*!< FLASH access control register, Address + offset: 0x00 */ + __IO uint32_t PDKEYR; /*!< FLASH power down key register, Address + offset: 0x04 */ + __IO uint32_t KEYR; /*!< FLASH key register, Address + offset: 0x08 */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address + offset: 0x0C */ + __IO uint32_t + SR; /*!< FLASH status register, Address offset: 0x10 */ + __IO uint32_t + CR; /*!< FLASH control register, Address offset: 0x14 */ + __IO uint32_t ECCR; /*!< FLASH ECC register, Address + offset: 0x18 */ + __IO uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x1C */ + __IO uint32_t OPTR; /*!< FLASH option register, Address + offset: 0x20 */ + __IO uint32_t PCROP1SR; /*!< FLASH bank1 PCROP start address register, Address + offset: 0x24 */ + __IO uint32_t PCROP1ER; /*!< FLASH bank1 PCROP end address register, Address + offset: 0x28 */ + __IO uint32_t WRP1AR; /*!< FLASH bank1 WRP area A address register, Address + offset: 0x2C */ + __IO uint32_t WRP1BR; /*!< FLASH bank1 WRP area B address register, Address + offset: 0x30 */ + uint32_t RESERVED2[4]; /*!< Reserved2, Address + offset: 0x34-0x40 */ + __IO uint32_t PCROP2SR; /*!< FLASH bank2 PCROP start address register, Address + offset: 0x44 */ + __IO uint32_t PCROP2ER; /*!< FLASH bank2 PCROP end address register, Address + offset: 0x48 */ + __IO uint32_t WRP2AR; /*!< FLASH bank2 WRP area A address register, Address + offset: 0x4C */ + __IO uint32_t WRP2BR; /*!< FLASH bank2 WRP area B address register, Address + offset: 0x50 */ +} FLASH_TypeDef; + +/** + * @brief Flexible Memory Controller + */ + +typedef struct { + __IO uint32_t + BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select + timing register(BTR), Address offset: 0x00-1C */ +} FMC_Bank1_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1E + */ + +typedef struct { + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: + 0x104-0x11C */ +} FMC_Bank1E_TypeDef; + +/** + * @brief Flexible Memory Controller Bank3 + */ + +typedef struct { + __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */ + __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address + offset: 0x84 */ + __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, + Address offset: 0x88 */ + __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, + Address offset: 0x8C */ + uint32_t RESERVED0; /*!< Reserved, 0x90 */ + __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 + */ +} FMC_Bank3_TypeDef; + +/** + * @brief General Purpose I/O + */ + +typedef struct { + __IO uint32_t + MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address + offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address + offset: 0x08 */ + __IO uint32_t + PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t + IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t + ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t + BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t + LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address + offset: 0x20-0x24 */ + __IO uint32_t + BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ + __IO uint32_t + ASCR; /*!< GPIO analog switch control register, Address offset: 0x2C */ + +} GPIO_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct { + __IO uint32_t + CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t + CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t + OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t + OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t + TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t + TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t + ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t + ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t + PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t + RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t + TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct { + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ +} IWDG_TypeDef; + +/** + * @brief LPTIMER + */ +typedef struct { + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: + 0x00 */ + __IO uint32_t + ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 + */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */ +} LPTIM_TypeDef; + +/** + * @brief Operational Amplifier (OPAMP) + */ + +typedef struct { + __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */ + __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, + Address offset: 0x04 */ + __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, + Address offset: 0x08 */ +} OPAMP_TypeDef; + +typedef struct { + __IO uint32_t CSR; /*!< OPAMP control/status register, used for bits common to + several OPAMP instances, Address offset: 0x00 */ +} OPAMP_Common_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct { + __IO uint32_t + CR1; /*!< PWR power control register 1, Address offset: 0x00 */ + __IO uint32_t + CR2; /*!< PWR power control register 2, Address offset: 0x04 */ + __IO uint32_t + CR3; /*!< PWR power control register 3, Address offset: 0x08 */ + __IO uint32_t + CR4; /*!< PWR power control register 4, Address offset: 0x0C */ + __IO uint32_t + SR1; /*!< PWR power status register 1, Address offset: 0x10 */ + __IO uint32_t + SR2; /*!< PWR power status register 2, Address offset: 0x14 */ + __IO uint32_t + SCR; /*!< PWR power status reset register, Address offset: 0x18 */ + uint32_t RESERVED; /*!< Reserved, Address offset: + 0x1C */ + __IO uint32_t + PUCRA; /*!< Pull_up control register of portA, Address offset: 0x20 */ + __IO uint32_t + PDCRA; /*!< Pull_Down control register of portA, Address offset: 0x24 */ + __IO uint32_t + PUCRB; /*!< Pull_up control register of portB, Address offset: 0x28 */ + __IO uint32_t + PDCRB; /*!< Pull_Down control register of portB, Address offset: 0x2C */ + __IO uint32_t + PUCRC; /*!< Pull_up control register of portC, Address offset: 0x30 */ + __IO uint32_t + PDCRC; /*!< Pull_Down control register of portC, Address offset: 0x34 */ + __IO uint32_t + PUCRD; /*!< Pull_up control register of portD, Address offset: 0x38 */ + __IO uint32_t + PDCRD; /*!< Pull_Down control register of portD, Address offset: 0x3C */ + __IO uint32_t + PUCRE; /*!< Pull_up control register of portE, Address offset: 0x40 */ + __IO uint32_t + PDCRE; /*!< Pull_Down control register of portE, Address offset: 0x44 */ + __IO uint32_t + PUCRF; /*!< Pull_up control register of portF, Address offset: 0x48 */ + __IO uint32_t + PDCRF; /*!< Pull_Down control register of portF, Address offset: 0x4C */ + __IO uint32_t + PUCRG; /*!< Pull_up control register of portG, Address offset: 0x50 */ + __IO uint32_t + PDCRG; /*!< Pull_Down control register of portG, Address offset: 0x54 */ + __IO uint32_t + PUCRH; /*!< Pull_up control register of portH, Address offset: 0x58 */ + __IO uint32_t + PDCRH; /*!< Pull_Down control register of portH, Address offset: 0x5C */ +} PWR_TypeDef; + +/** + * @brief QUAD Serial Peripheral Interface + */ + +typedef struct { + __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */ + __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: + 0x04 */ + __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */ + __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */ + __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address + offset: 0x14 */ + __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */ + __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C + */ + __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */ + __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address + offset: 0x24 */ + __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address + offset: 0x28 */ + __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: + 0x2C */ + __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: + 0x30 */ +} QUADSPI_TypeDef; + +/** + * @brief Reset and Clock Control + */ + +typedef struct { + __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ + __IO uint32_t ICSCR; /*!< RCC internal clock sources calibration register, + Address offset: 0x04 */ + __IO uint32_t + CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ + __IO uint32_t PLLCFGR; /*!< RCC system PLL configuration register, Address + offset: 0x0C */ + __IO uint32_t PLLSAI1CFGR; /*!< RCC PLL SAI1 configuration register, Address + offset: 0x10 */ + __IO uint32_t PLLSAI2CFGR; /*!< RCC PLL SAI2 configuration register, Address + offset: 0x14 */ + __IO uint32_t + CIER; /*!< RCC clock interrupt enable register, Address offset: 0x18 */ + __IO uint32_t + CIFR; /*!< RCC clock interrupt flag register, Address offset: 0x1C */ + __IO uint32_t + CICR; /*!< RCC clock interrupt clear register, Address offset: 0x20 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t + AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x28 */ + __IO uint32_t + AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x2C */ + __IO uint32_t + AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x30 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x34 */ + __IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, Address + offset: 0x38 */ + __IO uint32_t APB1RSTR2; /*!< RCC APB1 peripheral reset register 2, Address + offset: 0x3C */ + __IO uint32_t + APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x40 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x44 */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clocks enable register, + Address offset: 0x48 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clocks enable register, + Address offset: 0x4C */ + __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clocks enable register, + Address offset: 0x50 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x54 */ + __IO uint32_t APB1ENR1; /*!< RCC APB1 peripheral clocks enable register 1, + Address offset: 0x58 */ + __IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, + Address offset: 0x5C */ + __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clocks enable register, + Address offset: 0x60 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x64 */ + __IO uint32_t AHB1SMENR; /*!< RCC AHB1 peripheral clocks enable in sleep and + stop modes register, Address offset: 0x68 */ + __IO uint32_t AHB2SMENR; /*!< RCC AHB2 peripheral clocks enable in sleep and + stop modes register, Address offset: 0x6C */ + __IO uint32_t AHB3SMENR; /*!< RCC AHB3 peripheral clocks enable in sleep and + stop modes register, Address offset: 0x70 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x74 */ + __IO uint32_t + APB1SMENR1; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop + modes register 1, Address offset: 0x78 */ + __IO uint32_t + APB1SMENR2; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop + modes register 2, Address offset: 0x7C */ + __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clocks enable in sleep mode + and stop modes register, Address offset: 0x80 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x84 */ + __IO uint32_t CCIPR; /*!< RCC peripherals independent clock configuration + register, Address offset: 0x88 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x8C */ + __IO uint32_t + BDCR; /*!< RCC backup domain control register, Address offset: 0x90 */ + __IO uint32_t + CSR; /*!< RCC clock control & status register, Address offset: 0x94 */ +} RCC_TypeDef; + +/** + * @brief Real-Time Clock + */ + +typedef struct { + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ + __IO uint32_t + ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + uint32_t reserved; /*!< Reserved */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t + TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ + __IO uint32_t + TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */ + __IO uint32_t + ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t + ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */ + __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */ + __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */ + __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ + __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ + __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ + __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ + __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ + __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ + __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ + __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ + __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ + __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ + __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ + __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ + __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ + __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ + __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ + __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ + __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ + __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ + __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ + __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */ + __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */ + __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */ + __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */ + __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */ + __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */ + __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */ + __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */ + __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */ + __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */ + __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */ + __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */ +} RTC_TypeDef; + +/** + * @brief Serial Audio Interface + */ + +typedef struct { + __IO uint32_t GCR; /*!< SAI global configuration register, Address + offset: 0x00 */ +} SAI_TypeDef; + +typedef struct { + __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address + offset: 0x04 */ + __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address + offset: 0x08 */ + __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address + offset: 0x0C */ + __IO uint32_t SLOTR; /*!< SAI block x slot register, Address + offset: 0x10 */ + __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address + offset: 0x14 */ + __IO uint32_t + SR; /*!< SAI block x status register, Address offset: 0x18 */ + __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address + offset: 0x1C */ + __IO uint32_t + DR; /*!< SAI block x data register, Address offset: 0x20 */ +} SAI_Block_TypeDef; + +/** + * @brief Secure digital input/output Interface + */ + +typedef struct { + __IO uint32_t + POWER; /*!< SDMMC power control register, Address offset: 0x00 */ + __IO uint32_t + CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */ + __IO uint32_t + ARG; /*!< SDMMC argument register, Address offset: 0x08 */ + __IO uint32_t + CMD; /*!< SDMMC command register, Address offset: 0x0C */ + __I uint32_t + RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */ + __I uint32_t + RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */ + __I uint32_t + RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */ + __I uint32_t + RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */ + __I uint32_t + RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */ + __IO uint32_t + DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */ + __IO uint32_t + DLEN; /*!< SDMMC data length register, Address offset: 0x28 */ + __IO uint32_t + DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */ + __I uint32_t + DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */ + __I uint32_t + STA; /*!< SDMMC status register, Address offset: 0x34 */ + __IO uint32_t + ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */ + __IO uint32_t + MASK; /*!< SDMMC mask register, Address offset: 0x3C */ + uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */ + __I uint32_t + FIFOCNT; /*!< SDMMC FIFO counter register, Address offset: 0x48 */ + uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */ + __IO uint32_t + FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */ +} SDMMC_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct { + __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ + __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */ + __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */ + __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */ +} SPI_TypeDef; + +/** + * @brief Single Wire Protocol Master Interface SPWMI + */ + +typedef struct { + __IO uint32_t + CR; /*!< SWPMI Configuration/Control register, Address offset: 0x00 */ + __IO uint32_t BRR; /*!< SWPMI bitrate register, Address + offset: 0x04 */ + uint32_t RESERVED1; /*!< Reserved, 0x08 */ + __IO uint32_t ISR; /*!< SWPMI Interrupt and Status register, Address + offset: 0x0C */ + __IO uint32_t ICR; /*!< SWPMI Interrupt Flag Clear register, Address + offset: 0x10 */ + __IO uint32_t IER; /*!< SWPMI Interrupt Enable register, Address + offset: 0x14 */ + __IO uint32_t RFL; /*!< SWPMI Receive Frame Length register, Address + offset: 0x18 */ + __IO uint32_t TDR; /*!< SWPMI Transmit data register, Address + offset: 0x1C */ + __IO uint32_t RDR; /*!< SWPMI Receive data register, Address + offset: 0x20 */ + __IO uint32_t + OR; /*!< SWPMI Option register, Address offset: 0x24 */ +} SWPMI_TypeDef; + +/** + * @brief System configuration controller + */ + +typedef struct { + __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 + */ + __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: + 0x04 */ + __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration + registers, Address offset: 0x08-0x14 */ + __IO uint32_t SCSR; /*!< SYSCFG SRAM2 control and status register, Address + offset: 0x18 */ + __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: + 0x1C */ + __IO uint32_t SWPR; /*!< SYSCFG SRAM2 write protection register, Address + offset: 0x20 */ + __IO uint32_t SKR; /*!< SYSCFG SRAM2 key register, Address offset: 0x24 */ +} SYSCFG_TypeDef; + +/** + * @brief TIM + */ + +typedef struct { + __IO uint32_t CR1; /*!< TIM control register 1, Address + offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address + offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address + offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address + offset: 0x0C */ + __IO uint32_t + SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address + offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address + offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address + offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address + offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address + offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address + offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address + offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address + offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address + offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address + offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address + offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address + offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address + offset: 0x44 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address + offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address + offset: 0x4C */ + __IO uint32_t OR1; /*!< TIM option register 1, Address + offset: 0x50 */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address + offset: 0x54 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address + offset: 0x58 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address + offset: 0x5C */ + __IO uint32_t OR2; /*!< TIM option register 2, Address + offset: 0x60 */ + __IO uint32_t OR3; /*!< TIM option register 3, Address + offset: 0x64 */ +} TIM_TypeDef; + +/** + * @brief Touch Sensing Controller (TSC) + */ + +typedef struct { + __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */ + __IO uint32_t + IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address + offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t + IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t + IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */ + __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address + offset: 0x30 */ + __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address + offset: 0x34-50 */ +} TSC_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ + +typedef struct { + __IO uint32_t CR1; /*!< USART Control register 1, Address + offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address + offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address + offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address + offset: 0x0C */ + __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address + offset: 0x10 */ + uint16_t RESERVED2; /*!< Reserved, 0x12 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address + offset: 0x14 */ + __IO uint16_t RQR; /*!< USART Request register, Address + offset: 0x18 */ + uint16_t RESERVED3; /*!< Reserved, 0x1A */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address + offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address + offset: 0x20 */ + __IO uint16_t RDR; /*!< USART Receive Data register, Address + offset: 0x24 */ + uint16_t RESERVED4; /*!< Reserved, 0x26 */ + __IO uint16_t TDR; /*!< USART Transmit Data register, Address + offset: 0x28 */ + uint16_t RESERVED5; /*!< Reserved, 0x2A */ +} USART_TypeDef; + +/** + * @brief VREFBUF + */ + +typedef struct { + __IO uint32_t CSR; /*!< VREFBUF control and status register, Address + offset: 0x00 */ + __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address + offset: 0x04 */ +} VREFBUF_TypeDef; + +/** + * @brief Window WATCHDOG + */ + +typedef struct { + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + +/** + * @brief RNG + */ + +typedef struct { + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ +} RNG_TypeDef; + +/** + * @brief USB_OTG_Core_register + */ +typedef struct { + __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h*/ + __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h*/ + __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h*/ + __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch*/ + __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h*/ + __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h*/ + __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h*/ + __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch*/ + __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h*/ + __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h*/ + __IO uint32_t + DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h*/ + __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch*/ + uint32_t Reserved30[2]; /*!< Reserved 030h*/ + __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h*/ + __IO uint32_t CID; /*!< User ID Register 03Ch*/ + __IO uint32_t GSNPSID; /*!< USB_OTG core ID 040h*/ + __IO uint32_t GHWCFG1; /*!< User HW config1 044h*/ + __IO uint32_t GHWCFG2; /*!< User HW config2 048h*/ + __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch*/ + uint32_t Reserved6; /*!< Reserved 050h*/ + __IO uint32_t GLPMCFG; /*!< LPM Register 054h*/ + __IO uint32_t GPWRDN; /*!< Power Down Register 058h*/ + __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch*/ + __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register 060h*/ + uint32_t Reserved43[39]; /*!< Reserved 064h-0FFh*/ + __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h*/ + __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */ +} USB_OTG_GlobalTypeDef; + +/** + * @brief USB_OTG_device_Registers + */ +typedef struct { + __IO uint32_t DCFG; /* dev Configuration Register 800h*/ + __IO uint32_t DCTL; /* dev Control Register 804h*/ + __IO uint32_t DSTS; /* dev Status Register (RO) 808h*/ + uint32_t Reserved0C; /* Reserved 80Ch*/ + __IO uint32_t DIEPMSK; /* dev IN Endpoint Mask 810h*/ + __IO uint32_t DOEPMSK; /* dev OUT Endpoint Mask 814h*/ + __IO uint32_t DAINT; /* dev All Endpoints Itr Reg 818h*/ + __IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask 81Ch*/ + uint32_t Reserved20; /* Reserved 820h*/ + uint32_t Reserved24; /* Reserved 824h*/ + __IO uint32_t DVBUSDIS; /* dev VBUS discharge Register 828h*/ + __IO uint32_t DVBUSPULSE; /* dev VBUS Pulse Register 82Ch*/ + __IO uint32_t DTHRCTL; /* dev thr 830h*/ + __IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/ + __IO uint32_t DEACHINT; /* dedicated EP interrupt 838h*/ + __IO uint32_t DEACHMSK; /* dedicated EP msk 83Ch*/ + uint32_t Reserved40; /* Reserved 840h*/ + __IO uint32_t DINEP1MSK; /* dedicated EP mask 844h*/ + uint32_t Reserved44[15]; /* Reserved 848-880h*/ + __IO uint32_t DOUTEP1MSK; /* dedicated EP msk 884h*/ +} USB_OTG_DeviceTypeDef; + +/** + * @brief USB_OTG_IN_Endpoint-Specific_Register + */ +typedef struct { + __IO uint32_t + DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/ + uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + + 04h*/ + __IO uint32_t + DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/ + uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + + 0Ch*/ + __IO uint32_t + DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/ + __IO uint32_t + DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h*/ + __IO uint32_t + DTXFSTS; /*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/ + uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + + 1Ch*/ +} USB_OTG_INEndpointTypeDef; + +/** + * @brief USB_OTG_OUT_Endpoint-Specific_Registers + */ +typedef struct { + __IO uint32_t + DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/ + uint32_t + Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/ + __IO uint32_t + DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/ + uint32_t + Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/ + __IO uint32_t + DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/ + __IO uint32_t + DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/ + uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + + (ep_num * 20h) + 1Ch*/ +} USB_OTG_OUTEndpointTypeDef; + +/** + * @brief USB_OTG_Host_Mode_Register_Structures + */ +typedef struct { + __IO uint32_t HCFG; /* Host Configuration Register 400h*/ + __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/ + __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/ + uint32_t Reserved40C; /* Reserved 40Ch*/ + __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/ + __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/ + __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/ +} USB_OTG_HostTypeDef; + +/** + * @brief USB_OTG_Host_Channel_Specific_Registers + */ +typedef struct { + __IO uint32_t HCCHAR; + __IO uint32_t HCSPLT; + __IO uint32_t HCINT; + __IO uint32_t HCINTMSK; + __IO uint32_t HCTSIZ; + __IO uint32_t HCDMA; + uint32_t Reserved[2]; +} USB_OTG_HostChannelTypeDef; + +/** + * @} + */ + +/** @addtogroup Peripheral_memory_map + * @{ + */ +#define FLASH_BASE (0x08000000UL) /*!< FLASH(up to 1 MB) base address */ +#define SRAM1_BASE (0x20000000UL) /*!< SRAM1(up to 96 KB) base address */ +#define SRAM2_BASE (0x10000000UL) /*!< SRAM2(32 KB) base address */ +#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */ +#define FMC_BASE (0x60000000UL) /*!< FMC base address */ +#define QSPI_BASE \ + (0x90000000UL) /*!< QUADSPI memories accessible over AHB base address */ + +#define FMC_R_BASE (0xA0000000UL) /*!< FMC control registers base address */ +#define QSPI_R_BASE \ + (0xA0001000UL) /*!< QUADSPI control registers base address */ +#define SRAM1_BB_BASE \ + (0x22000000UL) /*!< SRAM1(96 KB) base address in the bit-band region */ +#define PERIPH_BB_BASE \ + (0x42000000UL) /*!< Peripheral base address in the bit-band region */ + +/* Legacy defines */ +#define SRAM_BASE SRAM1_BASE +#define SRAM_BB_BASE SRAM1_BB_BASE + +#define SRAM1_SIZE_MAX \ + (0x00018000UL) /*!< maximum SRAM1 size (up to 96 KBytes) */ +#define SRAM2_SIZE (0x00008000UL) /*!< SRAM2 size (32 KBytes) */ + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL) + +#define FMC_BANK1 FMC_BASE +#define FMC_BANK1_1 FMC_BANK1 +#define FMC_BANK1_2 (FMC_BANK1 + 0x04000000UL) +#define FMC_BANK1_3 (FMC_BANK1 + 0x08000000UL) +#define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000UL) +#define FMC_BANK3 (FMC_BASE + 0x20000000UL) + +/*!< APB1 peripherals */ +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL) +#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800UL) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800UL) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL) +#define UART5_BASE (APB1PERIPH_BASE + 0x5000UL) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL) +#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL) +#define CAN1_BASE (APB1PERIPH_BASE + 0x6400UL) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000UL) +#define DAC_BASE (APB1PERIPH_BASE + 0x7400UL) +#define DAC1_BASE (APB1PERIPH_BASE + 0x7400UL) +#define OPAMP_BASE (APB1PERIPH_BASE + 0x7800UL) +#define OPAMP1_BASE (APB1PERIPH_BASE + 0x7800UL) +#define OPAMP2_BASE (APB1PERIPH_BASE + 0x7810UL) +#define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00UL) +#define LPUART1_BASE (APB1PERIPH_BASE + 0x8000UL) +#define SWPMI1_BASE (APB1PERIPH_BASE + 0x8800UL) +#define LPTIM2_BASE (APB1PERIPH_BASE + 0x9400UL) + +/*!< APB2 peripherals */ +#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000UL) +#define VREFBUF_BASE (APB2PERIPH_BASE + 0x0030UL) +#define COMP1_BASE (APB2PERIPH_BASE + 0x0200UL) +#define COMP2_BASE (APB2PERIPH_BASE + 0x0204UL) +#define EXTI_BASE (APB2PERIPH_BASE + 0x0400UL) +#define FIREWALL_BASE (APB2PERIPH_BASE + 0x1C00UL) +#define SDMMC1_BASE (APB2PERIPH_BASE + 0x2800UL) +#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00UL) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL) +#define TIM8_BASE (APB2PERIPH_BASE + 0x3400UL) +#define USART1_BASE (APB2PERIPH_BASE + 0x3800UL) +#define TIM15_BASE (APB2PERIPH_BASE + 0x4000UL) +#define TIM16_BASE (APB2PERIPH_BASE + 0x4400UL) +#define TIM17_BASE (APB2PERIPH_BASE + 0x4800UL) +#define SAI1_BASE (APB2PERIPH_BASE + 0x5400UL) +#define SAI1_Block_A_BASE (SAI1_BASE + 0x0004UL) +#define SAI1_Block_B_BASE (SAI1_BASE + 0x0024UL) +#define SAI2_BASE (APB2PERIPH_BASE + 0x5800UL) +#define SAI2_Block_A_BASE (SAI2_BASE + 0x0004UL) +#define SAI2_Block_B_BASE (SAI2_BASE + 0x0024UL) +#define DFSDM1_BASE (APB2PERIPH_BASE + 0x6000UL) +#define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x0000UL) +#define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x0020UL) +#define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x0040UL) +#define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x0060UL) +#define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x0080UL) +#define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0x00A0UL) +#define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0x00C0UL) +#define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0x00E0UL) +#define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x0100UL) +#define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x0180UL) +#define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x0200UL) +#define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x0280UL) + +/*!< AHB1 peripherals */ +#define DMA1_BASE (AHB1PERIPH_BASE) +#define DMA2_BASE (AHB1PERIPH_BASE + 0x0400UL) +#define RCC_BASE (AHB1PERIPH_BASE + 0x1000UL) +#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000UL) +#define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL) +#define TSC_BASE (AHB1PERIPH_BASE + 0x4000UL) + +#define DMA1_Channel1_BASE (DMA1_BASE + 0x0008UL) +#define DMA1_Channel2_BASE (DMA1_BASE + 0x001CUL) +#define DMA1_Channel3_BASE (DMA1_BASE + 0x0030UL) +#define DMA1_Channel4_BASE (DMA1_BASE + 0x0044UL) +#define DMA1_Channel5_BASE (DMA1_BASE + 0x0058UL) +#define DMA1_Channel6_BASE (DMA1_BASE + 0x006CUL) +#define DMA1_Channel7_BASE (DMA1_BASE + 0x0080UL) +#define DMA1_CSELR_BASE (DMA1_BASE + 0x00A8UL) + +#define DMA2_Channel1_BASE (DMA2_BASE + 0x0008UL) +#define DMA2_Channel2_BASE (DMA2_BASE + 0x001CUL) +#define DMA2_Channel3_BASE (DMA2_BASE + 0x0030UL) +#define DMA2_Channel4_BASE (DMA2_BASE + 0x0044UL) +#define DMA2_Channel5_BASE (DMA2_BASE + 0x0058UL) +#define DMA2_Channel6_BASE (DMA2_BASE + 0x006CUL) +#define DMA2_Channel7_BASE (DMA2_BASE + 0x0080UL) +#define DMA2_CSELR_BASE (DMA2_BASE + 0x00A8UL) + +/*!< AHB2 peripherals */ +#define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000UL) +#define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400UL) +#define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800UL) +#define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00UL) +#define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000UL) +#define GPIOF_BASE (AHB2PERIPH_BASE + 0x1400UL) +#define GPIOG_BASE (AHB2PERIPH_BASE + 0x1800UL) +#define GPIOH_BASE (AHB2PERIPH_BASE + 0x1C00UL) + +#define USBOTG_BASE (AHB2PERIPH_BASE + 0x08000000UL) + +#define ADC1_BASE (AHB2PERIPH_BASE + 0x08040000UL) +#define ADC2_BASE (AHB2PERIPH_BASE + 0x08040100UL) +#define ADC3_BASE (AHB2PERIPH_BASE + 0x08040200UL) +#define ADC123_COMMON_BASE (AHB2PERIPH_BASE + 0x08040300UL) + +#define RNG_BASE (AHB2PERIPH_BASE + 0x08060800UL) + +/*!< FMC Banks registers base address */ +#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL) +#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL) +#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080UL) + +/* Debug MCU registers base address */ +#define DBGMCU_BASE (0xE0042000UL) + +/*!< USB registers base address */ +#define USB_OTG_FS_PERIPH_BASE (0x50000000UL) + +#define USB_OTG_GLOBAL_BASE (0x00000000UL) +#define USB_OTG_DEVICE_BASE (0x00000800UL) +#define USB_OTG_IN_ENDPOINT_BASE (0x00000900UL) +#define USB_OTG_OUT_ENDPOINT_BASE (0x00000B00UL) +#define USB_OTG_EP_REG_SIZE (0x00000020UL) +#define USB_OTG_HOST_BASE (0x00000400UL) +#define USB_OTG_HOST_PORT_BASE (0x00000440UL) +#define USB_OTG_HOST_CHANNEL_BASE (0x00000500UL) +#define USB_OTG_HOST_CHANNEL_SIZE (0x00000020UL) +#define USB_OTG_PCGCCTL_BASE (0x00000E00UL) +#define USB_OTG_FIFO_BASE (0x00001000UL) +#define USB_OTG_FIFO_SIZE (0x00001000UL) + +#define PACKAGE_BASE \ + (0x1FFF7500UL) /*!< Package data register base address */ +#define UID_BASE (0x1FFF7590UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE \ + (0x1FFF75E0UL) /*!< Flash size data register base address */ +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ +#define TIM2 ((TIM_TypeDef *)TIM2_BASE) +#define TIM3 ((TIM_TypeDef *)TIM3_BASE) +#define TIM4 ((TIM_TypeDef *)TIM4_BASE) +#define TIM5 ((TIM_TypeDef *)TIM5_BASE) +#define TIM6 ((TIM_TypeDef *)TIM6_BASE) +#define TIM7 ((TIM_TypeDef *)TIM7_BASE) +#define RTC ((RTC_TypeDef *)RTC_BASE) +#define WWDG ((WWDG_TypeDef *)WWDG_BASE) +#define IWDG ((IWDG_TypeDef *)IWDG_BASE) +#define SPI2 ((SPI_TypeDef *)SPI2_BASE) +#define SPI3 ((SPI_TypeDef *)SPI3_BASE) +#define USART2 ((USART_TypeDef *)USART2_BASE) +#define USART3 ((USART_TypeDef *)USART3_BASE) +#define UART4 ((USART_TypeDef *)UART4_BASE) +#define UART5 ((USART_TypeDef *)UART5_BASE) +#define I2C1 ((I2C_TypeDef *)I2C1_BASE) +#define I2C2 ((I2C_TypeDef *)I2C2_BASE) +#define I2C3 ((I2C_TypeDef *)I2C3_BASE) +#define CAN ((CAN_TypeDef *)CAN1_BASE) +#define CAN1 ((CAN_TypeDef *)CAN1_BASE) +#define PWR ((PWR_TypeDef *)PWR_BASE) +#define DAC ((DAC_TypeDef *)DAC1_BASE) +#define DAC1 ((DAC_TypeDef *)DAC1_BASE) +#define OPAMP ((OPAMP_TypeDef *)OPAMP_BASE) +#define OPAMP1 ((OPAMP_TypeDef *)OPAMP1_BASE) +#define OPAMP2 ((OPAMP_TypeDef *)OPAMP2_BASE) +#define OPAMP12_COMMON ((OPAMP_Common_TypeDef *)OPAMP1_BASE) +#define LPTIM1 ((LPTIM_TypeDef *)LPTIM1_BASE) +#define LPUART1 ((USART_TypeDef *)LPUART1_BASE) +#define SWPMI1 ((SWPMI_TypeDef *)SWPMI1_BASE) +#define LPTIM2 ((LPTIM_TypeDef *)LPTIM2_BASE) + +#define SYSCFG ((SYSCFG_TypeDef *)SYSCFG_BASE) +#define VREFBUF ((VREFBUF_TypeDef *)VREFBUF_BASE) +#define COMP1 ((COMP_TypeDef *)COMP1_BASE) +#define COMP2 ((COMP_TypeDef *)COMP2_BASE) +#define COMP12_COMMON ((COMP_Common_TypeDef *)COMP2_BASE) +#define EXTI ((EXTI_TypeDef *)EXTI_BASE) +#define FIREWALL ((FIREWALL_TypeDef *)FIREWALL_BASE) +#define SDMMC1 ((SDMMC_TypeDef *)SDMMC1_BASE) +#define TIM1 ((TIM_TypeDef *)TIM1_BASE) +#define SPI1 ((SPI_TypeDef *)SPI1_BASE) +#define TIM8 ((TIM_TypeDef *)TIM8_BASE) +#define USART1 ((USART_TypeDef *)USART1_BASE) +#define TIM15 ((TIM_TypeDef *)TIM15_BASE) +#define TIM16 ((TIM_TypeDef *)TIM16_BASE) +#define TIM17 ((TIM_TypeDef *)TIM17_BASE) +#define SAI1 ((SAI_TypeDef *)SAI1_BASE) +#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE) +#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE) +#define SAI2 ((SAI_TypeDef *)SAI2_BASE) +#define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE) +#define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE) +#define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *)DFSDM1_Channel0_BASE) +#define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *)DFSDM1_Channel1_BASE) +#define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *)DFSDM1_Channel2_BASE) +#define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *)DFSDM1_Channel3_BASE) +#define DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *)DFSDM1_Channel4_BASE) +#define DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *)DFSDM1_Channel5_BASE) +#define DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *)DFSDM1_Channel6_BASE) +#define DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *)DFSDM1_Channel7_BASE) +#define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *)DFSDM1_Filter0_BASE) +#define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *)DFSDM1_Filter1_BASE) +#define DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *)DFSDM1_Filter2_BASE) +#define DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *)DFSDM1_Filter3_BASE) +/* Aliases to keep compatibility after DFSDM renaming */ +#define DFSDM_Channel0 DFSDM1_Channel0 +#define DFSDM_Channel1 DFSDM1_Channel1 +#define DFSDM_Channel2 DFSDM1_Channel2 +#define DFSDM_Channel3 DFSDM1_Channel3 +#define DFSDM_Channel4 DFSDM1_Channel4 +#define DFSDM_Channel5 DFSDM1_Channel5 +#define DFSDM_Channel6 DFSDM1_Channel6 +#define DFSDM_Channel7 DFSDM1_Channel7 +#define DFSDM_Filter0 DFSDM1_Filter0 +#define DFSDM_Filter1 DFSDM1_Filter1 +#define DFSDM_Filter2 DFSDM1_Filter2 +#define DFSDM_Filter3 DFSDM1_Filter3 +#define DMA1 ((DMA_TypeDef *)DMA1_BASE) +#define DMA2 ((DMA_TypeDef *)DMA2_BASE) +#define RCC ((RCC_TypeDef *)RCC_BASE) +#define FLASH ((FLASH_TypeDef *)FLASH_R_BASE) +#define CRC ((CRC_TypeDef *)CRC_BASE) +#define TSC ((TSC_TypeDef *)TSC_BASE) + +#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *)GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *)GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *)GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *)GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *)GPIOG_BASE) +#define GPIOH ((GPIO_TypeDef *)GPIOH_BASE) +#define ADC1 ((ADC_TypeDef *)ADC1_BASE) +#define ADC2 ((ADC_TypeDef *)ADC2_BASE) +#define ADC3 ((ADC_TypeDef *)ADC3_BASE) +#define ADC123_COMMON ((ADC_Common_TypeDef *)ADC123_COMMON_BASE) +#define RNG ((RNG_TypeDef *)RNG_BASE) + +#define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE) +#define DMA1_CSELR ((DMA_Request_TypeDef *)DMA1_CSELR_BASE) + +#define DMA2_Channel1 ((DMA_Channel_TypeDef *)DMA2_Channel1_BASE) +#define DMA2_Channel2 ((DMA_Channel_TypeDef *)DMA2_Channel2_BASE) +#define DMA2_Channel3 ((DMA_Channel_TypeDef *)DMA2_Channel3_BASE) +#define DMA2_Channel4 ((DMA_Channel_TypeDef *)DMA2_Channel4_BASE) +#define DMA2_Channel5 ((DMA_Channel_TypeDef *)DMA2_Channel5_BASE) +#define DMA2_Channel6 ((DMA_Channel_TypeDef *)DMA2_Channel6_BASE) +#define DMA2_Channel7 ((DMA_Channel_TypeDef *)DMA2_Channel7_BASE) +#define DMA2_CSELR ((DMA_Request_TypeDef *)DMA2_CSELR_BASE) + +#define FMC_Bank1_R ((FMC_Bank1_TypeDef *)FMC_Bank1_R_BASE) +#define FMC_Bank1E_R ((FMC_Bank1E_TypeDef *)FMC_Bank1E_R_BASE) +#define FMC_Bank3_R ((FMC_Bank3_TypeDef *)FMC_Bank3_R_BASE) + +#define QUADSPI ((QUADSPI_TypeDef *)QSPI_R_BASE) + +#define DBGMCU ((DBGMCU_TypeDef *)DBGMCU_BASE) + +#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *)USB_OTG_FS_PERIPH_BASE) +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + +/** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers_Bits_Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ + +/* + * @brief Specific device feature definitions (not present on all devices in the + * STM32L4 serie) + */ +#define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific \ + devices: multimode available on devices with \ + several ADC instances */ + +/******************** Bit definition for ADC_ISR register *******************/ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP \ + ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC \ + ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS \ + ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ +#define ADC_ISR_JEOC_Pos (5U) +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC \ + ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */ +#define ADC_ISR_JEOS_Pos (6U) +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS \ + ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ +#define ADC_ISR_JQOVF_Pos (10U) +#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ +#define ADC_ISR_JQOVF \ + ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */ + +/******************** Bit definition for ADC_IER register *******************/ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE \ + ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE \ + ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt \ + */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE \ + ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions \ + interrupt */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE \ + ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ +#define ADC_IER_JEOCIE_Pos (5U) +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE \ + ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion \ + interrupt */ +#define ADC_IER_JEOSIE_Pos (6U) +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE \ + ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions \ + interrupt */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE \ + ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE \ + ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE \ + ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ +#define ADC_IER_JQOVFIE_Pos (10U) +#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ +#define ADC_IER_JQOVFIE \ + ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow \ + interrupt */ + +/* Legacy defines */ +#define ADC_IER_ADRDY (ADC_IER_ADRDYIE) +#define ADC_IER_EOSMP (ADC_IER_EOSMPIE) +#define ADC_IER_EOC (ADC_IER_EOCIE) +#define ADC_IER_EOS (ADC_IER_EOSIE) +#define ADC_IER_OVR (ADC_IER_OVRIE) +#define ADC_IER_JEOC (ADC_IER_JEOCIE) +#define ADC_IER_JEOS (ADC_IER_JEOSIE) +#define ADC_IER_AWD1 (ADC_IER_AWD1IE) +#define ADC_IER_AWD2 (ADC_IER_AWD2IE) +#define ADC_IER_AWD3 (ADC_IER_AWD3IE) +#define ADC_IER_JQOVF (ADC_IER_JQOVFIE) + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART \ + ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ +#define ADC_CR_JADSTART_Pos (3U) +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART \ + ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP \ + ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop \ + */ +#define ADC_CR_JADSTP_Pos (5U) +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP \ + ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN \ + ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable \ + */ +#define ADC_CR_DEEPPWD_Pos (29U) +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */ +#define ADC_CR_ADCALDIF_Pos (30U) +#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ +#define ADC_CR_ADCALDIF \ + ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ + +/******************** Bit definition for ADC_CFGR register ******************/ +#define ADC_CFGR_DMAEN_Pos (0U) +#define ADC_CFGR_DMAEN_Msk (0x1UL << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC_CFGR_DMACFG_Pos (1U) +#define ADC_CFGR_DMACFG_Msk (0x1UL << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC_CFGR_DMACFG \ + ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */ + +#define ADC_CFGR_RES_Pos (3U) +#define ADC_CFGR_RES_Msk (0x3UL << ADC_CFGR_RES_Pos) /*!< 0x00000018 */ +#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */ +#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR_ALIGN_Pos (5U) +#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */ +#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */ + +#define ADC_CFGR_EXTSEL_Pos (6U) +#define ADC_CFGR_EXTSEL_Msk (0xFUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */ +#define ADC_CFGR_EXTSEL \ + ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */ +#define ADC_CFGR_EXTSEL_0 (0x1UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR_EXTSEL_1 (0x2UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR_EXTSEL_2 (0x4UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR_EXTSEL_3 (0x8UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ + +#define ADC_CFGR_EXTEN_Pos (10U) +#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR_EXTEN \ + ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */ +#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR_OVRMOD_Pos (12U) +#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR_OVRMOD \ + ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */ +#define ADC_CFGR_CONT_Pos (13U) +#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR_CONT \ + ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */ +#define ADC_CFGR_AUTDLY_Pos (14U) +#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */ + +#define ADC_CFGR_DISCEN_Pos (16U) +#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR_DISCEN \ + ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ + +#define ADC_CFGR_DISCNUM_Pos (17U) +#define ADC_CFGR_DISCNUM_Msk \ + (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 \ + */ +#define ADC_CFGR_DISCNUM \ + ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number \ + of ranks */ +#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ + +#define ADC_CFGR_JDISCEN_Pos (20U) +#define ADC_CFGR_JDISCEN_Msk \ + (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 \ + */ +#define ADC_CFGR_JDISCEN \ + ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ +#define ADC_CFGR_JQM_Pos (21U) +#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ +#define ADC_CFGR_JQM \ + ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */ +#define ADC_CFGR_AWD1SGL_Pos (22U) +#define ADC_CFGR_AWD1SGL_Msk \ + (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 \ + */ +#define ADC_CFGR_AWD1SGL \ + ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel \ + or all channels */ +#define ADC_CFGR_AWD1EN_Pos (23U) +#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR_AWD1EN \ + ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group \ + regular */ +#define ADC_CFGR_JAWD1EN_Pos (24U) +#define ADC_CFGR_JAWD1EN_Msk \ + (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 \ + */ +#define ADC_CFGR_JAWD1EN \ + ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group \ + injected */ +#define ADC_CFGR_JAUTO_Pos (25U) +#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR_JAUTO \ + ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ + +#define ADC_CFGR_AWD1CH_Pos (26U) +#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR_AWD1CH \ + ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection \ + */ +#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ + +#define ADC_CFGR_JQDIS_Pos (31U) +#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */ +#define ADC_CFGR_JQDIS \ + ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */ + +/******************** Bit definition for ADC_CFGR2 register *****************/ +#define ADC_CFGR2_ROVSE_Pos (0U) +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE \ + ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular \ + */ +#define ADC_CFGR2_JOVSE_Pos (1U) +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE \ + ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected \ + */ + +#define ADC_CFGR2_OVSR_Pos (2U) +#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TROVS_Pos (9U) +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS \ + ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered \ + mode) for ADC group regular */ +#define ADC_CFGR2_ROVSM_Pos (10U) +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM \ + ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced \ + conversions of ADC group regular and group injected \ + */ + +/******************** Bit definition for ADC_SMPR1 register *****************/ +#define ADC_SMPR1_SMP0_Pos (0U) +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 \ + ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR1_SMP1_Pos (3U) +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 \ + ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR1_SMP2_Pos (6U) +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 \ + ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR1_SMP3_Pos (9U) +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 \ + ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR1_SMP4_Pos (12U) +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 \ + ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR1_SMP5_Pos (15U) +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 \ + ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR1_SMP6_Pos (18U) +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 \ + ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR1_SMP7_Pos (21U) +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 \ + ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR1_SMP8_Pos (24U) +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 \ + ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR1_SMP9_Pos (27U) +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 \ + ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +/******************** Bit definition for ADC_SMPR2 register *****************/ +#define ADC_SMPR2_SMP10_Pos (0U) +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 \ + ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR2_SMP11_Pos (3U) +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 \ + ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR2_SMP12_Pos (6U) +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 \ + ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR2_SMP13_Pos (9U) +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 \ + ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR2_SMP14_Pos (12U) +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14 \ + ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR2_SMP15_Pos (15U) +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15 \ + ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR2_SMP16_Pos (18U) +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16 \ + ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR2_SMP17_Pos (21U) +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17 \ + ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR2_SMP18_Pos (24U) +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18 \ + ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ + +/******************** Bit definition for ADC_TR1 register *******************/ +#define ADC_TR1_LT1_Pos (0U) +#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_TR1_LT1 \ + ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low \ + */ +#define ADC_TR1_LT1_0 (0x001UL << ADC_TR1_LT1_Pos) /*!< 0x00000001 */ +#define ADC_TR1_LT1_1 (0x002UL << ADC_TR1_LT1_Pos) /*!< 0x00000002 */ +#define ADC_TR1_LT1_2 (0x004UL << ADC_TR1_LT1_Pos) /*!< 0x00000004 */ +#define ADC_TR1_LT1_3 (0x008UL << ADC_TR1_LT1_Pos) /*!< 0x00000008 */ +#define ADC_TR1_LT1_4 (0x010UL << ADC_TR1_LT1_Pos) /*!< 0x00000010 */ +#define ADC_TR1_LT1_5 (0x020UL << ADC_TR1_LT1_Pos) /*!< 0x00000020 */ +#define ADC_TR1_LT1_6 (0x040UL << ADC_TR1_LT1_Pos) /*!< 0x00000040 */ +#define ADC_TR1_LT1_7 (0x080UL << ADC_TR1_LT1_Pos) /*!< 0x00000080 */ +#define ADC_TR1_LT1_8 (0x100UL << ADC_TR1_LT1_Pos) /*!< 0x00000100 */ +#define ADC_TR1_LT1_9 (0x200UL << ADC_TR1_LT1_Pos) /*!< 0x00000200 */ +#define ADC_TR1_LT1_10 (0x400UL << ADC_TR1_LT1_Pos) /*!< 0x00000400 */ +#define ADC_TR1_LT1_11 (0x800UL << ADC_TR1_LT1_Pos) /*!< 0x00000800 */ + +#define ADC_TR1_HT1_Pos (16U) +#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR1_HT1 \ + ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high \ + */ +#define ADC_TR1_HT1_0 (0x001UL << ADC_TR1_HT1_Pos) /*!< 0x00010000 */ +#define ADC_TR1_HT1_1 (0x002UL << ADC_TR1_HT1_Pos) /*!< 0x00020000 */ +#define ADC_TR1_HT1_2 (0x004UL << ADC_TR1_HT1_Pos) /*!< 0x00040000 */ +#define ADC_TR1_HT1_3 (0x008UL << ADC_TR1_HT1_Pos) /*!< 0x00080000 */ +#define ADC_TR1_HT1_4 (0x010UL << ADC_TR1_HT1_Pos) /*!< 0x00100000 */ +#define ADC_TR1_HT1_5 (0x020UL << ADC_TR1_HT1_Pos) /*!< 0x00200000 */ +#define ADC_TR1_HT1_6 (0x040UL << ADC_TR1_HT1_Pos) /*!< 0x00400000 */ +#define ADC_TR1_HT1_7 (0x080UL << ADC_TR1_HT1_Pos) /*!< 0x00800000 */ +#define ADC_TR1_HT1_8 (0x100UL << ADC_TR1_HT1_Pos) /*!< 0x01000000 */ +#define ADC_TR1_HT1_9 (0x200UL << ADC_TR1_HT1_Pos) /*!< 0x02000000 */ +#define ADC_TR1_HT1_10 (0x400UL << ADC_TR1_HT1_Pos) /*!< 0x04000000 */ +#define ADC_TR1_HT1_11 (0x800UL << ADC_TR1_HT1_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_TR2 register *******************/ +#define ADC_TR2_LT2_Pos (0U) +#define ADC_TR2_LT2_Msk (0xFFUL << ADC_TR2_LT2_Pos) /*!< 0x000000FF */ +#define ADC_TR2_LT2 \ + ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low \ + */ +#define ADC_TR2_LT2_0 (0x01UL << ADC_TR2_LT2_Pos) /*!< 0x00000001 */ +#define ADC_TR2_LT2_1 (0x02UL << ADC_TR2_LT2_Pos) /*!< 0x00000002 */ +#define ADC_TR2_LT2_2 (0x04UL << ADC_TR2_LT2_Pos) /*!< 0x00000004 */ +#define ADC_TR2_LT2_3 (0x08UL << ADC_TR2_LT2_Pos) /*!< 0x00000008 */ +#define ADC_TR2_LT2_4 (0x10UL << ADC_TR2_LT2_Pos) /*!< 0x00000010 */ +#define ADC_TR2_LT2_5 (0x20UL << ADC_TR2_LT2_Pos) /*!< 0x00000020 */ +#define ADC_TR2_LT2_6 (0x40UL << ADC_TR2_LT2_Pos) /*!< 0x00000040 */ +#define ADC_TR2_LT2_7 (0x80UL << ADC_TR2_LT2_Pos) /*!< 0x00000080 */ + +#define ADC_TR2_HT2_Pos (16U) +#define ADC_TR2_HT2_Msk (0xFFUL << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */ +#define ADC_TR2_HT2 \ + ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high \ + */ +#define ADC_TR2_HT2_0 (0x01UL << ADC_TR2_HT2_Pos) /*!< 0x00010000 */ +#define ADC_TR2_HT2_1 (0x02UL << ADC_TR2_HT2_Pos) /*!< 0x00020000 */ +#define ADC_TR2_HT2_2 (0x04UL << ADC_TR2_HT2_Pos) /*!< 0x00040000 */ +#define ADC_TR2_HT2_3 (0x08UL << ADC_TR2_HT2_Pos) /*!< 0x00080000 */ +#define ADC_TR2_HT2_4 (0x10UL << ADC_TR2_HT2_Pos) /*!< 0x00100000 */ +#define ADC_TR2_HT2_5 (0x20UL << ADC_TR2_HT2_Pos) /*!< 0x00200000 */ +#define ADC_TR2_HT2_6 (0x40UL << ADC_TR2_HT2_Pos) /*!< 0x00400000 */ +#define ADC_TR2_HT2_7 (0x80UL << ADC_TR2_HT2_Pos) /*!< 0x00800000 */ + +/******************** Bit definition for ADC_TR3 register *******************/ +#define ADC_TR3_LT3_Pos (0U) +#define ADC_TR3_LT3_Msk (0xFFUL << ADC_TR3_LT3_Pos) /*!< 0x000000FF */ +#define ADC_TR3_LT3 \ + ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low \ + */ +#define ADC_TR3_LT3_0 (0x01UL << ADC_TR3_LT3_Pos) /*!< 0x00000001 */ +#define ADC_TR3_LT3_1 (0x02UL << ADC_TR3_LT3_Pos) /*!< 0x00000002 */ +#define ADC_TR3_LT3_2 (0x04UL << ADC_TR3_LT3_Pos) /*!< 0x00000004 */ +#define ADC_TR3_LT3_3 (0x08UL << ADC_TR3_LT3_Pos) /*!< 0x00000008 */ +#define ADC_TR3_LT3_4 (0x10UL << ADC_TR3_LT3_Pos) /*!< 0x00000010 */ +#define ADC_TR3_LT3_5 (0x20UL << ADC_TR3_LT3_Pos) /*!< 0x00000020 */ +#define ADC_TR3_LT3_6 (0x40UL << ADC_TR3_LT3_Pos) /*!< 0x00000040 */ +#define ADC_TR3_LT3_7 (0x80UL << ADC_TR3_LT3_Pos) /*!< 0x00000080 */ + +#define ADC_TR3_HT3_Pos (16U) +#define ADC_TR3_HT3_Msk (0xFFUL << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */ +#define ADC_TR3_HT3 \ + ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high \ + */ +#define ADC_TR3_HT3_0 (0x01UL << ADC_TR3_HT3_Pos) /*!< 0x00010000 */ +#define ADC_TR3_HT3_1 (0x02UL << ADC_TR3_HT3_Pos) /*!< 0x00020000 */ +#define ADC_TR3_HT3_2 (0x04UL << ADC_TR3_HT3_Pos) /*!< 0x00040000 */ +#define ADC_TR3_HT3_3 (0x08UL << ADC_TR3_HT3_Pos) /*!< 0x00080000 */ +#define ADC_TR3_HT3_4 (0x10UL << ADC_TR3_HT3_Pos) /*!< 0x00100000 */ +#define ADC_TR3_HT3_5 (0x20UL << ADC_TR3_HT3_Pos) /*!< 0x00200000 */ +#define ADC_TR3_HT3_6 (0x40UL << ADC_TR3_HT3_Pos) /*!< 0x00400000 */ +#define ADC_TR3_HT3_7 (0x80UL << ADC_TR3_HT3_Pos) /*!< 0x00800000 */ + +/******************** Bit definition for ADC_SQR1 register ******************/ +#define ADC_SQR1_L_Pos (0U) +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L \ + ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ + +#define ADC_SQR1_SQ1_Pos (6U) +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 \ + ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 \ + */ +#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ + +#define ADC_SQR1_SQ2_Pos (12U) +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 \ + ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 \ + */ +#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ + +#define ADC_SQR1_SQ3_Pos (18U) +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 \ + ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 \ + */ +#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ + +#define ADC_SQR1_SQ4_Pos (24U) +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 \ + ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 \ + */ +#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR2 register ******************/ +#define ADC_SQR2_SQ5_Pos (0U) +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 \ + ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 \ + */ +#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ + +#define ADC_SQR2_SQ6_Pos (6U) +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 \ + ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 \ + */ +#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ + +#define ADC_SQR2_SQ7_Pos (12U) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 \ + ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 \ + */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ + +#define ADC_SQR2_SQ8_Pos (18U) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 \ + ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 \ + */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ + +#define ADC_SQR2_SQ9_Pos (24U) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 \ + ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 \ + */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR3 register ******************/ +#define ADC_SQR3_SQ10_Pos (0U) +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 \ + ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ +#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ + +#define ADC_SQR3_SQ11_Pos (6U) +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 \ + ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ +#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ + +#define ADC_SQR3_SQ12_Pos (12U) +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 \ + ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ +#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ + +#define ADC_SQR3_SQ13_Pos (18U) +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 \ + ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ +#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ + +#define ADC_SQR3_SQ14_Pos (24U) +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 \ + ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ +#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR4 register ******************/ +#define ADC_SQR4_SQ15_Pos (0U) +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 \ + ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ +#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ + +#define ADC_SQR4_SQ16_Pos (6U) +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 \ + ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ +#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_RDATA_Pos (0U) +#define ADC_DR_RDATA_Msk (0xFFFFUL << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_RDATA \ + ADC_DR_RDATA_Msk /*!< ADC group regular conversion data \ + */ +#define ADC_DR_RDATA_0 (0x0001UL << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ +#define ADC_DR_RDATA_1 (0x0002UL << ADC_DR_RDATA_Pos) /*!< 0x00000002 */ +#define ADC_DR_RDATA_2 (0x0004UL << ADC_DR_RDATA_Pos) /*!< 0x00000004 */ +#define ADC_DR_RDATA_3 (0x0008UL << ADC_DR_RDATA_Pos) /*!< 0x00000008 */ +#define ADC_DR_RDATA_4 (0x0010UL << ADC_DR_RDATA_Pos) /*!< 0x00000010 */ +#define ADC_DR_RDATA_5 (0x0020UL << ADC_DR_RDATA_Pos) /*!< 0x00000020 */ +#define ADC_DR_RDATA_6 (0x0040UL << ADC_DR_RDATA_Pos) /*!< 0x00000040 */ +#define ADC_DR_RDATA_7 (0x0080UL << ADC_DR_RDATA_Pos) /*!< 0x00000080 */ +#define ADC_DR_RDATA_8 (0x0100UL << ADC_DR_RDATA_Pos) /*!< 0x00000100 */ +#define ADC_DR_RDATA_9 (0x0200UL << ADC_DR_RDATA_Pos) /*!< 0x00000200 */ +#define ADC_DR_RDATA_10 (0x0400UL << ADC_DR_RDATA_Pos) /*!< 0x00000400 */ +#define ADC_DR_RDATA_11 (0x0800UL << ADC_DR_RDATA_Pos) /*!< 0x00000800 */ +#define ADC_DR_RDATA_12 (0x1000UL << ADC_DR_RDATA_Pos) /*!< 0x00001000 */ +#define ADC_DR_RDATA_13 (0x2000UL << ADC_DR_RDATA_Pos) /*!< 0x00002000 */ +#define ADC_DR_RDATA_14 (0x4000UL << ADC_DR_RDATA_Pos) /*!< 0x00004000 */ +#define ADC_DR_RDATA_15 (0x8000UL << ADC_DR_RDATA_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for ADC_JSQR register ******************/ +#define ADC_JSQR_JL_Pos (0U) +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL \ + ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ + +#define ADC_JSQR_JEXTSEL_Pos (2U) +#define ADC_JSQR_JEXTSEL_Msk \ + (0xFUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000003C \ + */ +#define ADC_JSQR_JEXTSEL \ + ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */ +#define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ + +#define ADC_JSQR_JEXTEN_Pos (6U) +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x000000C0 */ +#define ADC_JSQR_JEXTEN \ + ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000040 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ + +#define ADC_JSQR_JSQ1_Pos (8U) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001F00 */ +#define ADC_JSQR_JSQ1 \ + ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000100 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ + +#define ADC_JSQR_JSQ2_Pos (14U) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */ +#define ADC_JSQR_JSQ2 \ + ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ + +#define ADC_JSQR_JSQ3_Pos (20U) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x01F00000 */ +#define ADC_JSQR_JSQ3 \ + ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00100000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ + +#define ADC_JSQR_JSQ4_Pos (26U) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0x7C000000 */ +#define ADC_JSQR_JSQ4 \ + ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x04000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_OFR1 register ******************/ +#define ADC_OFR1_OFFSET1_Pos (0U) +#define ADC_OFR1_OFFSET1_Msk \ + (0xFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */ +#define ADC_OFR1_OFFSET1 \ + ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */ +#define ADC_OFR1_OFFSET1_0 \ + (0x001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 \ + */ +#define ADC_OFR1_OFFSET1_1 \ + (0x002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 \ + */ +#define ADC_OFR1_OFFSET1_2 \ + (0x004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 \ + */ +#define ADC_OFR1_OFFSET1_3 \ + (0x008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 \ + */ +#define ADC_OFR1_OFFSET1_4 \ + (0x010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 \ + */ +#define ADC_OFR1_OFFSET1_5 \ + (0x020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 \ + */ +#define ADC_OFR1_OFFSET1_6 \ + (0x040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 \ + */ +#define ADC_OFR1_OFFSET1_7 \ + (0x080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 \ + */ +#define ADC_OFR1_OFFSET1_8 \ + (0x100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 \ + */ +#define ADC_OFR1_OFFSET1_9 \ + (0x200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 \ + */ +#define ADC_OFR1_OFFSET1_10 \ + (0x400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 \ + */ +#define ADC_OFR1_OFFSET1_11 \ + (0x800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 \ + */ + +#define ADC_OFR1_OFFSET1_CH_Pos (26U) +#define ADC_OFR1_OFFSET1_CH_Msk \ + (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR1_OFFSET1_CH \ + ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */ +#define ADC_OFR1_OFFSET1_CH_0 \ + (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR1_OFFSET1_CH_1 \ + (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR1_OFFSET1_CH_2 \ + (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR1_OFFSET1_CH_3 \ + (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR1_OFFSET1_CH_4 \ + (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR1_OFFSET1_EN_Pos (31U) +#define ADC_OFR1_OFFSET1_EN_Msk \ + (0x1UL << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR1_OFFSET1_EN \ + ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */ + +/******************** Bit definition for ADC_OFR2 register ******************/ +#define ADC_OFR2_OFFSET2_Pos (0U) +#define ADC_OFR2_OFFSET2_Msk \ + (0xFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */ +#define ADC_OFR2_OFFSET2 \ + ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */ +#define ADC_OFR2_OFFSET2_0 \ + (0x001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 \ + */ +#define ADC_OFR2_OFFSET2_1 \ + (0x002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 \ + */ +#define ADC_OFR2_OFFSET2_2 \ + (0x004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 \ + */ +#define ADC_OFR2_OFFSET2_3 \ + (0x008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 \ + */ +#define ADC_OFR2_OFFSET2_4 \ + (0x010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 \ + */ +#define ADC_OFR2_OFFSET2_5 \ + (0x020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 \ + */ +#define ADC_OFR2_OFFSET2_6 \ + (0x040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 \ + */ +#define ADC_OFR2_OFFSET2_7 \ + (0x080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 \ + */ +#define ADC_OFR2_OFFSET2_8 \ + (0x100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 \ + */ +#define ADC_OFR2_OFFSET2_9 \ + (0x200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 \ + */ +#define ADC_OFR2_OFFSET2_10 \ + (0x400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 \ + */ +#define ADC_OFR2_OFFSET2_11 \ + (0x800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 \ + */ + +#define ADC_OFR2_OFFSET2_CH_Pos (26U) +#define ADC_OFR2_OFFSET2_CH_Msk \ + (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR2_OFFSET2_CH \ + ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */ +#define ADC_OFR2_OFFSET2_CH_0 \ + (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR2_OFFSET2_CH_1 \ + (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR2_OFFSET2_CH_2 \ + (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR2_OFFSET2_CH_3 \ + (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR2_OFFSET2_CH_4 \ + (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR2_OFFSET2_EN_Pos (31U) +#define ADC_OFR2_OFFSET2_EN_Msk \ + (0x1UL << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR2_OFFSET2_EN \ + ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */ + +/******************** Bit definition for ADC_OFR3 register ******************/ +#define ADC_OFR3_OFFSET3_Pos (0U) +#define ADC_OFR3_OFFSET3_Msk \ + (0xFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */ +#define ADC_OFR3_OFFSET3 \ + ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */ +#define ADC_OFR3_OFFSET3_0 \ + (0x001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 \ + */ +#define ADC_OFR3_OFFSET3_1 \ + (0x002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 \ + */ +#define ADC_OFR3_OFFSET3_2 \ + (0x004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 \ + */ +#define ADC_OFR3_OFFSET3_3 \ + (0x008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 \ + */ +#define ADC_OFR3_OFFSET3_4 \ + (0x010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 \ + */ +#define ADC_OFR3_OFFSET3_5 \ + (0x020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 \ + */ +#define ADC_OFR3_OFFSET3_6 \ + (0x040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 \ + */ +#define ADC_OFR3_OFFSET3_7 \ + (0x080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 \ + */ +#define ADC_OFR3_OFFSET3_8 \ + (0x100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 \ + */ +#define ADC_OFR3_OFFSET3_9 \ + (0x200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 \ + */ +#define ADC_OFR3_OFFSET3_10 \ + (0x400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 \ + */ +#define ADC_OFR3_OFFSET3_11 \ + (0x800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 \ + */ + +#define ADC_OFR3_OFFSET3_CH_Pos (26U) +#define ADC_OFR3_OFFSET3_CH_Msk \ + (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR3_OFFSET3_CH \ + ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */ +#define ADC_OFR3_OFFSET3_CH_0 \ + (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR3_OFFSET3_CH_1 \ + (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR3_OFFSET3_CH_2 \ + (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR3_OFFSET3_CH_3 \ + (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR3_OFFSET3_CH_4 \ + (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR3_OFFSET3_EN_Pos (31U) +#define ADC_OFR3_OFFSET3_EN_Msk \ + (0x1UL << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR3_OFFSET3_EN \ + ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */ + +/******************** Bit definition for ADC_OFR4 register ******************/ +#define ADC_OFR4_OFFSET4_Pos (0U) +#define ADC_OFR4_OFFSET4_Msk \ + (0xFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */ +#define ADC_OFR4_OFFSET4 \ + ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */ +#define ADC_OFR4_OFFSET4_0 \ + (0x001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 \ + */ +#define ADC_OFR4_OFFSET4_1 \ + (0x002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 \ + */ +#define ADC_OFR4_OFFSET4_2 \ + (0x004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 \ + */ +#define ADC_OFR4_OFFSET4_3 \ + (0x008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 \ + */ +#define ADC_OFR4_OFFSET4_4 \ + (0x010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 \ + */ +#define ADC_OFR4_OFFSET4_5 \ + (0x020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 \ + */ +#define ADC_OFR4_OFFSET4_6 \ + (0x040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 \ + */ +#define ADC_OFR4_OFFSET4_7 \ + (0x080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 \ + */ +#define ADC_OFR4_OFFSET4_8 \ + (0x100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 \ + */ +#define ADC_OFR4_OFFSET4_9 \ + (0x200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 \ + */ +#define ADC_OFR4_OFFSET4_10 \ + (0x400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 \ + */ +#define ADC_OFR4_OFFSET4_11 \ + (0x800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 \ + */ + +#define ADC_OFR4_OFFSET4_CH_Pos (26U) +#define ADC_OFR4_OFFSET4_CH_Msk \ + (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR4_OFFSET4_CH \ + ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */ +#define ADC_OFR4_OFFSET4_CH_0 \ + (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR4_OFFSET4_CH_1 \ + (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR4_OFFSET4_CH_2 \ + (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR4_OFFSET4_CH_3 \ + (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR4_OFFSET4_CH_4 \ + (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR4_OFFSET4_EN_Pos (31U) +#define ADC_OFR4_OFFSET4_EN_Msk \ + (0x1UL << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR4_OFFSET4_EN \ + ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */ + +/******************** Bit definition for ADC_JDR1 register ******************/ +#define ADC_JDR1_JDATA_Pos (0U) +#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR1_JDATA \ + ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data \ + */ +#define ADC_JDR1_JDATA_0 (0x0001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR1_JDATA_1 (0x0002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR1_JDATA_2 (0x0004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR1_JDATA_3 (0x0008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR1_JDATA_4 (0x0010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR1_JDATA_5 (0x0020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR1_JDATA_6 (0x0040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR1_JDATA_7 (0x0080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR1_JDATA_8 (0x0100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR1_JDATA_9 (0x0200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR1_JDATA_10 (0x0400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR1_JDATA_11 (0x0800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR1_JDATA_12 (0x1000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR1_JDATA_13 (0x2000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR1_JDATA_14 (0x4000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR1_JDATA_15 (0x8000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for ADC_JDR2 register ******************/ +#define ADC_JDR2_JDATA_Pos (0U) +#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR2_JDATA \ + ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data \ + */ +#define ADC_JDR2_JDATA_0 (0x0001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR2_JDATA_1 (0x0002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR2_JDATA_2 (0x0004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR2_JDATA_3 (0x0008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR2_JDATA_4 (0x0010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR2_JDATA_5 (0x0020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR2_JDATA_6 (0x0040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR2_JDATA_7 (0x0080UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR2_JDATA_8 (0x0100UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR2_JDATA_9 (0x0200UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR2_JDATA_10 (0x0400UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR2_JDATA_11 (0x0800UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR2_JDATA_12 (0x1000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR2_JDATA_13 (0x2000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR2_JDATA_14 (0x4000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR2_JDATA_15 (0x8000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for ADC_JDR3 register ******************/ +#define ADC_JDR3_JDATA_Pos (0U) +#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR3_JDATA \ + ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data \ + */ +#define ADC_JDR3_JDATA_0 (0x0001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR3_JDATA_1 (0x0002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR3_JDATA_2 (0x0004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR3_JDATA_3 (0x0008UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR3_JDATA_4 (0x0010UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR3_JDATA_5 (0x0020UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR3_JDATA_6 (0x0040UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR3_JDATA_7 (0x0080UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR3_JDATA_8 (0x0100UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR3_JDATA_9 (0x0200UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR3_JDATA_10 (0x0400UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR3_JDATA_11 (0x0800UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR3_JDATA_12 (0x1000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR3_JDATA_13 (0x2000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR3_JDATA_14 (0x4000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR3_JDATA_15 (0x8000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for ADC_JDR4 register ******************/ +#define ADC_JDR4_JDATA_Pos (0U) +#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR4_JDATA \ + ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data \ + */ +#define ADC_JDR4_JDATA_0 (0x0001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR4_JDATA_1 (0x0002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR4_JDATA_2 (0x0004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR4_JDATA_3 (0x0008UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR4_JDATA_4 (0x0010UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR4_JDATA_5 (0x0020UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR4_JDATA_6 (0x0040UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR4_JDATA_7 (0x0080UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR4_JDATA_8 (0x0100UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR4_JDATA_9 (0x0200UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR4_JDATA_10 (0x0400UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR4_JDATA_11 (0x0800UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR4_JDATA_12 (0x1000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR4_JDATA_13 (0x2000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR4_JDATA_14 (0x4000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR4_JDATA_15 (0x8000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for ADC_AWD2CR register ****************/ +#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Msk \ + (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD2CR_AWD2CH \ + ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection \ + */ +#define ADC_AWD2CR_AWD2CH_0 \ + (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 \ + (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 \ + (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 \ + (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 \ + (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 \ + (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 \ + (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 \ + (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 \ + (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 \ + (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 \ + (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 \ + (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 \ + (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 \ + (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 \ + (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 \ + (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 \ + (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 \ + (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 \ + (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_AWD3CR register ****************/ +#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Msk \ + (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD3CR_AWD3CH \ + ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection \ + */ +#define ADC_AWD3CR_AWD3CH_0 \ + (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 \ + (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 \ + (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 \ + (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 \ + (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 \ + (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 \ + (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 \ + (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 \ + (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 \ + (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 \ + (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 \ + (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 \ + (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 \ + (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 \ + (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 \ + (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 \ + (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 \ + (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 \ + (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_DIFSEL register ****************/ +#define ADC_DIFSEL_DIFSEL_Pos (0U) +#define ADC_DIFSEL_DIFSEL_Msk \ + (0x7FFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */ +#define ADC_DIFSEL_DIFSEL \ + ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */ +#define ADC_DIFSEL_DIFSEL_0 \ + (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_DIFSEL_1 \ + (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_2 \ + (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_3 \ + (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_4 \ + (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_5 \ + (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_6 \ + (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_7 \ + (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_8 \ + (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_9 \ + (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_10 \ + (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_11 \ + (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_12 \ + (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_13 \ + (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_14 \ + (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_15 \ + (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_16 \ + (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_17 \ + (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_18 \ + (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_CALFACT register ***************/ +#define ADC_CALFACT_CALFACT_S_Pos (0U) +#define ADC_CALFACT_CALFACT_S_Msk \ + (0x7FUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT_S \ + ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode \ + */ +#define ADC_CALFACT_CALFACT_S_0 \ + (0x01UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_S_1 \ + (0x02UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_S_2 \ + (0x04UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_S_3 \ + (0x08UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_S_4 \ + (0x10UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_S_5 \ + (0x20UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_S_6 \ + (0x40UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */ + +#define ADC_CALFACT_CALFACT_D_Pos (16U) +#define ADC_CALFACT_CALFACT_D_Msk \ + (0x7FUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */ +#define ADC_CALFACT_CALFACT_D \ + ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode \ + */ +#define ADC_CALFACT_CALFACT_D_0 \ + (0x01UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_CALFACT_D_1 \ + (0x02UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT_CALFACT_D_2 \ + (0x04UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT_CALFACT_D_3 \ + (0x08UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT_CALFACT_D_4 \ + (0x10UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT_CALFACT_D_5 \ + (0x20UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT_CALFACT_D_6 \ + (0x40UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CSR register *******************/ +#define ADC_CSR_ADRDY_MST_Pos (0U) +#define ADC_CSR_ADRDY_MST_Msk \ + (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST \ + ADC_CSR_ADRDY_MST_Msk /*!< ADC multimode master ready flag */ +#define ADC_CSR_EOSMP_MST_Pos (1U) +#define ADC_CSR_EOSMP_MST_Msk \ + (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST \ + ADC_CSR_EOSMP_MST_Msk /*!< ADC multimode master group regular end of \ + sampling flag */ +#define ADC_CSR_EOC_MST_Pos (2U) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST \ + ADC_CSR_EOC_MST_Msk /*!< ADC multimode master group regular end of unitary \ + conversion flag */ +#define ADC_CSR_EOS_MST_Pos (3U) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST \ + ADC_CSR_EOS_MST_Msk /*!< ADC multimode master group regular end of sequence \ + conversions flag */ +#define ADC_CSR_OVR_MST_Pos (4U) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST \ + ADC_CSR_OVR_MST_Msk /*!< ADC multimode master group regular overrun flag */ +#define ADC_CSR_JEOC_MST_Pos (5U) +#define ADC_CSR_JEOC_MST_Msk \ + (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 \ + */ +#define ADC_CSR_JEOC_MST \ + ADC_CSR_JEOC_MST_Msk /*!< ADC multimode master group injected end of unitary \ + conversion flag */ +#define ADC_CSR_JEOS_MST_Pos (6U) +#define ADC_CSR_JEOS_MST_Msk \ + (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 \ + */ +#define ADC_CSR_JEOS_MST \ + ADC_CSR_JEOS_MST_Msk /*!< ADC multimode master group injected end of \ + sequence conversions flag */ +#define ADC_CSR_AWD1_MST_Pos (7U) +#define ADC_CSR_AWD1_MST_Msk \ + (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 \ + */ +#define ADC_CSR_AWD1_MST \ + ADC_CSR_AWD1_MST_Msk /*!< ADC multimode master analog watchdog 1 flag */ +#define ADC_CSR_AWD2_MST_Pos (8U) +#define ADC_CSR_AWD2_MST_Msk \ + (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 \ + */ +#define ADC_CSR_AWD2_MST \ + ADC_CSR_AWD2_MST_Msk /*!< ADC multimode master analog watchdog 2 flag */ +#define ADC_CSR_AWD3_MST_Pos (9U) +#define ADC_CSR_AWD3_MST_Msk \ + (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 \ + */ +#define ADC_CSR_AWD3_MST \ + ADC_CSR_AWD3_MST_Msk /*!< ADC multimode master analog watchdog 3 flag */ +#define ADC_CSR_JQOVF_MST_Pos (10U) +#define ADC_CSR_JQOVF_MST_Msk \ + (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST \ + ADC_CSR_JQOVF_MST_Msk /*!< ADC multimode master group injected contexts \ + queue overflow flag */ + +#define ADC_CSR_ADRDY_SLV_Pos (16U) +#define ADC_CSR_ADRDY_SLV_Msk \ + (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV \ + ADC_CSR_ADRDY_SLV_Msk /*!< ADC multimode slave ready flag */ +#define ADC_CSR_EOSMP_SLV_Pos (17U) +#define ADC_CSR_EOSMP_SLV_Msk \ + (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV \ + ADC_CSR_EOSMP_SLV_Msk /*!< ADC multimode slave group regular end of sampling \ + flag */ +#define ADC_CSR_EOC_SLV_Pos (18U) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV \ + ADC_CSR_EOC_SLV_Msk /*!< ADC multimode slave group regular end of unitary \ + conversion flag */ +#define ADC_CSR_EOS_SLV_Pos (19U) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV \ + ADC_CSR_EOS_SLV_Msk /*!< ADC multimode slave group regular end of sequence \ + conversions flag */ +#define ADC_CSR_OVR_SLV_Pos (20U) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV \ + ADC_CSR_OVR_SLV_Msk /*!< ADC multimode slave group regular overrun flag */ +#define ADC_CSR_JEOC_SLV_Pos (21U) +#define ADC_CSR_JEOC_SLV_Msk \ + (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 \ + */ +#define ADC_CSR_JEOC_SLV \ + ADC_CSR_JEOC_SLV_Msk /*!< ADC multimode slave group injected end of unitary \ + conversion flag */ +#define ADC_CSR_JEOS_SLV_Pos (22U) +#define ADC_CSR_JEOS_SLV_Msk \ + (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 \ + */ +#define ADC_CSR_JEOS_SLV \ + ADC_CSR_JEOS_SLV_Msk /*!< ADC multimode slave group injected end of sequence \ + conversions flag */ +#define ADC_CSR_AWD1_SLV_Pos (23U) +#define ADC_CSR_AWD1_SLV_Msk \ + (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 \ + */ +#define ADC_CSR_AWD1_SLV \ + ADC_CSR_AWD1_SLV_Msk /*!< ADC multimode slave analog watchdog 1 flag */ +#define ADC_CSR_AWD2_SLV_Pos (24U) +#define ADC_CSR_AWD2_SLV_Msk \ + (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 \ + */ +#define ADC_CSR_AWD2_SLV \ + ADC_CSR_AWD2_SLV_Msk /*!< ADC multimode slave analog watchdog 2 flag */ +#define ADC_CSR_AWD3_SLV_Pos (25U) +#define ADC_CSR_AWD3_SLV_Msk \ + (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 \ + */ +#define ADC_CSR_AWD3_SLV \ + ADC_CSR_AWD3_SLV_Msk /*!< ADC multimode slave analog watchdog 3 flag */ +#define ADC_CSR_JQOVF_SLV_Pos (26U) +#define ADC_CSR_JQOVF_SLV_Msk \ + (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV \ + ADC_CSR_JQOVF_SLV_Msk /*!< ADC multimode slave group injected contexts queue \ + overflow flag */ + +/******************** Bit definition for ADC_CCR register *******************/ +#define ADC_CCR_DUAL_Pos (0U) +#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ +#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */ +#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ +#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ +#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ +#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ +#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ + +#define ADC_CCR_DELAY_Pos (8U) +#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ +#define ADC_CCR_DELAY \ + ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */ +#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ +#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ +#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ +#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ + +#define ADC_CCR_DMACFG_Pos (13U) +#define ADC_CCR_DMACFG_Msk (0x1UL << ADC_CCR_DMACFG_Pos) /*!< 0x00002000 */ +#define ADC_CCR_DMACFG \ + ADC_CCR_DMACFG_Msk /*!< ADC multimode DMA transfer configuration */ + +#define ADC_CCR_MDMA_Pos (14U) +#define ADC_CCR_MDMA_Msk (0x3UL << ADC_CCR_MDMA_Pos) /*!< 0x0000C000 */ +#define ADC_CCR_MDMA \ + ADC_CCR_MDMA_Msk /*!< ADC multimode DMA transfer enable \ + */ +#define ADC_CCR_MDMA_0 (0x1UL << ADC_CCR_MDMA_Pos) /*!< 0x00004000 */ +#define ADC_CCR_MDMA_1 (0x2UL << ADC_CCR_MDMA_Pos) /*!< 0x00008000 */ + +#define ADC_CCR_CKMODE_Pos (16U) +#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ +#define ADC_CCR_CKMODE \ + ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler \ + only for clock source synchronous) */ +#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ +#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ + +#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC \ + ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source \ + asynchronous */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN \ + ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN \ + ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ +#define ADC_CCR_VBATEN_Pos (24U) +#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN \ + ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ + +/******************** Bit definition for ADC_CDR register *******************/ +#define ADC_CDR_RDATA_MST_Pos (0U) +#define ADC_CDR_RDATA_MST_Msk \ + (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ +#define ADC_CDR_RDATA_MST \ + ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion \ + data */ +#define ADC_CDR_RDATA_MST_0 \ + (0x0001UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000001 */ +#define ADC_CDR_RDATA_MST_1 \ + (0x0002UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000002 */ +#define ADC_CDR_RDATA_MST_2 \ + (0x0004UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000004 */ +#define ADC_CDR_RDATA_MST_3 \ + (0x0008UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000008 */ +#define ADC_CDR_RDATA_MST_4 \ + (0x0010UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000010 */ +#define ADC_CDR_RDATA_MST_5 \ + (0x0020UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000020 */ +#define ADC_CDR_RDATA_MST_6 \ + (0x0040UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000040 */ +#define ADC_CDR_RDATA_MST_7 \ + (0x0080UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000080 */ +#define ADC_CDR_RDATA_MST_8 \ + (0x0100UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000100 */ +#define ADC_CDR_RDATA_MST_9 \ + (0x0200UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000200 */ +#define ADC_CDR_RDATA_MST_10 \ + (0x0400UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000400 */ +#define ADC_CDR_RDATA_MST_11 \ + (0x0800UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000800 */ +#define ADC_CDR_RDATA_MST_12 \ + (0x1000UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00001000 */ +#define ADC_CDR_RDATA_MST_13 \ + (0x2000UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00002000 */ +#define ADC_CDR_RDATA_MST_14 \ + (0x4000UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00004000 */ +#define ADC_CDR_RDATA_MST_15 \ + (0x8000UL << ADC_CDR_RDATA_MST_Pos) /*!< 0x00008000 */ + +#define ADC_CDR_RDATA_SLV_Pos (16U) +#define ADC_CDR_RDATA_SLV_Msk \ + (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ +#define ADC_CDR_RDATA_SLV \ + ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data \ + */ +#define ADC_CDR_RDATA_SLV_0 \ + (0x0001UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CDR_RDATA_SLV_1 \ + (0x0002UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CDR_RDATA_SLV_2 \ + (0x0004UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CDR_RDATA_SLV_3 \ + (0x0008UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CDR_RDATA_SLV_4 \ + (0x0010UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CDR_RDATA_SLV_5 \ + (0x0020UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CDR_RDATA_SLV_6 \ + (0x0040UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CDR_RDATA_SLV_7 \ + (0x0080UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CDR_RDATA_SLV_8 \ + (0x0100UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CDR_RDATA_SLV_9 \ + (0x0200UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CDR_RDATA_SLV_10 \ + (0x0400UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CDR_RDATA_SLV_11 \ + (0x0800UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x08000000 */ +#define ADC_CDR_RDATA_SLV_12 \ + (0x1000UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x10000000 */ +#define ADC_CDR_RDATA_SLV_13 \ + (0x2000UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x20000000 */ +#define ADC_CDR_RDATA_SLV_14 \ + (0x4000UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x40000000 */ +#define ADC_CDR_RDATA_SLV_15 \ + (0x8000UL << ADC_CDR_RDATA_SLV_Pos) /*!< 0x80000000 */ + +/******************************************************************************/ +/* */ +/* Controller Area Network */ +/* */ +/******************************************************************************/ +/*!*/ +#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ + +#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Msk \ + (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1 \ + DAC_SWTRIGR_SWTRIG1_Msk /*! u32 { + use core::sync::atomic::Ordering; + SYSTEM_CLOCK.load(Ordering::SeqCst) +} + +#[cfg(all(target_arch = "arm", target_os = "none"))] +pub static mut SYSTEM_TIME: Duration = Duration::new(0, 0); + +#[cfg(all(target_arch = "arm", target_os = "none"))] +pub fn get_current_time() -> Duration { + unsafe { SYSTEM_TIME } +} + +#[cfg(any(target_family = "windows", target_family = "unix"))] +pub fn get_current_time() -> Duration { + use std::time::Instant; + static mut INITIALIZE_INSTANT: Option = None; + unsafe { + if INITIALIZE_INSTANT.is_none() { + INITIALIZE_INSTANT = Some(Instant::now()); + Duration::new(0, 0) + } else { + INITIALIZE_INSTANT.unwrap().elapsed() + } + } +} diff --git a/minimal_async_basic/l0/src/lib.rs b/minimal_async_basic/l0/src/lib.rs new file mode 100644 index 0000000..5eb4f21 --- /dev/null +++ b/minimal_async_basic/l0/src/lib.rs @@ -0,0 +1,26 @@ +#![cfg_attr(not(test), no_std)] + +#[cfg(any(target_family = "windows", target_family = "unix"))] +extern crate std; + +// * Private to l0 +mod global; // Testable + +#[cfg(all(target_arch = "arm", target_os = "none"))] +mod rust_entry_point; + +// TODO, Add features +// #[cfg(feature = "stm32l475xx")] +#[cfg(all(target_arch = "arm", target_os = "none"))] +mod stm32l475xx; +#[cfg(all(target_arch = "arm", target_os = "none"))] +use stm32l475xx as chip; + +// * Public APIs usable when l0 is a dependency +mod utility; // Macro export makes macros always public, Testable +pub use utility::*; + +#[cfg(all(target_arch = "arm", target_os = "none"))] +pub use chip::public::*; + +pub use global::{get_current_time, get_system_clock}; diff --git a/minimal_async_basic/l0/src/rust_entry_point.rs b/minimal_async_basic/l0/src/rust_entry_point.rs new file mode 100644 index 0000000..aadebfe --- /dev/null +++ b/minimal_async_basic/l0/src/rust_entry_point.rs @@ -0,0 +1,6 @@ +use core::panic::PanicInfo; + +#[panic_handler] +pub fn panic(_panic: &PanicInfo<'_>) -> ! { + loop {} +} diff --git a/minimal_async_basic/l0/src/stm32l475xx/arm_cm4.rs b/minimal_async_basic/l0/src/stm32l475xx/arm_cm4.rs new file mode 100644 index 0000000..f7967fd --- /dev/null +++ b/minimal_async_basic/l0/src/stm32l475xx/arm_cm4.rs @@ -0,0 +1,73 @@ +pub mod nvic { + use crate::{write_register, Interrupt, NVIC_PORT, __NVIC_PRIO_BITS}; + + pub fn enable_irq(irq: Interrupt) { + // NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + let nvic_port = NVIC_PORT::port(); + write_register!( + nvic_port.ISER[(irq as usize) >> 5], + 1 << ((irq as u8) & 0x1F) + ); + } + + pub fn set_priority(irq: Interrupt, priority: u8) { + // NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + let nvic_port = NVIC_PORT::port(); + const SHIFT: u8 = 8 - __NVIC_PRIO_BITS as u8; + write_register!(nvic_port.IP[irq as usize], priority << SHIFT); + } +} + +pub mod arm { + use core::arch::asm; + + pub fn ldrexw(addr: *const u32) -> u32 { + // __ASM volatile("ldrex %0, %1" + // : "=r"(result) + // : "Q"(*addr)); + let result: u32; + unsafe { + asm!( + "ldrex {0}, [{1}]", out(reg) result, in(reg) addr); + } + result + } + + pub fn strexw(addr: *const u32, data: u32) -> u32 { + // __ASM volatile("strex %0, %2, %1" + // : "=&r"(result), "=Q"(*addr) + // : "r"(value)); + let result: u32; + unsafe { + asm!("strex {0}, {2}, [{1}]", out(reg) result, in(reg) addr, in(reg) data); + } + result + } + + /// Example usage: + /// let mut storage = 2; + /// let storage_mut = &mut storage; + /// loop { + /// let mut data = arm::ldrexw(storage_mut); + /// data += 25; // mutate or check data + /// let stored = arm::strexw(storage_mut, data); + /// if stored == 0 { + /// break; + /// } + /// } + pub fn simple_mutex(addr: *const u32, mut mutate_data_cb: F) + where + F: FnMut(u32) -> (u32, bool), + { + loop { + let data = ldrexw(addr); + let (data, store) = mutate_data_cb(data); + if !store { + break; + } + if strexw(addr, data) == 0 { + break; + } + } + } +} diff --git a/minimal_async_basic/l0/src/stm32l475xx/entry_point.rs b/minimal_async_basic/l0/src/stm32l475xx/entry_point.rs new file mode 100644 index 0000000..9687bc5 --- /dev/null +++ b/minimal_async_basic/l0/src/stm32l475xx/entry_point.rs @@ -0,0 +1,98 @@ +use core::{ops::Add, time::Duration}; + +use crate::{chip::controller_init, global::SYSTEM_TIME}; + +// NOTE, All the externed modules come here +#[no_mangle] +pub unsafe extern "C" fn Reset() { + // Data and BSS sections + extern "C" { + // .data section + static mut __data_end__: u8; + static mut __data_start__: u8; + static mut __etext: u8; + + // .bss section + static mut __bss_start__: u8; + static mut __bss_end__: u8; + } + + // Copy from VMA to LMA + let vma_data_end = &__data_end__ as *const u8; + let vma_data_start = &__data_start__ as *const u8; + let lma_data_start = &__etext as *const u8; + let count: usize = vma_data_end as usize - vma_data_start as usize; + // core::ptr::copy_nonoverlapping(lma_data_start, &mut __data_start__ as *mut u8, count); + core::ptr::copy_nonoverlapping(lma_data_start, vma_data_start as *mut u8, count); + + // Write 0 to .bss section + let bss_end = &__bss_end__ as *const u8; + let bss_start = &__bss_start__ as *const u8; + let count = bss_end as usize - bss_start as usize; + // core::ptr::write_bytes(&mut __bss_start__ as *mut u8, 0, count); + core::ptr::write_bytes(bss_start as *mut u8, 0, count); + + // Controller level startup system initialization + + // Jump to L0 controller system init + // TODO, Jump to L4 board init + // Jump to L5 main function + extern "Rust" { + fn main() -> !; + } + controller_init(); + main(); +} + +extern "C" { + fn __StackTop(); // Check `gcc_arm.ld` + fn NMI(); + fn HardFault(); + fn MemManage(); + fn BusFault(); + fn UsageFault(); + fn SVCall(); + fn PendSV(); +} + +#[repr(C)] +pub union Vector { + reserved: u32, + handler: unsafe extern "C" fn(), +} + +#[link_section = ".vector_table.exceptions"] +#[no_mangle] +pub static EXCEPTIONS: [Vector; 16] = [ + Vector { + handler: __StackTop, + }, + Vector { handler: Reset }, + Vector { handler: NMI }, + Vector { handler: HardFault }, + Vector { handler: MemManage }, + Vector { handler: BusFault }, + Vector { + handler: UsageFault, + }, + Vector { reserved: 0 }, + Vector { reserved: 0 }, + Vector { reserved: 0 }, + Vector { reserved: 0 }, + Vector { handler: SVCall }, + Vector { reserved: 0 }, // Debug Monitor Handler comes here + Vector { reserved: 0 }, + Vector { handler: PendSV }, + Vector { handler: SysTick }, +]; + +// SysTick interrupt +#[no_mangle] +unsafe extern "C" fn SysTick() { + SYSTEM_TIME = SYSTEM_TIME.add(Duration::from_millis(1)); +} + +#[no_mangle] +pub extern "C" fn DefaultExceptionHandler() { + loop {} +} diff --git a/minimal_async_basic/l0/src/stm32l475xx/interrupt.rs b/minimal_async_basic/l0/src/stm32l475xx/interrupt.rs new file mode 100644 index 0000000..c93c95b --- /dev/null +++ b/minimal_async_basic/l0/src/stm32l475xx/interrupt.rs @@ -0,0 +1,257 @@ +#[derive(Copy, Clone)] +pub enum Interrupt { + WWDG, + PVD_PVM, + RTC_TAMP_STAMP, + RTC_WKUP, + FLASH, + RCC, + EXTI0, + EXTI1, + EXTI2, + EXTI3, + EXTI4, + DMA1_CH1, + DMA1_CH2, + DMA1_CH3, + DMA1_CH4, + DMA1_CH5, + DMA1_CH6, + DMA1_CH7, + ADC1_2, + CAN1_TX, + CAN1_RX0, + CAN1_RX1, + CAN1_SCE, + EXTI9_5, + TIM1_BRK, + TIM1_UP, + TIM1_TRG_COM, + TIM1_CC, + TIM2, + TIM3, + TIM4, + I2C1_EV, + I2C1_ER, + I2C2_EV, + I2C2_ER, + SPI1, + SPI2, + USART1, + USART2, + USART3, + EXTI15_10, + RTC_ALARM, + DFSDM1_FLT3, + TIM8_BRK, + TIM8_UP, + TIM8_TRG_COM, + TIM8_CC, + ADC3, + FMC, + SDMMC1, + TIM5, + SPI3, + UART4, + UART5, + TIM6_DAC, + TIM7, + DMA2_CH1, + DMA2_CH2, + DMA2_CH3, + DMA2_CH4, + DMA2_CH5, + DFSDM1_FLT0, + DFSDM1_FLT1, + DFSDM1_FLT2, + COMP, + LPTIM1, + LPTIM2, + OTG_FS, + DMA2_CH6, + DMA2_CH7, + LPUART1, + QUADSPI, + I2C3_EV, + I2C3_ER, + SAI1, + SAI2, + SWPMI1, + TSC, + LCD, + AES, + RNG, + FPU, +} + +extern "C" { + fn WWDG_Interrupt_Handler(); + fn PVD_PVM_Interrupt_Handler(); + fn RTC_TAMP_STAMP_Interrupt_Handler(); + fn RTC_WKUP_Interrupt_Handler(); + fn FLASH_Interrupt_Handler(); + fn RCC_Interrupt_Handler(); + fn EXTI0_Interrupt_Handler(); + fn EXTI1_Interrupt_Handler(); + fn EXTI2_Interrupt_Handler(); + fn EXTI3_Interrupt_Handler(); + fn EXTI4_Interrupt_Handler(); + fn DMA1_CH1_Interrupt_Handler(); + fn DMA1_CH2_Interrupt_Handler(); + fn DMA1_CH3_Interrupt_Handler(); + fn DMA1_CH4_Interrupt_Handler(); + fn DMA1_CH5_Interrupt_Handler(); + fn DMA1_CH6_Interrupt_Handler(); + fn DMA1_CH7_Interrupt_Handler(); + fn ADC1_2_Interrupt_Handler(); + fn CAN1_TX_Interrupt_Handler(); + fn CAN1_RX0_Interrupt_Handler(); + fn CAN1_RX1_Interrupt_Handler(); + fn CAN1_SCE_Interrupt_Handler(); + fn EXTI9_5_Interrupt_Handler(); + fn TIM1_BRK_Interrupt_Handler(); + fn TIM1_UP_Interrupt_Handler(); + fn TIM1_TRG_COM_Interrupt_Handler(); + fn TIM1_CC_Interrupt_Handler(); + fn TIM2_Interrupt_Handler(); + fn TIM3_Interrupt_Handler(); + fn TIM4_Interrupt_Handler(); + fn I2C1_EV_Interrupt_Handler(); + fn I2C1_ER_Interrupt_Handler(); + fn I2C2_EV_Interrupt_Handler(); + fn I2C2_ER_Interrupt_Handler(); + fn SPI1_Interrupt_Handler(); + fn SPI2_Interrupt_Handler(); + fn USART1_Interrupt_Handler(); + fn USART2_Interrupt_Handler(); + fn USART3_Interrupt_Handler(); + fn EXTI15_10_Interrupt_Handler(); + fn RTC_ALARM_Interrupt_Handler(); + fn DFSDM1_FLT3_Interrupt_Handler(); + fn TIM8_BRK_Interrupt_Handler(); + fn TIM8_UP_Interrupt_Handler(); + fn TIM8_TRG_COM_Interrupt_Handler(); + fn TIM8_CC_Interrupt_Handler(); + fn ADC3_Interrupt_Handler(); + fn FMC_Interrupt_Handler(); + fn SDMMC1_Interrupt_Handler(); + fn TIM5_Interrupt_Handler(); + fn SPI3_Interrupt_Handler(); + fn UART4_Interrupt_Handler(); + fn UART5_Interrupt_Handler(); + fn TIM6_DAC_Interrupt_Handler(); + fn TIM7_Interrupt_Handler(); + fn DMA2_CH1_Interrupt_Handler(); + fn DMA2_CH2_Interrupt_Handler(); + fn DMA2_CH3_Interrupt_Handler(); + fn DMA2_CH4_Interrupt_Handler(); + fn DMA2_CH5_Interrupt_Handler(); + fn DFSDM1_FLT0_Interrupt_Handler(); + fn DFSDM1_FLT1_Interrupt_Handler(); + fn DFSDM1_FLT2_Interrupt_Handler(); + fn COMP_Interrupt_Handler(); + fn LPTIM1_Interrupt_Handler(); + fn LPTIM2_Interrupt_Handler(); + fn OTG_FS_Interrupt_Handler(); + fn DMA2_CH6_Interrupt_Handler(); + fn DMA2_CH7_Interrupt_Handler(); + fn LPUART1_Interrupt_Handler(); + fn QUADSPI_Interrupt_Handler(); + fn I2C3_EV_Interrupt_Handler(); + fn I2C3_ER_Interrupt_Handler(); + fn SAI1_Interrupt_Handler(); + fn SAI2_Interrupt_Handler(); + fn SWPMI1_Interrupt_Handler(); + fn TSC_Interrupt_Handler(); + fn LCD_Interrupt_Handler(); + fn AES_Interrupt_Handler(); + fn RNG_Interrupt_Handler(); + fn FPU_Interrupt_Handler(); +} + +#[link_section = ".vector_table.interrupts"] +#[no_mangle] +static INTERRUPTS: [unsafe extern "C" fn(); 82] = [ + WWDG_Interrupt_Handler, + PVD_PVM_Interrupt_Handler, + RTC_TAMP_STAMP_Interrupt_Handler, + RTC_WKUP_Interrupt_Handler, + FLASH_Interrupt_Handler, + RCC_Interrupt_Handler, + EXTI0_Interrupt_Handler, + EXTI1_Interrupt_Handler, + EXTI2_Interrupt_Handler, + EXTI3_Interrupt_Handler, + EXTI4_Interrupt_Handler, + DMA1_CH1_Interrupt_Handler, + DMA1_CH2_Interrupt_Handler, + DMA1_CH3_Interrupt_Handler, + DMA1_CH4_Interrupt_Handler, + DMA1_CH5_Interrupt_Handler, + DMA1_CH6_Interrupt_Handler, + DMA1_CH7_Interrupt_Handler, + ADC1_2_Interrupt_Handler, + CAN1_TX_Interrupt_Handler, + CAN1_RX0_Interrupt_Handler, + CAN1_RX1_Interrupt_Handler, + CAN1_SCE_Interrupt_Handler, + EXTI9_5_Interrupt_Handler, + TIM1_BRK_Interrupt_Handler, + TIM1_UP_Interrupt_Handler, + TIM1_TRG_COM_Interrupt_Handler, + TIM1_CC_Interrupt_Handler, + TIM2_Interrupt_Handler, + TIM3_Interrupt_Handler, + TIM4_Interrupt_Handler, + I2C1_EV_Interrupt_Handler, + I2C1_ER_Interrupt_Handler, + I2C2_EV_Interrupt_Handler, + I2C2_ER_Interrupt_Handler, + SPI1_Interrupt_Handler, + SPI2_Interrupt_Handler, + USART1_Interrupt_Handler, + USART2_Interrupt_Handler, + USART3_Interrupt_Handler, + EXTI15_10_Interrupt_Handler, + RTC_ALARM_Interrupt_Handler, + DFSDM1_FLT3_Interrupt_Handler, + TIM8_BRK_Interrupt_Handler, + TIM8_UP_Interrupt_Handler, + TIM8_TRG_COM_Interrupt_Handler, + TIM8_CC_Interrupt_Handler, + ADC3_Interrupt_Handler, + FMC_Interrupt_Handler, + SDMMC1_Interrupt_Handler, + TIM5_Interrupt_Handler, + SPI3_Interrupt_Handler, + UART4_Interrupt_Handler, + UART5_Interrupt_Handler, + TIM6_DAC_Interrupt_Handler, + TIM7_Interrupt_Handler, + DMA2_CH1_Interrupt_Handler, + DMA2_CH2_Interrupt_Handler, + DMA2_CH3_Interrupt_Handler, + DMA2_CH4_Interrupt_Handler, + DMA2_CH5_Interrupt_Handler, + DFSDM1_FLT0_Interrupt_Handler, + DFSDM1_FLT1_Interrupt_Handler, + DFSDM1_FLT2_Interrupt_Handler, + COMP_Interrupt_Handler, + LPTIM1_Interrupt_Handler, + LPTIM2_Interrupt_Handler, + OTG_FS_Interrupt_Handler, + DMA2_CH6_Interrupt_Handler, + DMA2_CH7_Interrupt_Handler, + LPUART1_Interrupt_Handler, + QUADSPI_Interrupt_Handler, + I2C3_EV_Interrupt_Handler, + I2C3_ER_Interrupt_Handler, + SAI1_Interrupt_Handler, + SAI2_Interrupt_Handler, + SWPMI1_Interrupt_Handler, + TSC_Interrupt_Handler, + LCD_Interrupt_Handler, + AES_Interrupt_Handler, + RNG_Interrupt_Handler, + FPU_Interrupt_Handler, +]; diff --git a/minimal_async_basic/l0/src/stm32l475xx/mod.rs b/minimal_async_basic/l0/src/stm32l475xx/mod.rs new file mode 100644 index 0000000..806064c --- /dev/null +++ b/minimal_async_basic/l0/src/stm32l475xx/mod.rs @@ -0,0 +1,17 @@ +#![allow(non_upper_case_globals)] +#![allow(non_camel_case_types)] +#![allow(non_snake_case)] + +mod arm_cm4; +mod entry_point; +mod interrupt; +// Generated controller bindings from C to Rust +mod controller; +mod registers; + +// Use only within L0 +mod private; +pub use private::*; + +// Allow dependents access to these APIs +pub mod public; diff --git a/minimal_async_basic/l0/src/stm32l475xx/private.rs b/minimal_async_basic/l0/src/stm32l475xx/private.rs new file mode 100644 index 0000000..b0df693 --- /dev/null +++ b/minimal_async_basic/l0/src/stm32l475xx/private.rs @@ -0,0 +1,49 @@ +use crate::{ + global::SYSTEM_CLOCK, read_register, write_assign_register, write_register, FLASH_BASE, + RCC_PORT, SCB_PORT, SYSTICK_PORT, +}; +use core::sync::atomic::Ordering; + +pub fn controller_init() { + // Update the System clock + let rcc_port = RCC_PORT::port(); + let cr_data = read_register!(rcc_port.CR); + let msi_range = (cr_data >> 4) & 0xF; + let system_clock: u32 = match msi_range { + 0 => todo!(), + 1 => todo!(), + 2 => todo!(), + 3 => todo!(), + 4 => 1_000_000, + 5 => 2_000_000, + 6 => 4_000_000, + 7 => todo!(), + 8 => todo!(), + 9 => todo!(), + 10 => todo!(), + 11 => todo!(), + _ => unreachable!(), + }; + SYSTEM_CLOCK.store(system_clock, Ordering::SeqCst); + + // Set SCB VTOR + let scb_port = SCB_PORT::port(); + write_register!(scb_port.VTOR, FLASH_BASE); + + // Configure SysTick + configure_systick_for_1ms(system_clock); +} + +// 1ms <- More realistic +// 1us <- Extremely granular +fn configure_systick_for_1ms(systemclock: u32) { + let systick_port = SYSTICK_PORT::port(); + // 1second -> systemclock cycles + // 1ms -> systemclock / 1000 - 1 cycles; + write_register!(systick_port.LOAD, (systemclock / 1000) - 1); + + const CTRL_ENABLE: u32 = 0; + const CTRL_TICKINT: u32 = 1; + const CTRL_CLKSOURCE: u32 = 2; + write_assign_register!(systick_port.CTRL, |, (1 << CTRL_CLKSOURCE) | (1 << CTRL_TICKINT) | (1 << CTRL_ENABLE)); +} diff --git a/minimal_async_basic/l0/src/stm32l475xx/public.rs b/minimal_async_basic/l0/src/stm32l475xx/public.rs new file mode 100644 index 0000000..de978a5 --- /dev/null +++ b/minimal_async_basic/l0/src/stm32l475xx/public.rs @@ -0,0 +1 @@ +pub use super::{arm_cm4::*, controller::*, interrupt::*, registers::*}; diff --git a/minimal_async_basic/l0/src/stm32l475xx/registers.rs b/minimal_async_basic/l0/src/stm32l475xx/registers.rs new file mode 100644 index 0000000..56d12d0 --- /dev/null +++ b/minimal_async_basic/l0/src/stm32l475xx/registers.rs @@ -0,0 +1,16 @@ +use crate::{ + EXTI_TypeDef, NVIC_Type, Port, RCC_TypeDef, SCB_Type, SYSCFG_TypeDef, SysTick_BASE, + SysTick_Type, USART_TypeDef, EXTI_BASE, NVIC_BASE, RCC_BASE, SCB_BASE, SYSCFG_BASE, + USART1_BASE, +}; + +// ARM specific +pub type SCB_PORT = Port; +pub type NVIC_PORT = Port; +pub type SYSTICK_PORT = Port; + +// STM32 specific +pub type RCC_PORT = Port; +pub type SYSCFG_PORT = Port; +pub type EXTI_PORT = Port; +pub type USART1_PORT = Port; diff --git a/minimal_async_basic/l0/src/utility/mod.rs b/minimal_async_basic/l0/src/utility/mod.rs new file mode 100644 index 0000000..691ea9a --- /dev/null +++ b/minimal_async_basic/l0/src/utility/mod.rs @@ -0,0 +1,41 @@ +use core::marker::PhantomData; + +#[macro_export] +macro_rules! get_port { + ($register_map_struct:ident, $address:ident) => { + unsafe { &mut *($address as *mut $register_map_struct) } + }; +} + +#[macro_export] +macro_rules! read_register { + ($register:expr) => { + unsafe { core::ptr::read_volatile(&$register) } + }; +} + +// TODO, Overload this macro to support $data:literal +#[macro_export] +macro_rules! write_register { + ($register:expr, $data:expr) => { + unsafe { core::ptr::write_volatile(&mut $register, $data) } + }; +} + +#[macro_export] +macro_rules! write_assign_register { + ($register:expr, $operation:tt, $data:expr) => { + let read_data = read_register!($register); + write_register!($register, read_data $operation $data); + }; +} + +pub struct Port { + pub marker: PhantomData, +} + +impl Port { + pub fn port() -> &'static mut T { + unsafe { &mut *(B as *mut T) } + } +} diff --git a/minimal_async_basic/l0/svd/STM32L4x5.svd b/minimal_async_basic/l0/svd/STM32L4x5.svd new file mode 100644 index 0000000..c845445 --- /dev/null +++ b/minimal_async_basic/l0/svd/STM32L4x5.svd @@ -0,0 +1,52941 @@ + + + STM32L4x5 + 1.4 + STM32L4x5 + + + CM4 + r1p0 + little + false + false + 3 + false + + + + 8 + + 32 + + 0x20 + 0x0 + 0xFFFFFFFF + + + DAC1 + Digital-to-analog converter + DAC + 0x40007400 + + 0x0 + 0x400 + registers + + + + CR + CR + control register + 0x0 + 0x20 + read-write + 0x00000000 + + + EN1 + DAC channel1 enable + 0 + 1 + + + TEN1 + DAC channel1 trigger + enable + 2 + 1 + + + TSEL1 + DAC channel1 trigger + selection + 3 + 3 + + + WAVE1 + DAC channel1 noise/triangle wave + generation enable + 6 + 2 + + + MAMP1 + DAC channel1 mask/amplitude + selector + 8 + 4 + + + DMAEN1 + DAC channel1 DMA enable + 12 + 1 + + + DMAUDRIE1 + DAC channel1 DMA Underrun Interrupt + enable + 13 + 1 + + + CEN1 + DAC Channel 1 calibration + enable + 14 + 1 + + + EN2 + DAC channel2 enable + 16 + 1 + + + TEN2 + DAC channel2 trigger + enable + 18 + 1 + + + TSEL2 + DAC channel2 trigger + selection + 19 + 3 + + + WAVE2 + DAC channel2 noise/triangle wave + generation enable + 22 + 2 + + + MAMP2 + DAC channel2 mask/amplitude + selector + 24 + 4 + + + DMAEN2 + DAC channel2 DMA enable + 28 + 1 + + + DMAUDRIE2 + DAC channel2 DMA underrun interrupt + enable + 29 + 1 + + + CEN2 + DAC Channel 2 calibration + enable + 30 + 1 + + + + + SWTRIGR + SWTRIGR + software trigger register + 0x4 + 0x20 + write-only + 0x00000000 + + + SWTRIG1 + DAC channel1 software + trigger + 0 + 1 + + + SWTRIG2 + DAC channel2 software + trigger + 1 + 1 + + + + + DHR12R1 + DHR12R1 + channel1 12-bit right-aligned data holding + register + 0x8 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 12-bit right-aligned + data + 0 + 12 + + + + + DHR12L1 + DHR12L1 + channel1 12-bit left-aligned data holding + register + 0xC + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 12-bit left-aligned + data + 4 + 12 + + + + + DHR8R1 + DHR8R1 + channel1 8-bit right-aligned data holding + register + 0x10 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 8-bit right-aligned + data + 0 + 8 + + + + + DHR12R2 + DHR12R2 + channel2 12-bit right aligned data holding + register + 0x14 + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DAC channel2 12-bit right-aligned + data + 0 + 12 + + + + + DHR12L2 + DHR12L2 + channel2 12-bit left aligned data holding + register + 0x18 + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DAC channel2 12-bit left-aligned + data + 4 + 12 + + + + + DHR8R2 + DHR8R2 + channel2 8-bit right-aligned data holding + register + 0x1C + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DAC channel2 8-bit right-aligned + data + 0 + 8 + + + + + DHR12RD + DHR12RD + Dual DAC 12-bit right-aligned data holding + register + 0x20 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 12-bit right-aligned + data + 0 + 12 + + + DACC2DHR + DAC channel2 12-bit right-aligned + data + 16 + 12 + + + + + DHR12LD + DHR12LD + DUAL DAC 12-bit left aligned data holding + register + 0x24 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 12-bit left-aligned + data + 4 + 12 + + + DACC2DHR + DAC channel2 12-bit left-aligned + data + 20 + 12 + + + + + DHR8RD + DHR8RD + DUAL DAC 8-bit right aligned data holding + register + 0x28 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 8-bit right-aligned + data + 0 + 8 + + + DACC2DHR + DAC channel2 8-bit right-aligned + data + 8 + 8 + + + + + DOR1 + DOR1 + channel1 data output register + 0x2C + 0x20 + read-only + 0x00000000 + + + DACC1DOR + DAC channel1 data output + 0 + 12 + + + + + DOR2 + DOR2 + channel2 data output register + 0x30 + 0x20 + read-only + 0x00000000 + + + DACC2DOR + DAC channel2 data output + 0 + 12 + + + + + SR + SR + status register + 0x34 + 0x20 + 0x00000000 + + + DMAUDR1 + DAC channel1 DMA underrun + flag + 13 + 1 + read-write + + + CAL_FLAG1 + DAC Channel 1 calibration offset + status + 14 + 1 + read-only + + + BWST1 + DAC Channel 1 busy writing sample time + flag + 15 + 1 + read-only + + + DMAUDR2 + DAC channel2 DMA underrun + flag + 29 + 1 + read-write + + + CAL_FLAG2 + DAC Channel 2 calibration offset + status + 30 + 1 + read-only + + + BWST2 + DAC Channel 2 busy writing sample time + flag + 31 + 1 + read-only + + + + + CCR + CCR + calibration control register + 0x38 + 0x20 + read-write + 0x00000000 + + + OTRIM1 + DAC Channel 1 offset trimming + value + 0 + 5 + + + OTRIM2 + DAC Channel 2 offset trimming + value + 16 + 5 + + + + + MCR + MCR + mode control register + 0x3C + 0x20 + read-write + 0x00000000 + + + MODE1 + DAC Channel 1 mode + 0 + 3 + + + MODE2 + DAC Channel 2 mode + 16 + 3 + + + + + SHSR1 + SHSR1 + Sample and Hold sample time register + 1 + 0x40 + 0x20 + read-write + 0x00000000 + + + TSAMPLE1 + DAC Channel 1 sample Time + 0 + 10 + + + + + SHSR2 + SHSR2 + Sample and Hold sample time register + 2 + 0x44 + 0x20 + read-write + 0x00000000 + + + TSAMPLE2 + DAC Channel 2 sample Time + 0 + 10 + + + + + SHHR + SHHR + Sample and Hold hold time + register + 0x48 + 0x20 + read-write + 0x00010001 + + + THOLD1 + DAC Channel 1 hold Time + 0 + 10 + + + THOLD2 + DAC Channel 2 hold time + 16 + 10 + + + + + SHRR + SHRR + Sample and Hold refresh time + register + 0x4C + 0x20 + read-write + 0x00000001 + + + TREFRESH1 + DAC Channel 1 refresh Time + 0 + 8 + + + TREFRESH2 + DAC Channel 2 refresh Time + 16 + 8 + + + + + + + DMA1 + Direct memory access controller + DMA + 0x40020000 + + 0x0 + 0x400 + registers + + + DMA1_Channel1 + DMA1 Channel1 global interrupt + 11 + + + DMA1_Channel1 + DMA1 Channel1 global interrupt + 11 + + + DMA1_Channel1 + DMA1 Channel1 global interrupt + 11 + + + DMA1_Channel2 + DMA1 Channel2 global interrupt + 12 + + + DMA1_Channel2 + DMA1 Channel2 global interrupt + 12 + + + DMA1_Channel2 + DMA1 Channel2 global interrupt + 12 + + + DMA1_Channel3 + DMA1 Channel3 interrupt + 13 + + + DMA1_Channel3 + DMA1 Channel3 interrupt + 13 + + + DMA1_Channel3 + DMA1 Channel3 interrupt + 13 + + + DMA1_Channel4 + DMA1 Channel4 interrupt + 14 + + + DMA1_Channel4 + DMA1 Channel4 interrupt + 14 + + + DMA1_Channel4 + DMA1 Channel4 interrupt + 14 + + + DMA1_Channel5 + DMA1 Channel5 interrupt + 15 + + + DMA1_Channel5 + DMA1 Channel5 interrupt + 15 + + + DMA1_Channel5 + DMA1 Channel5 interrupt + 15 + + + DMA1_Channel6 + DMA1 Channel6 interrupt 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(x = 1 + ..7) + 18 + 1 + + + TCIF5 + Channel x transfer complete flag (x = 1 + ..7) + 17 + 1 + + + GIF5 + Channel x global interrupt flag (x = 1 + ..7) + 16 + 1 + + + TEIF4 + Channel x transfer error flag (x = 1 + ..7) + 15 + 1 + + + HTIF4 + Channel x half transfer flag (x = 1 + ..7) + 14 + 1 + + + TCIF4 + Channel x transfer complete flag (x = 1 + ..7) + 13 + 1 + + + GIF4 + Channel x global interrupt flag (x = 1 + ..7) + 12 + 1 + + + TEIF3 + Channel x transfer error flag (x = 1 + ..7) + 11 + 1 + + + HTIF3 + Channel x half transfer flag (x = 1 + ..7) + 10 + 1 + + + TCIF3 + Channel x transfer complete flag (x = 1 + ..7) + 9 + 1 + + + GIF3 + Channel x global interrupt flag (x = 1 + ..7) + 8 + 1 + + + TEIF2 + Channel x transfer error flag (x = 1 + ..7) + 7 + 1 + + + HTIF2 + Channel x half transfer flag (x = 1 + ..7) + 6 + 1 + + + TCIF2 + Channel x transfer complete flag (x = 1 + ..7) + 5 + 1 + + + GIF2 + Channel x global interrupt flag (x = 1 + ..7) + 4 + 1 + + + TEIF1 + Channel x transfer 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(y= + 0..15) + 8 + 1 + + + BS7 + Port x set bit y (y= + 0..15) + 7 + 1 + + + BS6 + Port x set bit y (y= + 0..15) + 6 + 1 + + + BS5 + Port x set bit y (y= + 0..15) + 5 + 1 + + + BS4 + Port x set bit y (y= + 0..15) + 4 + 1 + + + BS3 + Port x set bit y (y= + 0..15) + 3 + 1 + + + BS2 + Port x set bit y (y= + 0..15) + 2 + 1 + + + BS1 + Port x set bit y (y= + 0..15) + 1 + 1 + + + BS0 + Port x set bit y (y= + 0..15) + 0 + 1 + + + + + LCKR + LCKR + GPIO port configuration lock + register + 0x1C + 0x20 + read-write + 0x00000000 + + + LCKK + Port x lock bit y (y= + 0..15) + 16 + 1 + + + LCK15 + Port x lock bit y (y= + 0..15) + 15 + 1 + + + LCK14 + Port x lock bit y (y= + 0..15) + 14 + 1 + + + LCK13 + Port x lock bit y (y= + 0..15) + 13 + 1 + + + LCK12 + Port x lock bit y (y= + 0..15) + 12 + 1 + + + LCK11 + Port x lock bit y (y= + 0..15) + 11 + 1 + + + LCK10 + Port x lock bit y (y= + 0..15) + 10 + 1 + + + LCK9 + Port x lock bit y (y= + 0..15) + 9 + 1 + + + LCK8 + Port x lock bit y (y= + 0..15) + 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Port x configuration bits (y = + 0..15) + 2 + 2 + + + OSPEEDR0 + Port x configuration bits (y = + 0..15) + 0 + 2 + + + + + PUPDR + PUPDR + GPIO port pull-up/pull-down + register + 0xC + 0x20 + read-write + 0x00000000 + + + PUPDR15 + Port x configuration bits (y = + 0..15) + 30 + 2 + + + PUPDR14 + Port x configuration bits (y = + 0..15) + 28 + 2 + + + PUPDR13 + Port x configuration bits (y = + 0..15) + 26 + 2 + + + PUPDR12 + Port x configuration bits (y = + 0..15) + 24 + 2 + + + PUPDR11 + Port x configuration bits (y = + 0..15) + 22 + 2 + + + PUPDR10 + Port x configuration bits (y = + 0..15) + 20 + 2 + + + PUPDR9 + Port x configuration bits (y = + 0..15) + 18 + 2 + + + PUPDR8 + Port x configuration bits (y = + 0..15) + 16 + 2 + + + PUPDR7 + Port x configuration bits (y = + 0..15) + 14 + 2 + + + PUPDR6 + Port x configuration bits (y = + 0..15) + 12 + 2 + + + PUPDR5 + Port x configuration bits (y = + 0..15) + 10 + 2 + + + PUPDR4 + Port x configuration bits (y = + 0..15) + 8 + 2 + + + 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0..15) + 3 + 1 + + + IDR2 + Port input data (y = + 0..15) + 2 + 1 + + + IDR1 + Port input data (y = + 0..15) + 1 + 1 + + + IDR0 + Port input data (y = + 0..15) + 0 + 1 + + + + + ODR + ODR + GPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + + + ODR15 + Port output data (y = + 0..15) + 15 + 1 + + + ODR14 + Port output data (y = + 0..15) + 14 + 1 + + + ODR13 + Port output data (y = + 0..15) + 13 + 1 + + + ODR12 + Port output data (y = + 0..15) + 12 + 1 + + + ODR11 + Port output data (y = + 0..15) + 11 + 1 + + + ODR10 + Port output data (y = + 0..15) + 10 + 1 + + + ODR9 + Port output data (y = + 0..15) + 9 + 1 + + + ODR8 + Port output data (y = + 0..15) + 8 + 1 + + + ODR7 + Port output data (y = + 0..15) + 7 + 1 + + + ODR6 + Port output data (y = + 0..15) + 6 + 1 + + + ODR5 + Port output data (y = + 0..15) + 5 + 1 + + + ODR4 + Port output data (y = + 0..15) + 4 + 1 + + + ODR3 + Port output data (y = + 0..15) + 3 + 1 + + + ODR2 + Port output data (y = + 0..15) + 2 + 1 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+ 0..15) + 17 + 1 + + + BR0 + Port x set bit y (y= + 0..15) + 16 + 1 + + + BS15 + Port x set bit y (y= + 0..15) + 15 + 1 + + + BS14 + Port x set bit y (y= + 0..15) + 14 + 1 + + + BS13 + Port x set bit y (y= + 0..15) + 13 + 1 + + + BS12 + Port x set bit y (y= + 0..15) + 12 + 1 + + + BS11 + Port x set bit y (y= + 0..15) + 11 + 1 + + + BS10 + Port x set bit y (y= + 0..15) + 10 + 1 + + + BS9 + Port x set bit y (y= + 0..15) + 9 + 1 + + + BS8 + Port x set bit y (y= + 0..15) + 8 + 1 + + + BS7 + Port x set bit y (y= + 0..15) + 7 + 1 + + + BS6 + Port x set bit y (y= + 0..15) + 6 + 1 + + + BS5 + Port x set bit y (y= + 0..15) + 5 + 1 + + + BS4 + Port x set bit y (y= + 0..15) + 4 + 1 + + + BS3 + Port x set bit y (y= + 0..15) + 3 + 1 + + + BS2 + Port x set bit y (y= + 0..15) + 2 + 1 + + + BS1 + Port x set bit y (y= + 0..15) + 1 + 1 + + + BS0 + Port x set bit y (y= + 0..15) + 0 + 1 + + + + + LCKR + LCKR + GPIO port configuration lock + register + 0x1C + 0x20 + read-write + 0x00000000 + + + LCKK + Port x lock bit y (y= + 0..15) + 16 + 1 + + + LCK15 + Port x lock bit y (y= + 0..15) + 15 + 1 + + + LCK14 + Port x lock bit y (y= + 0..15) + 14 + 1 + + + LCK13 + Port x lock bit y (y= + 0..15) + 13 + 1 + + + LCK12 + Port x lock bit y (y= + 0..15) + 12 + 1 + + + LCK11 + Port x lock bit y (y= + 0..15) + 11 + 1 + + + LCK10 + Port x lock bit y (y= + 0..15) + 10 + 1 + + + LCK9 + Port x lock bit y (y= + 0..15) + 9 + 1 + + + LCK8 + Port x lock bit y (y= + 0..15) + 8 + 1 + + + LCK7 + Port x lock bit y (y= + 0..15) + 7 + 1 + + + LCK6 + Port x lock bit y (y= + 0..15) + 6 + 1 + + + LCK5 + Port x lock bit y (y= + 0..15) + 5 + 1 + + + LCK4 + Port x lock bit y (y= + 0..15) + 4 + 1 + + + LCK3 + Port x lock bit y (y= + 0..15) + 3 + 1 + + + LCK2 + Port x lock bit y (y= + 0..15) + 2 + 1 + + + LCK1 + Port x lock bit y (y= + 0..15) + 1 + 1 + + + LCK0 + Port x lock bit y (y= + 0..15) + 0 + 1 + + + + + AFRL + AFRL + GPIO alternate function low + register + 0x20 + 0x20 + read-write + 0x00000000 + + + AFRL7 + Alternate function selection for port x + bit y (y = 0..7) + 28 + 4 + + + AFRL6 + Alternate function selection for port x + bit y (y = 0..7) + 24 + 4 + + + AFRL5 + Alternate function selection for port x + bit y (y = 0..7) + 20 + 4 + + + AFRL4 + Alternate function selection for port x + bit y (y = 0..7) + 16 + 4 + + + AFRL3 + Alternate function selection for port x + bit y (y = 0..7) + 12 + 4 + + + AFRL2 + Alternate function selection for port x + bit y (y = 0..7) + 8 + 4 + + + AFRL1 + Alternate function selection for port x + bit y (y = 0..7) + 4 + 4 + + + AFRL0 + Alternate function selection for port x + bit y (y = 0..7) + 0 + 4 + + + + + AFRH + AFRH + GPIO alternate function high + register + 0x24 + 0x20 + read-write + 0x00000000 + + + AFRH15 + Alternate function selection for port x + bit y (y = 8..15) + 28 + 4 + + + AFRH14 + Alternate function selection for port x + bit y (y = 8..15) + 24 + 4 + + + AFRH13 + Alternate function selection for port x + bit y (y = 8..15) + 20 + 4 + + + AFRH12 + Alternate function selection for port x + bit y (y = 8..15) + 16 + 4 + + + AFRH11 + Alternate function selection for port x + bit y (y = 8..15) + 12 + 4 + + + AFRH10 + Alternate function selection for port x + bit y (y = 8..15) + 8 + 4 + + + AFRH9 + Alternate function selection for port x + bit y (y = 8..15) + 4 + 4 + + + AFRH8 + Alternate function selection for port x + bit y (y = 8..15) + 0 + 4 + + + + + + + GPIOD + 0x48000C00 + + + GPIOE + 0x48001000 + + + GPIOH + 0x48001C00 + + + GPIOF + 0x48001400 + + + GPIOG + 0x48001800 + + + SAI1 + Serial audio interface + SAI + 0x40015400 + + 0x0 + 0x400 + registers + + + SAI1 + SAI1 global interrupt + 74 + + + SAI1 + SAI1 global interrupt + 74 + + + SAI1 + SAI1 global interrupt + 74 + + + + BCR1 + BCR1 + BConfiguration register 1 + 0x24 + 0x20 + read-write + 0x00000040 + + + MCJDIV + Master clock divider + 20 + 4 + + + NODIV + No divider + 19 + 1 + + + DMAEN + DMA enable + 17 + 1 + + + SAIBEN + Audio block B enable + 16 + 1 + + + OutDri + Output drive + 13 + 1 + + + MONO + Mono mode + 12 + 1 + + + SYNCEN + Synchronization enable + 10 + 2 + + + CKSTR + Clock strobing edge + 9 + 1 + + + LSBFIRST + Least significant bit + first + 8 + 1 + + + DS + Data size + 5 + 3 + + + PRTCFG + Protocol configuration + 2 + 2 + + + MODE + Audio block mode + 0 + 2 + + + + + BCR2 + BCR2 + BConfiguration register 2 + 0x28 + 0x20 + read-write + 0x00000000 + + + COMP + Companding mode + 14 + 2 + + + CPL + Complement bit + 13 + 1 + + + MUTECN + Mute counter + 7 + 6 + + + MUTEVAL + Mute value + 6 + 1 + + + MUTE + Mute + 5 + 1 + + + TRIS + Tristate management on data + line + 4 + 1 + + + FFLUS + FIFO flush + 3 + 1 + + + FTH + FIFO threshold + 0 + 3 + + + + + BFRCR + BFRCR + BFRCR + 0x2C + 0x20 + read-write + 0x00000007 + + + FSOFF + Frame synchronization + offset + 18 + 1 + + + FSPOL + Frame synchronization + polarity + 17 + 1 + + + FSDEF + Frame synchronization + definition + 16 + 1 + + + FSALL + Frame synchronization active level + length + 8 + 7 + + + FRL + Frame length + 0 + 8 + + + + + BSLOTR + BSLOTR + BSlot register + 0x30 + 0x20 + read-write + 0x00000000 + + + SLOTEN + Slot enable + 16 + 16 + + + NBSLOT + Number of slots in an audio + frame + 8 + 4 + + + SLOTSZ + Slot size + 6 + 2 + + + FBOFF + First bit offset + 0 + 5 + + + + + BIM + BIM + BInterrupt mask register2 + 0x34 + 0x20 + read-write + 0x00000000 + + + LFSDETIE + Late frame synchronization detection + interrupt enable + 6 + 1 + + + AFSDETIE + Anticipated frame synchronization + detection interrupt enable + 5 + 1 + + + CNRDYIE + Codec not ready interrupt + enable + 4 + 1 + + + FREQIE + FIFO request interrupt + enable + 3 + 1 + + + WCKCFG + Wrong clock configuration interrupt + enable + 2 + 1 + + + MUTEDET + Mute detection interrupt + enable + 1 + 1 + + + OVRUDRIE + Overrun/underrun interrupt + enable + 0 + 1 + + + + + BSR + BSR + BStatus register + 0x38 + 0x20 + read-only + 0x00000000 + + + FLVL + FIFO level threshold + 16 + 3 + + + LFSDET + Late frame synchronization + detection + 6 + 1 + + + AFSDET + Anticipated frame synchronization + detection + 5 + 1 + + + CNRDY + Codec not ready + 4 + 1 + + + FREQ + FIFO request + 3 + 1 + + + WCKCFG + Wrong clock configuration + flag + 2 + 1 + + + MUTEDET + Mute detection + 1 + 1 + + + OVRUDR + Overrun / underrun + 0 + 1 + + + + + BCLRFR + BCLRFR + BClear flag register + 0x3C + 0x20 + write-only + 0x00000000 + + + LFSDET + Clear late frame synchronization + detection flag + 6 + 1 + + + CAFSDET + Clear anticipated frame synchronization + detection flag + 5 + 1 + + + CNRDY + Clear codec not ready flag + 4 + 1 + + + WCKCFG + Clear wrong clock configuration + flag + 2 + 1 + + + MUTEDET + Mute detection flag + 1 + 1 + + + OVRUDR + Clear overrun / underrun + 0 + 1 + + + + + BDR + BDR + BData register + 0x40 + 0x20 + read-write + 0x00000000 + + + DATA + Data + 0 + 32 + + + + + ACR1 + ACR1 + AConfiguration register 1 + 0x4 + 0x20 + read-write + 0x00000040 + + + MCJDIV + Master clock divider + 20 + 4 + + + NODIV + No divider + 19 + 1 + + + DMAEN + DMA enable + 17 + 1 + + + SAIAEN + Audio block A enable + 16 + 1 + + + OutDri + Output drive + 13 + 1 + + + MONO + Mono mode + 12 + 1 + + + SYNCEN + Synchronization enable + 10 + 2 + + + CKSTR + Clock strobing edge + 9 + 1 + + + LSBFIRST + Least significant bit + first + 8 + 1 + + + DS + Data size + 5 + 3 + + + PRTCFG + Protocol configuration + 2 + 2 + + + MODE + Audio block mode + 0 + 2 + + + + + ACR2 + ACR2 + AConfiguration register 2 + 0x8 + 0x20 + read-write + 0x00000000 + + + COMP + Companding mode + 14 + 2 + + + CPL + Complement bit + 13 + 1 + + + MUTECN + Mute counter + 7 + 6 + + + MUTEVAL + Mute value + 6 + 1 + + + MUTE + Mute + 5 + 1 + + + TRIS + Tristate management on data + line + 4 + 1 + + + FFLUS + FIFO flush + 3 + 1 + + + FTH + FIFO threshold + 0 + 3 + + + + + AFRCR + AFRCR + AFRCR + 0xC + 0x20 + read-write + 0x00000007 + + + FSOFF + Frame synchronization + offset + 18 + 1 + + + FSPOL + Frame synchronization + polarity + 17 + 1 + + + FSDEF + Frame synchronization + definition + 16 + 1 + + + FSALL + Frame synchronization active level + length + 8 + 7 + + + FRL + Frame length + 0 + 8 + + + + + ASLOTR + ASLOTR + ASlot register + 0x10 + 0x20 + read-write + 0x00000000 + + + SLOTEN + Slot enable + 16 + 16 + + + NBSLOT + Number of slots in an audio + frame + 8 + 4 + + + SLOTSZ + Slot size + 6 + 2 + + + FBOFF + First bit offset + 0 + 5 + + + + + AIM + AIM + AInterrupt mask register2 + 0x14 + 0x20 + read-write + 0x00000000 + + + LFSDET + Late frame synchronization detection + interrupt enable + 6 + 1 + + + AFSDETIE + Anticipated frame synchronization + detection interrupt enable + 5 + 1 + + + CNRDYIE + Codec not ready interrupt + enable + 4 + 1 + + + FREQIE + FIFO request interrupt + enable + 3 + 1 + + + WCKCFG + Wrong clock configuration interrupt + enable + 2 + 1 + + + MUTEDET + Mute detection interrupt + enable + 1 + 1 + + + OVRUDRIE + Overrun/underrun interrupt + enable + 0 + 1 + + + + + ASR + ASR + AStatus register + 0x18 + 0x20 + read-write + 0x00000000 + + + FLVL + FIFO level threshold + 16 + 3 + + + LFSDET + Late frame synchronization + detection + 6 + 1 + + + AFSDET + Anticipated frame synchronization + detection + 5 + 1 + + + CNRDY + Codec not ready + 4 + 1 + + + FREQ + FIFO request + 3 + 1 + + + WCKCFG + Wrong clock configuration flag. This bit + is read only + 2 + 1 + + + MUTEDET + Mute detection + 1 + 1 + + + OVRUDR + Overrun / underrun + 0 + 1 + + + + + ACLRFR + ACLRFR + AClear flag register + 0x1C + 0x20 + read-write + 0x00000000 + + + LFSDET + Clear late frame synchronization + detection flag + 6 + 1 + + + CAFSDET + Clear anticipated frame synchronization + detection flag + 5 + 1 + + + CNRDY + Clear codec not ready flag + 4 + 1 + + + WCKCFG + Clear wrong clock configuration + flag + 2 + 1 + + + MUTEDET + Mute detection flag + 1 + 1 + + + OVRUDR + Clear overrun / underrun + 0 + 1 + + + + + ADR + ADR + AData register + 0x20 + 0x20 + read-write + 0x00000000 + + + DATA + Data + 0 + 32 + + + + + + + SAI2 + 0x40015800 + + SAI2 + SAI2 global interrupt + 75 + + + SAI2 + SAI2 global interrupt + 75 + + + SAI2 + SAI2 global interrupt + 75 + + + + TIM2 + General-purpose-timers + TIM + 0x40000000 + + 0x0 + 0x400 + registers + + + TIM2 + TIM2 global interrupt + 28 + + + TIM2 + TIM2 global interrupt + 28 + + + TIM2 + TIM2 global interrupt + 28 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + CKD + Clock division + 8 + 2 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + CMS + Center-aligned mode + selection + 5 + 2 + + + DIR + Direction + 4 + 1 + + + OPM + One-pulse mode + 3 + 1 + + + URS + Update request source + 2 + 1 + + + UDIS + Update disable + 1 + 1 + + + CEN + Counter enable + 0 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + TI1S + TI1 selection + 7 + 1 + + + MMS + Master mode selection + 4 + 3 + + + CCDS + Capture/compare DMA + selection + 3 + 1 + + + + + SMCR + SMCR + slave mode control register + 0x8 + 0x20 + read-write + 0x0000 + + + ETP + External trigger polarity + 15 + 1 + + + ECE + External clock enable + 14 + 1 + + + ETPS + External trigger prescaler + 12 + 2 + + + ETF + External trigger filter + 8 + 4 + + + MSM + Master/Slave mode + 7 + 1 + + + TS + Trigger selection + 4 + 3 + + + SMS + Slave mode selection + 0 + 3 + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + TDE + Trigger DMA request enable + 14 + 1 + + + COMDE + COM DMA request enable + 13 + 1 + + + CC4DE + Capture/Compare 4 DMA request + enable + 12 + 1 + + + CC3DE + Capture/Compare 3 DMA request + enable + 11 + 1 + + + CC2DE + Capture/Compare 2 DMA request + enable + 10 + 1 + + + CC1DE + Capture/Compare 1 DMA request + enable + 9 + 1 + + + UDE + Update DMA request enable + 8 + 1 + + + TIE + Trigger interrupt enable + 6 + 1 + + + CC4IE + Capture/Compare 4 interrupt + enable + 4 + 1 + + + CC3IE + Capture/Compare 3 interrupt + enable + 3 + 1 + + + CC2IE + Capture/Compare 2 interrupt + enable + 2 + 1 + + + CC1IE + Capture/Compare 1 interrupt + enable + 1 + 1 + + + UIE + Update interrupt enable + 0 + 1 + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x0000 + + + CC4OF + Capture/Compare 4 overcapture + flag + 12 + 1 + + + CC3OF + Capture/Compare 3 overcapture + flag + 11 + 1 + + + CC2OF + Capture/compare 2 overcapture + flag + 10 + 1 + + + CC1OF + Capture/Compare 1 overcapture + flag + 9 + 1 + + + TIF + Trigger interrupt flag + 6 + 1 + + + CC4IF + Capture/Compare 4 interrupt + flag + 4 + 1 + + + CC3IF + Capture/Compare 3 interrupt + flag + 3 + 1 + + + CC2IF + Capture/Compare 2 interrupt + flag + 2 + 1 + + + CC1IF + Capture/compare 1 interrupt + flag + 1 + 1 + + + UIF + Update interrupt flag + 0 + 1 + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x0000 + + + TG + Trigger generation + 6 + 1 + + + CC4G + Capture/compare 4 + generation + 4 + 1 + + + CC3G + Capture/compare 3 + generation + 3 + 1 + + + CC2G + Capture/compare 2 + generation + 2 + 1 + + + CC1G + Capture/compare 1 + generation + 1 + 1 + + + UG + Update generation + 0 + 1 + + + + + CCMR1_Output + CCMR1_Output + capture/compare mode register 1 (output + mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + OC2CE + Output compare 2 clear + enable + 15 + 1 + + + OC2M + Output compare 2 mode + 12 + 3 + + + OC2PE + Output compare 2 preload + enable + 11 + 1 + + + OC2FE + Output compare 2 fast + enable + 10 + 1 + + + CC2S + Capture/Compare 2 + selection + 8 + 2 + + + OC1CE + Output compare 1 clear + enable + 7 + 1 + + + OC1M + Output compare 1 mode + 4 + 3 + + + OC1PE + Output compare 1 preload + enable + 3 + 1 + + + OC1FE + Output compare 1 fast + enable + 2 + 1 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + CCMR1_Input + CCMR1_Input + capture/compare mode register 1 (input + mode) + CCMR1_Output + 0x18 + 0x20 + read-write + 0x00000000 + + + IC2F + Input capture 2 filter + 12 + 4 + + + IC2PSC + Input capture 2 prescaler + 10 + 2 + + + CC2S + Capture/compare 2 + selection + 8 + 2 + + + IC1F + Input capture 1 filter + 4 + 4 + + + IC1PSC + Input capture 1 prescaler + 2 + 2 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + CCMR2_Output + CCMR2_Output + capture/compare mode register 2 (output + mode) + 0x1C + 0x20 + read-write + 0x00000000 + + + OC4CE + Output compare 4 clear + enable + 15 + 1 + + + OC4M + Output compare 4 mode + 12 + 3 + + + OC4PE + Output compare 4 preload + enable + 11 + 1 + + + OC4FE + Output compare 4 fast + enable + 10 + 1 + + + CC4S + Capture/Compare 4 + selection + 8 + 2 + + + OC3CE + Output compare 3 clear + enable + 7 + 1 + + + OC3M + Output compare 3 mode + 4 + 3 + + + OC3PE + Output compare 3 preload + enable + 3 + 1 + + + OC3FE + Output compare 3 fast + enable + 2 + 1 + + + CC3S + Capture/Compare 3 + selection + 0 + 2 + + + + + CCMR2_Input + CCMR2_Input + capture/compare mode register 2 (input + mode) + CCMR2_Output + 0x1C + 0x20 + read-write + 0x00000000 + + + IC4F + Input capture 4 filter + 12 + 4 + + + IC4PSC + Input capture 4 prescaler + 10 + 2 + + + CC4S + Capture/Compare 4 + selection + 8 + 2 + + + IC3F + Input capture 3 filter + 4 + 4 + + + IC3PSC + Input capture 3 prescaler + 2 + 2 + + + CC3S + Capture/Compare 3 + selection + 0 + 2 + + + + + CCER + CCER + capture/compare enable + register + 0x20 + 0x20 + read-write + 0x0000 + + + CC4NP + Capture/Compare 4 output + Polarity + 15 + 1 + + + CC4P + Capture/Compare 3 output + Polarity + 13 + 1 + + + CC4E + Capture/Compare 4 output + enable + 12 + 1 + + + CC3NP + Capture/Compare 3 output + Polarity + 11 + 1 + + + CC3P + Capture/Compare 3 output + Polarity + 9 + 1 + + + CC3E + Capture/Compare 3 output + enable + 8 + 1 + + + CC2NP + Capture/Compare 2 output + Polarity + 7 + 1 + + + CC2P + Capture/Compare 2 output + Polarity + 5 + 1 + + + CC2E + Capture/Compare 2 output + enable + 4 + 1 + + + CC1NP + Capture/Compare 1 output + Polarity + 3 + 1 + + + CC1P + Capture/Compare 1 output + Polarity + 1 + 1 + + + CC1E + Capture/Compare 1 output + enable + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + read-write + 0x00000000 + + + CNT_H + High counter value (TIM2 + only) + 16 + 16 + + + CNT_L + Low counter value + 0 + 16 + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x0000 + + + PSC + Prescaler value + 0 + 16 + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x00000000 + + + ARR_H + High Auto-reload value (TIM2 + only) + 16 + 16 + + + ARR_L + Low Auto-reload value + 0 + 16 + + + + + CCR1 + CCR1 + capture/compare register 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR1_H + High Capture/Compare 1 value (TIM2 + only) + 16 + 16 + + + CCR1_L + Low Capture/Compare 1 + value + 0 + 16 + + + + + CCR2 + CCR2 + capture/compare register 2 + 0x38 + 0x20 + read-write + 0x00000000 + + + CCR2_H + High Capture/Compare 2 value (TIM2 + only) + 16 + 16 + + + CCR2_L + Low Capture/Compare 2 + value + 0 + 16 + + + + + CCR3 + CCR3 + capture/compare register 3 + 0x3C + 0x20 + read-write + 0x00000000 + + + CCR3_H + High Capture/Compare value (TIM2 + only) + 16 + 16 + + + CCR3_L + Low Capture/Compare value + 0 + 16 + + + + + CCR4 + CCR4 + capture/compare register 4 + 0x40 + 0x20 + read-write + 0x00000000 + + + CCR4_H + High Capture/Compare value (TIM2 + only) + 16 + 16 + + + CCR4_L + Low Capture/Compare value + 0 + 16 + + + + + DCR + DCR + DMA control register + 0x48 + 0x20 + read-write + 0x0000 + + + DBL + DMA burst length + 8 + 5 + + + DBA + DMA base address + 0 + 5 + + + + + DMAR + DMAR + DMA address for full transfer + 0x4C + 0x20 + read-write + 0x0000 + + + DMAB + DMA register for burst + accesses + 0 + 16 + + + + + OR + OR + TIM2 option register + 0x50 + 0x20 + read-write + 0x0000 + + + ETR_RMP + Timer2 ETR remap + 0 + 3 + + + TI4_RMP + Internal trigger + 3 + 2 + + + + + + + TIM5 + 0x40000C00 + + TIM5 + TIM5 global Interrupt + 50 + + + TIM5 + TIM5 global Interrupt + 50 + + + TIM5 + TIM5 global Interrupt + 50 + + + + TIM4 + 0x40000800 + + TIM4 + TIM4 global interrupt + 30 + + + TIM4 + TIM4 global interrupt + 30 + + + TIM4 + TIM4 global interrupt + 30 + + + + TIM3 + 0x40000400 + + TIM3 + TIM3 global interrupt + 29 + + + TIM3 + TIM3 global interrupt + 29 + + + TIM3 + TIM3 global interrupt + 29 + + + + TIM15 + General purpose timers + TIM + 0x40014000 + + 0x0 + 0x400 + registers + + + TIM15 + Timer 15 global interrupt + 24 + + + TIM15 + Timer 15 global interrupt + 24 + + + TIM15 + Timer 15 global interrupt + 24 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + CEN + Counter enable + 0 + 1 + + + UDIS + Update disable + 1 + 1 + + + URS + Update request source + 2 + 1 + + + OPM + One-pulse mode + 3 + 1 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + CKD + Clock division + 8 + 2 + + + UIFREMAP + UIF status bit remapping + 11 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + OIS1N + Output Idle state 1 + 9 + 1 + + + OIS1 + Output Idle state 1 + 8 + 1 + + + CCDS + Capture/compare DMA + selection + 3 + 1 + + + CCUS + Capture/compare control update + selection + 2 + 1 + + + CCPC + Capture/compare preloaded + control + 0 + 1 + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + TDE + Trigger DMA request enable + 14 + 1 + + + COMDE + COM DMA request enable + 13 + 1 + + + CC1DE + Capture/Compare 1 DMA request + enable + 9 + 1 + + + UDE + Update DMA request enable + 8 + 1 + + + BIE + Break interrupt enable + 7 + 1 + + + TIE + Trigger interrupt enable + 6 + 1 + + + COMIE + COM interrupt enable + 5 + 1 + + + CC1IE + Capture/Compare 1 interrupt + enable + 1 + 1 + + + UIE + Update interrupt enable + 0 + 1 + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x0000 + + + CC1OF + Capture/Compare 1 overcapture + flag + 9 + 1 + + + BIF + Break interrupt flag + 7 + 1 + + + TIF + Trigger interrupt flag + 6 + 1 + + + COMIF + COM interrupt flag + 5 + 1 + + + CC1IF + Capture/compare 1 interrupt + flag + 1 + 1 + + + UIF + Update interrupt flag + 0 + 1 + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x0000 + + + BG + Break generation + 7 + 1 + + + TG + Trigger generation + 6 + 1 + + + COMG + Capture/Compare control update + generation + 5 + 1 + + + CC1G + Capture/compare 1 + generation + 1 + 1 + + + UG + Update generation + 0 + 1 + + + + + CCMR1_Output + CCMR1_Output + capture/compare mode register (output + mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + OC1M_2 + Output Compare 1 mode + 16 + 1 + + + OC1M + Output Compare 1 mode + 4 + 3 + + + OC1PE + Output Compare 1 preload + enable + 3 + 1 + + + OC1FE + Output Compare 1 fast + enable + 2 + 1 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + CCMR1_Input + CCMR1_Input + capture/compare mode register 1 (input + mode) + CCMR1_Output + 0x18 + 0x20 + read-write + 0x00000000 + + + IC1F + Input capture 1 filter + 4 + 4 + + + IC1PSC + Input capture 1 prescaler + 2 + 2 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + CCER + CCER + capture/compare enable + register + 0x20 + 0x20 + read-write + 0x0000 + + + CC1NP + Capture/Compare 1 output + Polarity + 3 + 1 + + + CC1NE + Capture/Compare 1 complementary output + enable + 2 + 1 + + + CC1P + Capture/Compare 1 output + Polarity + 1 + 1 + + + CC1E + Capture/Compare 1 output + enable + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + 0x00000000 + + + CNT + counter value + 0 + 16 + read-write + + + UIFCPY + UIF Copy + 31 + 1 + read-only + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x0000 + + + PSC + Prescaler value + 0 + 16 + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x00000000 + + + ARR + Auto-reload value + 0 + 16 + + + + + RCR + RCR + repetition counter register + 0x30 + 0x20 + read-write + 0x0000 + + + REP + Repetition counter value + 0 + 8 + + + + + CCR1 + CCR1 + capture/compare register 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR1 + Capture/Compare 1 value + 0 + 16 + + + + + BDTR + BDTR + break and dead-time register + 0x44 + 0x20 + read-write + 0x0000 + + + DTG + Dead-time generator setup + 0 + 8 + + + LOCK + Lock configuration + 8 + 2 + + + OSSI + Off-state selection for Idle + mode + 10 + 1 + + + OSSR + Off-state selection for Run + mode + 11 + 1 + + + BKE + Break enable + 12 + 1 + + + BKP + Break polarity + 13 + 1 + + + AOE + Automatic output enable + 14 + 1 + + + MOE + Main output enable + 15 + 1 + + + BKF + Break filter + 16 + 4 + + + + + DCR + DCR + DMA control register + 0x48 + 0x20 + read-write + 0x0000 + + + DBL + DMA burst length + 8 + 5 + + + DBA + DMA base address + 0 + 5 + + + + + DMAR + DMAR + DMA address for full transfer + 0x4C + 0x20 + read-write + 0x0000 + + + DMAB + DMA register for burst + accesses + 0 + 16 + + + + + + + TIM16 + General purpose timers + TIM + 0x40014400 + + 0x0 + 0x400 + registers + + + TIM16 + Timer 16 global interrupt + 25 + + + TIM16 + Timer 16 global interrupt + 25 + + + TIM16 + Timer 16 global interrupt + 25 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + CEN + Counter enable + 0 + 1 + + + UDIS + Update disable + 1 + 1 + + + URS + Update request source + 2 + 1 + + + OPM + One-pulse mode + 3 + 1 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + CKD + Clock division + 8 + 2 + + + UIFREMAP + UIF status bit remapping + 11 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + OIS1N + Output Idle state 1 + 9 + 1 + + + OIS1 + Output Idle state 1 + 8 + 1 + + + CCDS + Capture/compare DMA + selection + 3 + 1 + + + CCUS + Capture/compare control update + selection + 2 + 1 + + + CCPC + Capture/compare preloaded + control + 0 + 1 + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + TDE + Trigger DMA request enable + 14 + 1 + + + COMDE + COM DMA request enable + 13 + 1 + + + CC1DE + Capture/Compare 1 DMA request + enable + 9 + 1 + + + UDE + Update DMA request enable + 8 + 1 + + + BIE + Break interrupt enable + 7 + 1 + + + TIE + Trigger interrupt enable + 6 + 1 + + + COMIE + COM interrupt enable + 5 + 1 + + + CC1IE + Capture/Compare 1 interrupt + enable + 1 + 1 + + + UIE + Update interrupt enable + 0 + 1 + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x0000 + + + CC1OF + Capture/Compare 1 overcapture + flag + 9 + 1 + + + BIF + Break interrupt flag + 7 + 1 + + + TIF + Trigger interrupt flag + 6 + 1 + + + COMIF + COM interrupt flag + 5 + 1 + + + CC1IF + Capture/compare 1 interrupt + flag + 1 + 1 + + + UIF + Update interrupt flag + 0 + 1 + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x0000 + + + BG + Break generation + 7 + 1 + + + TG + Trigger generation + 6 + 1 + + + COMG + Capture/Compare control update + generation + 5 + 1 + + + CC1G + Capture/compare 1 + generation + 1 + 1 + + + UG + Update generation + 0 + 1 + + + + + CCMR1_Output + CCMR1_Output + capture/compare mode register (output + mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + OC1M_2 + Output Compare 1 mode + 16 + 1 + + + OC1M + Output Compare 1 mode + 4 + 3 + + + OC1PE + Output Compare 1 preload + enable + 3 + 1 + + + OC1FE + Output Compare 1 fast + enable + 2 + 1 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + CCMR1_Input + CCMR1_Input + capture/compare mode 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0x30 + 0x20 + read-write + 0x0000 + + + REP + Repetition counter value + 0 + 8 + + + + + CCR1 + CCR1 + capture/compare register 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR1 + Capture/Compare 1 value + 0 + 16 + + + + + CCR2 + CCR2 + capture/compare register 2 + 0x38 + 0x20 + read-write + 0x00000000 + + + CCR2 + Capture/Compare 2 value + 0 + 16 + + + + + CCR3 + CCR3 + capture/compare register 3 + 0x3C + 0x20 + read-write + 0x00000000 + + + CCR3 + Capture/Compare value + 0 + 16 + + + + + CCR4 + CCR4 + capture/compare register 4 + 0x40 + 0x20 + read-write + 0x00000000 + + + CCR4 + Capture/Compare value + 0 + 16 + + + + + BDTR + BDTR + break and dead-time register + 0x44 + 0x20 + read-write + 0x0000 + + + MOE + Main output enable + 15 + 1 + + + AOE + Automatic output enable + 14 + 1 + + + BKP + Break polarity + 13 + 1 + + + BKE + Break enable + 12 + 1 + + + OSSR + Off-state selection for Run + mode + 11 + 1 + + + OSSI + Off-state selection for Idle + mode + 10 + 1 + + + LOCK + Lock configuration + 8 + 2 + + + DTG + Dead-time generator setup + 0 + 8 + + + + + DCR + DCR + DMA control register + 0x48 + 0x20 + read-write + 0x0000 + + + DBL + DMA burst length + 8 + 5 + + + DBA + DMA base address + 0 + 5 + + + + + DMAR + DMAR + DMA address for full transfer + 0x4C + 0x20 + read-write + 0x0000 + + + DMAB + DMA register for burst + accesses + 0 + 16 + + + + + OR1 + OR1 + DMA address for full transfer + 0x50 + 0x20 + read-write + 0x0000 + + + ETR_ADC1_RMP + External trigger remap on ADC1 analog + watchdog + 0 + 2 + + + ETR_ADC3_RMP + External trigger remap on ADC3 analog + watchdog + 2 + 2 + + + TI1_RMP + Input Capture 1 remap + 4 + 1 + + + + + CCMR3_Output + CCMR3_Output + capture/compare mode register 2 (output + mode) + 0x54 + 0x20 + read-write + 0x00000000 + + + OC6M_bit3 + Output Compare 6 mode bit + 3 + 24 + 1 + + + OC5M_bit3 + Output Compare 5 mode bit + 3 + 16 + 3 + + + OC6CE + Output compare 6 clear + enable + 15 + 1 + + + OC6M + Output compare 6 mode + 12 + 3 + + + OC6PE + Output compare 6 preload + enable + 11 + 1 + + + OC6FE + Output compare 6 fast + enable + 10 + 1 + + + OC5CE + Output compare 5 clear + enable + 7 + 1 + + + OC5M + Output compare 5 mode + 4 + 3 + + + OC5PE + Output compare 5 preload + enable + 3 + 1 + + + OC5FE + Output compare 5 fast + enable + 2 + 1 + + + + + CCR5 + CCR5 + capture/compare register 4 + 0x58 + 0x20 + read-write + 0x00000000 + + + CCR5 + Capture/Compare value + 0 + 16 + + + GC5C1 + Group Channel 5 and Channel + 1 + 29 + 1 + + + GC5C2 + Group Channel 5 and Channel + 2 + 30 + 1 + + + GC5C3 + Group Channel 5 and Channel + 3 + 31 + 1 + + + + + CCR6 + CCR6 + capture/compare register 4 + 0x5C + 0x20 + read-write + 0x00000000 + + + CCR6 + Capture/Compare value + 0 + 16 + + + + + OR2 + OR2 + DMA address for full transfer + 0x60 + 0x20 + read-write + 0x00000001 + + + BKINE + BRK BKIN input enable + 0 + 1 + + + BKCMP1E + BRK COMP1 enable + 1 + 1 + + + BKCMP2E + BRK COMP2 enable + 2 + 1 + + + BKDFBK0E + BRK DFSDM_BREAK0 enable + 8 + 1 + + + BKINP + BRK BKIN input polarity + 9 + 1 + + + BKCMP1P + BRK COMP1 input polarity + 10 + 1 + + + BKCMP2P + BRK COMP2 input polarity + 11 + 1 + + + ETRSEL + ETR source selection + 14 + 3 + + + + + OR3 + OR3 + DMA address for full transfer + 0x64 + 0x20 + read-write + 0x00000001 + + + BK2INE + BRK2 BKIN input enable + 0 + 1 + + + BK2CMP1E + BRK2 COMP1 enable + 1 + 1 + + + BK2CMP2E + BRK2 COMP2 enable + 2 + 1 + + + BK2DFBK0E + BRK2 DFSDM_BREAK0 enable + 8 + 1 + + + BK2INP + BRK2 BKIN input polarity + 9 + 1 + + + BK2CMP1P + BRK2 COMP1 input polarity + 10 + 1 + + + BK2CMP2P + BRK2 COMP2 input polarity + 11 + 1 + + + + + + + TIM6 + Basic-timers + TIM + 0x40001000 + + 0x0 + 0x400 + registers + + + TIM6_DAC + TIM6 global and DAC1 and 2 underrun error + interrupts + 54 + + + TIM6_DAC + TIM6 global and DAC1 and 2 underrun error + interrupts + 54 + + + TIM6_DAC + TIM6 global and DAC1 and 2 underrun error + interrupts + 54 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + OPM + One-pulse mode + 3 + 1 + + + URS + Update request source + 2 + 1 + + + UDIS + Update disable + 1 + 1 + + + CEN + Counter enable + 0 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + MMS + Master mode selection + 4 + 3 + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + UDE + Update DMA request enable + 8 + 1 + + + UIE + Update interrupt enable + 0 + 1 + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x0000 + + + UIF + Update interrupt flag + 0 + 1 + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x0000 + + + UG + Update generation + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + read-write + 0x00000000 + + + CNT + Low counter value + 0 + 16 + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x0000 + + + PSC + Prescaler value + 0 + 16 + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x00000000 + + + ARR + Low Auto-reload value + 0 + 16 + + + + + + + TIM7 + 0x40001400 + + TIM7 + TIM7 global interrupt + 55 + + + TIM7 + TIM7 global interrupt + 55 + + + TIM7 + TIM7 global interrupt + 55 + + + + LPTIM1 + Low power timer + LPTIM + 0x40007C00 + + 0x0 + 0x400 + registers + + + LPTIM1 + LP TIM1 interrupt + 65 + + + LPTIM1 + LP TIM1 interrupt + 65 + + + LPTIM1 + LP TIM1 interrupt + 65 + + + + ISR + ISR + Interrupt and Status Register + 0x0 + 0x20 + read-only + 0x00000000 + + + DOWN + Counter direction change up to + down + 6 + 1 + + + UP + Counter direction change down to + up + 5 + 1 + + + ARROK + Autoreload register update + OK + 4 + 1 + + + CMPOK + Compare register update OK + 3 + 1 + + + EXTTRIG + External trigger edge + event + 2 + 1 + + + ARRM + Autoreload match + 1 + 1 + + + CMPM + Compare match + 0 + 1 + + + + + ICR + ICR + Interrupt Clear Register + 0x4 + 0x20 + write-only + 0x00000000 + + + DOWNCF + Direction change to down Clear + Flag + 6 + 1 + + + UPCF + Direction change to UP Clear + Flag + 5 + 1 + + + ARROKCF + Autoreload register update OK Clear + Flag + 4 + 1 + + + CMPOKCF + Compare register update OK Clear + Flag + 3 + 1 + + + EXTTRIGCF + External trigger valid edge Clear + Flag + 2 + 1 + + + ARRMCF + Autoreload match Clear + Flag + 1 + 1 + + + CMPMCF + compare match Clear Flag + 0 + 1 + + + + + IER + IER + Interrupt Enable Register + 0x8 + 0x20 + read-write + 0x00000000 + + + DOWNIE + Direction change to down Interrupt + Enable + 6 + 1 + + + UPIE + Direction change to UP Interrupt + Enable + 5 + 1 + + + ARROKIE + Autoreload register update OK Interrupt + Enable + 4 + 1 + + + CMPOKIE + Compare register update OK Interrupt + Enable + 3 + 1 + + + EXTTRIGIE + External trigger valid edge Interrupt + Enable + 2 + 1 + + + ARRMIE + Autoreload match Interrupt + Enable + 1 + 1 + + + CMPMIE + Compare match Interrupt + Enable + 0 + 1 + + + + + CFGR + CFGR + Configuration Register + 0xC + 0x20 + read-write + 0x00000000 + + + ENC + Encoder mode enable + 24 + 1 + + + COUNTMODE + counter mode enabled + 23 + 1 + + + PRELOAD + Registers update mode + 22 + 1 + + + WAVPOL + Waveform shape polarity + 21 + 1 + + + WAVE + Waveform shape + 20 + 1 + + + TIMOUT + Timeout enable + 19 + 1 + + + TRIGEN + Trigger enable and + polarity + 17 + 2 + + + TRIGSEL + Trigger selector + 13 + 3 + + + PRESC + Clock prescaler + 9 + 3 + + + TRGFLT + Configurable digital filter for + trigger + 6 + 2 + + + CKFLT + Configurable digital filter for external + clock + 3 + 2 + + + CKPOL + Clock Polarity + 1 + 2 + + + CKSEL + Clock selector + 0 + 1 + + + + + CR + CR + Control Register + 0x10 + 0x20 + read-write + 0x00000000 + + + CNTSTRT + Timer start in continuous + mode + 2 + 1 + + + SNGSTRT + LPTIM start in single mode + 1 + 1 + + + ENABLE + LPTIM Enable + 0 + 1 + + + + + CMP + CMP + Compare Register + 0x14 + 0x20 + read-write + 0x00000000 + + + CMP + Compare value + 0 + 16 + + + + + ARR + ARR + Autoreload Register + 0x18 + 0x20 + read-write + 0x00000001 + + + ARR + Auto reload value + 0 + 16 + + + + + CNT + CNT + Counter Register + 0x1C + 0x20 + read-only + 0x00000000 + + + CNT + Counter value + 0 + 16 + + + + + + + LPTIM2 + 0x40009400 + + LPTIM2 + LP TIM2 interrupt + 66 + + + LPTIM2 + LP TIM2 interrupt + 66 + + + LPTIM2 + LP TIM2 interrupt + 66 + + + + USART1 + Universal synchronous asynchronous receiver + transmitter + USART + 0x40013800 + + 0x0 + 0x400 + registers + + + USART1 + USART1 global interrupt + 37 + + + USART1 + USART1 global interrupt + 37 + + + USART1 + USART1 global interrupt + 37 + + + + CR1 + CR1 + Control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + M1 + Word length + 28 + 1 + + + EOBIE + End of Block interrupt + enable + 27 + 1 + + + RTOIE + Receiver timeout interrupt + enable + 26 + 1 + + + DEAT4 + Driver Enable assertion + time + 25 + 1 + + + DEAT3 + DEAT3 + 24 + 1 + + + DEAT2 + DEAT2 + 23 + 1 + + + DEAT1 + DEAT1 + 22 + 1 + + + DEAT0 + DEAT0 + 21 + 1 + + + DEDT4 + Driver Enable de-assertion + time + 20 + 1 + + + DEDT3 + DEDT3 + 19 + 1 + + + DEDT2 + DEDT2 + 18 + 1 + + + DEDT1 + DEDT1 + 17 + 1 + + + DEDT0 + DEDT0 + 16 + 1 + + + OVER8 + Oversampling mode + 15 + 1 + + + CMIE + Character match interrupt + enable + 14 + 1 + + + MME + Mute mode enable + 13 + 1 + + + M0 + Word length + 12 + 1 + + + WAKE + Receiver wakeup method + 11 + 1 + + + PCE + Parity control enable + 10 + 1 + + + PS + Parity selection + 9 + 1 + + + PEIE + PE interrupt enable + 8 + 1 + + + TXEIE + interrupt enable + 7 + 1 + + + TCIE + Transmission complete interrupt + enable + 6 + 1 + + + RXNEIE + RXNE interrupt enable + 5 + 1 + + + IDLEIE + IDLE interrupt enable + 4 + 1 + + + TE + Transmitter enable + 3 + 1 + + + RE + Receiver enable + 2 + 1 + + + UESM + USART enable in Stop mode + 1 + 1 + + + UE + USART enable + 0 + 1 + + + + + CR2 + CR2 + Control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + ADD4_7 + Address of the USART node + 28 + 4 + + + ADD0_3 + Address of the USART node + 24 + 4 + + + RTOEN + Receiver timeout enable + 23 + 1 + + + ABRMOD1 + Auto baud rate mode + 22 + 1 + + + ABRMOD0 + ABRMOD0 + 21 + 1 + + + ABREN + Auto baud rate enable + 20 + 1 + + + MSBFIRST + Most significant bit first + 19 + 1 + + + TAINV + Binary data inversion + 18 + 1 + + + TXINV + TX pin active level + inversion + 17 + 1 + + + RXINV + RX pin active level + inversion + 16 + 1 + + + SWAP + Swap TX/RX pins + 15 + 1 + + + LINEN + LIN mode enable + 14 + 1 + + + STOP + STOP bits + 12 + 2 + + + CLKEN + Clock enable + 11 + 1 + + + CPOL + Clock polarity + 10 + 1 + + + CPHA + Clock phase + 9 + 1 + + + LBCL + Last bit clock pulse + 8 + 1 + + + LBDIE + LIN break detection interrupt + enable + 6 + 1 + + + LBDL + LIN break detection length + 5 + 1 + + + ADDM7 + 7-bit Address Detection/4-bit Address + Detection + 4 + 1 + + + + + CR3 + CR3 + Control register 3 + 0x8 + 0x20 + read-write + 0x0000 + + + WUFIE + Wakeup from Stop mode interrupt + enable + 22 + 1 + + + WUS + Wakeup from Stop mode interrupt flag + selection + 20 + 2 + + + SCARCNT + Smartcard auto-retry count + 17 + 3 + + + DEP + Driver enable polarity + selection + 15 + 1 + + + DEM + Driver enable mode + 14 + 1 + + + DDRE + DMA Disable on Reception + Error + 13 + 1 + + + OVRDIS + Overrun Disable + 12 + 1 + + + ONEBIT + One sample bit method + enable + 11 + 1 + + + CTSIE + CTS interrupt enable + 10 + 1 + + + CTSE + CTS enable + 9 + 1 + + + RTSE + RTS enable + 8 + 1 + + + DMAT + DMA enable transmitter + 7 + 1 + + + DMAR + DMA enable receiver + 6 + 1 + + + SCEN + Smartcard mode enable + 5 + 1 + + + NACK + Smartcard NACK enable + 4 + 1 + + + HDSEL + Half-duplex selection + 3 + 1 + + + IRLP + Ir low-power + 2 + 1 + + + IREN + Ir mode enable + 1 + 1 + + + EIE + Error interrupt enable + 0 + 1 + + + + + BRR + BRR + Baud rate register + 0xC + 0x20 + read-write + 0x0000 + + + DIV_Mantissa + DIV_Mantissa + 4 + 12 + + + DIV_Fraction + DIV_Fraction + 0 + 4 + + + + + GTPR + GTPR + Guard time and prescaler + register + 0x10 + 0x20 + read-write + 0x0000 + + + GT + Guard time value + 8 + 8 + + + PSC + Prescaler value + 0 + 8 + + + + + RTOR + RTOR + Receiver timeout register + 0x14 + 0x20 + read-write + 0x0000 + + + BLEN + Block Length + 24 + 8 + + + RTO + Receiver timeout value + 0 + 24 + + + + + RQR + RQR + Request register + 0x18 + 0x20 + write-only + 0x0000 + + + TXFRQ + Transmit data flush + request + 4 + 1 + + + RXFRQ + Receive data flush request + 3 + 1 + + + MMRQ + Mute mode request + 2 + 1 + + + SBKRQ + Send break request + 1 + 1 + + + ABRRQ + Auto baud rate request + 0 + 1 + + + + + ISR + ISR + Interrupt & status + register + 0x1C + 0x20 + read-only + 0x00C0 + + + REACK + REACK + 22 + 1 + + + TEACK + TEACK + 21 + 1 + + + WUF + WUF + 20 + 1 + + + RWU + RWU + 19 + 1 + + + SBKF + SBKF + 18 + 1 + + + CMF + CMF + 17 + 1 + + + BUSY + BUSY + 16 + 1 + + + ABRF + ABRF + 15 + 1 + + + ABRE + ABRE + 14 + 1 + + + EOBF + EOBF + 12 + 1 + + + RTOF + RTOF + 11 + 1 + + + CTS + CTS + 10 + 1 + + + CTSIF + CTSIF + 9 + 1 + + + LBDF + LBDF + 8 + 1 + + + TXE + TXE + 7 + 1 + + + TC + TC + 6 + 1 + + + RXNE + RXNE + 5 + 1 + + + IDLE + IDLE + 4 + 1 + + + ORE + ORE + 3 + 1 + + + NF + NF + 2 + 1 + + + FE + FE + 1 + 1 + + + PE + PE + 0 + 1 + + + + + ICR + ICR + Interrupt flag clear register + 0x20 + 0x20 + write-only + 0x0000 + + + WUCF + Wakeup from Stop mode clear + flag + 20 + 1 + + + CMCF + Character match clear flag + 17 + 1 + + + EOBCF + End of block clear flag + 12 + 1 + + + RTOCF + Receiver timeout clear + flag + 11 + 1 + + + CTSCF + CTS clear flag + 9 + 1 + + + LBDCF + LIN break detection clear + flag + 8 + 1 + + + TCCF + Transmission complete clear + flag + 6 + 1 + + + IDLECF + Idle line detected clear + flag + 4 + 1 + + + ORECF + Overrun error clear flag + 3 + 1 + + + NCF + Noise detected clear flag + 2 + 1 + + + FECF + Framing error clear flag + 1 + 1 + + + PECF + Parity error clear flag + 0 + 1 + + + + + RDR + RDR + Receive data register + 0x24 + 0x20 + read-only + 0x0000 + + + RDR + Receive data value + 0 + 9 + + + + + TDR + TDR + Transmit data register + 0x28 + 0x20 + read-write + 0x0000 + + + TDR + Transmit data value + 0 + 9 + + + + + + + USART2 + 0x40004400 + + USART2 + USART2 global interrupt + 38 + + + USART2 + USART2 global interrupt + 38 + + + USART2 + USART2 global interrupt + 38 + + + + USART3 + 0x40004800 + + USART3 + USART3 global interrupt + 39 + + + USART3 + USART3 global interrupt + 39 + + + USART3 + USART3 global interrupt + 39 + + + + UART5 + 0x40005000 + + UART5 + UART5 global Interrupt + 53 + + + UART5 + UART5 global Interrupt + 53 + + + UART5 + UART5 global Interrupt + 53 + + + + UART4 + 0x40004C00 + + UART4 + UART4 global Interrupt + 52 + + + UART4 + UART4 global Interrupt + 52 + + + UART4 + UART4 global Interrupt + 52 + + + + LPUART1 + Universal synchronous asynchronous receiver + transmitter + USART + 0x40008000 + + 0x0 + 0x400 + registers + + + + CR1 + CR1 + Control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + M1 + Word length + 28 + 1 + + + DEAT4 + Driver Enable assertion + time + 25 + 1 + + + DEAT3 + DEAT3 + 24 + 1 + + + DEAT2 + DEAT2 + 23 + 1 + + + DEAT1 + DEAT1 + 22 + 1 + + + DEAT0 + DEAT0 + 21 + 1 + + + DEDT4 + Driver Enable de-assertion + time + 20 + 1 + + + DEDT3 + DEDT3 + 19 + 1 + + + DEDT2 + DEDT2 + 18 + 1 + + + DEDT1 + DEDT1 + 17 + 1 + + + DEDT0 + DEDT0 + 16 + 1 + + + CMIE + Character match interrupt + enable + 14 + 1 + + + MME + Mute mode enable + 13 + 1 + + + M0 + Word length + 12 + 1 + + + WAKE + Receiver wakeup method + 11 + 1 + + + PCE + Parity control enable + 10 + 1 + + + PS + Parity selection + 9 + 1 + + + PEIE + PE interrupt enable + 8 + 1 + + + TXEIE + interrupt enable + 7 + 1 + + + TCIE + Transmission complete interrupt + enable + 6 + 1 + + + RXNEIE + RXNE interrupt enable + 5 + 1 + + + IDLEIE + IDLE interrupt enable + 4 + 1 + + + TE + Transmitter enable + 3 + 1 + + + RE + Receiver enable + 2 + 1 + + + UESM + USART enable in Stop mode + 1 + 1 + + + UE + USART enable + 0 + 1 + + + + + CR2 + CR2 + Control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + ADD4_7 + Address of the USART node + 28 + 4 + + + ADD0_3 + Address of the USART node + 24 + 4 + + + MSBFIRST + Most significant bit first + 19 + 1 + + + TAINV + Binary data inversion + 18 + 1 + + + TXINV + TX pin active level + inversion + 17 + 1 + + + RXINV + RX pin active level + inversion + 16 + 1 + + + SWAP + Swap TX/RX pins + 15 + 1 + + + STOP + STOP bits + 12 + 2 + + + CLKEN + Clock enable + 11 + 1 + + + ADDM7 + 7-bit Address Detection/4-bit Address + Detection + 4 + 1 + + + + + CR3 + CR3 + Control register 3 + 0x8 + 0x20 + read-write + 0x0000 + + + WUFIE + Wakeup from Stop mode interrupt + enable + 22 + 1 + + + WUS + Wakeup from Stop mode interrupt flag + selection + 20 + 2 + + + DEP + Driver enable polarity + selection + 15 + 1 + + + DEM + Driver enable mode + 14 + 1 + + + DDRE + DMA Disable on Reception + Error + 13 + 1 + + + OVRDIS + Overrun Disable + 12 + 1 + + + CTSIE + CTS interrupt enable + 10 + 1 + + + CTSE + CTS enable + 9 + 1 + + + RTSE + RTS enable + 8 + 1 + + + DMAT + DMA enable transmitter + 7 + 1 + + + DMAR + DMA enable receiver + 6 + 1 + + + HDSEL + Half-duplex selection + 3 + 1 + + + EIE + Error interrupt enable + 0 + 1 + + + + + BRR + BRR + Baud rate register + 0xC + 0x20 + read-write + 0x0000 + + + BRR + BRR + 0 + 20 + + + + + RQR + RQR + Request register + 0x18 + 0x20 + write-only + 0x0000 + + + RXFRQ + Receive data flush request + 3 + 1 + + + MMRQ + Mute mode request + 2 + 1 + + + SBKRQ + Send break request + 1 + 1 + + + + + ISR + ISR + Interrupt & status + register + 0x1C + 0x20 + read-only + 0x00C0 + + + REACK + REACK + 22 + 1 + + + TEACK + TEACK + 21 + 1 + + + WUF + WUF + 20 + 1 + + + RWU + RWU + 19 + 1 + + + SBKF + SBKF + 18 + 1 + + + CMF + CMF + 17 + 1 + + + BUSY + BUSY + 16 + 1 + + + CTS + CTS + 10 + 1 + + + CTSIF + CTSIF + 9 + 1 + + + TXE + TXE + 7 + 1 + + + TC + TC + 6 + 1 + + + RXNE + RXNE + 5 + 1 + + + IDLE + IDLE + 4 + 1 + + + ORE + ORE + 3 + 1 + + + NF + NF + 2 + 1 + + + FE + FE + 1 + 1 + + + PE + PE + 0 + 1 + + + + + ICR + ICR + Interrupt flag clear register + 0x20 + 0x20 + write-only + 0x0000 + + + WUCF + Wakeup from Stop mode clear + flag + 20 + 1 + + + CMCF + Character match clear flag + 17 + 1 + + + CTSCF + CTS clear flag + 9 + 1 + + + TCCF + Transmission complete clear + flag + 6 + 1 + + + IDLECF + Idle line detected clear + flag + 4 + 1 + + + ORECF + Overrun error clear flag + 3 + 1 + + + NCF + Noise detected clear flag + 2 + 1 + + + FECF + Framing error clear flag + 1 + 1 + + + PECF + Parity error clear flag + 0 + 1 + + + + + RDR + RDR + Receive data register + 0x24 + 0x20 + read-only + 0x0000 + + + RDR + Receive data value + 0 + 9 + + + + + TDR + TDR + Transmit data register + 0x28 + 0x20 + read-write + 0x0000 + + + TDR + Transmit data value + 0 + 9 + + + + + + + SPI1 + Serial peripheral interface/Inter-IC + sound + SPI + 0x40013000 + + 0x0 + 0x400 + registers + + + SPI1 + SPI1 global interrupt + 35 + + + SPI1 + SPI1 global interrupt + 35 + + + SPI1 + SPI1 global interrupt + 35 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + BIDIMODE + Bidirectional data mode + enable + 15 + 1 + + + BIDIOE + Output enable in bidirectional + mode + 14 + 1 + + + CRCEN + Hardware CRC calculation + enable + 13 + 1 + + + CRCNEXT + CRC transfer next + 12 + 1 + + + DFF + Data frame format + 11 + 1 + + + RXONLY + Receive only + 10 + 1 + + + SSM + Software slave management + 9 + 1 + + + SSI + Internal slave select + 8 + 1 + + + LSBFIRST + Frame format + 7 + 1 + + + SPE + SPI enable + 6 + 1 + + + BR + Baud rate control + 3 + 3 + + + MSTR + Master selection + 2 + 1 + + + CPOL + Clock polarity + 1 + 1 + + + CPHA + Clock phase + 0 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + RXDMAEN + Rx buffer DMA enable + 0 + 1 + + + TXDMAEN + Tx buffer DMA enable + 1 + 1 + + + SSOE + SS output enable + 2 + 1 + + + NSSP + NSS pulse management + 3 + 1 + + + FRF + Frame format + 4 + 1 + + + ERRIE + Error interrupt enable + 5 + 1 + + + RXNEIE + RX buffer not empty interrupt + enable + 6 + 1 + + + TXEIE + Tx buffer empty interrupt + enable + 7 + 1 + + + DS + Data size + 8 + 4 + + + FRXTH + FIFO reception threshold + 12 + 1 + + + LDMA_RX + Last DMA transfer for + reception + 13 + 1 + + + LDMA_TX + Last DMA transfer for + transmission + 14 + 1 + + + + + SR + SR + status register + 0x8 + 0x20 + 0x0002 + + + RXNE + Receive buffer not empty + 0 + 1 + read-only + + + TXE + Transmit buffer empty + 1 + 1 + read-only + + + CRCERR + CRC error flag + 4 + 1 + read-write + + + MODF + Mode fault + 5 + 1 + read-only + + + OVR + Overrun flag + 6 + 1 + read-only + + + BSY + Busy flag + 7 + 1 + read-only + + + TIFRFE + TI frame format error + 8 + 1 + read-only + + + FRLVL + FIFO reception level + 9 + 2 + read-only + + + FTLVL + FIFO transmission level + 11 + 2 + read-only + + + + + DR + DR + data register + 0xC + 0x20 + read-write + 0x0000 + + + DR + Data register + 0 + 16 + + + + + CRCPR + CRCPR + CRC polynomial register + 0x10 + 0x20 + read-write + 0x0007 + + + CRCPOLY + CRC polynomial register + 0 + 16 + + + + + RXCRCR + RXCRCR + RX CRC register + 0x14 + 0x20 + read-only + 0x0000 + + + RxCRC + Rx CRC register + 0 + 16 + + + + + TXCRCR + TXCRCR + TX CRC register + 0x18 + 0x20 + read-only + 0x0000 + + + TxCRC + Tx CRC register + 0 + 16 + + + + + + + SPI2 + 0x40003800 + + SPI2 + SPI2 global interrupt + 36 + + + SPI2 + SPI2 global interrupt + 36 + + + SPI2 + SPI2 global interrupt + 36 + + + + SPI3 + 0x40003C00 + + SPI3 + SPI3 global Interrupt + 51 + + + SPI3 + SPI3 global Interrupt + 51 + + + SPI3 + SPI3 global Interrupt + 51 + + + + SDMMC + Secure digital input/output + interface + SDIO + 0x40012800 + + 0x0 + 0x400 + registers + + + SDMMC + SDMMC global Interrupt + 49 + + + SDMMC + SDMMC global Interrupt + 49 + + + SDMMC + SDMMC global Interrupt + 49 + + + + POWER + POWER + power control register + 0x0 + 0x20 + read-write + 0x00000000 + + + PWRCTRL + PWRCTRL + 0 + 2 + + + + + CLKCR + CLKCR + SDI clock control register + 0x4 + 0x20 + read-write + 0x00000000 + + + HWFC_EN + HW Flow Control enable + 14 + 1 + + + NEGEDGE + SDIO_CK dephasing selection + bit + 13 + 1 + + + WIDBUS + Wide bus mode enable bit + 11 + 2 + + + BYPASS + Clock divider bypass enable + bit + 10 + 1 + + + PWRSAV + Power saving configuration + bit + 9 + 1 + + + CLKEN + Clock enable bit + 8 + 1 + + + CLKDIV + Clock divide factor + 0 + 8 + + + + + ARG + ARG + argument register + 0x8 + 0x20 + read-write + 0x00000000 + + + CMDARG + Command argument + 0 + 32 + + + + + CMD + CMD + command register + 0xC + 0x20 + read-write + 0x00000000 + + + CE_ATACMD + CE-ATA command + 14 + 1 + + + nIEN + not Interrupt Enable + 13 + 1 + + + ENCMDcompl + Enable CMD completion + 12 + 1 + + + SDIOSuspend + SD I/O suspend command + 11 + 1 + + + CPSMEN + Command path state machine (CPSM) Enable + bit + 10 + 1 + + + WAITPEND + CPSM Waits for ends of data transfer + (CmdPend internal signal) + 9 + 1 + + + WAITINT + CPSM waits for interrupt + request + 8 + 1 + + + WAITRESP + Wait for response bits + 6 + 2 + + + CMDINDEX + Command index + 0 + 6 + + + + + RESPCMD + RESPCMD + command response register + 0x10 + 0x20 + read-only + 0x00000000 + + + RESPCMD + Response command index + 0 + 6 + + + + + RESP1 + RESP1 + response 1..4 register + 0x14 + 0x20 + read-only + 0x00000000 + + + CARDSTATUS1 + see Table 132 + 0 + 32 + + + + + RESP2 + RESP2 + response 1..4 register + 0x18 + 0x20 + read-only + 0x00000000 + + + CARDSTATUS2 + see Table 132 + 0 + 32 + + + + + RESP3 + RESP3 + response 1..4 register + 0x1C + 0x20 + read-only + 0x00000000 + + + CARDSTATUS3 + see Table 132 + 0 + 32 + + + + + RESP4 + RESP4 + response 1..4 register + 0x20 + 0x20 + read-only + 0x00000000 + + + CARDSTATUS4 + see Table 132 + 0 + 32 + + + + + DTIMER + DTIMER + data timer register + 0x24 + 0x20 + read-write + 0x00000000 + + + DATATIME + Data timeout period + 0 + 32 + + + + + DLEN + DLEN + data length register + 0x28 + 0x20 + read-write + 0x00000000 + + + DATALENGTH + Data length value + 0 + 25 + + + + + DCTRL + DCTRL + data control register + 0x2C + 0x20 + read-write + 0x00000000 + + + SDIOEN + SD I/O enable functions + 11 + 1 + + + RWMOD + Read wait mode + 10 + 1 + + + RWSTOP + Read wait stop + 9 + 1 + + + RWSTART + Read wait start + 8 + 1 + + + DBLOCKSIZE + Data block size + 4 + 4 + + + DMAEN + DMA enable bit + 3 + 1 + + + DTMODE + Data transfer mode selection 1: Stream + or SDIO multibyte data transfer + 2 + 1 + + + DTDIR + Data transfer direction + selection + 1 + 1 + + + DTEN + DTEN + 0 + 1 + + + + + DCOUNT + DCOUNT + data counter register + 0x30 + 0x20 + read-only + 0x00000000 + + + DATACOUNT + Data count value + 0 + 25 + + + + + STA + STA + status register + 0x34 + 0x20 + read-only + 0x00000000 + + + CEATAEND + CE-ATA command completion signal + received for CMD61 + 23 + 1 + + + SDIOIT + SDIO interrupt received + 22 + 1 + + + RXDAVL + Data available in receive + FIFO + 21 + 1 + + + TXDAVL + Data available in transmit + FIFO + 20 + 1 + + + RXFIFOE + Receive FIFO empty + 19 + 1 + + + TXFIFOE + Transmit FIFO empty + 18 + 1 + + + RXFIFOF + Receive FIFO full + 17 + 1 + + + TXFIFOF + Transmit FIFO full + 16 + 1 + + + RXFIFOHF + Receive FIFO half full: there are at + least 8 words in the FIFO + 15 + 1 + + + TXFIFOHE + Transmit FIFO half empty: at least 8 + words can be written into the FIFO + 14 + 1 + + + RXACT + Data receive in progress + 13 + 1 + + + TXACT + Data transmit in progress + 12 + 1 + + + CMDACT + Command transfer in + progress + 11 + 1 + + + DBCKEND + Data block sent/received (CRC check + passed) + 10 + 1 + + + STBITERR + Start bit not detected on all data + signals in wide bus mode + 9 + 1 + + + DATAEND + Data end (data counter, SDIDCOUNT, is + zero) + 8 + 1 + + + CMDSENT + Command sent (no response + required) + 7 + 1 + + + CMDREND + Command response received (CRC check + passed) + 6 + 1 + + + RXOVERR + Received FIFO overrun + error + 5 + 1 + + + TXUNDERR + Transmit FIFO underrun + error + 4 + 1 + + + DTIMEOUT + Data timeout + 3 + 1 + + + CTIMEOUT + Command response timeout + 2 + 1 + + + DCRCFAIL + Data block sent/received (CRC check + failed) + 1 + 1 + + + CCRCFAIL + Command response received (CRC check + failed) + 0 + 1 + + + + + ICR + ICR + interrupt clear register + 0x38 + 0x20 + read-write + 0x00000000 + + + CEATAENDC + CEATAEND flag clear bit + 23 + 1 + + + SDIOITC + SDIOIT flag clear bit + 22 + 1 + + + DBCKENDC + DBCKEND flag clear bit + 10 + 1 + + + STBITERRC + STBITERR flag clear bit + 9 + 1 + + + DATAENDC + DATAEND flag clear bit + 8 + 1 + + + CMDSENTC + CMDSENT flag clear bit + 7 + 1 + + + CMDRENDC + CMDREND flag clear bit + 6 + 1 + + + RXOVERRC + RXOVERR flag clear bit + 5 + 1 + + + TXUNDERRC + TXUNDERR flag clear bit + 4 + 1 + + + DTIMEOUTC + DTIMEOUT flag clear bit + 3 + 1 + + + CTIMEOUTC + CTIMEOUT flag clear bit + 2 + 1 + + + DCRCFAILC + DCRCFAIL flag clear bit + 1 + 1 + + + CCRCFAILC + CCRCFAIL flag clear bit + 0 + 1 + + + + + MASK + MASK + mask register + 0x3C + 0x20 + read-write + 0x00000000 + + + CEATAENDIE + CE-ATA command completion signal + received interrupt enable + 23 + 1 + + + SDIOITIE + SDIO mode interrupt received interrupt + enable + 22 + 1 + + + RXDAVLIE + Data available in Rx FIFO interrupt + enable + 21 + 1 + + + TXDAVLIE + Data available in Tx FIFO interrupt + enable + 20 + 1 + + + RXFIFOEIE + Rx FIFO empty interrupt + enable + 19 + 1 + + + TXFIFOEIE + Tx FIFO empty interrupt + enable + 18 + 1 + + + RXFIFOFIE + Rx FIFO full interrupt + enable + 17 + 1 + + + TXFIFOFIE + Tx FIFO full interrupt + enable + 16 + 1 + + + RXFIFOHFIE + Rx FIFO half full interrupt + enable + 15 + 1 + + + TXFIFOHEIE + Tx FIFO half empty interrupt + enable + 14 + 1 + + + RXACTIE + Data receive acting interrupt + enable + 13 + 1 + + + TXACTIE + Data transmit acting interrupt + enable + 12 + 1 + + + CMDACTIE + Command acting interrupt + enable + 11 + 1 + + + DBCKENDIE + Data block end interrupt + enable + 10 + 1 + + + STBITERRIE + Start bit error interrupt + enable + 9 + 1 + + + DATAENDIE + Data end interrupt enable + 8 + 1 + + + CMDSENTIE + Command sent interrupt + enable + 7 + 1 + + + CMDRENDIE + Command response received interrupt + enable + 6 + 1 + + + RXOVERRIE + Rx FIFO overrun error interrupt + enable + 5 + 1 + + + TXUNDERRIE + Tx FIFO underrun error interrupt + enable + 4 + 1 + + + DTIMEOUTIE + Data timeout interrupt + enable + 3 + 1 + + + CTIMEOUTIE + Command timeout interrupt + enable + 2 + 1 + + + DCRCFAILIE + Data CRC fail interrupt + enable + 1 + 1 + + + CCRCFAILIE + Command CRC fail interrupt + enable + 0 + 1 + + + + + FIFOCNT + FIFOCNT + FIFO counter register + 0x48 + 0x20 + read-only + 0x00000000 + + + FIFOCOUNT + Remaining number of words to be written + to or read from the FIFO + 0 + 24 + + + + + FIFO + FIFO + data FIFO register + 0x80 + 0x20 + read-write + 0x00000000 + + + FIFOData + Receive and transmit FIFO + data + 0 + 32 + + + + + + + EXTI + External interrupt/event + controller + EXTI + 0x40010400 + + 0x0 + 0x400 + registers + + + PVD + PVD through EXTI line detection + 1 + + + PVD + PVD through EXTI line detection + 1 + + + PVD + PVD through EXTI line detection + 1 + + + EXTI0 + EXTI Line 0 interrupt + 6 + + + EXTI0 + EXTI Line 0 interrupt + 6 + + + EXTI0 + EXTI Line 0 interrupt + 6 + + + EXTI1 + EXTI Line 1 interrupt + 7 + + + EXTI1 + EXTI Line 1 interrupt + 7 + + + EXTI1 + EXTI Line 1 interrupt + 7 + + + EXTI2 + EXTI Line 2 interrupt + 8 + + + EXTI2 + EXTI Line 2 interrupt + 8 + + + EXTI2 + EXTI Line 2 interrupt + 8 + + + EXTI3 + EXTI Line 3 interrupt + 9 + + + EXTI3 + EXTI Line 3 interrupt + 9 + + + EXTI3 + EXTI Line 3 interrupt + 9 + + + EXTI4 + EXTI Line4 interrupt + 10 + + + EXTI4 + EXTI Line4 interrupt + 10 + + + EXTI4 + EXTI Line4 interrupt + 10 + + + EXTI9_5 + EXTI Line5 to Line9 interrupts + 23 + + + EXTI9_5 + EXTI Line5 to Line9 interrupts + 23 + + + EXTI9_5 + EXTI Line5 to Line9 interrupts + 23 + + + EXTI15_10 + EXTI Lines 10 to 15 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MR17 + Interrupt Mask on line 17 + 17 + 1 + + + MR18 + Interrupt Mask on line 18 + 18 + 1 + + + MR19 + Interrupt Mask on line 19 + 19 + 1 + + + MR20 + Interrupt Mask on line 20 + 20 + 1 + + + MR21 + Interrupt Mask on line 21 + 21 + 1 + + + MR22 + Interrupt Mask on line 22 + 22 + 1 + + + MR23 + Interrupt Mask on line 23 + 23 + 1 + + + MR24 + Interrupt Mask on line 24 + 24 + 1 + + + MR25 + Interrupt Mask on line 25 + 25 + 1 + + + MR26 + Interrupt Mask on line 26 + 26 + 1 + + + MR27 + Interrupt Mask on line 27 + 27 + 1 + + + MR28 + Interrupt Mask on line 28 + 28 + 1 + + + MR29 + Interrupt Mask on line 29 + 29 + 1 + + + MR30 + Interrupt Mask on line 30 + 30 + 1 + + + MR31 + Interrupt Mask on line 31 + 31 + 1 + + + + + EMR1 + EMR1 + Event mask register + 0x4 + 0x20 + read-write + 0x00000000 + + + MR0 + Event Mask on line 0 + 0 + 1 + + + MR1 + Event Mask on line 1 + 1 + 1 + + + MR2 + Event Mask on line 2 + 2 + 1 + + + MR3 + Event Mask on line 3 + 3 + 1 + + + MR4 + Event Mask on line 4 + 4 + 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differential + pairs + 0 + 5 + + + TRIMOFFSETP + Trim for PMOS differential + pairs + 8 + 5 + + + + + OPAMP2_LPOTR + OPAMP2_LPOTR + OPAMP2 offset trimming register in low-power + mode + 0x18 + 0x20 + read-write + 0x00000000 + + + TRIMLPOFFSETN + Trim for NMOS differential + pairs + 0 + 5 + + + TRIMLPOFFSETP + Trim for PMOS differential + pairs + 8 + 5 + + + + + + + NVIC + Nested Vectored Interrupt + Controller + NVIC + 0xE000E100 + + 0x0 + 0x356 + registers + + + + ISER0 + ISER0 + Interrupt Set-Enable Register + 0x0 + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ISER1 + ISER1 + Interrupt Set-Enable Register + 0x4 + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ISER2 + ISER2 + Interrupt Set-Enable Register + 0x8 + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ICER0 + ICER0 + Interrupt Clear-Enable + Register + 0x80 + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ICER1 + ICER1 + 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+ IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR3 + IPR3 + Interrupt Priority Register + 0x30C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR4 + IPR4 + Interrupt Priority Register + 0x310 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR5 + IPR5 + Interrupt Priority Register + 0x314 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR6 + IPR6 + Interrupt Priority Register + 0x318 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR7 + IPR7 + Interrupt Priority Register + 0x31C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR8 + IPR8 + Interrupt Priority Register + 0x320 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR9 + IPR9 + Interrupt Priority Register + 0x324 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR10 + IPR10 + Interrupt Priority Register + 0x328 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR11 + IPR11 + Interrupt Priority Register + 0x32C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR12 + IPR12 + Interrupt Priority Register + 0x330 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR13 + IPR13 + Interrupt Priority Register + 0x334 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR14 + IPR14 + Interrupt Priority Register + 0x338 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR15 + IPR15 + Interrupt Priority Register + 0x33C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR16 + IPR16 + Interrupt Priority Register + 0x340 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR17 + IPR17 + Interrupt Priority Register + 0x344 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR18 + IPR18 + Interrupt Priority Register + 0x348 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR19 + IPR19 + Interrupt Priority Register + 0x34C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR20 + IPR20 + Interrupt Priority Register + 0x350 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + + + CRS + Clock recovery system + CRS + 0x40006000 + + 0x0 + 0x400 + registers + + + + CR + CR + control register + 0x0 + 0x20 + read-write + 0x00002000 + + + TRIM + HSI48 oscillator smooth + trimming + 8 + 6 + + + SWSYNC + Generate software SYNC + event + 7 + 1 + + + AUTOTRIMEN + Automatic trimming enable + 6 + 1 + + + CEN + Frequency error counter + enable + 5 + 1 + + + ESYNCIE + Expected SYNC interrupt + enable + 3 + 1 + + + ERRIE + Synchronization or trimming error + interrupt enable + 2 + 1 + + + SYNCWARNIE + SYNC warning interrupt + enable + 1 + 1 + + + SYNCOKIE + SYNC event OK interrupt + enable + 0 + 1 + + + + + CFGR + CFGR + configuration register + 0x4 + 0x20 + read-write + 0x2022BB7F + + + SYNCPOL + SYNC polarity selection + 31 + 1 + + + SYNCSRC + SYNC signal source + selection + 28 + 2 + + + SYNCDIV + SYNC divider + 24 + 3 + + + FELIM + Frequency error limit + 16 + 8 + + + RELOAD + Counter reload value + 0 + 16 + + + + + ISR + ISR + interrupt and status register + 0x8 + 0x20 + read-only + 0x00000000 + + + FECAP + Frequency error capture + 16 + 16 + + + FEDIR + Frequency error direction + 15 + 1 + + + TRIMOVF + Trimming overflow or + underflow + 10 + 1 + + + SYNCMISS + SYNC missed + 9 + 1 + + + SYNCERR + SYNC error + 8 + 1 + + + ESYNCF + Expected SYNC flag + 3 + 1 + + + ERRF + Error flag + 2 + 1 + + + SYNCWARNF + SYNC warning flag + 1 + 1 + + + SYNCOKF + SYNC event OK flag + 0 + 1 + + + + + ICR + ICR + interrupt flag clear register + 0xC + 0x20 + read-write + 0x00000000 + + + ESYNCC + Expected SYNC clear flag + 3 + 1 + + + ERRC + Error clear flag + 2 + 1 + + + SYNCWARNC + SYNC warning clear flag + 1 + 1 + + + SYNCOKC + SYNC event OK clear flag + 0 + 1 + + + + + + + USB + Universal serial bus full-speed device + interface + USB + 0x40006C00 + + 0x0 + 0x400 + registers + + + + EP0R + EP0R + endpoint 0 register + 0x0 + 0x20 + read-write + 0x00000000 + + + EA + Endpoint address + 0 + 4 + + + STAT_TX + Status bits, for transmission + transfers + 4 + 2 + + + DTOG_TX + Data Toggle, for transmission + transfers + 6 + 1 + + + CTR_TX + Correct Transfer for + transmission + 7 + 1 + + + EP_KIND + Endpoint kind + 8 + 1 + + + EP_TYPE + Endpoint type + 9 + 2 + + + SETUP + Setup transaction + completed + 11 + 1 + + + STAT_RX + Status bits, for reception + transfers + 12 + 2 + + + DTOG_RX + Data Toggle, for reception + transfers + 14 + 1 + + + CTR_RX + Correct transfer for + reception + 15 + 1 + + + + + EP1R + EP1R + endpoint 1 register + 0x4 + 0x20 + read-write + 0x00000000 + + + EA + Endpoint address + 0 + 4 + + + STAT_TX + Status bits, for transmission + transfers + 4 + 2 + + + DTOG_TX + Data Toggle, for transmission + transfers + 6 + 1 + + + CTR_TX + Correct Transfer for + transmission + 7 + 1 + + + EP_KIND + Endpoint kind + 8 + 1 + + + EP_TYPE + Endpoint type + 9 + 2 + + + SETUP + Setup transaction + completed + 11 + 1 + + + STAT_RX + Status bits, for reception + transfers + 12 + 2 + + + DTOG_RX + Data Toggle, for reception + transfers + 14 + 1 + + + CTR_RX + Correct transfer for + reception + 15 + 1 + + + + + EP2R + EP2R + endpoint 2 register + 0x8 + 0x20 + read-write + 0x00000000 + + + EA + Endpoint address + 0 + 4 + + + STAT_TX + Status bits, for transmission + transfers + 4 + 2 + + + DTOG_TX + Data Toggle, for transmission + transfers + 6 + 1 + + + CTR_TX + Correct Transfer for + transmission + 7 + 1 + + + EP_KIND + Endpoint kind + 8 + 1 + + + EP_TYPE + Endpoint type + 9 + 2 + + + SETUP + Setup transaction + completed + 11 + 1 + + + STAT_RX + Status bits, for reception + transfers + 12 + 2 + + + DTOG_RX + Data Toggle, for reception + transfers + 14 + 1 + + + CTR_RX + Correct transfer for + reception + 15 + 1 + + + + + EP3R + EP3R + endpoint 3 register + 0xC + 0x20 + read-write + 0x00000000 + + + EA + Endpoint address + 0 + 4 + + + STAT_TX + Status bits, for transmission + transfers + 4 + 2 + + + DTOG_TX + Data Toggle, for transmission + transfers + 6 + 1 + + + CTR_TX + Correct Transfer for + transmission + 7 + 1 + + + EP_KIND + Endpoint kind + 8 + 1 + + + EP_TYPE + Endpoint type + 9 + 2 + + + SETUP + Setup transaction + completed + 11 + 1 + + + STAT_RX + Status bits, for reception + transfers + 12 + 2 + + + DTOG_RX + Data Toggle, for reception + transfers + 14 + 1 + + + CTR_RX + Correct transfer for + reception + 15 + 1 + + + + + EP4R + EP4R + endpoint 4 register + 0x10 + 0x20 + read-write + 0x00000000 + + + EA + Endpoint address + 0 + 4 + + + STAT_TX + Status bits, for transmission + transfers + 4 + 2 + + + DTOG_TX + Data Toggle, for transmission + transfers + 6 + 1 + + + CTR_TX + Correct Transfer for + transmission + 7 + 1 + + + EP_KIND + Endpoint kind + 8 + 1 + + + EP_TYPE + Endpoint type + 9 + 2 + + + SETUP + Setup transaction + completed + 11 + 1 + + + STAT_RX + Status bits, for reception + transfers + 12 + 2 + + + DTOG_RX + Data Toggle, for reception + transfers + 14 + 1 + + + CTR_RX + Correct transfer for + reception + 15 + 1 + + + + + EP5R + EP5R + endpoint 5 register + 0x14 + 0x20 + read-write + 0x00000000 + + + EA + Endpoint address + 0 + 4 + + + STAT_TX + Status bits, for transmission + transfers + 4 + 2 + + + DTOG_TX + Data Toggle, for transmission + transfers + 6 + 1 + + + CTR_TX + Correct Transfer for + transmission + 7 + 1 + + + EP_KIND + Endpoint kind + 8 + 1 + + + EP_TYPE + Endpoint type + 9 + 2 + + + SETUP + Setup transaction + completed + 11 + 1 + + + STAT_RX + Status bits, for reception + transfers + 12 + 2 + + + DTOG_RX + Data Toggle, for reception + transfers + 14 + 1 + + + CTR_RX + Correct transfer for + reception + 15 + 1 + + + + + EP6R + EP6R + endpoint 6 register + 0x18 + 0x20 + read-write + 0x00000000 + + + EA + Endpoint address + 0 + 4 + + + STAT_TX + Status bits, for transmission + transfers + 4 + 2 + + + DTOG_TX + Data Toggle, for transmission + transfers + 6 + 1 + + + CTR_TX + Correct Transfer for + transmission + 7 + 1 + + + EP_KIND + Endpoint kind + 8 + 1 + + + EP_TYPE + Endpoint type + 9 + 2 + + + SETUP + Setup transaction + completed + 11 + 1 + + + STAT_RX + Status bits, for reception + transfers + 12 + 2 + + + DTOG_RX + Data Toggle, for reception + transfers + 14 + 1 + + + CTR_RX + Correct transfer for + reception + 15 + 1 + + + + + EP7R + EP7R + endpoint 7 register + 0x1C + 0x20 + read-write + 0x00000000 + + + EA + Endpoint address + 0 + 4 + + + STAT_TX + Status bits, for transmission + transfers + 4 + 2 + + + DTOG_TX + Data Toggle, for transmission + transfers + 6 + 1 + + + CTR_TX + Correct Transfer for + transmission + 7 + 1 + + + EP_KIND + Endpoint kind + 8 + 1 + + + EP_TYPE + Endpoint type + 9 + 2 + + + SETUP + Setup transaction + completed + 11 + 1 + + + STAT_RX + Status bits, for reception + transfers + 12 + 2 + + + DTOG_RX + Data Toggle, for reception + transfers + 14 + 1 + + + CTR_RX + Correct transfer for + reception + 15 + 1 + + + + + CNTR + CNTR + control register + 0x40 + 0x20 + read-write + 0x00000003 + + + FRES + Force USB Reset + 0 + 1 + + + PDWN + Power down + 1 + 1 + + + LPMODE + Low-power mode + 2 + 1 + + + FSUSP + Force suspend + 3 + 1 + + + RESUME + Resume request + 4 + 1 + + + L1RESUME + LPM L1 Resume request + 5 + 1 + + + L1REQM + LPM L1 state request interrupt + mask + 7 + 1 + + + ESOFM + Expected start of frame interrupt + mask + 8 + 1 + + + SOFM + Start of frame interrupt + mask + 9 + 1 + + + RESETM + USB reset interrupt mask + 10 + 1 + + + SUSPM + Suspend mode interrupt + mask + 11 + 1 + + + WKUPM + Wakeup interrupt mask + 12 + 1 + + + ERRM + Error interrupt mask + 13 + 1 + + + PMAOVRM + Packet memory area over / underrun + interrupt mask + 14 + 1 + + + CTRM + Correct transfer interrupt + mask + 15 + 1 + + + + + ISTR + ISTR + interrupt status register + 0x44 + 0x20 + 0x00000000 + + + EP_ID + Endpoint Identifier + 0 + 4 + read-only + + + DIR + Direction of transaction + 4 + 1 + read-only + + + L1REQ + LPM L1 state request + 7 + 1 + read-write + + + ESOF + Expected start frame + 8 + 1 + read-write + + + SOF + start of frame + 9 + 1 + read-write + + + RESET + reset request + 10 + 1 + read-write + + + SUSP + Suspend mode request + 11 + 1 + read-write + + + WKUP + Wakeup + 12 + 1 + read-write + + + ERR + Error + 13 + 1 + read-write + + + PMAOVR + Packet memory area over / + underrun + 14 + 1 + read-write + + + CTR + Correct transfer + 15 + 1 + read-only + + + + + FNR + FNR + frame number register + 0x48 + 0x20 + read-only + 0x0000 + + + FN + Frame number + 0 + 11 + + + LSOF + Lost SOF + 11 + 2 + + + LCK + Locked + 13 + 1 + + + RXDM + Receive data - line status + 14 + 1 + + + RXDP + Receive data + line status + 15 + 1 + + + + + DADDR + DADDR + device address + 0x4C + 0x20 + read-write + 0x0000 + + + ADD + Device address + 0 + 7 + + + EF + Enable function + 7 + 1 + + + + + BTABLE + BTABLE + Buffer table address + 0x50 + 0x20 + read-write + 0x0000 + + + BTABLE + Buffer table + 3 + 13 + + + + + + + QUADSPI + QuadSPI interface + QUADSPI + 0xA0001000 + + 0x0 + 0x400 + registers + + + QUADSPI + Quad SPI global interrupt + 71 + + + QUADSPI + Quad SPI global interrupt + 71 + + + QUADSPI + Quad SPI global interrupt + 71 + + + + CR + CR + control register + 0x0 + 0x20 + read-write + 0x00000000 + + + PRESCALER + Clock prescaler + 24 + 8 + + + PMM + Polling match mode + 23 + 1 + + + APMS + Automatic poll mode stop + 22 + 1 + + + TOIE + TimeOut interrupt enable + 20 + 1 + + + SMIE + Status match interrupt + enable + 19 + 1 + + + FTIE + FIFO threshold interrupt + enable + 18 + 1 + + + TCIE + Transfer complete interrupt + enable + 17 + 1 + + + TEIE + Transfer error interrupt + enable + 16 + 1 + + + FTHRES + IFO threshold level + 8 + 5 + + + FSEL + FLASH memory selection + 7 + 1 + + + DFM + Dual-flash mode + 6 + 1 + + + SSHIFT + Sample shift + 4 + 1 + + + TCEN + Timeout counter enable + 3 + 1 + + + DMAEN + DMA enable + 2 + 1 + + + ABORT + Abort request + 1 + 1 + + + EN + Enable + 0 + 1 + + + + + DCR + DCR + device configuration register + 0x4 + 0x20 + read-write + 0x00000000 + + + FSIZE + FLASH memory size + 16 + 5 + + + CSHT + Chip select high time + 8 + 3 + + + CKMODE + Mode 0 / mode 3 + 0 + 1 + + + + + SR + SR + status register + 0x8 + 0x20 + read-only + 0x00000000 + + + FLEVEL + FIFO level + 8 + 7 + + + BUSY + Busy + 5 + 1 + + + TOF + Timeout flag + 4 + 1 + + + SMF + Status match flag + 3 + 1 + + + FTF + FIFO threshold flag + 2 + 1 + + + TCF + Transfer complete flag + 1 + 1 + + + TEF + Transfer error flag + 0 + 1 + + + + + FCR + FCR + flag clear register + 0xC + 0x20 + read-write + 0x00000000 + + + CTOF + Clear timeout flag + 4 + 1 + + + CSMF + Clear status match flag + 3 + 1 + + + CTCF + Clear transfer complete + flag + 1 + 1 + + + CTEF + Clear transfer error flag + 0 + 1 + + + + + DLR + DLR + data length register + 0x10 + 0x20 + read-write + 0x00000000 + + + DL + Data length + 0 + 32 + + + + + CCR + CCR + communication configuration + register + 0x14 + 0x20 + read-write + 0x00000000 + + + DDRM + Double data rate mode + 31 + 1 + + + DHHC + DDR hold half cycle + 30 + 1 + + + SIOO + Send instruction only once + mode + 28 + 1 + + + FMODE + Functional mode + 26 + 2 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AWSCD6R + AWSCD6R + 0xC8 + 0x20 + read-write + 0x0 + + + AWFORD + AWFORD + 22 + 2 + + + AWFOSR + AWFOSR + 16 + 5 + + + BKSCD + BKSCD + 12 + 4 + + + SCDT + SCDT + 0 + 8 + + + + + CHWDAT6R + CHWDAT6R + CHWDAT6R + 0xCC + 0x20 + read-write + 0x0 + + + WDATA + WDATA + 0 + 16 + + + + + CHDATIN6R + CHDATIN6R + CHDATIN6R + 0xD0 + 0x20 + read-write + 0x0 + + + INDAT1 + INDAT1 + 16 + 16 + + + INDAT0 + INDAT0 + 0 + 16 + + + + + CHCFG7R1 + CHCFG7R1 + CHCFG7R1 + 0xE0 + 0x20 + read-write + 0x0 + + + DATPACK + DATPACK + 14 + 2 + + + DATMPX + DATMPX + 12 + 2 + + + CHINSEL + CHINSEL + 8 + 1 + + + CHEN + CHEN + 7 + 1 + + + CKABEN + CKABEN + 6 + 1 + + + SCDEN + SCDEN + 5 + 1 + + + SPICKSEL + SPICKSEL + 2 + 2 + + + SITP + SITP + 0 + 2 + + + + + CHCFG7R2 + CHCFG7R2 + CHCFG7R2 + 0xE4 + 0x20 + read-write + 0x0 + + + OFFSET + OFFSET + 8 + 24 + + + DTRBS + DTRBS + 3 + 5 + + + + + AWSCD7R + AWSCD7R + AWSCD7R + 0xE8 + 0x20 + read-write + 0x0 + + + AWFORD + AWFORD + 22 + 2 + + + AWFOSR + AWFOSR + 16 + 5 + + + BKSCD + BKSCD + 12 + 4 + + + SCDT + SCDT + 0 + 8 + + + + + CHWDAT7R + CHWDAT7R + CHWDAT7R + 0xEC + 0x20 + read-write + 0x0 + + + WDATA + WDATA + 0 + 16 + + + + + CHDATIN7R + CHDATIN7R + CHDATIN7R + 0xF0 + 0x20 + read-write + 0x0 + + + INDAT1 + INDAT1 + 16 + 16 + + + INDAT0 + INDAT0 + 0 + 16 + + + + + DFSDM0_CR1 + DFSDM0_CR1 + control register 1 + 0x100 + 0x20 + read-write + 0x00000000 + + + AWFSEL + Analog watchdog fast mode + select + 30 + 1 + + + FAST + Fast conversion mode selection for + regular conversions + 29 + 1 + + + RCH + Regular channel selection + 24 + 3 + + + RDMAEN + DMA channel enabled to read data for the + regular conversion + 21 + 1 + + + RSYNC + Launch regular conversion synchronously + with DFSDM0 + 19 + 1 + + + RCONT + Continuous mode selection for regular + conversions + 18 + 1 + + + RSWSTART + Software start of a conversion on the + regular channel + 17 + 1 + + + JEXTEN + Trigger enable and trigger edge + selection for injected conversions + 13 + 2 + + + JEXTSEL + Trigger signal selection for launching + injected conversions + 8 + 3 + + + JDMAEN + DMA channel enabled to read data for the + injected channel group + 5 + 1 + + + JSCAN + Scanning conversion mode for injected + conversions + 4 + 1 + + + JSYNC + Launch an injected conversion + synchronously with the DFSDM0 JSWSTART + trigger + 3 + 1 + + + JSWSTART + Start a conversion of the injected group + of channels + 1 + 1 + + + DFEN + DFSDM enable + 0 + 1 + + + + + DFSDM0_CR2 + DFSDM0_CR2 + control register 2 + 0x104 + 0x20 + read-write + 0x00000000 + + + AWDCH + Analog watchdog channel + selection + 16 + 8 + + + EXCH + Extremes detector channel + selection + 8 + 8 + + + CKABIE + Clock absence interrupt + enable + 6 + 1 + + + SCDIE + Short-circuit detector interrupt + enable + 5 + 1 + + + AWDIE + Analog watchdog interrupt + enable + 4 + 1 + + + ROVRIE + Regular data overrun interrupt + enable + 3 + 1 + + + JOVRIE + Injected data overrun interrupt + enable + 2 + 1 + + + REOCIE + Regular end of conversion interrupt + enable + 1 + 1 + + + JEOCIE + Injected end of conversion interrupt + enable + 0 + 1 + + + + + DFSDM0_ISR + DFSDM0_ISR + interrupt and status register + 0x108 + 0x20 + read-only + 0x00FF0000 + + + SCDF + short-circuit detector + flag + 24 + 8 + + + CKABF + Clock absence flag + 16 + 8 + + + RCIP + Regular conversion in progress + status + 14 + 1 + + + JCIP + Injected conversion in progress + status + 13 + 1 + + + AWDF + Analog watchdog + 4 + 1 + + + ROVRF + Regular conversion overrun + flag + 3 + 1 + + + JOVRF + Injected conversion overrun + flag + 2 + 1 + + + REOCF + End of regular conversion + flag + 1 + 1 + + + JEOCF + End of injected conversion + flag + 0 + 1 + + + + + DFSDM0_ICR + DFSDM0_ICR + interrupt flag clear register + 0x10C + 0x20 + read-write + 0x00000000 + + + CLRSCDF + Clear the short-circuit detector + flag + 24 + 8 + + + CLRCKABF + Clear the clock absence + flag + 16 + 8 + + + CLRROVRF + Clear the regular conversion overrun + flag + 3 + 1 + + + CLRJOVRF + Clear the injected conversion overrun + flag + 2 + 1 + + + + + DFSDM0_JCHGR + DFSDM0_JCHGR + injected channel group selection + register + 0x110 + 0x20 + read-write + 0x00000001 + + + JCHG + Injected channel group + selection + 0 + 8 + + + + + DFSDM0_FCR + DFSDM0_FCR + filter control register + 0x114 + 0x20 + read-write + 0x00000000 + + + FORD + Sinc filter order + 29 + 3 + + + FOSR + Sinc filter oversampling ratio + (decimation rate) + 16 + 10 + + + IOSR + Integrator oversampling ratio (averaging + length) + 0 + 8 + + + + + DFSDM0_JDATAR + DFSDM0_JDATAR + data register for injected + group + 0x118 + 0x20 + read-only + 0x00000000 + + + JDATA + Injected group conversion + data + 8 + 24 + + + JDATACH + Injected channel most recently + converted + 0 + 3 + + + + + DFSDM0_RDATAR + DFSDM0_RDATAR + data register for the regular + channel + 0x11C + 0x20 + read-only + 0x00000000 + + + RDATA + Regular channel conversion + data + 8 + 24 + + + RPEND + Regular channel pending + data + 4 + 1 + + + RDATACH + Regular channel most recently + converted + 0 + 3 + + + + + DFSDM0_AWHTR + DFSDM0_AWHTR + analog watchdog high threshold + register + 0x120 + 0x20 + read-write + 0x00000000 + + + AWHT + Analog watchdog high + threshold + 8 + 24 + + + BKAWH + Break signal assignment to analog + watchdog high threshold event + 0 + 4 + + + + + DFSDM0_AWLTR + DFSDM0_AWLTR + analog watchdog low threshold + register + 0x124 + 0x20 + read-write + 0x00000000 + + + AWLT + Analog watchdog low + threshold + 8 + 24 + + + BKAWL + Break signal assignment to analog + watchdog low threshold event + 0 + 4 + + + + + DFSDM0_AWSR + DFSDM0_AWSR + analog watchdog status + register + 0x128 + 0x20 + read-only + 0x00000000 + + + AWHTF + Analog watchdog high threshold + flag + 8 + 8 + + + AWLTF + Analog watchdog low threshold + flag + 0 + 8 + + + + + DFSDM0_AWCFR + DFSDM0_AWCFR + analog watchdog clear flag + register + 0x12C + 0x20 + read-write + 0x00000000 + + + CLRAWHTF + Clear the analog watchdog high threshold + flag + 8 + 8 + + + CLRAWLTF + Clear the analog watchdog low threshold + flag + 0 + 8 + + + + + DFSDM0_EXMAX + DFSDM0_EXMAX + Extremes detector maximum + register + 0x130 + 0x20 + read-only + 0x80000000 + + + EXMAX + Extremes detector maximum + value + 8 + 24 + + + EXMAXCH + Extremes detector maximum data + channel + 0 + 3 + + + + + DFSDM0_EXMIN + DFSDM0_EXMIN + Extremes detector minimum + register + 0x134 + 0x20 + read-only + 0x7FFFFF00 + + + EXMIN + EXMIN + 8 + 24 + + + EXMINCH + Extremes detector minimum data + channel + 0 + 3 + + + + + DFSDM0_CNVTIMR + DFSDM0_CNVTIMR + conversion timer register + 0x138 + 0x20 + read-only + 0x00000000 + + + CNVCNT + 28-bit timer counting conversion time t + = CNVCNT[27:0] / fDFSDM_CKIN + 4 + 28 + + + + + DFSDM1_CR1 + DFSDM1_CR1 + control register 1 + 0x200 + 0x20 + read-write + 0x00000000 + + + AWFSEL + Analog watchdog fast mode + select + 30 + 1 + + + FAST + Fast conversion mode selection for + regular conversions + 29 + 1 + + + RCH + Regular channel selection + 24 + 3 + + + RDMAEN + DMA channel enabled to read data for the + regular conversion + 21 + 1 + + + RSYNC + Launch regular conversion synchronously + with DFSDM0 + 19 + 1 + + + RCONT + Continuous mode selection for regular + conversions + 18 + 1 + + + RSWSTART + Software start of a conversion on the + regular channel + 17 + 1 + + + JEXTEN + Trigger enable and trigger edge + selection for injected conversions + 13 + 2 + + + JEXTSEL + Trigger signal selection for launching + injected conversions + 8 + 3 + + + JDMAEN + DMA channel enabled to read data for the + injected channel group + 5 + 1 + + + JSCAN + Scanning conversion mode for injected + conversions + 4 + 1 + + + JSYNC + Launch an injected conversion + synchronously with the DFSDM0 JSWSTART + trigger + 3 + 1 + + + JSWSTART + Start a conversion of the injected group + of channels + 1 + 1 + + + DFEN + DFSDM enable + 0 + 1 + + + + + DFSDM1_CR2 + DFSDM1_CR2 + control register 2 + 0x204 + 0x20 + read-write + 0x00000000 + + + AWDCH + Analog watchdog channel + selection + 16 + 8 + + + EXCH + Extremes detector channel + selection + 8 + 8 + + + CKABIE + Clock absence interrupt + enable + 6 + 1 + + + SCDIE + Short-circuit detector interrupt + enable + 5 + 1 + + + AWDIE + Analog watchdog interrupt + enable + 4 + 1 + + + ROVRIE + Regular data overrun interrupt + enable + 3 + 1 + + + JOVRIE + Injected data overrun interrupt + enable + 2 + 1 + + + REOCIE + Regular end of conversion interrupt + enable + 1 + 1 + + + JEOCIE + Injected end of conversion interrupt + enable + 0 + 1 + + + + + DFSDM1_ISR + DFSDM1_ISR + interrupt and status register + 0x208 + 0x20 + read-only + 0x00FF0000 + + + SCDF + short-circuit detector + flag + 24 + 8 + + + CKABF + Clock absence flag + 16 + 8 + + + RCIP + Regular conversion in progress + status + 14 + 1 + + + JCIP + Injected conversion in progress + status + 13 + 1 + + + AWDF + Analog watchdog + 4 + 1 + + + ROVRF + Regular conversion overrun + flag + 3 + 1 + + + JOVRF + Injected conversion overrun + flag + 2 + 1 + + + REOCF + End of regular conversion + flag + 1 + 1 + + + JEOCF + End of injected conversion + flag + 0 + 1 + + + + + DFSDM1_ICR + DFSDM1_ICR + interrupt flag clear register + 0x20C + 0x20 + read-write + 0x00000000 + + + CLRSCDF + Clear the short-circuit detector + flag + 24 + 8 + + + CLRCKABF + Clear the clock absence + flag + 16 + 8 + + + CLRROVRF + Clear the regular conversion overrun + flag + 3 + 1 + + + CLRJOVRF + Clear the injected conversion overrun + flag + 2 + 1 + + + + + DFSDM1_JCHGR + DFSDM1_JCHGR + injected channel group selection + register + 0x210 + 0x20 + read-write + 0x00000001 + + + JCHG + Injected channel group + selection + 0 + 8 + + + + + DFSDM1_FCR + DFSDM1_FCR + filter control register + 0x214 + 0x20 + read-write + 0x00000000 + + + FORD + Sinc filter order + 29 + 3 + + + FOSR + Sinc filter oversampling ratio + (decimation rate) + 16 + 10 + + + IOSR + Integrator oversampling ratio (averaging + length) + 0 + 8 + + + + + DFSDM1_JDATAR + DFSDM1_JDATAR + data register for injected + group + 0x218 + 0x20 + read-only + 0x00000000 + + + JDATA + Injected group conversion + data + 8 + 24 + + + JDATACH + Injected channel most recently + converted + 0 + 3 + + + + + DFSDM1_RDATAR + DFSDM1_RDATAR + data register for the regular + channel + 0x21C + 0x20 + read-only + 0x00000000 + + + RDATA + Regular channel conversion + data + 8 + 24 + + + RPEND + Regular channel pending + data + 4 + 1 + + + RDATACH + Regular channel most recently + converted + 0 + 3 + + + + + DFSDM1_AWHTR + DFSDM1_AWHTR + analog watchdog high threshold + register + 0x220 + 0x20 + read-write + 0x00000000 + + + AWHT + Analog watchdog high + threshold + 8 + 24 + + + BKAWH + Break signal assignment to analog + watchdog high threshold event + 0 + 4 + + + + + DFSDM1_AWLTR + DFSDM1_AWLTR + analog watchdog low threshold + register + 0x224 + 0x20 + read-write + 0x00000000 + + + AWLT + Analog watchdog low + threshold + 8 + 24 + + + BKAWL + Break signal assignment to analog + watchdog low threshold event + 0 + 4 + + + + + DFSDM1_AWSR + DFSDM1_AWSR + analog watchdog status + register + 0x228 + 0x20 + read-only + 0x00000000 + + + AWHTF + Analog watchdog high threshold + flag + 8 + 8 + + + AWLTF + Analog watchdog low threshold + flag + 0 + 8 + + + + + DFSDM1_AWCFR + DFSDM1_AWCFR + analog watchdog clear flag + register + 0x22C + 0x20 + read-write + 0x00000000 + + + CLRAWHTF + Clear the analog watchdog high threshold + flag + 8 + 8 + + + CLRAWLTF + Clear the analog watchdog low threshold + flag + 0 + 8 + + + + + DFSDM1_EXMAX + DFSDM1_EXMAX + Extremes detector maximum + register + 0x230 + 0x20 + read-only + 0x80000000 + + + EXMAX + Extremes detector maximum + value + 8 + 24 + + + EXMAXCH + Extremes detector maximum data + channel + 0 + 3 + + + + + DFSDM1_EXMIN + DFSDM1_EXMIN + Extremes detector minimum + register + 0x234 + 0x20 + read-only + 0x7FFFFF00 + + + EXMIN + EXMIN + 8 + 24 + + + EXMINCH + Extremes detector minimum data + channel + 0 + 3 + + + + + DFSDM1_CNVTIMR + DFSDM1_CNVTIMR + conversion timer register + 0x238 + 0x20 + read-only + 0x00000000 + + + CNVCNT + 28-bit timer counting conversion time t + = CNVCNT[27:0] / fDFSDM_CKIN + 4 + 28 + + + + + DFSDM2_CR1 + DFSDM2_CR1 + control register 1 + 0x300 + 0x20 + read-write + 0x00000000 + + + AWFSEL + Analog watchdog fast mode + select + 30 + 1 + + + FAST + Fast conversion mode selection for + regular conversions + 29 + 1 + + + RCH + Regular channel selection + 24 + 3 + + + RDMAEN + DMA channel enabled to read data for the + regular conversion + 21 + 1 + + + RSYNC + Launch regular conversion synchronously + with DFSDM0 + 19 + 1 + + + RCONT + Continuous mode selection for regular + conversions + 18 + 1 + + + RSWSTART + Software start of a conversion on the + regular channel + 17 + 1 + + + JEXTEN + Trigger enable and trigger edge + selection for injected conversions + 13 + 2 + + + JEXTSEL + Trigger signal selection for launching + injected conversions + 8 + 3 + + + JDMAEN + DMA channel enabled to read data for the + injected channel group + 5 + 1 + + + JSCAN + Scanning conversion mode for injected + conversions + 4 + 1 + + + JSYNC + Launch an injected conversion + synchronously with the DFSDM0 JSWSTART + trigger + 3 + 1 + + + JSWSTART + Start a conversion of the injected group + of channels + 1 + 1 + + + DFEN + DFSDM enable + 0 + 1 + + + + + DFSDM2_CR2 + DFSDM2_CR2 + control register 2 + 0x304 + 0x20 + read-write + 0x00000000 + + + AWDCH + Analog watchdog channel + selection + 16 + 8 + + + EXCH + Extremes detector channel + selection + 8 + 8 + + + CKABIE + Clock absence interrupt + enable + 6 + 1 + + + SCDIE + Short-circuit detector interrupt + enable + 5 + 1 + + + AWDIE + Analog watchdog interrupt + enable + 4 + 1 + + + ROVRIE + Regular data overrun interrupt + enable + 3 + 1 + + + JOVRIE + Injected data overrun interrupt + enable + 2 + 1 + + + REOCIE + Regular end of conversion interrupt + enable + 1 + 1 + + + JEOCIE + Injected end of conversion interrupt + enable + 0 + 1 + + + + + DFSDM2_ISR + DFSDM2_ISR + interrupt and status register + 0x308 + 0x20 + read-only + 0x00FF0000 + + + SCDF + short-circuit detector + flag + 24 + 8 + + + CKABF + Clock absence flag + 16 + 8 + + + RCIP + Regular conversion in progress + status + 14 + 1 + + + JCIP + Injected conversion in progress + status + 13 + 1 + + + AWDF + Analog watchdog + 4 + 1 + + + ROVRF + Regular conversion overrun + flag + 3 + 1 + + + JOVRF + Injected conversion overrun + flag + 2 + 1 + + + REOCF + End of regular conversion + flag + 1 + 1 + + + JEOCF + End of injected conversion + flag + 0 + 1 + + + + + DFSDM2_ICR + DFSDM2_ICR + interrupt flag clear register + 0x30C + 0x20 + read-write + 0x00000000 + + + CLRSCDF + Clear the short-circuit detector + flag + 24 + 8 + + + CLRCKABF + Clear the clock absence + flag + 16 + 8 + + + CLRROVRF + Clear the regular conversion overrun + flag + 3 + 1 + + + CLRJOVRF + Clear the injected conversion overrun + flag + 2 + 1 + + + + + DFSDM2_JCHGR + DFSDM2_JCHGR + injected channel group selection + register + 0x310 + 0x20 + read-write + 0x00000001 + + + JCHG + Injected channel group + selection + 0 + 8 + + + + + DFSDM2_FCR + DFSDM2_FCR + filter control register + 0x314 + 0x20 + read-write + 0x00000000 + + + FORD + Sinc filter order + 29 + 3 + + + FOSR + Sinc filter oversampling ratio + (decimation rate) + 16 + 10 + + + IOSR + Integrator oversampling ratio (averaging + length) + 0 + 8 + + + + + DFSDM2_JDATAR + DFSDM2_JDATAR + data register for injected + group + 0x318 + 0x20 + read-only + 0x00000000 + + + JDATA + Injected group conversion + data + 8 + 24 + + + JDATACH + Injected channel most recently + converted + 0 + 3 + + + + + DFSDM2_RDATAR + DFSDM2_RDATAR + data register for the regular + channel + 0x31C + 0x20 + read-only + 0x00000000 + + + RDATA + Regular channel conversion + data + 8 + 24 + + + RPEND + Regular channel pending + data + 4 + 1 + + + RDATACH + Regular channel most recently + converted + 0 + 3 + + + + + DFSDM2_AWHTR + DFSDM2_AWHTR + analog watchdog high threshold + register + 0x320 + 0x20 + read-write + 0x00000000 + + + AWHT + Analog watchdog high + threshold + 8 + 24 + + + BKAWH + Break signal assignment to analog + watchdog high threshold event + 0 + 4 + + + + + DFSDM2_AWLTR + DFSDM2_AWLTR + analog watchdog low threshold + register + 0x324 + 0x20 + read-write + 0x00000000 + + + AWLT + Analog watchdog low + threshold + 8 + 24 + + + BKAWL + Break signal assignment to analog + watchdog low threshold event + 0 + 4 + + + + + DFSDM2_AWSR + DFSDM2_AWSR + analog watchdog status + register + 0x328 + 0x20 + read-only + 0x00000000 + + + AWHTF + Analog watchdog high threshold + flag + 8 + 8 + + + AWLTF + Analog watchdog low threshold + flag + 0 + 8 + + + + + DFSDM2_AWCFR + DFSDM2_AWCFR + analog watchdog clear flag + register + 0x32C + 0x20 + read-write + 0x00000000 + + + CLRAWHTF + Clear the analog watchdog high threshold + flag + 8 + 8 + + + CLRAWLTF + Clear the analog watchdog low threshold + flag + 0 + 8 + + + + + DFSDM2_EXMAX + DFSDM2_EXMAX + Extremes detector maximum + register + 0x330 + 0x20 + read-only + 0x80000000 + + + EXMAX + Extremes detector maximum + value + 8 + 24 + + + EXMAXCH + Extremes detector maximum data + channel + 0 + 3 + + + + + DFSDM2_EXMIN + DFSDM2_EXMIN + Extremes detector minimum + register + 0x334 + 0x20 + read-only + 0x7FFFFF00 + + + EXMIN + EXMIN + 8 + 24 + + + EXMINCH + Extremes detector minimum data + channel + 0 + 3 + + + + + DFSDM2_CNVTIMR + DFSDM2_CNVTIMR + conversion timer register + 0x338 + 0x20 + read-only + 0x00000000 + + + CNVCNT + 28-bit timer counting conversion time t + = CNVCNT[27:0] / fDFSDM_CKIN + 4 + 28 + + + + + DFSDM3_CR1 + DFSDM3_CR1 + control register 1 + 0x400 + 0x20 + read-write + 0x00000000 + + + AWFSEL + Analog watchdog fast mode + select + 30 + 1 + + + FAST + Fast conversion mode selection for + regular conversions + 29 + 1 + + + RCH + Regular channel selection + 24 + 3 + + + RDMAEN + DMA channel enabled to read data for the + regular conversion + 21 + 1 + + + RSYNC + Launch regular conversion synchronously + with DFSDM0 + 19 + 1 + + + RCONT + Continuous mode selection for regular + conversions + 18 + 1 + + + RSWSTART + Software start of a conversion on the + regular channel + 17 + 1 + + + JEXTEN + Trigger enable and trigger edge + selection for injected conversions + 13 + 2 + + + JEXTSEL + Trigger signal selection for launching + injected conversions + 8 + 3 + + + JDMAEN + DMA channel enabled to read data for the + injected channel group + 5 + 1 + + + JSCAN + Scanning conversion mode for injected + conversions + 4 + 1 + + + JSYNC + Launch an injected conversion + synchronously with the DFSDM0 JSWSTART + trigger + 3 + 1 + + + JSWSTART + Start a conversion of the injected group + of channels + 1 + 1 + + + DFEN + DFSDM enable + 0 + 1 + + + + + DFSDM3_CR2 + DFSDM3_CR2 + control register 2 + 0x404 + 0x20 + read-write + 0x00000000 + + + AWDCH + Analog watchdog channel + selection + 16 + 8 + + + EXCH + Extremes detector channel + selection + 8 + 8 + + + CKABIE + Clock absence interrupt + enable + 6 + 1 + + + SCDIE + Short-circuit detector interrupt + enable + 5 + 1 + + + AWDIE + Analog watchdog interrupt + enable + 4 + 1 + + + ROVRIE + Regular data overrun interrupt + enable + 3 + 1 + + + JOVRIE + Injected data overrun interrupt + enable + 2 + 1 + + + REOCIE + Regular end of conversion interrupt + enable + 1 + 1 + + + JEOCIE + Injected end of conversion interrupt + enable + 0 + 1 + + + + + DFSDM3_ISR + DFSDM3_ISR + interrupt and status register + 0x408 + 0x20 + read-only + 0x00FF0000 + + + SCDF + short-circuit detector + flag + 24 + 8 + + + CKABF + Clock absence flag + 16 + 8 + + + RCIP + Regular conversion in progress + status + 14 + 1 + + + JCIP + Injected conversion in progress + status + 13 + 1 + + + AWDF + Analog watchdog + 4 + 1 + + + ROVRF + Regular conversion overrun + flag + 3 + 1 + + + JOVRF + Injected conversion overrun + flag + 2 + 1 + + + REOCF + End of regular conversion + flag + 1 + 1 + + + JEOCF + End of injected conversion + flag + 0 + 1 + + + + + DFSDM3_ICR + DFSDM3_ICR + interrupt flag clear register + 0x40C + 0x20 + read-write + 0x00000000 + + + CLRSCDF + Clear the short-circuit detector + flag + 24 + 8 + + + CLRCKABF + Clear the clock absence + flag + 16 + 8 + + + CLRROVRF + Clear the regular conversion overrun + flag + 3 + 1 + + + CLRJOVRF + Clear the injected conversion overrun + flag + 2 + 1 + + + + + DFSDM3_JCHGR + DFSDM3_JCHGR + injected channel group selection + register + 0x410 + 0x20 + read-write + 0x00000001 + + + JCHG + Injected channel group + selection + 0 + 8 + + + + + DFSDM3_FCR + DFSDM3_FCR + filter control register + 0x414 + 0x20 + read-write + 0x00000000 + + + FORD + Sinc filter order + 29 + 3 + + + FOSR + Sinc filter oversampling ratio + (decimation rate) + 16 + 10 + + + IOSR + Integrator oversampling ratio (averaging + length) + 0 + 8 + + + + + DFSDM3_JDATAR + DFSDM3_JDATAR + data register for injected + group + 0x418 + 0x20 + read-only + 0x00000000 + + + JDATA + Injected group conversion + data + 8 + 24 + + + JDATACH + Injected channel most recently + converted + 0 + 3 + + + + + DFSDM3_RDATAR + DFSDM3_RDATAR + data register for the regular + channel + 0x41C + 0x20 + read-only + 0x00000000 + + + RDATA + Regular channel conversion + data + 8 + 24 + + + RPEND + Regular channel pending + data + 4 + 1 + + + RDATACH + Regular channel most recently + converted + 0 + 3 + + + + + DFSDM3_AWHTR + DFSDM3_AWHTR + analog watchdog high threshold + register + 0x420 + 0x20 + read-write + 0x00000000 + + + AWHT + Analog watchdog high + threshold + 8 + 24 + + + BKAWH + Break signal assignment to analog + watchdog high threshold event + 0 + 4 + + + + + DFSDM3_AWLTR + DFSDM3_AWLTR + analog watchdog low threshold + register + 0x424 + 0x20 + read-write + 0x00000000 + + + AWLT + Analog watchdog low + threshold + 8 + 24 + + + BKAWL + Break signal assignment to analog + watchdog low threshold event + 0 + 4 + + + + + DFSDM3_AWSR + DFSDM3_AWSR + analog watchdog status + register + 0x428 + 0x20 + read-only + 0x00000000 + + + AWHTF + Analog watchdog high threshold + flag + 8 + 8 + + + AWLTF + Analog watchdog low threshold + flag + 0 + 8 + + + + + DFSDM3_AWCFR + DFSDM3_AWCFR + analog watchdog clear flag + register + 0x42C + 0x20 + read-write + 0x00000000 + + + CLRAWHTF + Clear the analog watchdog high threshold + flag + 8 + 8 + + + CLRAWLTF + Clear the analog watchdog low threshold + flag + 0 + 8 + + + + + DFSDM3_EXMAX + DFSDM3_EXMAX + Extremes detector maximum + register + 0x430 + 0x20 + read-only + 0x80000000 + + + EXMAX + Extremes detector maximum + value + 8 + 24 + + + EXMAXCH + Extremes detector maximum data + channel + 0 + 3 + + + + + DFSDM3_EXMIN + DFSDM3_EXMIN + Extremes detector minimum + register + 0x434 + 0x20 + read-only + 0x7FFFFF00 + + + EXMIN + EXMIN + 8 + 24 + + + EXMINCH + Extremes detector minimum data + channel + 0 + 3 + + + + + DFSDM3_CNVTIMR + DFSDM3_CNVTIMR + conversion timer register + 0x438 + 0x20 + read-only + 0x00000000 + + + CNVCNT + 28-bit timer counting conversion time t + = CNVCNT[27:0] / fDFSDM_CKIN + 4 + 28 + + + + + + + TIM8 + Advanced-timers + TIM + 0x40013400 + + 0x0 + 0x400 + registers + + + TIM8_BRK + TIM8 Break Interrupt + 43 + + + TIM8_BRK + TIM8 Break Interrupt + 43 + + + TIM8_BRK + TIM8 Break Interrupt + 43 + + + TIM8 + TIM8 Update Interrupt + 44 + + + TIM8 + TIM8 Update Interrupt + 44 + + + TIM8 + TIM8 Update Interrupt + 44 + + + TIM8_TRG_COM + TIM8 Trigger and Commutation + Interrupt + 45 + + + TIM8_TRG_COM + TIM8 Trigger and Commutation + Interrupt + 45 + + + TIM8_TRG_COM + TIM8 Trigger and Commutation + Interrupt + 45 + + + TIM8_CC + TIM8 Capture Compare Interrupt + 46 + + + TIM8_CC + TIM8 Capture Compare Interrupt + 46 + + + TIM8_CC + TIM8 Capture Compare Interrupt + 46 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + CKD + Clock division + 8 + 2 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + CMS + Center-aligned mode + selection + 5 + 2 + + + DIR + Direction + 4 + 1 + + + OPM + One-pulse mode + 3 + 1 + + + URS + Update request source + 2 + 1 + + + UDIS + Update disable + 1 + 1 + + + CEN + Counter enable + 0 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + OIS4 + Output Idle state 4 + 14 + 1 + + + OIS3N + Output Idle state 3 + 13 + 1 + + + OIS3 + Output Idle state 3 + 12 + 1 + + + OIS2N + Output Idle state 2 + 11 + 1 + + + OIS2 + Output Idle state 2 + 10 + 1 + + + OIS1N + Output Idle state 1 + 9 + 1 + + + OIS1 + Output Idle state 1 + 8 + 1 + + + TI1S + TI1 selection + 7 + 1 + + + MMS + Master mode selection + 4 + 3 + + + CCDS + Capture/compare DMA + selection + 3 + 1 + + + CCUS + Capture/compare control update + selection + 2 + 1 + + + CCPC + Capture/compare preloaded + control + 0 + 1 + + + + + SMCR + SMCR + slave mode control register + 0x8 + 0x20 + read-write + 0x0000 + + + ETP + External trigger polarity + 15 + 1 + + + ECE + External clock enable + 14 + 1 + + + ETPS + External trigger prescaler + 12 + 2 + + + ETF + External trigger filter + 8 + 4 + + + MSM + Master/Slave mode + 7 + 1 + + + TS + Trigger selection + 4 + 3 + + + SMS + Slave mode selection + 0 + 3 + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + TDE + Trigger DMA request enable + 14 + 1 + + + COMDE + COM DMA request enable + 13 + 1 + + + CC4DE + Capture/Compare 4 DMA request + enable + 12 + 1 + + + CC3DE + Capture/Compare 3 DMA request + enable + 11 + 1 + + + CC2DE + Capture/Compare 2 DMA request + enable + 10 + 1 + + + CC1DE + Capture/Compare 1 DMA request + enable + 9 + 1 + + + UDE + Update DMA request enable + 8 + 1 + + + TIE + Trigger interrupt enable + 6 + 1 + + + CC4IE + Capture/Compare 4 interrupt + enable + 4 + 1 + + + CC3IE + Capture/Compare 3 interrupt + enable + 3 + 1 + + + CC2IE + Capture/Compare 2 interrupt + enable + 2 + 1 + + + CC1IE + Capture/Compare 1 interrupt + enable + 1 + 1 + + + UIE + Update interrupt enable + 0 + 1 + + + BIE + Break interrupt enable + 7 + 1 + + + COMIE + COM interrupt enable + 5 + 1 + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x0000 + + + CC4OF + Capture/Compare 4 overcapture + flag + 12 + 1 + + + CC3OF + Capture/Compare 3 overcapture + flag + 11 + 1 + + + CC2OF + Capture/compare 2 overcapture + flag + 10 + 1 + + + CC1OF + Capture/Compare 1 overcapture + flag + 9 + 1 + + + BIF + Break interrupt flag + 7 + 1 + + + TIF + Trigger interrupt flag + 6 + 1 + + + COMIF + COM interrupt flag + 5 + 1 + + + CC4IF + Capture/Compare 4 interrupt + flag + 4 + 1 + + + CC3IF + Capture/Compare 3 interrupt + flag + 3 + 1 + + + CC2IF + Capture/Compare 2 interrupt + flag + 2 + 1 + + + CC1IF + Capture/compare 1 interrupt + flag + 1 + 1 + + + UIF + Update interrupt flag + 0 + 1 + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x0000 + + + BG + Break generation + 7 + 1 + + + TG + Trigger generation + 6 + 1 + + + COMG + Capture/Compare control update + generation + 5 + 1 + + + CC4G + Capture/compare 4 + generation + 4 + 1 + + + CC3G + Capture/compare 3 + generation + 3 + 1 + + + CC2G + Capture/compare 2 + generation + 2 + 1 + + + CC1G + Capture/compare 1 + generation + 1 + 1 + + + UG + Update generation + 0 + 1 + + + + + CCMR1_Output + CCMR1_Output + capture/compare mode register 1 (output + mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + OC2CE + Output Compare 2 clear + enable + 15 + 1 + + + OC2M + Output Compare 2 mode + 12 + 3 + + + OC2PE + Output Compare 2 preload + enable + 11 + 1 + + + OC2FE + Output Compare 2 fast + enable + 10 + 1 + + + CC2S + Capture/Compare 2 + selection + 8 + 2 + + + OC1CE + Output Compare 1 clear + enable + 7 + 1 + + + OC1M + Output Compare 1 mode + 4 + 3 + + + OC1PE + Output Compare 1 preload + enable + 3 + 1 + + + OC1FE + Output Compare 1 fast + enable + 2 + 1 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + CCMR1_Input + CCMR1_Input + capture/compare mode register 1 (input + mode) + CCMR1_Output + 0x18 + 0x20 + read-write + 0x00000000 + + + IC2F + Input capture 2 filter + 12 + 4 + + + IC2PCS + Input capture 2 prescaler + 10 + 2 + + + CC2S + Capture/Compare 2 + selection + 8 + 2 + + + IC1F + Input capture 1 filter + 4 + 4 + + + ICPCS + Input capture 1 prescaler + 2 + 2 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + CCMR2_Output + CCMR2_Output + capture/compare mode register 2 (output + mode) + 0x1C + 0x20 + read-write + 0x00000000 + + + OC4CE + Output compare 4 clear + enable + 15 + 1 + + + OC4M + Output compare 4 mode + 12 + 3 + + + OC4PE + Output compare 4 preload + enable + 11 + 1 + + + OC4FE + Output compare 4 fast + enable + 10 + 1 + + + CC4S + Capture/Compare 4 + selection + 8 + 2 + + + OC3CE + Output compare 3 clear + enable + 7 + 1 + + + OC3M + Output compare 3 mode + 4 + 3 + + + OC3PE + Output compare 3 preload + enable + 3 + 1 + + + OC3FE + Output compare 3 fast + enable + 2 + 1 + + + CC3S + Capture/Compare 3 + selection + 0 + 2 + + + + + CCMR2_Input + CCMR2_Input + capture/compare mode register 2 (input + mode) + CCMR2_Output + 0x1C + 0x20 + read-write + 0x00000000 + + + IC4F + Input capture 4 filter + 12 + 4 + + + IC4PSC + Input capture 4 prescaler + 10 + 2 + + + CC4S + Capture/Compare 4 + selection + 8 + 2 + + + IC3F + Input capture 3 filter + 4 + 4 + + + IC3PSC + Input capture 3 prescaler + 2 + 2 + + + CC3S + Capture/compare 3 + selection + 0 + 2 + + + + + CCER + CCER + capture/compare enable + register + 0x20 + 0x20 + read-write + 0x0000 + + + CC4P + Capture/Compare 3 output + Polarity + 13 + 1 + + + CC4E + Capture/Compare 4 output + enable + 12 + 1 + + + CC3NP + Capture/Compare 3 output + Polarity + 11 + 1 + + + CC3NE + Capture/Compare 3 complementary output + enable + 10 + 1 + + + CC3P + Capture/Compare 3 output + Polarity + 9 + 1 + + + CC3E + Capture/Compare 3 output + enable + 8 + 1 + + + CC2NP + Capture/Compare 2 output + Polarity + 7 + 1 + + + CC2NE + Capture/Compare 2 complementary output + enable + 6 + 1 + + + CC2P + Capture/Compare 2 output + Polarity + 5 + 1 + + + CC2E + Capture/Compare 2 output + enable + 4 + 1 + + + CC1NP + Capture/Compare 1 output + Polarity + 3 + 1 + + + CC1NE + Capture/Compare 1 complementary output + enable + 2 + 1 + + + CC1P + Capture/Compare 1 output + Polarity + 1 + 1 + + + CC1E + Capture/Compare 1 output + enable + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + read-write + 0x00000000 + + + CNT + counter value + 0 + 16 + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x0000 + + + PSC + Prescaler value + 0 + 16 + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x00000000 + + + ARR + Auto-reload value + 0 + 16 + + + + + RCR + RCR + repetition counter register + 0x30 + 0x20 + read-write + 0x0000 + + + REP + Repetition counter value + 0 + 8 + + + + + CCR1 + CCR1 + capture/compare register 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR1 + Capture/Compare 1 value + 0 + 16 + + + + + CCR2 + CCR2 + capture/compare register 2 + 0x38 + 0x20 + read-write + 0x00000000 + + + CCR2 + Capture/Compare 2 value + 0 + 16 + + + + + CCR3 + CCR3 + capture/compare register 3 + 0x3C + 0x20 + read-write + 0x00000000 + + + CCR3 + Capture/Compare value + 0 + 16 + + + + + CCR4 + CCR4 + capture/compare register 4 + 0x40 + 0x20 + read-write + 0x00000000 + + + CCR4 + Capture/Compare value + 0 + 16 + + + + + BDTR + BDTR + break and dead-time register + 0x44 + 0x20 + read-write + 0x0000 + + + MOE + Main output enable + 15 + 1 + + + AOE + Automatic output enable + 14 + 1 + + + BKP + Break polarity + 13 + 1 + + + BKE + Break enable + 12 + 1 + + + OSSR + Off-state selection for Run + mode + 11 + 1 + + + OSSI + Off-state selection for Idle + mode + 10 + 1 + + + LOCK + Lock configuration + 8 + 2 + + + DTG + Dead-time generator setup + 0 + 8 + + + + + DCR + DCR + DMA control register + 0x48 + 0x20 + read-write + 0x0000 + + + DBL + DMA burst length + 8 + 5 + + + DBA + DMA base address + 0 + 5 + + + + + DMAR + DMAR + DMA address for full transfer + 0x4C + 0x20 + read-write + 0x0000 + + + DMAB + DMA register for burst + accesses + 0 + 16 + + + + + OR1 + OR1 + DMA address for full transfer + 0x50 + 0x20 + read-write + 0x0000 + + + ETR_ADC2_RMP + External trigger remap on ADC2 analog + watchdog + 0 + 2 + + + ETR_ADC3_RMP + External trigger remap on ADC3 analog + watchdog + 2 + 2 + + + TI1_RMP + Input Capture 1 remap + 4 + 1 + + + + + CCMR3_Output + CCMR3_Output + capture/compare mode register 2 (output + mode) + 0x54 + 0x20 + read-write + 0x00000000 + + + OC6M_bit3 + Output Compare 6 mode bit + 3 + 24 + 1 + + + OC5M_bit3 + Output Compare 5 mode bit + 3 + 16 + 3 + + + OC6CE + Output compare 6 clear + enable + 15 + 1 + + + OC6M + Output compare 6 mode + 12 + 3 + + + OC6PE + Output compare 6 preload + enable + 11 + 1 + + + OC6FE + Output compare 6 fast + enable + 10 + 1 + + + OC5CE + Output compare 5 clear + enable + 7 + 1 + + + OC5M + Output compare 5 mode + 4 + 3 + + + OC5PE + Output compare 5 preload + enable + 3 + 1 + + + OC5FE + Output compare 5 fast + enable + 2 + 1 + + + + + CCR5 + CCR5 + capture/compare register 4 + 0x58 + 0x20 + read-write + 0x00000000 + + + CCR5 + Capture/Compare value + 0 + 16 + + + GC5C1 + Group Channel 5 and Channel + 1 + 29 + 1 + + + GC5C2 + Group Channel 5 and Channel + 2 + 30 + 1 + + + GC5C3 + Group Channel 5 and Channel + 3 + 31 + 1 + + + + + CCR6 + CCR6 + capture/compare register 4 + 0x5C + 0x20 + read-write + 0x00000000 + + + CCR6 + Capture/Compare value + 0 + 16 + + + + + OR2 + OR2 + DMA address for full transfer + 0x60 + 0x20 + read-write + 0x00000001 + + + BKINE + BRK BKIN input enable + 0 + 1 + + + BKCMP1E + BRK COMP1 enable + 1 + 1 + + + BKCMP2E + BRK COMP2 enable + 2 + 1 + + + BKDFBK2E + BRK DFSDM_BREAK2 enable + 8 + 1 + + + BKINP + BRK BKIN input polarity + 9 + 1 + + + BKCMP1P + BRK COMP1 input polarity + 10 + 1 + + + BKCMP2P + BRK COMP2 input polarity + 11 + 1 + + + ETRSEL + ETR source selection + 14 + 3 + + + + + OR3 + OR3 + DMA address for full transfer + 0x64 + 0x20 + read-write + 0x00000001 + + + BK2INE + BRK2 BKIN input enable + 0 + 1 + + + BK2CMP1E + BRK2 COMP1 enable + 1 + 1 + + + BK2CMP2E + BRK2 COMP2 enable + 2 + 1 + + + BK2DFBK3E + BRK2 DFSDM_BREAK3 enable + 8 + 1 + + + BK2INP + BRK2 BKIN input polarity + 9 + 1 + + + BK2CMP1P + BRK2 COMP1 input polarity + 10 + 1 + + + BK2CMP2P + BRK2 COMP2 input polarity + 11 + 1 + + + + + + + RCC + Reset and clock control + RCC + 0x40021000 + + 0x0 + 0x400 + registers + + + RCC + RCC global interrupt + 5 + + + RCC + RCC global interrupt + 5 + + + RCC + RCC global interrupt + 5 + + + RCC + RCC global interrupt + 5 + + + + CR + CR + Clock control register + 0x0 + 0x20 + 0x00000063 + + + PLLSAI2RDY + SAI2 PLL clock ready flag + 29 + 1 + read-only + + + PLLSAI2ON + SAI2 PLL enable + 28 + 1 + read-write + + + PLLSAI1RDY + SAI1 PLL clock ready flag + 27 + 1 + read-only + + + PLLSAI1ON + SAI1 PLL enable + 26 + 1 + read-write + + + PLLRDY + Main PLL clock ready flag + 25 + 1 + read-only + + + PLLON + Main PLL enable + 24 + 1 + read-write + + + CSSON + Clock security system + enable + 19 + 1 + write-only + + + HSEBYP + HSE crystal oscillator + bypass + 18 + 1 + read-write + + + HSERDY + HSE clock ready flag + 17 + 1 + read-only + + + HSEON + HSE clock enable + 16 + 1 + read-write + + + HSIASFS + HSI automatic start from + Stop + 11 + 1 + read-write + + + HSIRDY + HSI clock ready flag + 10 + 1 + read-only + + + HSIKERON + HSI always enable for peripheral + kernels + 9 + 1 + read-write + + + HSION + HSI clock enable + 8 + 1 + read-write + + + MSIRANGE + MSI clock ranges + 4 + 4 + read-write + + + MSIRGSEL + MSI clock range selection + 3 + 1 + write-only + + + MSIPLLEN + MSI clock PLL enable + 2 + 1 + read-write + + + MSIRDY + MSI clock ready flag + 1 + 1 + read-only + + + MSION + MSI clock enable + 0 + 1 + read-write + + + + + ICSCR + ICSCR + Internal clock sources calibration + register + 0x4 + 0x20 + 0x10000000 + + + HSITRIM + HSI clock trimming + 24 + 5 + read-write + + + HSICAL + HSI clock calibration + 16 + 8 + read-only + + + MSITRIM + MSI clock trimming + 8 + 8 + read-write + + + MSICAL + MSI clock calibration + 0 + 8 + read-only + + + + + CFGR + CFGR + Clock configuration register + 0x8 + 0x20 + 0x00000000 + + + MCOPRE + Microcontroller clock output + prescaler + 28 + 3 + read-only + + + MCOSEL + Microcontroller clock + output + 24 + 3 + read-write + + + STOPWUCK + Wakeup from Stop and CSS backup clock + selection + 15 + 1 + read-write + + + PPRE2 + APB high-speed prescaler + (APB2) + 11 + 3 + read-write + + + PPRE1 + PB low-speed prescaler + (APB1) + 8 + 3 + read-write + + + HPRE + AHB prescaler + 4 + 4 + read-write + + + SWS + System clock switch status + 2 + 2 + read-only + + + SW + System clock switch + 0 + 2 + read-write + + + + + PLLCFGR + PLLCFGR + PLL configuration register + 0xC + 0x20 + read-write + 0x00001000 + + + PLLR + Main PLL division factor for PLLCLK + (system clock) + 25 + 2 + + + PLLREN + Main PLL PLLCLK output + enable + 24 + 1 + + + PLLQ + Main PLL division factor for + PLLUSB1CLK(48 MHz clock) + 21 + 2 + + + PLLQEN + Main PLL PLLUSB1CLK output + enable + 20 + 1 + + + PLLP + Main PLL division factor for PLLSAI3CLK + (SAI1 and SAI2 clock) + 17 + 1 + + + PLLPEN + Main PLL PLLSAI3CLK output + enable + 16 + 1 + + + PLLN + Main PLL multiplication factor for + VCO + 8 + 7 + + + PLLM + Division factor for the main PLL and + audio PLL (PLLSAI1 and PLLSAI2) input + clock + 4 + 3 + + + PLLSRC + Main PLL, PLLSAI1 and PLLSAI2 entry + clock source + 0 + 2 + + + + + PLLSAI1CFGR + PLLSAI1CFGR + PLLSAI1 configuration register + 0x10 + 0x20 + read-write + 0x00001000 + + + PLLSAI1R + PLLSAI1 division factor for PLLADC1CLK + (ADC clock) + 25 + 2 + + + PLLSAI1REN + PLLSAI1 PLLADC1CLK output + enable + 24 + 1 + + + PLLSAI1Q + SAI1PLL division factor for PLLUSB2CLK + (48 MHz clock) + 21 + 2 + + + PLLSAI1QEN + SAI1PLL PLLUSB2CLK output + enable + 20 + 1 + + + PLLSAI1P + SAI1PLL division factor for PLLSAI1CLK + (SAI1 or SAI2 clock) + 17 + 1 + + + PLLSAI1PEN + SAI1PLL PLLSAI1CLK output + enable + 16 + 1 + + + PLLSAI1N + SAI1PLL multiplication factor for + VCO + 8 + 7 + + + + + PLLSAI2CFGR + PLLSAI2CFGR + PLLSAI2 configuration register + 0x14 + 0x20 + read-write + 0x00001000 + + + PLLSAI2R + PLLSAI2 division factor for PLLADC2CLK + (ADC clock) + 25 + 2 + + + PLLSAI2REN + PLLSAI2 PLLADC2CLK output + enable + 24 + 1 + + + PLLSAI2P + SAI1PLL division factor for PLLSAI2CLK + (SAI1 or SAI2 clock) + 17 + 1 + + + PLLSAI2PEN + SAI2PLL PLLSAI2CLK output + enable + 16 + 1 + + + PLLSAI2N + SAI2PLL multiplication factor for + VCO + 8 + 7 + + + + + CIER + CIER + Clock interrupt enable + register + 0x18 + 0x20 + read-write + 0x00000000 + + + LSECSSIE + LSE clock security system interrupt + enable + 9 + 1 + + + PLLSAI2RDYIE + PLLSAI2 ready interrupt + enable + 7 + 1 + + + PLLSAI1RDYIE + PLLSAI1 ready interrupt + enable + 6 + 1 + + + PLLRDYIE + PLL ready interrupt enable + 5 + 1 + + + HSERDYIE + HSE ready interrupt enable + 4 + 1 + + + HSIRDYIE + HSI ready interrupt enable + 3 + 1 + + + MSIRDYIE + MSI ready interrupt enable + 2 + 1 + + + LSERDYIE + LSE ready interrupt enable + 1 + 1 + + + LSIRDYIE + LSI ready interrupt enable + 0 + 1 + + + + + CIFR + CIFR + Clock interrupt flag register + 0x1C + 0x20 + read-only + 0x00000000 + + + LSECSSF + LSE Clock security system interrupt + flag + 9 + 1 + + + CSSF + Clock security system interrupt + flag + 8 + 1 + + + PLLSAI2RDYF + PLLSAI2 ready interrupt + flag + 7 + 1 + + + PLLSAI1RDYF + PLLSAI1 ready interrupt + flag + 6 + 1 + + + PLLRDYF + PLL ready interrupt flag + 5 + 1 + + + HSERDYF + HSE ready interrupt flag + 4 + 1 + + + HSIRDYF + HSI ready interrupt flag + 3 + 1 + + + MSIRDYF + MSI ready interrupt flag + 2 + 1 + + + LSERDYF + LSE ready interrupt flag + 1 + 1 + + + LSIRDYF + LSI ready interrupt flag + 0 + 1 + + + + + CICR + CICR + Clock interrupt clear register + 0x20 + 0x20 + write-only + 0x00000000 + + + LSECSSC + LSE Clock security system interrupt + clear + 9 + 1 + + + CSSC + Clock security system interrupt + clear + 8 + 1 + + + PLLSAI2RDYC + PLLSAI2 ready interrupt + clear + 7 + 1 + + + PLLSAI1RDYC + PLLSAI1 ready interrupt + clear + 6 + 1 + + + PLLRDYC + PLL ready interrupt clear + 5 + 1 + + + HSERDYC + HSE ready interrupt clear + 4 + 1 + + + HSIRDYC + HSI ready interrupt clear + 3 + 1 + + + MSIRDYC + MSI ready interrupt clear + 2 + 1 + + + LSERDYC + LSE ready interrupt clear + 1 + 1 + + + LSIRDYC + LSI ready interrupt clear + 0 + 1 + + + + + AHB1RSTR + AHB1RSTR + AHB1 peripheral reset register + 0x28 + 0x20 + read-write + 0x00000000 + + + TSCRST + Touch Sensing Controller + reset + 16 + 1 + + + CRCRST + CRC reset + 11 + 1 + + + FLASHRST + Flash memory interface + reset + 8 + 1 + + + DMA2RST + DMA2 reset + 1 + 1 + + + DMA1RST + DMA1 reset + 0 + 1 + + + + + AHB2RSTR + AHB2RSTR + AHB2 peripheral reset register + 0x2C + 0x20 + read-write + 0x00000000 + + + RNGRST + Random number generator + reset + 18 + 1 + + + AESRST + AES hardware accelerator + reset + 16 + 1 + + + ADCRST + ADC reset + 13 + 1 + + + OTGFSRST + USB OTG FS reset + 12 + 1 + + + GPIOHRST + IO port H reset + 7 + 1 + + + GPIOGRST + IO port G reset + 6 + 1 + + + GPIOFRST + IO port F reset + 5 + 1 + + + GPIOERST + IO port E reset + 4 + 1 + + + GPIODRST + IO port D reset + 3 + 1 + + + GPIOCRST + IO port C reset + 2 + 1 + + + GPIOBRST + IO port B reset + 1 + 1 + + + GPIOARST + IO port A reset + 0 + 1 + + + + + AHB3RSTR + AHB3RSTR + AHB3 peripheral reset register + 0x30 + 0x20 + read-write + 0x00000000 + + + QSPIRST + Quad SPI memory interface + reset + 8 + 1 + + + FMCRST + Flexible memory controller + reset + 0 + 1 + + + + + APB1RSTR1 + APB1RSTR1 + APB1 peripheral reset register + 1 + 0x38 + 0x20 + read-write + 0x00000000 + + + LPTIM1RST + Low Power Timer 1 reset + 31 + 1 + + + OPAMPRST + OPAMP interface reset + 30 + 1 + + + DAC1RST + DAC1 interface reset + 29 + 1 + + + PWRRST + Power interface reset + 28 + 1 + + + CAN1RST + CAN1 reset + 25 + 1 + + + I2C3RST + I2C3 reset + 23 + 1 + + + I2C2RST + I2C2 reset + 22 + 1 + + + I2C1RST + I2C1 reset + 21 + 1 + + + UART5RST + UART5 reset + 20 + 1 + + + UART4RST + UART4 reset + 19 + 1 + + + USART3RST + USART3 reset + 18 + 1 + + + USART2RST + USART2 reset + 17 + 1 + + + SPI3RST + SPI3 reset + 15 + 1 + + + SPI2RST + SPI2 reset + 14 + 1 + + + LCDRST + LCD interface reset + 9 + 1 + + + TIM7RST + TIM7 timer reset + 5 + 1 + + + TIM6RST + TIM6 timer reset + 4 + 1 + + + TIM5RST + TIM5 timer reset + 3 + 1 + + + TIM4RST + TIM3 timer reset + 2 + 1 + + + TIM3RST + TIM3 timer reset + 1 + 1 + + + TIM2RST + TIM2 timer reset + 0 + 1 + + + + + APB1RSTR2 + APB1RSTR2 + APB1 peripheral reset register + 2 + 0x3C + 0x20 + read-write + 0x00000000 + + + LPTIM2RST + Low-power timer 2 reset + 5 + 1 + + + SWPMI1RST + Single wire protocol reset + 2 + 1 + + + LPUART1RST + Low-power UART 1 reset + 0 + 1 + + + + + APB2RSTR + APB2RSTR + APB2 peripheral reset register + 0x40 + 0x20 + read-write + 0x00000000 + + + DFSDMRST + Digital filters for sigma-delata + modulators (DFSDM) reset + 24 + 1 + + + SAI2RST + Serial audio interface 2 (SAI2) + reset + 22 + 1 + + + SAI1RST + Serial audio interface 1 (SAI1) + reset + 21 + 1 + + + TIM17RST + TIM17 timer reset + 18 + 1 + + + TIM16RST + TIM16 timer reset + 17 + 1 + + + TIM15RST + TIM15 timer reset + 16 + 1 + + + USART1RST + USART1 reset + 14 + 1 + + + TIM8RST + TIM8 timer reset + 13 + 1 + + + SPI1RST + SPI1 reset + 12 + 1 + + + TIM1RST + TIM1 timer reset + 11 + 1 + + + SDMMCRST + SDMMC reset + 10 + 1 + + + SYSCFGRST + System configuration (SYSCFG) + reset + 0 + 1 + + + + + AHB1ENR + AHB1ENR + AHB1 peripheral clock enable + register + 0x48 + 0x20 + read-write + 0x00000100 + + + TSCEN + Touch Sensing Controller clock + enable + 16 + 1 + + + CRCEN + CRC clock enable + 11 + 1 + + + FLASHEN + Flash memory interface clock + enable + 8 + 1 + + + DMA2EN + DMA2 clock enable + 1 + 1 + + + DMA1EN + DMA1 clock enable + 0 + 1 + + + + + AHB2ENR + AHB2ENR + AHB2 peripheral clock enable + register + 0x4C + 0x20 + read-write + 0x00000000 + + + RNGEN + Random Number Generator clock + enable + 18 + 1 + + + AESEN + AES accelerator clock + enable + 16 + 1 + + + ADCEN + ADC clock enable + 13 + 1 + + + OTGFSEN + OTG full speed clock + enable + 12 + 1 + + + GPIOHEN + IO port H clock enable + 7 + 1 + + + GPIOGEN + IO port G clock enable + 6 + 1 + + + GPIOFEN + IO port F clock enable + 5 + 1 + + + GPIOEEN + IO port E clock enable + 4 + 1 + + + GPIODEN + IO port D clock enable + 3 + 1 + + + GPIOCEN + IO port C clock enable + 2 + 1 + + + GPIOBEN + IO port B clock enable + 1 + 1 + + + GPIOAEN + IO port A clock enable + 0 + 1 + + + + + AHB3ENR + AHB3ENR + AHB3 peripheral clock enable + register + 0x50 + 0x20 + read-write + 0x00000000 + + + QSPIEN + QSPIEN + 8 + 1 + + + FMCEN + Flexible memory controller clock + enable + 0 + 1 + + + + + APB1ENR1 + APB1ENR1 + APB1ENR1 + 0x58 + 0x20 + read-write + 0x00000000 + + + LPTIM1EN + Low power timer 1 clock + enable + 31 + 1 + + + OPAMPEN + OPAMP interface clock + enable + 30 + 1 + + + DAC1EN + DAC1 interface clock + enable + 29 + 1 + + + PWREN + Power interface clock + enable + 28 + 1 + + + CAN1EN + CAN1 clock enable + 25 + 1 + + + I2C3EN + I2C3 clock enable + 23 + 1 + + + I2C2EN + I2C2 clock enable + 22 + 1 + + + I2C1EN + I2C1 clock enable + 21 + 1 + + + UART5EN + UART5 clock enable + 20 + 1 + + + UART4EN + UART4 clock enable + 19 + 1 + + + USART3EN + USART3 clock enable + 18 + 1 + + + USART2EN + USART2 clock enable + 17 + 1 + + + SP3EN + SPI3 clock enable + 15 + 1 + + + SPI2EN + SPI2 clock enable + 14 + 1 + + + WWDGEN + Window watchdog clock + enable + 11 + 1 + + + LCDEN + LCD clock enable + 9 + 1 + + + TIM7EN + TIM7 timer clock enable + 5 + 1 + + + TIM6EN + TIM6 timer clock enable + 4 + 1 + + + TIM5EN + TIM5 timer clock enable + 3 + 1 + + + TIM4EN + TIM4 timer clock enable + 2 + 1 + + + TIM3EN + TIM3 timer clock enable + 1 + 1 + + + TIM2EN + TIM2 timer clock enable + 0 + 1 + + + + + APB1ENR2 + APB1ENR2 + APB1 peripheral clock enable register + 2 + 0x5C + 0x20 + read-write + 0x00000000 + + + LPTIM2EN + LPTIM2EN + 5 + 1 + + + SWPMI1EN + Single wire protocol clock + enable + 2 + 1 + + + LPUART1EN + Low power UART 1 clock + enable + 0 + 1 + + + + + APB2ENR + APB2ENR + APB2ENR + 0x60 + 0x20 + read-write + 0x00000000 + + + DFSDMEN + DFSDM timer clock enable + 24 + 1 + + + SAI2EN + SAI2 clock enable + 22 + 1 + + + SAI1EN + SAI1 clock enable + 21 + 1 + + + TIM17EN + TIM17 timer clock enable + 18 + 1 + + + TIM16EN + TIM16 timer clock enable + 17 + 1 + + + TIM15EN + TIM15 timer clock enable + 16 + 1 + + + USART1EN + USART1clock enable + 14 + 1 + + + TIM8EN + TIM8 timer clock enable + 13 + 1 + + + SPI1EN + SPI1 clock enable + 12 + 1 + + + TIM1EN + TIM1 timer clock enable + 11 + 1 + + + SDMMCEN + SDMMC clock enable + 10 + 1 + + + FIREWALLEN + Firewall clock enable + 7 + 1 + + + SYSCFGEN + SYSCFG clock enable + 0 + 1 + + + + + AHB1SMENR + AHB1SMENR + AHB1 peripheral clocks enable in Sleep and + Stop modes register + 0x68 + 0x20 + read-write + 0x00011303 + + + TSCSMEN + Touch Sensing Controller clocks enable + during Sleep and Stop modes + 16 + 1 + + + CRCSMEN + CRCSMEN + 11 + 1 + + + SRAM1SMEN + SRAM1 interface clocks enable during + Sleep and Stop modes + 9 + 1 + + + FLASHSMEN + Flash memory interface clocks enable + during Sleep and Stop modes + 8 + 1 + + + DMA2SMEN + DMA2 clocks enable during Sleep and Stop + modes + 1 + 1 + + + DMA1SMEN + DMA1 clocks enable during Sleep and Stop + modes + 0 + 1 + + + + + AHB2SMENR + AHB2SMENR + AHB2 peripheral clocks enable in Sleep and + Stop modes register + 0x6C + 0x20 + read-write + 0x000532FF + + + RNGSMEN + Random Number Generator clocks enable + during Sleep and Stop modes + 18 + 1 + + + AESSMEN + AES accelerator clocks enable during + Sleep and Stop modes + 16 + 1 + + + ADCFSSMEN + ADC clocks enable during Sleep and Stop + modes + 13 + 1 + + + OTGFSSMEN + OTG full speed clocks enable during + Sleep and Stop modes + 12 + 1 + + + SRAM2SMEN + SRAM2 interface clocks enable during + Sleep and Stop modes + 9 + 1 + + + GPIOHSMEN + IO port H clocks enable during Sleep and + Stop modes + 7 + 1 + + + GPIOGSMEN + IO port G clocks enable during Sleep and + Stop modes + 6 + 1 + + + GPIOFSMEN + IO port F clocks enable during Sleep and + Stop modes + 5 + 1 + + + GPIOESMEN + IO port E clocks enable during Sleep and + Stop modes + 4 + 1 + + + GPIODSMEN + IO port D clocks enable during Sleep and + Stop modes + 3 + 1 + + + GPIOCSMEN + IO port C clocks enable during Sleep and + Stop modes + 2 + 1 + + + GPIOBSMEN + IO port B clocks enable during Sleep and + Stop modes + 1 + 1 + + + GPIOASMEN + IO port A clocks enable during Sleep and + Stop modes + 0 + 1 + + + + + AHB3SMENR + AHB3SMENR + AHB3 peripheral clocks enable in Sleep and + Stop modes register + 0x70 + 0x20 + read-write + 0x000000101 + + + QSPISMEN + QSPISMEN + 8 + 1 + + + FMCSMEN + Flexible memory controller clocks enable + during Sleep and Stop modes + 0 + 1 + + + + + APB1SMENR1 + APB1SMENR1 + APB1SMENR1 + 0x78 + 0x20 + read-write + 0xF2FECA3F + + + LPTIM1SMEN + Low power timer 1 clocks enable during + Sleep and Stop modes + 31 + 1 + + + OPAMPSMEN + OPAMP interface clocks enable during + Sleep and Stop modes + 30 + 1 + + + DAC1SMEN + DAC1 interface clocks enable during + Sleep and Stop modes + 29 + 1 + + + PWRSMEN + Power interface clocks enable during + Sleep and Stop modes + 28 + 1 + + + CAN1SMEN + CAN1 clocks enable during Sleep and Stop + modes + 25 + 1 + + + I2C3SMEN + I2C3 clocks enable during Sleep and Stop + modes + 23 + 1 + + + I2C2SMEN + I2C2 clocks enable during Sleep and Stop + modes + 22 + 1 + + + I2C1SMEN + I2C1 clocks enable during Sleep and Stop + modes + 21 + 1 + + + UART5SMEN + UART5 clocks enable during Sleep and + Stop modes + 20 + 1 + + + UART4SMEN + UART4 clocks enable during Sleep and + Stop modes + 19 + 1 + + + USART3SMEN + USART3 clocks enable during Sleep and + Stop modes + 18 + 1 + + + USART2SMEN + USART2 clocks enable during Sleep and + Stop modes + 17 + 1 + + + SP3SMEN + SPI3 clocks enable during Sleep and Stop + modes + 15 + 1 + + + SPI2SMEN + SPI2 clocks enable during Sleep and Stop + modes + 14 + 1 + + + WWDGSMEN + Window watchdog clocks enable during + Sleep and Stop modes + 11 + 1 + + + LCDSMEN + LCD clocks enable during Sleep and Stop + modes + 9 + 1 + + + TIM7SMEN + TIM7 timer clocks enable during Sleep + and Stop modes + 5 + 1 + + + TIM6SMEN + TIM6 timer clocks enable during Sleep + and Stop modes + 4 + 1 + + + TIM5SMEN + TIM5 timer clocks enable during Sleep + and Stop modes + 3 + 1 + + + TIM4SMEN + TIM4 timer clocks enable during Sleep + and Stop modes + 2 + 1 + + + TIM3SMEN + TIM3 timer clocks enable during Sleep + and Stop modes + 1 + 1 + + + TIM2SMEN + TIM2 timer clocks enable during Sleep + and Stop modes + 0 + 1 + + + + + APB1SMENR2 + APB1SMENR2 + APB1 peripheral clocks enable in Sleep and + Stop modes register 2 + 0x7C + 0x20 + read-write + 0x000000025 + + + LPTIM2SMEN + LPTIM2SMEN + 5 + 1 + + + SWPMI1SMEN + Single wire protocol clocks enable + during Sleep and Stop modes + 2 + 1 + + + LPUART1SMEN + Low power UART 1 clocks enable during + Sleep and Stop modes + 0 + 1 + + + + + APB2SMENR + APB2SMENR + APB2SMENR + 0x80 + 0x20 + read-write + 0x01677C01 + + + DFSDMSMEN + DFSDM timer clocks enable during Sleep + and Stop modes + 24 + 1 + + + SAI2SMEN + SAI2 clocks enable during Sleep and Stop + modes + 22 + 1 + + + SAI1SMEN + SAI1 clocks enable during Sleep and Stop + modes + 21 + 1 + + + TIM17SMEN + TIM17 timer clocks enable during Sleep + and Stop modes + 18 + 1 + + + TIM16SMEN + TIM16 timer clocks enable during Sleep + and Stop modes + 17 + 1 + + + TIM15SMEN + TIM15 timer clocks enable during Sleep + and Stop modes + 16 + 1 + + + USART1SMEN + USART1clocks enable during Sleep and + Stop modes + 14 + 1 + + + TIM8SMEN + TIM8 timer clocks enable during Sleep + and Stop modes + 13 + 1 + + + SPI1SMEN + SPI1 clocks enable during Sleep and Stop + modes + 12 + 1 + + + TIM1SMEN + TIM1 timer clocks enable during Sleep + and Stop modes + 11 + 1 + + + SDMMCSMEN + SDMMC clocks enable during Sleep and + Stop modes + 10 + 1 + + + SYSCFGSMEN + SYSCFG clocks enable during Sleep and + Stop modes + 0 + 1 + + + + + CCIPR + CCIPR + CCIPR + 0x88 + 0x20 + read-write + 0x00000000 + + + DFSDMSEL + DFSDM clock source + selection + 31 + 1 + + + SWPMI1SEL + SWPMI1 clock source + selection + 30 + 1 + + + ADCSEL + ADCs clock source + selection + 28 + 2 + + + CLK48SEL + 48 MHz clock source + selection + 26 + 2 + + + SAI2SEL + SAI2 clock source + selection + 24 + 2 + + + SAI1SEL + SAI1 clock source + selection + 22 + 2 + + + LPTIM2SEL + Low power timer 2 clock source + selection + 20 + 2 + + + LPTIM1SEL + Low power timer 1 clock source + selection + 18 + 2 + + + I2C3SEL + I2C3 clock source + selection + 16 + 2 + + + I2C2SEL + I2C2 clock source + selection + 14 + 2 + + + I2C1SEL + I2C1 clock source + selection + 12 + 2 + + + LPUART1SEL + LPUART1 clock source + selection + 10 + 2 + + + UART5SEL + UART5 clock source + selection + 8 + 2 + + + UART4SEL + UART4 clock source + selection + 6 + 2 + + + USART3SEL + USART3 clock source + selection + 4 + 2 + + + USART2SEL + USART2 clock source + selection + 2 + 2 + + + USART1SEL + USART1 clock source + selection + 0 + 2 + + + + + BDCR + BDCR + BDCR + 0x90 + 0x20 + 0x00000000 + + + LSCOSEL + Low speed clock output + selection + 25 + 1 + read-write + + + LSCOEN + Low speed clock output + enable + 24 + 1 + read-write + + + BDRST + Backup domain software + reset + 16 + 1 + read-write + + + RTCEN + RTC clock enable + 15 + 1 + read-write + + + RTCSEL + RTC clock source selection + 8 + 2 + read-write + + + LSECSSD + LSECSSD + 6 + 1 + read-only + + + LSECSSON + LSECSSON + 5 + 1 + read-write + + + LSEDRV + SE oscillator drive + capability + 3 + 2 + read-write + + + LSEBYP + LSE oscillator bypass + 2 + 1 + read-write + + + LSERDY + LSE oscillator ready + 1 + 1 + read-only + + + LSEON + LSE oscillator enable + 0 + 1 + read-write + + + + + CSR + CSR + CSR + 0x94 + 0x20 + 0x0C000600 + + + LPWRSTF + Low-power reset flag + 31 + 1 + read-only + + + WWDGRSTF + Window watchdog reset flag + 30 + 1 + read-only + + + IWDGRSTF + Independent window watchdog reset + flag + 29 + 1 + read-only + + + SFTRSTF + Software reset flag + 28 + 1 + read-only + + + BORRSTF + BOR flag + 27 + 1 + read-only + + + PINRSTF + Pin reset flag + 26 + 1 + read-only + + + OBLRSTF + Option byte loader reset + flag + 25 + 1 + read-only + + + FIREWALLRSTF + Firewall reset flag + 24 + 1 + read-only + + + RMVF + Remove reset flag + 23 + 1 + read-write + + + MSISRANGE + SI range after Standby + mode + 8 + 4 + read-write + + + LSIRDY + LSI oscillator ready + 1 + 1 + read-only + + + LSION + LSI oscillator enable + 0 + 1 + read-write + + + + + + + ADC123_Common + Analog-to-Digital Converter + ADC + 0x50040300 + + 0x0 + 0x11 + registers + + + + CSR + CSR + ADC Common status register + 0x0 + 0x20 + read-only + 0x00000000 + + + ADDRDY_MST + ADDRDY_MST + 0 + 1 + + + EOSMP_MST + EOSMP_MST + 1 + 1 + + + EOC_MST + EOC_MST + 2 + 1 + + + EOS_MST + EOS_MST + 3 + 1 + + + OVR_MST + OVR_MST + 4 + 1 + + + JEOC_MST + JEOC_MST + 5 + 1 + + + JEOS_MST + JEOS_MST + 6 + 1 + + + AWD1_MST + AWD1_MST + 7 + 1 + + + AWD2_MST + AWD2_MST + 8 + 1 + + + AWD3_MST + AWD3_MST + 9 + 1 + + + JQOVF_MST + JQOVF_MST + 10 + 1 + + + ADRDY_SLV + ADRDY_SLV + 16 + 1 + + + EOSMP_SLV + EOSMP_SLV + 17 + 1 + + + EOC_SLV + End of regular conversion of the slave + ADC + 18 + 1 + + + EOS_SLV + End of regular sequence flag of the + slave ADC + 19 + 1 + + + OVR_SLV + Overrun flag of the slave + ADC + 20 + 1 + + + JEOC_SLV + End of injected conversion flag of the + slave ADC + 21 + 1 + + + JEOS_SLV + End of injected sequence flag of the + slave ADC + 22 + 1 + + + AWD1_SLV + Analog watchdog 1 flag of the slave + ADC + 23 + 1 + + + AWD2_SLV + Analog watchdog 2 flag of the slave + ADC + 24 + 1 + + + AWD3_SLV + Analog watchdog 3 flag of the slave + ADC + 25 + 1 + + + JQOVF_SLV + Injected Context Queue Overflow flag of + the slave ADC + 26 + 1 + + + + + CCR + CCR + ADC common control register + 0x8 + 0x20 + read-write + 0x00000000 + + + MULT + Multi ADC mode selection + 0 + 5 + + + DELAY + Delay between 2 sampling + phases + 8 + 4 + + + DMACFG + DMA configuration (for multi-ADC + mode) + 13 + 1 + + + MDMA + Direct memory access mode for multi ADC + mode + 14 + 2 + + + CKMODE + ADC clock mode + 16 + 2 + + + VREFEN + VREFINT enable + 22 + 1 + + + TSEN + Temperature sensor enable + 23 + 1 + + + VBATEN + VBAT enable + 24 + 1 + + + + + CDR + CDR + ADC common regular data register for dual + and triple modes + 0xC + 0x20 + read-only + 0x00000000 + + + RDATA_SLV + Regular data of the slave + ADC + 16 + 16 + + + RDATA_MST + Regular data of the master + ADC + 0 + 16 + + + + + + + DBGMCU + Debug support + DBGMCU + 0xE0042000 + + 0x0 + 0x400 + registers + + + + IDCODE + IDCODE + MCU Device ID Code Register + 0x0 + 0x20 + read-only + 0x0 + + + DEV_ID + Device Identifier + 0 + 16 + + + REV_ID + Revision Identifier + 16 + 16 + + + + + CR + CR + Debug MCU Configuration + Register + 0x4 + 0x20 + read-write + 0x0 + + + DBG_SLEEP + Debug Sleep Mode + 0 + 1 + + + DBG_STOP + Debug Stop Mode + 1 + 1 + + + DBG_STANDBY + Debug Standby Mode + 2 + 1 + + + TRACE_IOEN + Trace pin assignment + control + 5 + 1 + + + TRACE_MODE + Trace pin assignment + control + 6 + 2 + + + + + APB1_FZR1 + APB1_FZR1 + APB Low Freeze Register 1 + 0x8 + 0x20 + read-write + 0x0 + + + DBG_TIMER2_STOP + Debug Timer 2 stopped when Core is + halted + 0 + 1 + + + DBG_TIM3_STOP + TIM3 counter stopped when core is + halted + 1 + 1 + + + DBG_TIM4_STOP + TIM4 counter stopped when core is + halted + 2 + 1 + + + DBG_TIM5_STOP + TIM5 counter stopped when core is + halted + 3 + 1 + + + DBG_TIMER6_STOP + Debug Timer 6 stopped when Core is + halted + 4 + 1 + + + DBG_TIM7_STOP + TIM7 counter stopped when core is + halted + 5 + 1 + + + DBG_RTC_STOP + Debug RTC stopped when Core is + halted + 10 + 1 + + + DBG_WWDG_STOP + Debug Window Wachdog stopped when Core + is halted + 11 + 1 + + + DBG_IWDG_STOP + Debug Independent Wachdog stopped when + Core is halted + 12 + 1 + + + DBG_I2C1_STOP + I2C1 SMBUS timeout mode stopped when + core is halted + 21 + 1 + + + DBG_I2C2_STOP + I2C2 SMBUS timeout mode stopped when + core is halted + 22 + 1 + + + DBG_I2C3_STOP + I2C3 SMBUS timeout counter stopped when + core is halted + 23 + 1 + + + DBG_CAN_STOP + bxCAN stopped when core is + halted + 25 + 1 + + + DBG_LPTIMER_STOP + LPTIM1 counter stopped when core is + halted + 31 + 1 + + + + + APB1_FZR2 + APB1_FZR2 + APB Low Freeze Register 2 + 0xC + 0x20 + read-write + 0x0 + + + DBG_LPTIM2_STOP + LPTIM2 counter stopped when core is + halted + 5 + 1 + + + + + APB2_FZR + APB2_FZR + APB High Freeze Register + 0x10 + 0x20 + read-write + 0x0 + + + DBG_TIM1_STOP + TIM1 counter stopped when core is + halted + 11 + 1 + + + DBG_TIM8_STOP + TIM8 counter stopped when core is + halted + 13 + 1 + + + DBG_TIM15_STOP + TIM15 counter stopped when core is + halted + 16 + 1 + + + DBG_TIM16_STOP + TIM16 counter stopped when core is + halted + 17 + 1 + + + DBG_TIM17_STOP + TIM17 counter stopped when core is + halted + 18 + 1 + + + + + + + FPU + Floting point unit + FPU + 0xE000EF34 + + 0x0 + 0xD + registers + + + FPU + Floating point interrupt + 81 + + + + FPCCR + FPCCR + Floating-point context control + register + 0x0 + 0x20 + read-write + 0x00000000 + + + LSPACT + LSPACT + 0 + 1 + + + USER + USER + 1 + 1 + + + THREAD + THREAD + 3 + 1 + + + HFRDY + HFRDY + 4 + 1 + + + MMRDY + MMRDY + 5 + 1 + + + BFRDY + BFRDY + 6 + 1 + + + MONRDY + MONRDY + 8 + 1 + + + LSPEN + LSPEN + 30 + 1 + + + ASPEN + ASPEN + 31 + 1 + + + + + FPCAR + FPCAR + Floating-point context address + register + 0x4 + 0x20 + read-write + 0x00000000 + + + ADDRESS + Location of unpopulated + floating-point + 3 + 29 + + + + + FPSCR + FPSCR + Floating-point status control + register + 0x8 + 0x20 + read-write + 0x00000000 + + + IOC + Invalid operation cumulative exception + bit + 0 + 1 + + + DZC + Division by zero cumulative exception + bit. + 1 + 1 + + + OFC + Overflow cumulative exception + bit + 2 + 1 + + + UFC + Underflow cumulative exception + bit + 3 + 1 + + + IXC + Inexact cumulative exception + bit + 4 + 1 + + + IDC + Input denormal cumulative exception + bit. + 7 + 1 + + + RMode + Rounding Mode control + field + 22 + 2 + + + FZ + Flush-to-zero mode control + bit: + 24 + 1 + + + DN + Default NaN mode control + bit + 25 + 1 + + + AHP + Alternative half-precision control + bit + 26 + 1 + + + V + Overflow condition code + flag + 28 + 1 + + + C + Carry condition code flag + 29 + 1 + + + Z + Zero condition code flag + 30 + 1 + + + N + Negative condition code + flag + 31 + 1 + + + + + + + MPU + Memory protection unit + MPU + 0xE000ED90 + + 0x0 + 0x15 + registers + + + + MPU_TYPER + MPU_TYPER + MPU type register + 0x0 + 0x20 + read-only + 0X00000800 + + + SEPARATE + Separate flag + 0 + 1 + + + DREGION + Number of MPU data regions + 8 + 8 + + + IREGION + Number of MPU instruction + regions + 16 + 8 + + + + + MPU_CTRL + MPU_CTRL + MPU control register + 0x4 + 0x20 + read-only + 0X00000000 + + + ENABLE + Enables the MPU + 0 + 1 + + + HFNMIENA + Enables the operation of MPU during hard + fault + 1 + 1 + + + PRIVDEFENA + Enable priviliged software access to + default memory map + 2 + 1 + + + + + MPU_RNR + MPU_RNR + MPU region number register + 0x8 + 0x20 + read-write + 0X00000000 + + + REGION + MPU region + 0 + 8 + + + + + MPU_RBAR + MPU_RBAR + MPU region base address + register + 0xC + 0x20 + read-write + 0X00000000 + + + REGION + MPU region field + 0 + 4 + + + VALID + MPU region number valid + 4 + 1 + + + ADDR + Region base address field + 5 + 27 + + + + + MPU_RASR + MPU_RASR + MPU region attribute and size + register + 0x10 + 0x20 + read-write + 0X00000000 + + + ENABLE + Region enable bit. + 0 + 1 + + + SIZE + Size of the MPU protection + region + 1 + 5 + + + SRD + Subregion disable bits + 8 + 8 + + + B + memory attribute + 16 + 1 + + + C + memory attribute + 17 + 1 + + + S + Shareable memory attribute + 18 + 1 + + + TEX + memory attribute + 19 + 3 + + + AP + Access permission + 24 + 3 + + + XN + Instruction access disable + bit + 28 + 1 + + + + + + + STK + SysTick timer + STK + 0xE000E010 + + 0x0 + 0x11 + registers + + + + CTRL + CTRL + SysTick control and status + register + 0x0 + 0x20 + read-write + 0X00000000 + + + ENABLE + Counter enable + 0 + 1 + + + TICKINT + SysTick exception request + enable + 1 + 1 + + + CLKSOURCE + Clock source selection + 2 + 1 + + + COUNTFLAG + COUNTFLAG + 16 + 1 + + + + + LOAD + LOAD + SysTick reload value register + 0x4 + 0x20 + read-write + 0X00000000 + + + RELOAD + RELOAD value + 0 + 24 + + + + + VAL + VAL + SysTick current value register + 0x8 + 0x20 + read-write + 0X00000000 + + + CURRENT + Current counter value + 0 + 24 + + + + + CALIB + CALIB + SysTick calibration value + register + 0xC + 0x20 + read-write + 0X00000000 + + + TENMS + Calibration value + 0 + 24 + + + SKEW + SKEW flag: Indicates whether the TENMS + value is exact + 30 + 1 + + + NOREF + NOREF flag. Reads as zero + 31 + 1 + + + + + + + SCB + System control block + SCB + 0xE000ED00 + + 0x0 + 0x41 + registers + + + + CPUID + CPUID + CPUID base register + 0x0 + 0x20 + read-only + 0x410FC241 + + + Revision + Revision number + 0 + 4 + + + PartNo + Part number of the + processor + 4 + 12 + + + Constant + Reads as 0xF + 16 + 4 + + + Variant + Variant number + 20 + 4 + + + Implementer + Implementer code + 24 + 8 + + + + + ICSR + ICSR + Interrupt control and state + register + 0x4 + 0x20 + read-write + 0x00000000 + + + VECTACTIVE + Active vector + 0 + 9 + + + RETTOBASE + Return to base level + 11 + 1 + + + VECTPENDING + Pending vector + 12 + 7 + + + ISRPENDING + Interrupt pending flag + 22 + 1 + + + PENDSTCLR + SysTick exception clear-pending + bit + 25 + 1 + + + PENDSTSET + SysTick exception set-pending + bit + 26 + 1 + + + PENDSVCLR + PendSV clear-pending bit + 27 + 1 + + + PENDSVSET + PendSV set-pending bit + 28 + 1 + + + NMIPENDSET + NMI set-pending bit. + 31 + 1 + + + + + VTOR + VTOR + Vector table offset register + 0x8 + 0x20 + read-write + 0x00000000 + + + TBLOFF + Vector table base offset + field + 9 + 21 + + + + + AIRCR + AIRCR + Application interrupt and reset control + register + 0xC + 0x20 + read-write + 0x00000000 + + + VECTRESET + VECTRESET + 0 + 1 + + + VECTCLRACTIVE + VECTCLRACTIVE + 1 + 1 + + + SYSRESETREQ + SYSRESETREQ + 2 + 1 + + + PRIGROUP + PRIGROUP + 8 + 3 + + + ENDIANESS + ENDIANESS + 15 + 1 + + + VECTKEYSTAT + Register key + 16 + 16 + + + + + SCR + SCR + System control register + 0x10 + 0x20 + read-write + 0x00000000 + + + SLEEPONEXIT + SLEEPONEXIT + 1 + 1 + + + SLEEPDEEP + SLEEPDEEP + 2 + 1 + + + SEVEONPEND + Send Event on Pending bit + 4 + 1 + + + + + CCR + CCR + Configuration and control + register + 0x14 + 0x20 + read-write + 0x00000000 + + + NONBASETHRDENA + Configures how the processor enters + Thread mode + 0 + 1 + + + USERSETMPEND + USERSETMPEND + 1 + 1 + + + UNALIGN__TRP + UNALIGN_ TRP + 3 + 1 + + + DIV_0_TRP + DIV_0_TRP + 4 + 1 + + + BFHFNMIGN + BFHFNMIGN + 8 + 1 + + + STKALIGN + STKALIGN + 9 + 1 + + + + + SHPR1 + SHPR1 + System handler priority + registers + 0x18 + 0x20 + read-write + 0x00000000 + + + PRI_4 + Priority of system handler + 4 + 0 + 8 + + + PRI_5 + Priority of system handler + 5 + 8 + 8 + + + PRI_6 + Priority of system handler + 6 + 16 + 8 + + + + + SHPR2 + SHPR2 + System handler priority + registers + 0x1C + 0x20 + read-write + 0x00000000 + + + PRI_11 + Priority of system handler + 11 + 24 + 8 + + + + + SHPR3 + SHPR3 + System handler priority + registers + 0x20 + 0x20 + read-write + 0x00000000 + + + PRI_14 + Priority of system handler + 14 + 16 + 8 + + + PRI_15 + Priority of system handler + 15 + 24 + 8 + + + + + SHCRS + SHCRS + System handler control and state + register + 0x24 + 0x20 + read-write + 0x00000000 + + + MEMFAULTACT + Memory management fault exception active + bit + 0 + 1 + + + BUSFAULTACT + Bus fault exception active + bit + 1 + 1 + + + USGFAULTACT + Usage fault exception active + bit + 3 + 1 + + + SVCALLACT + SVC call active bit + 7 + 1 + + + MONITORACT + Debug monitor active bit + 8 + 1 + + + PENDSVACT + PendSV exception active + bit + 10 + 1 + + + SYSTICKACT + SysTick exception active + bit + 11 + 1 + + + USGFAULTPENDED + Usage fault exception pending + bit + 12 + 1 + + + MEMFAULTPENDED + Memory management fault exception + pending bit + 13 + 1 + + + BUSFAULTPENDED + Bus fault exception pending + bit + 14 + 1 + + + SVCALLPENDED + SVC call pending bit + 15 + 1 + + + MEMFAULTENA + Memory management fault enable + bit + 16 + 1 + + + BUSFAULTENA + Bus fault enable bit + 17 + 1 + + + USGFAULTENA + Usage fault enable bit + 18 + 1 + + + + + CFSR_UFSR_BFSR_MMFSR + CFSR_UFSR_BFSR_MMFSR + Configurable fault status + register + 0x28 + 0x20 + read-write + 0x00000000 + + + IACCVIOL + Instruction access violation + flag + 1 + 1 + + + MUNSTKERR + Memory manager fault on unstacking for a + return from exception + 3 + 1 + + + MSTKERR + Memory manager fault on stacking for + exception entry. + 4 + 1 + + + MLSPERR + MLSPERR + 5 + 1 + + + MMARVALID + Memory Management Fault Address Register + (MMAR) valid flag + 7 + 1 + + + IBUSERR + Instruction bus error + 8 + 1 + + + PRECISERR + Precise data bus error + 9 + 1 + + + IMPRECISERR + Imprecise data bus error + 10 + 1 + + + UNSTKERR + Bus fault on unstacking for a return + from exception + 11 + 1 + + + STKERR + Bus fault on stacking for exception + entry + 12 + 1 + + + LSPERR + Bus fault on floating-point lazy state + preservation + 13 + 1 + + + BFARVALID + Bus Fault Address Register (BFAR) valid + flag + 15 + 1 + + + UNDEFINSTR + Undefined instruction usage + fault + 16 + 1 + + + INVSTATE + Invalid state usage fault + 17 + 1 + + + INVPC + Invalid PC load usage + fault + 18 + 1 + + + NOCP + No coprocessor usage + fault. + 19 + 1 + + + UNALIGNED + Unaligned access usage + fault + 24 + 1 + + + DIVBYZERO + Divide by zero usage fault + 25 + 1 + + + + + HFSR + HFSR + Hard fault status register + 0x2C + 0x20 + read-write + 0x00000000 + + + VECTTBL + Vector table hard fault + 1 + 1 + + + FORCED + Forced hard fault + 30 + 1 + + + DEBUG_VT + Reserved for Debug use + 31 + 1 + + + + + MMFAR + MMFAR + Memory management fault address + register + 0x34 + 0x20 + read-write + 0x00000000 + + + MMFAR + Memory management fault + address + 0 + 32 + + + + + BFAR + BFAR + Bus fault address register + 0x38 + 0x20 + read-write + 0x00000000 + + + BFAR + Bus fault address + 0 + 32 + + + + + AFSR + AFSR + Auxiliary fault status + register + 0x3C + 0x20 + read-write + 0x00000000 + + + IMPDEF + Implementation defined + 0 + 32 + + + + + + + NVIC_STIR + Nested vectored interrupt + controller + NVIC + 0xE000EF00 + + 0x0 + 0x5 + registers + + + + STIR + STIR + Software trigger interrupt + register + 0x0 + 0x20 + read-write + 0x00000000 + + + INTID + Software generated interrupt + ID + 0 + 9 + + + + + + + FPU_CPACR + Floating point unit CPACR + FPU + 0xE000ED88 + + 0x0 + 0x5 + registers + + + + CPACR + CPACR + Coprocessor access control + register + 0x0 + 0x20 + read-write + 0x0000000 + + + CP + CP + 20 + 4 + + + + + + + SCB_ACTRL + System control block ACTLR + SCB + 0xE000E008 + + 0x0 + 0x5 + registers + + + + ACTRL + ACTRL + Auxiliary control register + 0x0 + 0x20 + read-write + 0x00000000 + + + DISMCYCINT + DISMCYCINT + 0 + 1 + + + DISDEFWBUF + DISDEFWBUF + 1 + 1 + + + DISFOLD + DISFOLD + 2 + 1 + + + DISFPCA + DISFPCA + 8 + 1 + + + DISOOFP + DISOOFP + 9 + 1 + + + + + + + diff --git a/minimal_async_basic/l2/Cargo.toml b/minimal_async_basic/l2/Cargo.toml new file mode 100644 index 0000000..628c9cf --- /dev/null +++ b/minimal_async_basic/l2/Cargo.toml @@ -0,0 +1,15 @@ +[package] +name = "l2" +version = "0.1.0" +authors = ["Niket Naidu "] +edition = "2021" +readme = "README.md" + +# See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html + +[dependencies] +l0 = { path = "../l0" } + +# Add libraries here +bitflags = "1.3.2" +heapless = "0.7.16" diff --git a/minimal_async_basic/l2/src/cooperative/async_mutex.rs b/minimal_async_basic/l2/src/cooperative/async_mutex.rs new file mode 100644 index 0000000..2f9b4e7 --- /dev/null +++ b/minimal_async_basic/l2/src/cooperative/async_mutex.rs @@ -0,0 +1,90 @@ +use core::cell::{RefCell, RefMut}; + +use crate::wait_and_return; + +pub struct AsyncMutex { + data: RefCell, +} + +impl AsyncMutex { + pub const fn new(data: T) -> Self { + Self { + data: RefCell::new(data), + } + } + + #[must_use] + pub async fn lock(&self) -> AsyncScopedMutex { + let data = wait_and_return(|| { + let result = self.data.try_borrow_mut(); + match result { + Ok(data) => (Some(data), true), + Err(_) => (None, false), + } + }) + .await; + AsyncScopedMutex { data } + } +} + +pub struct AsyncScopedMutex<'a, T> { + data: RefMut<'a, T>, +} + +impl<'a, T> AsyncScopedMutex<'a, T> { + pub fn action(self, cb: impl Fn(RefMut)) { + cb(self.data) + } +} + +#[cfg(test)] +mod tests { + use crate::{block_on, join_tasks, sleep_via_wait, AsyncMutex, AsyncTask}; + use core::pin::pin; + use core::time::Duration; + + #[test] + fn async_mutex_nowait_test() { + let shared_data = AsyncMutex::new(0_u32); + + let async_addition = async { + shared_data.lock().await.action(|mut data| { + *data += 2; + }); + }; + + block_on(async_addition); + assert_eq!(shared_data.data.take(), 2); + } + + #[test] + fn async_mutex_wait_test() { + let shared_data = AsyncMutex::new(0_u32); + + let async_addition1 = async { + let sd = shared_data.lock().await; + sleep_via_wait(Duration::from_secs(1)).await; + sd.action(|mut data| { + *data += 2; + }); + }; + + let async_addition2 = async { + shared_data.lock().await.action(|mut data| { + *data += 2; + }); + }; + + block_on(async { + let async_addition1 = pin!(async_addition1); + let async_addition2 = pin!(async_addition2); + join_tasks([ + AsyncTask::new(async_addition1), + AsyncTask::new(async_addition2), + ]) + .await; + }); + + assert_eq!(shared_data.data.take(), 4); + } +} diff --git a/minimal_async_basic/l2/src/cooperative/async_task.rs b/minimal_async_basic/l2/src/cooperative/async_task.rs new file mode 100644 index 0000000..f8f9622 --- /dev/null +++ b/minimal_async_basic/l2/src/cooperative/async_task.rs @@ -0,0 +1,103 @@ +use core::{ + future::Future, + pin::Pin, + ptr, + task::{Context, Poll, RawWaker, Waker}, +}; + +use super::VTABLE; + +// Async Task that does not have any Waker support +// The only way to resolve the future is to keep polling +pub struct AsyncTask<'a> { + future: Pin<&'a mut dyn Future>, + ready: bool, +} + +impl<'a> AsyncTask<'a> { + pub fn new(future: Pin<&'a mut dyn Future>) -> Self { + Self { + future, + ready: false, + } + } + + fn poll(&mut self) { + // Waker constructed inplace with no AtomicBool to indicate wakeup + let waker = unsafe { Waker::from_raw(RawWaker::new(ptr::null(), &VTABLE)) }; + let mut context = Context::from_waker(&waker); + self.ready = self.future.as_mut().poll(&mut context).is_ready(); + } +} + +// Join async tasks so that they can run concurrently +pub fn join_tasks<'a, const N: usize>(tasks: [AsyncTask<'a>; N]) -> impl Future + 'a { + Join { tasks } +} + +struct Join<'a, const N: usize> { + tasks: [AsyncTask<'a>; N], +} + +impl<'a, const N: usize> Future for Join<'a, N> { + type Output = (); + fn poll(mut self: Pin<&mut Self>, _: &mut Context<'_>) -> Poll { + let pending_tasks = self + .tasks + .iter_mut() + // Filter by tasks that are pending (we do not want to poll ready tasks) + .filter(|t| !t.ready) + // Poll the tasks that are pending + .map(|t| { + t.poll(); + t.ready + }) + // Filter and count the tasks that are still pending + .filter(|ready| !ready) + .count(); + + if pending_tasks == 0 { + Poll::Ready(()) + } else { + Poll::Pending + } + } +} + +#[cfg(test)] +mod tests { + use super::*; + use crate::block_on; + use crate::wait; + use core::cell::Cell; + use core::pin::pin; + + #[test] + fn join_task_test() { + let success = Cell::new(false); + + let f1 = pin!(async { + println!("F1: Started"); + wait(|| success.get()).await; + println!("F1: Ended"); + }); + + let f2 = pin!(async { + println!("F2: Setting true"); + success.set(true); + println!("F2: Ended"); + }); + + let f3 = pin!(async { + println!("F3: Started"); + wait(|| success.get()).await; + println!("F3: Ended"); + }); + + block_on(async { + join_tasks([AsyncTask::new(f1), AsyncTask::new(f2), AsyncTask::new(f3)]).await; + }); + + // assert_eq!(true, false); + } +} diff --git a/minimal_async_basic/l2/src/cooperative/async_timer.rs b/minimal_async_basic/l2/src/cooperative/async_timer.rs new file mode 100644 index 0000000..b91f518 --- /dev/null +++ b/minimal_async_basic/l2/src/cooperative/async_timer.rs @@ -0,0 +1,126 @@ +use core::{ + future::Future, + ops::{Add, Sub}, + task::Poll, + time::Duration, +}; + +use l0::get_current_time; + +use crate::{wait, wait_and_return}; + +#[derive(Debug, PartialEq)] +pub enum WaitUntilReason { + DataReady, + Timeout, +} + +pub fn wait_until bool>( + ready: F, + timeout: Duration, +) -> impl Future { + let timeout_time = get_current_time().add(timeout); + wait_and_return(move || { + if ready() { + (Some(WaitUntilReason::DataReady), true) + } else if get_current_time() >= timeout_time { + (Some(WaitUntilReason::Timeout), true) + } else { + (None, false) + } + }) +} + +pub fn sleep_via_wait(wait_duration: Duration) -> impl Future { + let wakeup_time = get_current_time().add(wait_duration); + wait(move || get_current_time() >= wakeup_time) +} + +pub fn sleep_via_timer(wait_duration: Duration) -> impl Future { + AsyncTimer::new(wait_duration) +} + +struct AsyncTimer { + wait_duration: Duration, + start_time: Duration, +} + +impl AsyncTimer { + fn new(wait_duration: Duration) -> Self { + Self { + wait_duration, + start_time: get_current_time(), + } + } +} + +impl Future for AsyncTimer { + type Output = (); + + fn poll( + self: core::pin::Pin<&mut Self>, + _: &mut core::task::Context<'_>, + ) -> core::task::Poll { + if get_current_time().sub(self.start_time) >= self.wait_duration { + Poll::Ready(()) + } else { + Poll::Pending + } + } +} + +#[cfg(test)] +mod tests { + use core::time::Duration; + use std::time::Instant; + + use crate::{block_on, sleep_via_timer, sleep_via_wait, wait_until, WaitUntilReason}; + + #[test] + fn sleep_via_wait_test() { + let async_timer_cb = async { + sleep_via_wait(Duration::from_secs(1)).await; + }; + let instant = Instant::now(); + block_on(async_timer_cb); + let duration = instant.elapsed(); + assert!(duration.as_secs() >= 1); + } + + #[test] + fn sleep_via_timer_test() { + let async_timer_cb = async { + sleep_via_timer(Duration::from_secs(1)).await; + }; + let instant = Instant::now(); + block_on(async_timer_cb); + let duration = instant.elapsed(); + assert!(duration.as_secs() >= 1); + } + + #[test] + fn wait_until_timeout_test() { + let async_sleep_until_cb = async { + let reason = wait_until(|| false, Duration::from_secs(1)).await; + assert_eq!(reason, WaitUntilReason::Timeout); + }; + + let instant = Instant::now(); + block_on(async_sleep_until_cb); + let duration = instant.elapsed(); + assert!(duration.as_secs() >= 1); + } + + #[test] + fn wait_until_dataready_test() { + let async_sleep_until_cb = async { + let reason = wait_until(|| true, Duration::from_secs(1)).await; + assert_eq!(reason, WaitUntilReason::DataReady); + }; + + let instant = Instant::now(); + block_on(async_sleep_until_cb); + let duration = instant.elapsed(); + assert!(duration.as_secs() < 1); + } +} diff --git a/minimal_async_basic/l2/src/cooperative/async_util.rs b/minimal_async_basic/l2/src/cooperative/async_util.rs new file mode 100644 index 0000000..628a9d9 --- /dev/null +++ b/minimal_async_basic/l2/src/cooperative/async_util.rs @@ -0,0 +1,29 @@ +use core::{future::Future, task::Poll}; + +pub fn wait(ready: impl Fn() -> bool) -> impl Future { + wait_and_return(move || (Some(()), ready())) +} + +pub fn wait_and_return(ready: impl Fn() -> (Option, bool)) -> impl Future { + Wait { ready } +} + +struct Wait (Option, bool)> { + ready: F, +} + +impl (Option, bool)> Future for Wait { + type Output = T; + + fn poll( + self: core::pin::Pin<&mut Self>, + _: &mut core::task::Context<'_>, + ) -> Poll { + let (data, ready) = (self.ready)(); + if ready { + Poll::Ready(data.unwrap()) + } else { + Poll::Pending + } + } +} diff --git a/minimal_async_basic/l2/src/cooperative/mod.rs b/minimal_async_basic/l2/src/cooperative/mod.rs new file mode 100644 index 0000000..60626a0 --- /dev/null +++ b/minimal_async_basic/l2/src/cooperative/mod.rs @@ -0,0 +1,51 @@ +use core::{ + sync::atomic::AtomicBool, + task::{RawWaker, RawWakerVTable}, +}; + +mod async_mutex; +pub use async_mutex::*; + +mod async_timer; +pub use async_timer::*; + +mod async_task; +pub use async_task::*; + +mod async_util; +pub use async_util::*; + +mod simple_executor; +pub use simple_executor::*; + +// RawWakerVTable for efficient wakeups +static VTABLE: RawWakerVTable = { + unsafe fn clone(p: *const ()) -> RawWaker { + RawWaker::new(p, &VTABLE) + } + unsafe fn wake(p: *const ()) { + wake_by_ref(p) + } + unsafe fn wake_by_ref(p: *const ()) { + if p.is_null() { + return; + } + // TODO, Use this when Waker support is implemented + // Otherwise should only be castable to AtomicBool + let indicate_ready = &*(p as *const AtomicBool); // unsafe operation (be careful when constructing a RawWaker) + indicate_ready.store(true, core::sync::atomic::Ordering::SeqCst); + } + unsafe fn drop(_: *const ()) { + // no-op + } + RawWakerVTable::new(clone, wake, wake_by_ref, drop) +}; + +// TODO, Needs AsyncQueue implementation with Producer and Consumer implementation +// TODO, AsyncSPSC -> Simple producer/consumer processing queues +// TODO, AsyncSPMC -> Triggering events +// TODO, AsyncMPSC -> Writing data to console +// TODO, AsyncMPMC -> Interrupts + +// ^ +// TODO, Needs AsyncSemaphore implementation (should use AsyncQueue under the hood) diff --git a/minimal_async_basic/l2/src/cooperative/simple_executor.rs b/minimal_async_basic/l2/src/cooperative/simple_executor.rs new file mode 100644 index 0000000..503bfac --- /dev/null +++ b/minimal_async_basic/l2/src/cooperative/simple_executor.rs @@ -0,0 +1,23 @@ +use core::{ + future::Future, + pin::pin, + ptr, + task::{Context, RawWaker, Waker}, +}; + +use super::VTABLE; + +// Run one async task till completion +// Blocks the current thread and no other concurrent operations takes place till this future is resolved +pub fn block_on(future: impl Future) -> T { + let mut future = pin!(future); + // let mut task = AsyncTask::new(future); + let waker = unsafe { Waker::from_raw(RawWaker::new(ptr::null(), &VTABLE)) }; + let mut context = Context::from_waker(&waker); + loop { + match future.as_mut().poll(&mut context) { + core::task::Poll::Ready(data) => break data, + core::task::Poll::Pending => {} + } + } +} diff --git a/minimal_async_basic/l2/src/lib.rs b/minimal_async_basic/l2/src/lib.rs new file mode 100644 index 0000000..7ea46e8 --- /dev/null +++ b/minimal_async_basic/l2/src/lib.rs @@ -0,0 +1,8 @@ +#![cfg_attr(not(test), no_std)] + +pub use bitflags::bitflags; +pub use heapless; + +// Asynchronous support +mod cooperative; +pub use cooperative::*; diff --git a/minimal_async_basic/l3/Cargo.toml b/minimal_async_basic/l3/Cargo.toml new file mode 100644 index 0000000..5f38210 --- /dev/null +++ b/minimal_async_basic/l3/Cargo.toml @@ -0,0 +1,12 @@ +[package] +name = "l3" +version = "0.1.0" +authors = ["Niket Naidu "] +edition = "2021" +readme = "README.md" + +# See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html + +[dependencies] +l0 = { path = "../l0" } +l2 = { path = "../l2" } diff --git a/minimal_async_basic/l3/src/interfaces/gpio_interface.rs b/minimal_async_basic/l3/src/interfaces/gpio_interface.rs new file mode 100644 index 0000000..9bd4388 --- /dev/null +++ b/minimal_async_basic/l3/src/interfaces/gpio_interface.rs @@ -0,0 +1,30 @@ +use crate::EnumToNum; + +#[derive(PartialEq, Eq)] +pub enum GpioValue { + Low, + High, +} + +impl EnumToNum for GpioValue { + fn to_num(&self) -> u32 { + match self { + GpioValue::Low => 0x0, + GpioValue::High => 0x1, + } + } +} + +pub trait GpioOut { + fn write(&mut self, value: GpioValue); + fn set(&mut self) { + self.write(GpioValue::High); + } + fn reset(&mut self) { + self.write(GpioValue::Low); + } +} + +pub trait GpioIn { + fn read(&self) -> GpioValue; +} diff --git a/minimal_async_basic/l3/src/interfaces/mod.rs b/minimal_async_basic/l3/src/interfaces/mod.rs new file mode 100644 index 0000000..cf74472 --- /dev/null +++ b/minimal_async_basic/l3/src/interfaces/mod.rs @@ -0,0 +1,8 @@ +pub mod gpio_interface; +pub use gpio_interface::*; + +pub mod usart_interface; +pub use usart_interface::*; + +pub mod utility_interface; +pub use utility_interface::*; diff --git a/minimal_async_basic/l3/src/interfaces/usart_interface.rs b/minimal_async_basic/l3/src/interfaces/usart_interface.rs new file mode 100644 index 0000000..6fedc90 --- /dev/null +++ b/minimal_async_basic/l3/src/interfaces/usart_interface.rs @@ -0,0 +1,19 @@ +use core::fmt::Write; + +// * Instead of having an `UsartOut` trait, we can use the Rust core library `core::fmt::Write` trait + +pub trait UsartIn { + /// Blocking read + fn read_character(&mut self) -> char; +} + +pub trait UsartBufferedIn { + /// Number of elements contained within the queue + fn size(&self) -> usize; + /// Non blocking read + fn try_read_character(&mut self) -> Option; +} + +pub trait UsartInOut: UsartIn + Write {} + +pub trait UsartBufferedInOut: UsartBufferedIn + Write {} diff --git a/minimal_async_basic/l3/src/interfaces/utility_interface.rs b/minimal_async_basic/l3/src/interfaces/utility_interface.rs new file mode 100644 index 0000000..5128990 --- /dev/null +++ b/minimal_async_basic/l3/src/interfaces/utility_interface.rs @@ -0,0 +1,4 @@ +// Trait to convert enums to numbers +pub trait EnumToNum { + fn to_num(&self) -> u32; +} diff --git a/minimal_async_basic/l3/src/lib.rs b/minimal_async_basic/l3/src/lib.rs new file mode 100644 index 0000000..c50440c --- /dev/null +++ b/minimal_async_basic/l3/src/lib.rs @@ -0,0 +1,14 @@ +#![cfg_attr(not(test), no_std)] + +mod interfaces; +pub use interfaces::*; + +pub mod singleton; +pub use singleton::*; + +// TODO, Add features +// #[cfg(feature = "stm32l475xx")] +#[cfg(all(target_arch = "arm", target_os = "none"))] +pub mod stm32l475xx; +#[cfg(all(target_arch = "arm", target_os = "none"))] +pub use stm32l475xx::*; diff --git a/minimal_async_basic/l3/src/singleton.rs b/minimal_async_basic/l3/src/singleton.rs new file mode 100644 index 0000000..2ae5bca --- /dev/null +++ b/minimal_async_basic/l3/src/singleton.rs @@ -0,0 +1,94 @@ +use core::{ + cell::{RefCell, RefMut}, + ops::{Deref, DerefMut}, +}; + +// RefCell takes 8 bytes of space +pub struct Singleton { + data: RefCell, +} + +pub struct SingletonGuard<'a, T> { + data: RefMut<'a, T>, +} + +impl<'a, T> Deref for SingletonGuard<'a, T> { + type Target = T; + fn deref(&self) -> &Self::Target { + self.data.deref() + } +} + +impl<'a, T> DerefMut for SingletonGuard<'a, T> { + fn deref_mut(&mut self) -> &mut Self::Target { + self.data.deref_mut() + } +} + +// TODO, Check if more traits are required for SingletonGuard + +impl Singleton { + pub const fn new(data: T) -> Self { + Self { + data: RefCell::new(data), + } + } + + pub fn take(&self) -> SingletonGuard { + SingletonGuard { + data: self.data.borrow_mut(), + } + } +} + +unsafe impl Sync for Singleton {} + +// TODO, Check if more traits are required for Singleton + +#[cfg(test)] +mod tests { + use super::*; + + struct Tester; + + impl Tester { + fn tester(&self) {} + fn tester_mut(&mut self) {} + } + + #[test] + fn singleton_local() { + let singleton: Singleton = Singleton::new(Tester {}); + + // Non mutable + { + let lock = singleton.take(); + lock.tester(); + } + + // Mutable + { + let mut lock = singleton.take(); + lock.tester(); + lock.tester_mut(); + } + } + + static TESTER: Singleton = Singleton::new(Tester {}); + + #[test] + fn singleton_static() { + // Non mutable + { + let lock = TESTER.take(); + lock.tester(); + } + + // Mutable + { + let mut lock = TESTER.take(); + lock.tester(); + lock.tester_mut(); + } + } +} diff --git a/minimal_async_basic/l3/src/stm32l475xx/exti.rs b/minimal_async_basic/l3/src/stm32l475xx/exti.rs new file mode 100644 index 0000000..1413130 --- /dev/null +++ b/minimal_async_basic/l3/src/stm32l475xx/exti.rs @@ -0,0 +1,50 @@ +use l0::{get_port, read_register, write_assign_register, write_register, EXTI_TypeDef, EXTI_BASE}; + +pub enum EXTIType { + RisingEdge, + FallingEdge, + RisingAndFallingEdge, +} + +pub struct EXTIRegister { + port: &'static mut EXTI_TypeDef, +} + +impl EXTIRegister { + pub fn configure_interrupt(&mut self, pin: u32, interrupt_type: EXTIType) { + write_assign_register!(self.port.IMR1, |, 1 << pin); + + match interrupt_type { + EXTIType::RisingEdge => { + write_assign_register!(self.port.RTSR1, |, 1 << pin); + } + EXTIType::FallingEdge => { + write_assign_register!(self.port.FTSR1, |, 1 << pin); + } + EXTIType::RisingAndFallingEdge => { + write_assign_register!(self.port.RTSR1, |, 1 << pin); + write_assign_register!(self.port.FTSR1, |, 1 << pin); + } + } + } + + pub fn is_pending_interrupt(&self, pin: u32) -> bool { + read_register!(self.port.PR1) >> pin & 0x01 == 1 + } + + pub fn clear_pending_interrupt(&mut self, pin: u32) { + write_register!(self.port.PR1, 1 << pin); + } +} + +pub struct EXTIPeripheral; + +impl EXTIPeripheral { + pub fn get_register() -> EXTIRegister { + EXTIRegister { + port: get_port!(EXTI_TypeDef, B), + } + } +} + +pub type EXTI = EXTIPeripheral; diff --git a/minimal_async_basic/l3/src/stm32l475xx/gpio.rs b/minimal_async_basic/l3/src/stm32l475xx/gpio.rs new file mode 100644 index 0000000..2ed1176 --- /dev/null +++ b/minimal_async_basic/l3/src/stm32l475xx/gpio.rs @@ -0,0 +1,287 @@ +#![allow(dead_code)] + +use crate::Singleton; +use crate::{EnumToNum, GpioIn, GpioOut, GpioValue}; +use l0::{ + get_port, read_register, write_register, GPIO_TypeDef, GPIOA_BASE, GPIOB_BASE, GPIOC_BASE, + GPIOD_BASE, GPIOE_BASE, GPIOF_BASE, GPIOG_BASE, GPIOH_BASE, +}; + +pub enum GPIOMode { + Input, + Output, + AlternateFunction, + AnalogMode, +} + +impl EnumToNum for GPIOMode { + fn to_num(&self) -> u32 { + match self { + GPIOMode::Input => 0x0, + GPIOMode::Output => 0x1, + GPIOMode::AlternateFunction => 0x2, + GPIOMode::AnalogMode => 0x3, + } + } +} + +pub enum GPIOType { + PushPull, + OpenDrain, +} + +impl EnumToNum for GPIOType { + fn to_num(&self) -> u32 { + match self { + GPIOType::PushPull => 0x0, + GPIOType::OpenDrain => 0x1, + } + } +} + +pub enum GPIOPull { + NoPullupOrPulldown, + Pullup, + Pulldown, +} + +impl EnumToNum for GPIOPull { + fn to_num(&self) -> u32 { + match self { + GPIOPull::NoPullupOrPulldown => 0x0, + GPIOPull::Pullup => 0x1, + GPIOPull::Pulldown => 0x2, + } + } +} + +pub enum GPIOSpeed { + LowSpeed, + MediumSpeed, + HighSpeed, + VeryHighSpeed, +} + +impl EnumToNum for GPIOSpeed { + fn to_num(&self) -> u32 { + match self { + GPIOSpeed::LowSpeed => 0x0, + GPIOSpeed::MediumSpeed => 0x1, + GPIOSpeed::HighSpeed => 0x2, + GPIOSpeed::VeryHighSpeed => 0x3, + } + } +} + +pub enum GPIOAlternate { + AF0, + AF1, + AF2, + AF3, + AF4, + AF5, + AF6, + AF7, + AF8, + AF9, + AF10, + AF11, + AF12, + AF13, + AF14, + AF15, +} + +impl EnumToNum for GPIOAlternate { + fn to_num(&self) -> u32 { + match self { + GPIOAlternate::AF0 => 0, + GPIOAlternate::AF1 => 1, + GPIOAlternate::AF2 => 2, + GPIOAlternate::AF3 => 3, + GPIOAlternate::AF4 => 4, + GPIOAlternate::AF5 => 5, + GPIOAlternate::AF6 => 6, + GPIOAlternate::AF7 => 7, + GPIOAlternate::AF8 => 8, + GPIOAlternate::AF9 => 9, + GPIOAlternate::AF10 => 10, + GPIOAlternate::AF11 => 11, + GPIOAlternate::AF12 => 12, + GPIOAlternate::AF13 => 13, + GPIOAlternate::AF14 => 14, + GPIOAlternate::AF15 => 15, + } + } +} + +pub struct GPIOFunction { + port: &'static mut GPIO_TypeDef, + pin: u32, +} + +impl GPIOFunction { + fn via_config(&mut self, config: &GPIOConfig) { + self.set_moder(&config.moder); + self.set_otyper(&config.otyper); + self.set_pupdr(&config.pupdr); + self.set_ospeedr(&config.ospeedr); + self.set_afr(&config.afr); + } + + fn set_moder(&mut self, moder: &GPIOMode) { + let mut moder_data = read_register!(self.port.MODER); + moder_data &= !(0x3 << self.pin * 2); // clear mode register + moder_data |= moder.to_num() << self.pin * 2; + write_register!(self.port.MODER, moder_data); + } + + fn set_otyper(&mut self, otyper: &GPIOType) { + let mut otyper_data = read_register!(self.port.OTYPER); + otyper_data &= !(0x1 << self.pin); // clear type register + otyper_data |= otyper.to_num() << self.pin; + write_register!(self.port.OTYPER, otyper_data); + } + + fn set_ospeedr(&mut self, ospeedr: &GPIOSpeed) { + let mut ospeedr_data = read_register!(self.port.OSPEEDR); + ospeedr_data &= !(0x3 << self.pin * 2); // clear ospeedr register + ospeedr_data |= ospeedr.to_num() << self.pin * 2; + write_register!(self.port.OSPEEDR, ospeedr_data); + } + + fn set_pupdr(&mut self, pupdr: &GPIOPull) { + let mut pupdr_data = read_register!(self.port.PUPDR); + pupdr_data &= !(0x3 << self.pin * 2); + pupdr_data |= pupdr.to_num() << self.pin * 2; + write_register!(self.port.PUPDR, pupdr_data); + } + + fn set_afr(&mut self, afr: &GPIOAlternate) { + let (index, pin) = if self.pin > 7 { + // Use AFRH + (1, self.pin - 7) + } else { + // Use AFRL + (0, self.pin) + }; + + let mut afr_data = read_register!(self.port.AFR[index]); + afr_data &= !(0xF << (pin << 2)); + afr_data |= afr.to_num() << (pin << 2); + write_register!(self.port.AFR[index], afr_data); + } + + fn set_bsrr(&mut self) { + let mut bsrr_data = read_register!(self.port.BSRR); + bsrr_data |= 1 << self.pin; + write_register!(self.port.BSRR, bsrr_data); + } + + fn set_brr(&mut self) { + let mut brr_data = read_register!(self.port.BRR); + brr_data |= 1 << self.pin; + write_register!(self.port.BRR, brr_data); + } +} + +impl GpioOut for GPIOFunction { + fn write(&mut self, value: GpioValue) { + match value { + GpioValue::Low => self.set_brr(), + GpioValue::High => self.set_bsrr(), + } + } +} + +impl GpioIn for GPIOFunction { + fn read(&self) -> GpioValue { + let idr = read_register!(self.port.IDR); + let value = (idr >> self.pin) & 0x01; + let value = match value { + 0x0 => GpioValue::Low, + 0x1 => GpioValue::High, + _ => unreachable!(), + }; + value + } +} + +// Put functionality here i.e various valid configurations for your peripheral +pub struct GPIOPeripheral; + +impl GPIOPeripheral { + pub fn configure_for_output(&self, pin: u32) -> impl GpioOut { + let config = GPIOConfig { + pin, + moder: GPIOMode::Output, + otyper: GPIOType::PushPull, + pupdr: GPIOPull::NoPullupOrPulldown, + ospeedr: GPIOSpeed::LowSpeed, + afr: GPIOAlternate::AF0, + }; + Self::configure(&config) + } + + pub fn configure_for_input(&self, pin: u32) -> impl GpioIn { + let config = GPIOConfig { + pin, + moder: GPIOMode::Input, + otyper: GPIOType::PushPull, + pupdr: GPIOPull::NoPullupOrPulldown, + ospeedr: GPIOSpeed::LowSpeed, + afr: GPIOAlternate::AF0, + }; + Self::configure(&config) + } + + pub fn configure_for_usart(&self, afr: GPIOAlternate, pin: u32) -> GPIOFunction { + let config = GPIOConfig { + pin, + moder: GPIOMode::AlternateFunction, + otyper: GPIOType::PushPull, + pupdr: GPIOPull::NoPullupOrPulldown, + ospeedr: GPIOSpeed::VeryHighSpeed, + afr, + }; + Self::configure(&config) + } + + pub fn configure(config: &GPIOConfig) -> GPIOFunction { + let mut gpio = GPIOFunction { + port: get_port!(GPIO_TypeDef, B), + pin: config.pin, + }; + gpio.via_config(&config); + gpio + } +} + +pub struct GPIOConfig { + pin: u32, + moder: GPIOMode, + otyper: GPIOType, + pupdr: GPIOPull, + ospeedr: GPIOSpeed, + afr: GPIOAlternate, +} + +// Create established ports here + +type GPIOA = GPIOPeripheral; +type GPIOB = GPIOPeripheral; +type GPIOC = GPIOPeripheral; +type GPIOD = GPIOPeripheral; +type GPIOE = GPIOPeripheral; +type GPIOF = GPIOPeripheral; +type GPIOG = GPIOPeripheral; +type GPIOH = GPIOPeripheral; + +pub static GPIOA_GLOBAL: Singleton = Singleton::new(GPIOA {}); +pub static GPIOB_GLOBAL: Singleton = Singleton::new(GPIOB {}); +pub static GPIOC_GLOBAL: Singleton = Singleton::new(GPIOC {}); +pub static GPIOD_GLOBAL: Singleton = Singleton::new(GPIOD {}); +pub static GPIOE_GLOBAL: Singleton = Singleton::new(GPIOE {}); +pub static GPIOF_GLOBAL: Singleton = Singleton::new(GPIOF {}); +pub static GPIOG_GLOBAL: Singleton = Singleton::new(GPIOG {}); +pub static GPIOH_GLOBAL: Singleton = Singleton::new(GPIOH {}); diff --git a/minimal_async_basic/l3/src/stm32l475xx/mod.rs b/minimal_async_basic/l3/src/stm32l475xx/mod.rs new file mode 100644 index 0000000..3cf4e04 --- /dev/null +++ b/minimal_async_basic/l3/src/stm32l475xx/mod.rs @@ -0,0 +1,12 @@ +mod rcc; +pub use rcc::*; + +mod exti; +pub use exti::*; + +// Contains interfaces +mod gpio; +pub use gpio::*; + +mod usart; +pub use usart::*; diff --git a/minimal_async_basic/l3/src/stm32l475xx/rcc.rs b/minimal_async_basic/l3/src/stm32l475xx/rcc.rs new file mode 100644 index 0000000..24877f7 --- /dev/null +++ b/minimal_async_basic/l3/src/stm32l475xx/rcc.rs @@ -0,0 +1,64 @@ +#![allow(non_camel_case_types)] + +use l0::{get_port, read_register, write_register, RCC_TypeDef, RCC_BASE}; +use l2::bitflags; + +use crate::Singleton; + +bitflags! { + pub struct RCC_AHB2ENR : u32 { + const GPIOAEN = 1 << 0; + const GPIOBEN = 1 << 1; + const GPIOCEN = 1 << 2; + const GPIODEN = 1 << 3; + const GPIOEEN = 1 << 4; + const GPIOFEN = 1 << 5; + const GPIOGEN = 1 << 6; + const GPIOHEN = 1 << 7; + const GPIOIEN = 1 << 8; + // TODO, Add more + } +} + +bitflags! { + pub struct RCC_APB2ENR : u32 { + const SYSCFGEN = 1 << 0; + const USART1EN = 1 << 14; + // TODO, Add more + } +} + +pub struct RCCRegister { + port: &'static mut RCC_TypeDef, +} + +impl RCCRegister { + pub fn set_ahb2enr(&mut self, ahb2: RCC_AHB2ENR) { + let mut ahb2enr_data = read_register!(self.port.AHB2ENR); + ahb2enr_data |= ahb2.bits(); + write_register!(self.port.AHB2ENR, ahb2enr_data); + } + + pub fn set_apb2enr(&mut self, apb2: RCC_APB2ENR) { + let mut apb2enr_data = read_register!(self.port.APB2ENR); + apb2enr_data |= apb2.bits(); + write_register!(self.port.APB2ENR, apb2enr_data); + } +} + +// Put functionality here i.e various valid configurations for your port +pub struct RCCPeripheral; + +impl RCCPeripheral { + pub fn get_register(&self) -> RCCRegister { + RCCRegister { + port: get_port!(RCC_TypeDef, B), + } + } +} + +// Create established ports here + +type RCC = RCCPeripheral; + +pub static RCC_GLOBAL: Singleton = Singleton::new(RCC {}); diff --git a/minimal_async_basic/l3/src/stm32l475xx/usart.rs b/minimal_async_basic/l3/src/stm32l475xx/usart.rs new file mode 100644 index 0000000..3b8f8be --- /dev/null +++ b/minimal_async_basic/l3/src/stm32l475xx/usart.rs @@ -0,0 +1,355 @@ +#![allow(non_camel_case_types)] + +use core::fmt::Write; + +use l0::{get_port, get_system_clock, read_register, write_register, USART_TypeDef, USART1_BASE}; +use l2::{bitflags, heapless::spsc::Queue}; + +use crate::{Singleton, UsartBufferedIn, UsartBufferedInOut, UsartIn, UsartInOut}; + +bitflags! { + pub struct USART_CR1 : u32 { + const UE = 1 << 0; + const RE = 1 << 2; + const TE = 1 << 3; + const RXNEIE = 1 << 5; + const M0 = 1 << 12; + const OVER8 = 1 << 15; + const M1 = 1 << 28; + } +} + +bitflags! { + pub struct USART_CR2 : u32 { + const STOP = 3 << 12; + } +} + +/// USARTConfig + +pub struct USARTConfig { + mode: USARTMode, + word_length: USARTWordLength, + stop_bit: USARTStopBit, + baud_rate: u32, +} + +pub enum USARTWordLength { + Len8, + Len9, + Len7, +} + +pub enum USARTStopBit { + Bit1_0, + Bit0_5, + Bit2_0, + Bit1_5, +} + +pub enum USARTMode { + Inactive, + RxOnly, + TxOnly, + RxTx, +} + +/// USARTPolledFunction + +pub struct USARTPolledFunction { + port: &'static mut USART_TypeDef, +} + +impl USARTPolledFunction { + fn via_configure(&mut self, config: &USARTConfig) { + // Disable USART + self.reset_cr1(USART_CR1::UE); + + // Baud rate + let system_clock = get_system_clock(); + let usartdiv = system_clock / config.baud_rate; + write_register!(self.port.BRR, usartdiv); + + // Stop bits + let mut cr2_data = read_register!(self.port.CR2); + cr2_data &= (!USART_CR2::STOP).bits(); + cr2_data |= match config.stop_bit { + USARTStopBit::Bit1_0 => 0 << 12, + USARTStopBit::Bit0_5 => 1 << 12, + USARTStopBit::Bit2_0 => 2 << 12, + USARTStopBit::Bit1_5 => 3 << 12, + }; + write_register!(self.port.CR2, cr2_data); + + // Set word length, usart mode and enable + let mut cr1_data = read_register!(self.port.CR1); + cr1_data &= (!USART_CR1::all()).bits(); + + // Set word length + cr1_data |= match config.word_length { + USARTWordLength::Len8 => 0, + USARTWordLength::Len9 => USART_CR1::M0.bits(), + USARTWordLength::Len7 => USART_CR1::M1.bits(), + }; + + // Set Mode + cr1_data |= match config.mode { + USARTMode::Inactive => 0, + USARTMode::RxOnly => USART_CR1::RE.bits(), + USARTMode::TxOnly => USART_CR1::TE.bits(), + USARTMode::RxTx => (USART_CR1::RE | USART_CR1::TE).bits(), + }; + + // Enable + cr1_data |= USART_CR1::UE.bits(); + + write_register!(self.port.CR1, cr1_data); + } + + fn reset_cr1(&mut self, cr1: USART_CR1) { + let mut cr1_data = read_register!(self.port.CR1); + cr1_data &= !(cr1.bits()); + write_register!(self.port.CR1, cr1_data); + } +} + +impl UsartIn for USARTPolledFunction { + fn read_character(&mut self) -> char { + const ISR_RXNE: u32 = 5; + while (read_register!(self.port.ISR) & 1 << ISR_RXNE) == 0 {} + let data = read_register!(self.port.RDR) as u8; + data as char + } +} + +impl Write for USARTPolledFunction { + fn write_str(&mut self, s: &str) -> core::fmt::Result { + let bit_not_set = |bit: u32| { + let isr_data = read_register!(self.port.ISR); + isr_data & (1 << bit) == 0 + }; + + const ISR_TXE: u32 = 7; + const ISR_TC: u32 = 6; + s.chars().for_each(|c| { + while bit_not_set(ISR_TXE) {} + write_register!(self.port.TDR, c as u16); + }); + while bit_not_set(ISR_TC) {} + Ok(()) + } +} + +impl UsartInOut for USARTPolledFunction {} + +/// USARTBufferedFunction + +pub struct USARTBufferedFunction { + port: &'static mut USART_TypeDef, + rx: Option<&'static mut Queue>, + tx: Option<&'static mut Queue>, +} + +impl USARTBufferedFunction { + fn via_configure(&mut self, config: &USARTConfig) { + // Disable USART + self.reset_cr1(USART_CR1::UE); + + // Baud rate + let system_clock = get_system_clock(); + let usartdiv = system_clock / config.baud_rate; + write_register!(self.port.BRR, usartdiv); + + // Stop bits + let mut cr2_data = read_register!(self.port.CR2); + cr2_data &= (!USART_CR2::STOP).bits(); + cr2_data |= match config.stop_bit { + USARTStopBit::Bit1_0 => 0 << 12, + USARTStopBit::Bit0_5 => 1 << 12, + USARTStopBit::Bit2_0 => 2 << 12, + USARTStopBit::Bit1_5 => 3 << 12, + }; + write_register!(self.port.CR2, cr2_data); + + // Set word length, usart mode and enable + let mut cr1_data = read_register!(self.port.CR1); + cr1_data &= (!USART_CR1::all()).bits(); + + // Set word length + cr1_data |= match config.word_length { + USARTWordLength::Len8 => 0, + USARTWordLength::Len9 => USART_CR1::M0.bits(), + USARTWordLength::Len7 => USART_CR1::M1.bits(), + }; + + // Set Mode + cr1_data |= match config.mode { + USARTMode::Inactive => 0, + USARTMode::RxOnly => (USART_CR1::RE | USART_CR1::RXNEIE).bits(), + USARTMode::TxOnly => USART_CR1::TE.bits(), + USARTMode::RxTx => (USART_CR1::RE | USART_CR1::RXNEIE | USART_CR1::TE).bits(), + }; + + // Enable + cr1_data |= USART_CR1::UE.bits(); + + write_register!(self.port.CR1, cr1_data); + } + + fn reset_cr1(&mut self, cr1: USART_CR1) { + let mut cr1_data = read_register!(self.port.CR1); + cr1_data &= !(cr1.bits()); + write_register!(self.port.CR1, cr1_data); + } +} + +impl UsartBufferedIn for USARTBufferedFunction { + fn size(&self) -> usize { + match &self.rx { + Some(rx) => rx.len(), + None => 0, + } + } + + fn try_read_character(&mut self) -> Option { + match &mut self.rx { + Some(rx) => rx.dequeue(), + None => None, + } + } +} + +impl Write for USARTBufferedFunction { + fn write_str(&mut self, s: &str) -> core::fmt::Result { + if let None = self.tx { + return Err(core::fmt::Error); + } + + let cr1_data = read_register!(self.port.CR1); + const TXEIE: u32 = 7; + let txeie = cr1_data >> TXEIE & 0x01 == 1; + if !txeie { + // Enable txeie + write_register!(self.port.CR1, cr1_data | (1 << TXEIE)); + } + + // Fill the buffer + s.chars().for_each(|d| { + self.tx.as_mut().unwrap().enqueue(d).unwrap(); + }); + return Ok(()); + } +} + +impl UsartBufferedInOut for USARTBufferedFunction {} + +/// USARTPeripheral + +// Put functionality here i.e various valid configurations for your peripheral +pub struct USARTPeripheral {} + +impl USARTPeripheral { + pub fn configure_polled_rx(&self) -> impl UsartIn { + Self::polled_configure(&USARTConfig { + mode: USARTMode::RxOnly, + word_length: USARTWordLength::Len8, + stop_bit: USARTStopBit::Bit1_0, + baud_rate: 115200, + }) + } + + pub fn configure_polled_tx(&self) -> impl Write { + Self::polled_configure(&USARTConfig { + mode: USARTMode::TxOnly, + word_length: USARTWordLength::Len8, + stop_bit: USARTStopBit::Bit1_0, + baud_rate: 115200, + }) + } + + pub fn configure_polled_rx_tx(&self) -> impl UsartInOut { + Self::polled_configure(&USARTConfig { + mode: USARTMode::RxTx, + word_length: USARTWordLength::Len8, + stop_bit: USARTStopBit::Bit1_0, + baud_rate: 115200, + }) + } + + fn polled_configure(config: &USARTConfig) -> USARTPolledFunction { + let mut usart = USARTPolledFunction { + port: get_port!(USART_TypeDef, B), + }; + usart.via_configure(&config); + usart + } + + pub fn configure_buffered_rx( + &self, + rx: &'static mut Queue, + ) -> impl UsartBufferedIn { + Self::buffered_configure( + &USARTConfig { + mode: USARTMode::RxTx, + word_length: USARTWordLength::Len8, + stop_bit: USARTStopBit::Bit1_0, + baud_rate: 115200, + }, + Some(rx), + None, + ) + } + + pub fn configure_buffered_tx( + &self, + tx: &'static mut Queue, + ) -> impl Write { + Self::buffered_configure( + &USARTConfig { + mode: USARTMode::RxTx, + word_length: USARTWordLength::Len8, + stop_bit: USARTStopBit::Bit1_0, + baud_rate: 115200, + }, + None, + Some(tx), + ) + } + + pub fn configure_buffered_rx_tx( + &self, + rx: &'static mut Queue, + tx: &'static mut Queue, + ) -> impl UsartBufferedInOut { + Self::buffered_configure( + &USARTConfig { + mode: USARTMode::RxTx, + word_length: USARTWordLength::Len8, + stop_bit: USARTStopBit::Bit1_0, + baud_rate: 115200, + }, + Some(rx), + Some(tx), + ) + } + + fn buffered_configure( + config: &USARTConfig, + rx: Option<&'static mut Queue>, + tx: Option<&'static mut Queue>, + ) -> USARTBufferedFunction { + let mut usart = USARTBufferedFunction { + port: get_port!(USART_TypeDef, B), + rx, + tx, + }; + usart.via_configure(&config); + usart + } +} + +// Create established ports here + +type USART1 = USARTPeripheral; + +pub static USART1_GLOBAL: Singleton = Singleton::new(USART1 {}); diff --git a/minimal_async_basic/l4/Cargo.toml b/minimal_async_basic/l4/Cargo.toml new file mode 100644 index 0000000..2f4bbdd --- /dev/null +++ b/minimal_async_basic/l4/Cargo.toml @@ -0,0 +1,11 @@ +[package] +name = "l4" +version = "0.1.0" +authors = ["Niket Naidu "] +edition = "2021" +readme = "README.md" + +# See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html + +[dependencies] +l3 = { path = "../l3" } diff --git a/minimal_async_basic/l4/src/button.rs b/minimal_async_basic/l4/src/button.rs new file mode 100644 index 0000000..1c76c12 --- /dev/null +++ b/minimal_async_basic/l4/src/button.rs @@ -0,0 +1,20 @@ +use l3::{GpioIn, GpioValue}; + +pub struct Button<'a> { + gpio: &'a dyn GpioIn, + default: GpioValue, // Default value when button is not pressed +} + +impl<'a> Button<'a> { + pub fn new(gpio: &'a dyn GpioIn, default: GpioValue) -> Self { + Self { gpio, default } + } + + pub fn pressed(&self) -> bool { + let mut pressed = false; + if self.gpio.read() != self.default { + pressed = true; + } + pressed + } +} diff --git a/minimal_async_basic/l4/src/led.rs b/minimal_async_basic/l4/src/led.rs new file mode 100644 index 0000000..5d295ce --- /dev/null +++ b/minimal_async_basic/l4/src/led.rs @@ -0,0 +1,19 @@ +use l3::GpioOut; + +pub struct Led<'a> { + gpio: &'a mut dyn GpioOut, +} + +impl<'a> Led<'a> { + pub fn new(gpio: &'a mut dyn GpioOut) -> Self { + Self { gpio } + } + + pub fn on(&mut self) { + self.gpio.set(); + } + + pub fn off(&mut self) { + self.gpio.reset(); + } +} diff --git a/minimal_async_basic/l4/src/lib.rs b/minimal_async_basic/l4/src/lib.rs new file mode 100644 index 0000000..194d1b3 --- /dev/null +++ b/minimal_async_basic/l4/src/lib.rs @@ -0,0 +1,7 @@ +#![cfg_attr(not(test), no_std)] + +pub mod led; +pub use led::*; + +pub mod button; +pub use button::*; diff --git a/minimal_async_basic/l5/Cargo.toml b/minimal_async_basic/l5/Cargo.toml new file mode 100644 index 0000000..5f95fcc --- /dev/null +++ b/minimal_async_basic/l5/Cargo.toml @@ -0,0 +1,14 @@ +[package] +name = "application" +version = "0.1.0" +authors = ["Niket Naidu "] +edition = "2021" +readme = "README.md" + +# See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html + +[dependencies] +l0 = { path = "../l0" } +l2 = { path = "../l2" } +l3 = { path = "../l3" } +l4 = { path = "../l4" } diff --git a/minimal_async_basic/l5/build.rs b/minimal_async_basic/l5/build.rs new file mode 100644 index 0000000..da8a068 --- /dev/null +++ b/minimal_async_basic/l5/build.rs @@ -0,0 +1,26 @@ +//! This build script copies the `memory.x` file from the crate root into +//! a directory where the linker can always find it at build time. +//! For many projects this is optional, as the linker always searches the +//! project root directory -- wherever `Cargo.toml` is. However, if you +//! are using a workspace or have a more complicated build setup, this +//! build script becomes required. Additionally, by requesting that +//! Cargo re-run the build script whenever `memory.x` is changed, +//! updating `memory.x` ensures a rebuild of the application with the +//! new memory settings. + +use std::env; +use std::path::PathBuf; + +fn reference() { + let out: &PathBuf = &PathBuf::from(env::var_os("OUT_DIR").unwrap()); + println!("{}", out.display()); +} + +fn linker_script() { + println!("cargo:rerun-if-changed=gcc_arm.ld"); +} + +fn main() { + reference(); + linker_script(); +} diff --git a/minimal_async_basic/l5/src/main.rs b/minimal_async_basic/l5/src/main.rs new file mode 100644 index 0000000..ffab773 --- /dev/null +++ b/minimal_async_basic/l5/src/main.rs @@ -0,0 +1,195 @@ +#![cfg_attr(not(test), no_std)] +#![cfg_attr(not(test), no_main)] +#![allow(unused_imports)] + +#[cfg(not(test))] +#[cfg(all(target_arch = "arm", target_os = "none"))] +#[no_mangle] +fn main() -> ! { + use core::{ + fmt::Write, + ops::Add, + pin::pin, + ptr, + sync::atomic::{AtomicBool, Ordering}, + time::Duration, + }; + use l0::*; + use l2::{ + block_on, heapless::spsc::Queue, join_tasks, sleep_via_timer, sleep_via_wait, wait, + AsyncMutex, AsyncTask, + }; + use l3::*; + use l4::*; + + // GPIOA Pin 5 + fn configure_gpio_output() -> impl GpioOut { + let gpioa_peripheral = GPIOA_GLOBAL.take(); + // Configure GPIOA port and Pin 5 as output + let gpio_out_at_pin5 = gpioa_peripheral.configure_for_output(5); + gpio_out_at_pin5 + } + + // GPIOC Pin 13 + fn configure_gpio_input() -> impl GpioIn { + let gpioc_peripheral = GPIOC_GLOBAL.take(); + // Configure GPIOC port and Pin 13 as input + let gpio_in_at_pin13 = gpioc_peripheral.configure_for_input(13); + gpio_in_at_pin13 + } + + // GPIOB Pin 6, 7 + fn configure_usart_rx_tx() -> impl UsartBufferedInOut { + let gpiob_peripheral = GPIOB_GLOBAL.take(); + // Configure GPIOB port Pin 6 and Pin 7 for USART + gpiob_peripheral.configure_for_usart(GPIOAlternate::AF7, 6); + gpiob_peripheral.configure_for_usart(GPIOAlternate::AF7, 7); + + let usart1_rx_tx = USART1_GLOBAL + .take() + .configure_buffered_rx_tx(unsafe { &mut RX_BUF }, unsafe { &mut TX_BUF }); + usart1_rx_tx + } + + fn configure_usart_rx_tx_interrupt() { + nvic::enable_irq(Interrupt::USART1); + } + + // Start + let mut rcc_register = RCC_GLOBAL.take().get_register(); + // Activate clock control for GPIOA, GPIOB and GPIOC and USART1EN + rcc_register.set_ahb2enr(RCC_AHB2ENR::GPIOAEN | RCC_AHB2ENR::GPIOBEN | RCC_AHB2ENR::GPIOCEN); + rcc_register.set_apb2enr(RCC_APB2ENR::USART1EN | RCC_APB2ENR::SYSCFGEN); + + // LED module + let mut gpio_output = configure_gpio_output(); + let mut led = Led::new(&mut gpio_output); + + // Button module + let gpio_in = configure_gpio_input(); + let button = Button::new(&gpio_in, GpioValue::High); + + // USART + let usart1_rx_tx = AsyncMutex::new(configure_usart_rx_tx()); + + // NOTE, Queue implementation is very heavy + // Uses 4 bytes per character + static mut RX_BUF: Queue = Queue::new(); + static mut TX_BUF: Queue = Queue::new(); + static IS_NEWLINE: AtomicBool = AtomicBool::new(false); + #[no_mangle] + extern "C" fn USART1_Interrupt_Handler() { + let usart1_port = USART1_PORT::port(); + let isr_data = read_register!(usart1_port.ISR); + const RXNE: u32 = 5; + // const TC: u32 = 6; + const TXE: u32 = 7; + const TXEIE: u32 = 7; + if (isr_data >> RXNE) & 0x01 == 1 { + // Read data + let rdr_data = read_register!(usart1_port.RDR) as u8 as char; + if rdr_data == '\n' || rdr_data == '\r' { + IS_NEWLINE.store(true, Ordering::SeqCst); + } + unsafe { RX_BUF.enqueue(rdr_data).unwrap() }; + } + + if (isr_data >> TXE) & 0x01 == 1 { + unsafe { + match TX_BUF.dequeue() { + Some(data) => { + write_register!(usart1_port.TDR, data as u16); + } + None => { + // Reset the CR1 TXEIE register + write_assign_register!(usart1_port.CR1, &, !(1 << TXEIE)); + } + } + }; + } + } + configure_usart_rx_tx_interrupt(); + + // Async tasks here + let async_button_press = async { + let mut counter = 0; + loop { + // Wait for button to be pressed + wait(|| button.pressed()).await; + + usart1_rx_tx.lock().await.action(|mut serial| { + let current_time = get_current_time(); + serial + .write_fmt(format_args!("Button {counter} {:?}\r\n", current_time)) + .unwrap(); + }); + counter += 1; + + // Wait for button to be released + wait(|| !button.pressed()).await; + } + }; + + let async_newline_recv = async { + loop { + wait(|| IS_NEWLINE.load(Ordering::SeqCst)).await; + + usart1_rx_tx.lock().await.action(|mut serial| { + serial.write_str("Printing\r\n").unwrap(); + while serial.size() != 0 { + let c = serial.try_read_character().unwrap(); + serial.write_char(c).unwrap(); + } + serial.write_str("\r\n").unwrap(); + }); + + IS_NEWLINE.store(false, Ordering::SeqCst); + } + }; + + let async_print_time = async { + loop { + sleep_via_timer(Duration::from_millis(1000)).await; + let current_time = get_current_time(); + + usart1_rx_tx.lock().await.action(|mut serial| { + serial + .write_fmt(format_args!("Time: {:?}\r\n", current_time)) + .unwrap(); + }); + } + }; + + let async_blink_led = async { + loop { + led.on(); + sleep_via_timer(Duration::from_millis(1000)).await; + led.off(); + sleep_via_timer(Duration::from_millis(1000)).await; + } + }; + + let async_button_press = pin!(async_button_press); + let async_newline_recv = pin!(async_newline_recv); + let async_print_time = pin!(async_print_time); + let async_blink_led = pin!(async_blink_led); + + block_on(async { + join_tasks([ + AsyncTask::new(async_button_press), + AsyncTask::new(async_newline_recv), + AsyncTask::new(async_print_time), + AsyncTask::new(async_blink_led), + ]) + .await; + }); + unreachable!(); +} + +#[cfg(test)] +mod tests { + #[test] + fn unit_tests_work() { + assert_eq!(1, 1); + } +} diff --git a/minimal_async_basic/stm32l4discovery.cfg b/minimal_async_basic/stm32l4discovery.cfg new file mode 100644 index 0000000..8b79841 --- /dev/null +++ b/minimal_async_basic/stm32l4discovery.cfg @@ -0,0 +1,13 @@ +# Explicitly for the STM32L476 discovery board: +# http://www.st.com/web/en/catalog/tools/PF261635 +# but perfectly functional for any other STM32L4 board connected via +# an stlink-v2-1 interface. +# This is for STM32L4 boards that are connected via stlink-v2-1. + +source [find interface/stlink.cfg] + +transport select hla_swd + +source [find target/stm32l4x.cfg] + +reset_config srst_only