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torvaldstorvalds
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Merge branch 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc
Pull powerpc fixes from Ben Herrenschmidt: "Here are a few more fixes for powerpc 3.10. It's a bit more than I would have liked this late in the game but I suppose that's what happens with a brand new chip generation coming out. A few regression fixes, some last minute fixes for new P8 features such as transactional memory,... There's also one powerpc KVM patch that I requested that adds two missing functions to our in-kernel interrupt controller support which is itself a new 3.10 feature. These are defined by the base hypervisor specification. We didn't implement them originally because Linux doesn't use them but they are simple and I'm not comfortable having a half-implemented interface in 3.10 and having to deal with versionning etc... later when something starts needing those calls. They cannot be emulated in qemu when using in-kernel interrupt controller (not enough shared state). Just added a last minute patch to fix a typo introducing a breakage in our cputable for Power7+ processors, sorry about that, but the regression it fixes just hurt me :-)" * 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: powerpc/cputable: Fix typo on P7+ cputable entry powerpc/perf: Add missing SIER support powerpc/perf: Revert to original NO_SIPR logic powerpc/pci: Remove the unused variables in pci_process_bridge_OF_ranges powerpc/pci: Remove the stale comments of pci_process_bridge_OF_ranges powerpc/pseries: Always enable CONFIG_HOTPLUG_CPU on PSERIES SMP powerpc/kvm/book3s: Add support for H_IPOLL and H_XIRR_X in XICS emulation powerpc/32bit:Store temporary result in r0 instead of r8 powerpc/mm: Always invalidate tlb on hpte invalidate and update powerpc/pseries: Improve stream generation comments in copypage/user powerpc/pseries: Kill all prefetch streams on context switch powerpc/cputable: Fix oprofile_cpu_type on power8 powerpc/mpic: Fix irq distribution problem when MPIC_SINGLE_DEST_CPU powerpc/tm: Fix userspace stack corruption on signal delivery for active transactions powerpc/tm: Move TM abort cause codes to uapi powerpc/tm: Abort on emulation and alignment faults powerpc/tm: Update cause codes documentation powerpc/tm: Make room for hypervisor in abort cause codes
2 parents 008bd2d + badec11 commit aa3ae6d

27 files changed

+262
-125
lines changed

‎Documentation/powerpc/transactional_memory.txt‎

Lines changed: 25 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -147,6 +147,25 @@ Example signal handler:
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fix_the_problem(ucp->dar);
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}
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When in an active transaction that takes a signal, we need to be careful with
151+
the stack. It's possible that the stack has moved back up after the tbegin.
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The obvious case here is when the tbegin is called inside a function that
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returns before a tend. In this case, the stack is part of the checkpointed
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transactional memory state. If we write over this non transactionally or in
155+
suspend, we are in trouble because if we get a tm abort, the program counter and
156+
stack pointer will be back at the tbegin but our in memory stack won't be valid
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anymore.
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159+
To avoid this, when taking a signal in an active transaction, we need to use
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the stack pointer from the checkpointed state, rather than the speculated
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state. This ensures that the signal context (written tm suspended) will be
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written below the stack required for the rollback. The transaction is aborted
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becuase of the treclaim, so any memory written between the tbegin and the
164+
signal will be rolled back anyway.
165+
166+
For signals taken in non-TM or suspended mode, we use the
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normal/non-checkpointed stack pointer.
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Failure cause codes used by kernel
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==================================
@@ -155,14 +174,18 @@ These are defined in <asm/reg.h>, and distinguish different reasons why the
155174
kernel aborted a transaction:
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157176
TM_CAUSE_RESCHED Thread was rescheduled.
177+
TM_CAUSE_TLBI Software TLB invalide.
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TM_CAUSE_FAC_UNAV FP/VEC/VSX unavailable trap.
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TM_CAUSE_SYSCALL Currently unused; future syscalls that must abort
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transactions for consistency will use this.
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TM_CAUSE_SIGNAL Signal delivered.
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TM_CAUSE_MISC Currently unused.
183+
TM_CAUSE_ALIGNMENT Alignment fault.
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TM_CAUSE_EMULATE Emulation that touched memory.
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164-
These can be checked by the user program's abort handler as TEXASR[0:7].
165-
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These can be checked by the user program's abort handler as TEXASR[0:7]. If
187+
bit 7 is set, it indicates that the error is consider persistent. For example
188+
a TM_CAUSE_ALIGNMENT will be persistent while a TM_CAUSE_RESCHED will not.q
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GDB
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===

‎arch/powerpc/include/asm/hvcall.h‎

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Original file line numberDiff line numberDiff line change
@@ -264,6 +264,7 @@
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#define H_GET_MPP 0x2D4
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#define H_HOME_NODE_ASSOCIATIVITY 0x2EC
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#define H_BEST_ENERGY 0x2F4
267+
#define H_XIRR_X 0x2FC
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#define H_RANDOM 0x300
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#define H_COP 0x304
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#define H_GET_MPP_X 0x314

‎arch/powerpc/include/asm/ppc_asm.h‎

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -523,6 +523,17 @@ END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,946)
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#define PPC440EP_ERR42
524524
#endif
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526+
/* The following stops all load and store data streams associated with stream
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* ID (ie. streams created explicitly). The embedded and server mnemonics for
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* dcbt are different so we use machine "power4" here explicitly.
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*/
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#define DCBT_STOP_ALL_STREAM_IDS(scratch) \
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.machine push ; \
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.machine "power4" ; \
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lis scratch,0x60000000@h; \
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dcbt r0,scratch,0b01010; \
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.machine pop
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/*
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* toreal/fromreal/tophys/tovirt macros. 32-bit BookE makes them
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* keep the address intact to be compatible with code shared with

‎arch/powerpc/include/asm/processor.h‎

Lines changed: 4 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -409,21 +409,16 @@ static inline void prefetchw(const void *x)
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#endif
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411411
#ifdef CONFIG_PPC64
412-
static inline unsigned long get_clean_sp(struct pt_regs *regs, int is_32)
412+
static inline unsigned long get_clean_sp(unsigned long sp, int is_32)
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{
414-
unsigned long sp;
415-
416414
if (is_32)
417-
sp = regs->gpr[1] & 0x0ffffffffUL;
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else
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sp = regs->gpr[1];
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return sp & 0x0ffffffffUL;
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return sp;
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}
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#else
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static inline unsigned long get_clean_sp(struct pt_regs *regs, int is_32)
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static inline unsigned long get_clean_sp(unsigned long sp, int is_32)
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{
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return regs->gpr[1];
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return sp;
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}
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#endif
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‎arch/powerpc/include/asm/reg.h‎

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Original file line numberDiff line numberDiff line change
@@ -111,17 +111,6 @@
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#define MSR_TM_TRANSACTIONAL(x) (((x) & MSR_TS_MASK) == MSR_TS_T)
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#define MSR_TM_SUSPENDED(x) (((x) & MSR_TS_MASK) == MSR_TS_S)
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114-
/* Reason codes describing kernel causes for transaction aborts. By
115-
convention, bit0 is copied to TEXASR[56] (IBM bit 7) which is set if
116-
the failure is persistent.
117-
*/
118-
#define TM_CAUSE_RESCHED 0xfe
119-
#define TM_CAUSE_TLBI 0xfc
120-
#define TM_CAUSE_FAC_UNAV 0xfa
121-
#define TM_CAUSE_SYSCALL 0xf9 /* Persistent */
122-
#define TM_CAUSE_MISC 0xf6
123-
#define TM_CAUSE_SIGNAL 0xf4
124-
125114
#if defined(CONFIG_PPC_BOOK3S_64)
126115
#define MSR_64BIT MSR_SF
127116

‎arch/powerpc/include/asm/signal.h‎

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Original file line numberDiff line numberDiff line change
@@ -3,5 +3,8 @@
33

44
#define __ARCH_HAS_SA_RESTORER
55
#include <uapi/asm/signal.h>
6+
#include <uapi/asm/ptrace.h>
7+
8+
extern unsigned long get_tm_stackpointer(struct pt_regs *regs);
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#endif /* _ASM_POWERPC_SIGNAL_H */

‎arch/powerpc/include/asm/tm.h‎

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Original file line numberDiff line numberDiff line change
@@ -5,6 +5,8 @@
55
* Copyright 2012 Matt Evans & Michael Neuling, IBM Corporation.
66
*/
77

8+
#include <uapi/asm/tm.h>
9+
810
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
911
extern void do_load_up_transact_fpu(struct thread_struct *thread);
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extern void do_load_up_transact_altivec(struct thread_struct *thread);

‎arch/powerpc/include/uapi/asm/Kbuild‎

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Original file line numberDiff line numberDiff line change
@@ -40,6 +40,7 @@ header-y += statfs.h
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header-y += swab.h
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header-y += termbits.h
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header-y += termios.h
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header-y += tm.h
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header-y += types.h
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header-y += ucontext.h
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header-y += unistd.h

‎arch/powerpc/include/uapi/asm/tm.h‎

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,18 @@
1+
#ifndef _ASM_POWERPC_TM_H
2+
#define _ASM_POWERPC_TM_H
3+
4+
/* Reason codes describing kernel causes for transaction aborts. By
5+
* convention, bit0 is copied to TEXASR[56] (IBM bit 7) which is set if
6+
* the failure is persistent. PAPR saves 0xff-0xe0 for the hypervisor.
7+
*/
8+
#define TM_CAUSE_PERSISTENT 0x01
9+
#define TM_CAUSE_RESCHED 0xde
10+
#define TM_CAUSE_TLBI 0xdc
11+
#define TM_CAUSE_FAC_UNAV 0xda
12+
#define TM_CAUSE_SYSCALL 0xd8 /* future use */
13+
#define TM_CAUSE_MISC 0xd6 /* future use */
14+
#define TM_CAUSE_SIGNAL 0xd4
15+
#define TM_CAUSE_ALIGNMENT 0xd2
16+
#define TM_CAUSE_EMULATE 0xd0
17+
18+
#endif

‎arch/powerpc/kernel/cputable.c‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -453,7 +453,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
453453
.icache_bsize = 128,
454454
.dcache_bsize = 128,
455455
.oprofile_type = PPC_OPROFILE_POWER4,
456-
.oprofile_cpu_type = "ppc64/ibm-compat-v1",
456+
.oprofile_cpu_type = 0,
457457
.cpu_setup = __setup_cpu_power8,
458458
.cpu_restore = __restore_cpu_power8,
459459
.platform = "power8",
@@ -482,7 +482,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
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.cpu_name = "POWER7+ (raw)",
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.cpu_features = CPU_FTRS_POWER7,
484484
.cpu_user_features = COMMON_USER_POWER7,
485-
.cpu_user_features = COMMON_USER2_POWER7,
485+
.cpu_user_features2 = COMMON_USER2_POWER7,
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.mmu_features = MMU_FTRS_POWER7,
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.icache_bsize = 128,
488488
.dcache_bsize = 128,
@@ -506,7 +506,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
506506
.dcache_bsize = 128,
507507
.num_pmcs = 6,
508508
.pmc_type = PPC_PMC_IBM,
509-
.oprofile_cpu_type = "ppc64/power8",
509+
.oprofile_cpu_type = 0,
510510
.oprofile_type = PPC_OPROFILE_POWER4,
511511
.cpu_setup = __setup_cpu_power8,
512512
.cpu_restore = __restore_cpu_power8,

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