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Commits on May 2, 2026

• [DispatchCreation] Tighten scatter-skip predicate in CollapseDimensions (#24334)

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  yzhang93

  and

  claude

  authored
  0935008

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Commits on May 1, 2026

• [Codegen][DMA] Fix unaligned swizzle offset computation in gather-to-lds lowering (#24241)

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  Yu-Zhewen

  authored
  f4d1908

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• [LLVMGPU][nfc] Modernize the rest of LLVMGPU pipeline tests. (#24341)

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  hanhanW

  authored
  7098bdf

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• [LLVMGPU][nfc] Modernize vector distribution pipeline tests. (#24340)

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  hanhanW

  authored
  316c1c1

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• [DispatchCreation] Refactor and add low-parallelism split reduction parameter set (#24293)

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  yzhang93

  and

  claude

  authored
  8fc32e0

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• Refactor vector.multi_reduction into flattening, unrolling, and lowering passes. (#24183)

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  amd-eochoalo

  and

  efric

  authored
  3be9dc6

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• Bump llvm to llvm-project@88e5eeb292f (#24339)

  nirvedhmeshram

  authored
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• [Codegen] Support pack/unpack/linalg generic transpose in CombineLayoutTransformation (#24273)

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  Muzammiluddin-Syed-ECE

  authored
  dd5a6e3

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• [Codegen][CPU] Teach the lowering strategy about inner_tiled. (#24328)

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  bjacob

  authored
  c40c7a3

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• [LinalgExt] Fix ArgCompareOp::generateResultTileValue for producer fusion (#24317)

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  bangtianliu

  authored
  174808a

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• Update CODEOWNERS for spreading review responsibility (#24332)

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  hanhanW

  authored
  83a30bb

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• [Codegen] NFC: Lift DataTiledMMA inner_tiled lowering helpers into MMAUtils. (#24326)

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  bjacob

  authored
  404b958

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• [Codegen][CPU] Fix RHS indexing map in materialize-encoding inner_tiled lowering. (#24325)

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  bjacob

  authored
  0a73681

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• [DispatchCreation] Fuse scalar reductions with their parallel consumers (#24166)

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  Abhishek-Varma

  authored
  01c52eb

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• Reapply "[Codegen] Use local binders for optimization flags in codegen (#24220)" (#24333)

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  hanhanW

  authored
  64031dd

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Commits on Apr 30, 2026

• [CI] Ease contention on self hosted machines (#24316)

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  amd-eochoalo

  authored
  e6139f6

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• Bump stablehlo to stablehlo@806a6844dfd92cca (#24330)

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  nirvedhmeshram

  authored
  d055923

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• [LLVMGPU][ROCDL] Add pass to group global loads for better instruction scheduling (#24247)

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  Max191

  and

  claude

  authored
  7247601

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• Bump iree-org/torch-mlir@d2768f876d (#24320)

  rsuderman

  authored
  ce12fef

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• [CPU] Add ContiguousMemrefGather1DToConditionalLoads vector lowering. (#24327)

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  hanhanW

  authored
  967b794

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• Bump LLVM to llvm-project@6f1e6e47bdf (#24314)

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  nirvedhmeshram

  authored
  fcbd569

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• [CI] Update iree-test-suite ref (#24304)

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  amd-eochoalo

  authored
  9f7a14e

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• [Codegen][CPU] Pick inner-tiled unroll factors from a register budget. (#24303)

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  bjacob

  authored
  5872dc2

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• [IREEGPU] Define and expand `subgroup_scan` (#24188)

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  sommerlukas

  authored
  0380544

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• [LLVMGPU] Remove unused `--iree-codegen-llvmgpu-use-unaligned-gemm-vector-distribution` flag (#24308)

  yzhang93

  authored
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• [HAL/AMDGPU] Initial host-side AMDGPU HAL implementation (#24298)

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  benvanik

  authored
  dfe8134

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Commits on Apr 29, 2026

• [HAL/AMDGPU] Use status matcher in notification test

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  benvanik

  committed
  b42f44c

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• [HAL/AMDGPU] Disable queue upload rings by default

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  benvanik

  committed
  bf7d2b5

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• [HAL/AMDGPU] Remove dynamic binding slot sidecars

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  benvanik

  committed
  3ac4164

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• [HAL/AMDGPU] Specialize all-dynamic dispatch replay

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  benvanik

  committed
  8d437bd

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• [HAL/AMDGPU] Compact dynamic binding pointer replay

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  benvanik

  committed
  237efe6

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• [HAL/AMDGPU] Bake dynamic binding slots into command buffers

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  benvanik

  committed
  34c5ba3

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• [HAL/AMDGPU] Sample counter ranges on a profile queue

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  benvanik

  committed
  2fc0cac

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• [HAL/AMDGPU] Fix patched-template profile metadata

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  benvanik

  committed
  85117aa

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• [HAL/AMDGPU] Add queue-range counter profiling

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  benvanik

  committed
  6ebc9c9

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